LTC2489

LTC2489 16-Bit 2-/4-Channel ΔΣ ADC with Easy Drive Input Current Cancellation and I2C Interface FEATURES ■ ■ DESCRIPTION The LTC®2489 is a 4-channel (2-channel differential), 16-bit, No Latency ΔΣ™ ADC with Easy Drive technology and a 2-wire, I2C interface. The patented sampling scheme eliminates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current. This allows large external source impedances and rail-to-rail input signals to be directly digitized while maintaining exceptional DC accuracy. The LTC2489 includes an integrated oscillator. This device can be configured to measure an external signal from combinations of 4 analog input channels operating in singleended or differential modes. It automatically rejects line frequencies of 50Hz and 60Hz simultaneously. The LTC2489 allows a wide, common mode input range (0V to VCC), independent of the reference voltage. Any combination of single-ended or differential inputs can be selected and the first conversion, after a new channel is selected, is valid. Access to the multiplexer output enables optional external amplifiers to be shared between all analog inputs and auto calibration continuously removes their associated offset and drift. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. No Latency ΔΣ and Easy Drive are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Up to 2 Differential or 4 Single-Ended Inputs Easy DriveTM Technology Enables Rail-to-Rail Inputs with Zero Differential Input Current Directly Digitizes High Impedance Sensors with Full Accuracy 2-Wire I2C Interface with 9 Addresses Plus One Global Address for Synchronization 600nV RMS Noise (0.02LSB Transition Noise) GND to VCC Input/Reference Common Mode Range Simultaneous 50Hz/60Hz Rejection 2ppm INL, No Missing Codes 1ppm Offset and 15ppm Full-Scale Error No Latency: Digital Filter Settles in a Single Cycle, Even After a New Channel is Selected Single Supply, 2.7V to 5.5V Operation (0.8mW) Internal Oscillator Tiny 4mm × 3mm DFN Package APPLICATIONS ■ ■ ■ ■ Direct Sensor Digitizer Direct Temperature Measurement Instrumentation Industrial Process Control TYPICAL APPLICATION Data Acquisition System with Temperature Compensation 2.7V TO 5.5V 0.1μF 10μF +FS ERROR (ppm) +FS Error vs RSOURCE at IN+ and IN– 80 VCC = 5V 60 VREF = 5V VIN+ = 3.75V – 40 VIN = 1.25V FO = GND 20 TA = 25°C CIN = 1μF 0 –20 –40 CH0 CH1 REF + VCC 4-CHANNEL MUX CH2 CH3 COM IN+ 1.7k SDA SCL CA1 CA0 FO OSC 2489 TA01a 16-BIT ΔΣ ADC WITH EASY-DRIVE IN– REF – 2-WIRE I2C INTERFACE 9-PIN SELECTABLE ADDRESSES –60 –80 1 10 100 1k RSOURCE (Ω) 10k 100k 2489 TA01b 2489f 1 LTC2489 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION FO CA0 CA1 SCL SDA GND COM 1 2 3 4 5 6 7 15 14 REF– 13 REF+ 12 VCC 11 CH3 10 CH2 9 CH1 8 CH0 Supply Voltage (VCC) ................................... –0.3V to 6V Analog Input Voltage (CH0 to CH3, COM) ..................–0.3V to (VCC + 0.3V) REF+, REF– ....................................–0.3V to (VCC + 0.3V) Digital Input Voltage......................–0.3V to (VCC + 0.3V) Digital Output Voltage ...................–0.3V to (VCC + 0.3V) Operating Temperature Range LTC2489C ................................................ 0°C to 70°C LTC2489I ............................................. –40°C to 85°C Storage Temperature Range................... –65°C to 150°C DE PACKAGE 14-LEAD (4mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 37°C/W EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LTC2489CDE#PBF LTC2489IDE#PBF TAPE AND REEL LTC2489CDE#TRPBF LTC2489IDE#TRPBF PART MARKING 2489 2489 PACKAGE DESCRIPTION 14-Lead (4mm × 3mm) Plastic DFN 14-Lead (4mm × 3mm) Plastic DFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2489f 2 LTC2489 ELECTRICAL CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Total Unadjusted Error CONDITIONS 0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF , IN– = 0.75VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF , IN– = 0.75VREF 5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V 2.7V < VCC < 5.5V, 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 12) ● ● ● ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) MIN 16 2 1 0.5 10 32 0.1 32 0.1 15 15 15 0.6 20 2.5 TYP MAX UNITS Bits ppm of VREF ppm of VREF μV nV/°C ppm of VREF ppm of VREF/°C ppm of VREF ppm of VREF/°C ppm of VREF ppm of VREF ppm of VREF μVRMS Output Noise CONVERTER CHARACTERISTICS PARAMETER Input Common Mode Rejection DC Input Normal Mode Rejection 50Hz/60Hz ±2% Reference Common Mode Rejection DC Power Supply Rejection DC Power Supply Rejection, 50Hz ±2% Power Supply Rejection, 60Hz ±2% CONDITIONS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) MIN ● ● ● TYP MAX UNITS dB dB 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 9) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) VREF = 2.5V, IN+ = IN– = GND VREF = 2.5V, IN+ = IN– = GND (Notes 7, 9) VREF = 2.5V, IN+ = IN– = GND (Notes 8, 9) 140 87 120 140 120 120 120 dB dB dB dB ANALOG INPUT AND REFERENCE SYMBOL IN+ IN– VIN FS LSB REF+ REF– VREF CS(IN+) CS(IN–) CS(VREF) IDC_LEAK(IN+) PARAMETER The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS MIN GND – 0.3V GND – 0.3V ● ● ● ● ● ● TYP MAX VCC + 0.3V VCC + 0.3V +FS UNITS V V V V Absolute/Common Mode IN+ Voltage (IN+ Corresponds to the Selected Positive Input Channel) Absolute/Common Mode IN– Voltage (IN– Corresponds to the Selected Negative Input Channel) Input Differential Voltage Range (IN+ – IN–) Full Scale of the Differential Input (IN+ – IN–) Least Significant Bit of the Output Code Absolute/Common Mode REF+ Voltage Absolute/Common Mode REF– Voltage Reference Voltage Range (REF+ – REF–) IN+ Sampling Capacitance IN– Sampling Capacitance VREF Sampling Capacitance IN+ DC Leakage Current Sleep Mode, IN+ = GND ● –FS 0.5VREF FS/216 0.1 GND 0.1 11 11 11 –10 1 VCC + – 0.1V REF VCC V V V pF pF pF 10 nA 2489f 3 LTC2489 ANALOG INPUT AND REFERENCE IDC_LEAK(IN–) IDC_LEAK(REF–) tOPEN QIRR IN– DC Leakage Current REF– DC Leakage Current MUX Break-Before-Make MUX Off Isolation VIN = 2VP-P DC to 1.8MHz IDC_LEAK(REF+) REF+ DC Leakage Current The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) Sleep Mode, IN– = GND Sleep Mode, REF+ = VCC Sleep Mode, REF– = GND ● ● ● –10 –100 –100 1 1 1 50 120 10 100 100 nA nA nA ns dB I2C INPUTS AND DIGITAL OUTPUTS SYMBOL VIH VIL VIHA VILA RINH RINL RINF II VHYS VOL tOF IIN CCAX PARAMETER High Level Input Voltage Low Level Input Voltage High Level Input Voltage for Address Pins CA0, CA1 Low Level Input Voltage for Address Pins CA0, CA1 Resistance from CA0, CA1 to VCC to Set Chip Address Bit to 1 Resistance from CA0, CA1 to GND to Set Chip Address Bit to 0 Resistance from CA0, CA1 to GND or VCC to Set Chip Address Bit to Float Digital Input Current Hysteresis of Schmidt Trigger Inputs Low Level Output Voltage (SDA) Output Fall Time VIH(MIN) to VIL(MAX) Input Leakage The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS ● ● ● ● ● ● ● ● MIN 0.7VCC TYP MAX 0.3VCC UNITS V V V V kΩ kΩ MΩ 0.95VCC 0.05VCC 10 10 2 –10 0.05VCC 0.4 20 + 0.1CB 250 1 10 10 μA V V ns μA pF (Note 5) I = 3mA Bus Load CB 10pF to 400pF (Note 14) 0.1VCC ≤ VIN ≤ VCC ● ● ● ● ● External Capacitative Load on Chip Address Pins (CA0, CA1) for Valid Float POWER REQUIREMENTS SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS ● MIN 2.7 ● ● TYP 160 1 MAX 5.5 275 2 UNITS V μA μA Conversion Current (Note 11) Sleep Mode (Note 11) 2489f 4 LTC2489 DIGITAL INPUTS AND DIGITAL OUTPUTS SYMBOL fEOSC tHEO tLEO tCONV PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time Internal Oscillator External Oscillator (Note 10) CONDITIONS (Note 16) ● ● ● ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) MIN 10 0.125 0.125 144.1 146.9 41036/fEOSC (in kHz) TYP MAX 4000 50 50 149.9 UNITS kHz μs μs ms ms I2C TIMING CHARACTERISTICS SYMBOL fSCL tHD(STA) tLOW tHIGH tSU(STA) tHD(DAT) tSU(DAT) tr tf tSU(STO) PARAMETER SCL Clock Frequency Hold Time (Repeated) Start Condition Low Period of the SCL Pin High Period of the SCL Pin Set-Up Time for a Repeated Start Condition Data Hold Time Data Set-Up Time Rise Time for SDA Signals Fall Time for SDA Signals Set-Up Time for Stop Condition The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3, 15) CONDITIONS ● ● ● ● ● ● ● MIN 0 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 TYP MAX 400 UNITS kHz μs μs μs μs 0.9 300 300 μs ns ns ns μs (Note 14) (Note 14) ● ● ● Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7V to 5.5V unless otherwise specified. VREFCM = VREF/2, FS = 0.5VREF VIN = IN+ – IN–, VIN(CM) = (IN+ – IN–)/2, where IN+ and IN– are the selected input channels. Note 4: Use internal conversion clock or external conversion clock source with fEOSC = 307.2kHz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: fEOSC = 256kHz ±2% (external oscillator). Note 8: fEOSC = 307.2kHz ±2% (external oscillator). Note 9: Simultaneous 50Hz/60Hz (internal oscillator) or fEOSC = 280kHz ±2% (external oscillator). Note 10: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 11: The converter uses its internal oscillator. Note 12: The output noise includes the contribution of the internal calibration operations. Note 13: Guaranteed by design and test correlation. Note 14: CB = capacitance of one bus line in pF (10pF ≤ CB ≤ 400pF). Note 15: All values refer to VIH(MIN) and VIL(MAX) levels. Note 16: Refer to Applications Information section for performance versus data rate graphs. 2489f 5 LTC2489 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity (VCC = 5V, VREF = 5V) 3 2 INL (ppm OF VREF) 1 0 85°C –1 –2 –3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) 3 VCC = 5V VREF = 5V VIN(CM) = 2.5V FO = GND INL (ppm OF VREF) –45°C 25°C 2 1 0 –1 –2 –3 –1.25 Integral Nonlinearity (VCC = 5V, VREF = 2.5V) VCC = 5V VREF = 2.5V VIN(CM) = 1.25V FO = GND INL (ppm OF VREF) –45°C, 25°C, 85°C 3 2 1 0 –1 –2 Integral Nonlinearity (VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V FO = GND –45°C, 25°C, 85°C 2 2.5 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2489 G02 –3 –1.25 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2489 G03 2489 G01 Total Unadjusted Error (VCC = 5V, VREF = 5V) 12 8 TUE (ppm OF VREF) 4 0 –4 –8 –12 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) –45°C VCC = 5V VREF = 5V VIN(CM) = 2.5V FO = GND 12 8 TUE (ppm OF VREF) 4 0 –4 –8 Total Unadjusted Error (VCC = 5V, VREF = 2.5V) VCC = 5V VREF = 2.5V VIN(CM) = 1.25V FO = GND 12 85°C 25°C 8 TUE (ppm OF VREF) 4 0 –4 –8 Total Unadjusted Error (VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V FO = GND 25°C 85°C 25°C 85°C –45°C –45°C 2 2.5 –12 –1.25 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2489 G05 –12 –1.25 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2489 G06 2489 G04 Offset Error vs VIN(CM) 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –1 0 1 3 2 VIN(CM) (V) 4 5 6 2489 G07 Offset Error vs Temperature 0.3 0.2 0.1 0 VCC = 5V VREF = 5V VIN = 0V FO = GND 0.3 0.2 0.1 0 –0.1 –0.2 Offset Error vs VCC REF+ = 2.5V REF– = GND VIN = 0V VIN(CM) = GND TA = 25°C FO = GND OFFSET ERROR (ppm OF VREF) OFFSET ERROR (ppm OF VREF) –0.1 –0.2 OFFSET ERROR (ppm OF VREF) VCC = 5V VREF = 5V VIN = 0V TA = 25°C FO = GND –0.3 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 –0.3 2.7 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5 2489 G08 2489 G09 2489f 6 LTC2489 TYPICAL PERFORMANCE CHARACTERISTICS Offset Error vs VREF 0.3 0.2 0.1 0 310 VCC = 5V REF – = GND VIN = 0V VIN(CM) = GND TA = 25°C FO = GND On-Chip Oscillator Frequency vs Temperature 310 On-Chip Oscillator Frequency vs VCC VREF = 2.5V VIN = 0V VIN(CM) = GND FO = GND TA = 25°C OFFSET ERROR (ppm OF VREF) 308 FREQUENCY (kHz) FREQUENCY (kHz) 75 90 308 306 306 304 VCC = 4.1V VREF = 2.5V VIN = 0V VIN(CM) = GND FO = GND 0 15 30 45 60 TEMPERATURE (°C) 304 –0.1 –0.2 302 302 –0.3 0 1 2 3 VREF (V) 4 5 2489 G10 300 –45 –30 –15 300 2.7 3.0 3.5 4.0 4.5 VCC (V) 5.0 5.5 2489 G12 2489 G11 PSRR vs Frequency at VCC 0 –20 –40 REJECTION (dB) –60 –80 –100 –120 –140 1 10 10k 100k 1k 100 FREQUENCY AT VCC (Hz) 1M VCC = 4.1V DC ±0.7V VREF = 2.5V IN+ = GND IN– = GND FO = GND TA = 25°C 0 –20 –40 REJECTION (dB) –60 –80 –100 –120 –140 PSRR vs Frequency at VCC VCC = 4.1V DC ±1.4V VREF = 2.5V IN+ = GND IN– = GND FO = GND TA = 25°C 0 –20 PSRR vs Frequency at VCC VCC = 4.1V DC ±0.7V VREF = 2.5V IN+ = GND IN– = GND –40 FO = GND TA = 25°C REJECTION (dB) –60 –80 –100 –120 –140 30600 0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT VCC (Hz) 2489 G14 30650 30700 30750 FREQUENCY AT VCC (Hz) 30800 2489 G15 2489 G13 Conversion Current vs Temperature 200 FO = GND SLEEP MODE CURRENT (μA) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 100 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 Sleep Mode Current vs Temperature 500 FO = GND 450 SUPPLY CURRENT (μA) 400 350 300 250 200 150 100 0 15 30 45 60 TEMPERATURE (°C) 75 90 Conversion Current vs Output Data Rate VREF = VCC IN+ = GND IN– = GND TA = 25°C VCC = 5V CONVERSION CURRENT (μA) 180 VCC = 5V 160 VCC = 2.7V VCC = 5V 140 VCC = 3V VCC = 2.7V 120 0 –45 –30 –15 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2489 G18 2489 G16 2489 G17 2489f 7 LTC2489 PIN FUNCTIONS FO (Pin 1): Frequency Control Pin. Digital input that controls the internal conversion clock rate. When FO is connected to GND, the converter uses its internal oscillator running at 307.2kHz. The conversion clock may also be overridden by driving the FO pin with an external clock in order to change the output rate and the digital filter rejection null. CA0, CA1 (Pins 2, 3): Chip Address Control Pins. These pins are configured as a three-state (LOW, HIGH, Floating) address control bits for the device’s I2C address. SCL (Pin 4): Serial Clock Pin of the I2C Interface. The LTC2489 can only act as a slave and the SCL pin only accepts an external serial clock. Data is shifted into the SDA pin on the rising edges of the SCL clock and output through the SDA pin on the falling edges of the SCL clock. SDA (Pin 5): Bidirectional Serial Data Line of the Interface. In the transmitter mode (Read), the conversion result is output through the SDA pin, while in the receiver mode (Write), the device channel select bits are input through the SDA pin. The pin is high impedance during the data input mode and is an open drain output (requires an appropriate pull-up device to VCC) during the data output mode. GND (Pin 6): Ground. Connect this pin to a common ground plane through a low impedance connection. I2C COM (Pin 7): The Common Negative Input (IN –) for All Single-Ended Multiplexer Configurations. The voltage on CH0-CH3 and COM pins can have any value between GND – 0.3V to VCC + 0.3V. Within these limits, the two selected inputs (IN+ and IN– ) provide a bipolar input range (VIN = IN+ – IN– ) from –0.5 • VREF to 0.5 • VREF . Outside this input range, the converter produces unique over-range and under-range output codes. CH0 to CH3 (Pin 8-Pin 11): Analog Inputs. May be programmed for single-ended or differential mode. VCC (Pin 12): Positive Supply Voltage. Bypass to GND with a 10μF tantalum capacitor in parallel with a 0.1μF ceramic capacitor as close to the part as possible. REF+, REF – (Pin 13, Pin 14): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF+, remains more positive than the negative reference input, REF–, by at least 0.1V. The differential voltage (VREF = REF+ – REF –) sets the full-scale range for all input channels. Exposed Pad (Pin 15): Ground. This pin is ground and must be soldered to the PCB ground plane. For prototyping purposes, this pin may remain floating. FUNCTIONAL BLOCK DIAGRAM VCC GND REF + REF – CH0 CH1 CH2 CH3 COM IN+ MUX IN– AUTOCALIBRATION AND CONTROL INTERNAL OSCILLATOR FO (INT/EXT) – + I2C INTERFACE DECIMATING FIR ADDRESS 2489 BD 1.7k SDA SCL CA0 CA1 DIFFERENTIAL 3RD ORDER ΔΣ MODULATOR 2489f 8 LTC2489 APPLICATIONS INFORMATION CONVERTER OPERATION Converter Operation Cycle The LTC2489 is a multichannel, low power, delta-sigma analog-to-digital converter with a 2-wire, I2C interface. Its operation is made up of four states (see Figure 1). The converter operating cycle begins with the conversion, followed by the sleep state and ends with the data input/output cycle . POWER-ON RESET DEFAULT INPUT CHANNEL: IN+ = CH0, IN– = CH1 the LTC2489 is addressed for a read operation, the device begins outputting the conversion result under the control of the serial clock (SCL). There is no latency in the conversion result. The data output is 24 bits long and contains a 16-bit plus sign conversion result. Data is updated on the falling edges of SCL allowing the user to reliably latch data on the rising edge of SCL. A new conversion is initiated by a stop condition following a valid write operation or an incomplete read operation. The conversion automatically begins at the conclusion of a complete read cycle (all 24 bits read out of the device). Ease of Use The LTC2489 data output has no latency, filter settling delay, or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog inputs is straightforward. Each conversion, immediately following a newly selected input is valid and accurate to the full specifications of the device. The LTC2489 automatically performs offset and full-scale calibration every conversion cycle independent of the input channel selected. This calibration is transparent to the user and has no effect on the operation cycle described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage variation, input channel, and temperature drift. Easy Drive Input Current Cancellation CONVERSION SLEEP NO ACKNOWLEDGE YES DATA OUTPUT/INPUT NO STOP OR READ 24 BITS YES 2489 F01 Figure 1. State Transition Table Initially, at power-up, the LTC2489 performs a conversion. Once the conversion is complete, the device enters the sleep state. In the sleep state, power consumption is reduced by two orders of magnitude. The part remains in the sleep state as long it is not addressed for a read/write operation. The conversion result is held indefinitely in a static shift register while the part is in the sleep state. The device will not acknowledge an external request during the conversion state. After a conversion is finished, the device is ready to accept a read/write request. Once The LTC2489 combines a high precision, delta-sigma ADC with an automatic, differential, input current cancellation front end. A proprietary front end passive sampling network transparently removes the differential input current. This enables external RC networks and high impedance sensors to directly interface to the LTC2489 without external amplifiers. The remaining common mode input current is eliminated by either balancing the differential input impedances or setting the common mode input equal to the common mode reference (see the Automatic Differential Input Current Cancellation section). This unique architecture does not require on-chip buffers, thereby enabling signals to swing beyond ground and VCC. Moreover, the 2489f 9 LTC2489 APPLICATIONS INFORMATION cancellation does not interfere with the transparent offset and full-scale auto-calibration and the absolute accuracy (full scale + offset + linearity + drift) is maintained even with external RC networks. Power-Up Sequence The LTC2489 automatically enters an internal reset state when the power supply voltage, VCC, drops below approximately 2.0V. This feature guarantees the integrity of the conversion result and input channel selection. When VCC rises above this threshold, the converter creates an internal power-on-reset (POR) signal with a duration of approximately 4ms. The POR signal clears all internal registers. The conversion immediately following a POR cycle is performed on the input channels IN+ = CH0 and IN – = CH1. The first conversion following a POR cycle is accurate within the specification of the device if the power supply voltage is restored to (2.7V to 5.5V) before the end of the POR interval. A new input channel can be programmed into the device during this first data input/ output cycle. Reference Voltage Range This converter accepts a truly differential, external reference voltage. The absolute/common mode voltage range for the REF+ and REF – pins covers the entire operating range of the device (GND to VCC). For correct converter operation, VREF must be positive (REF+ > REF –). The LTC2489 differential reference input range is 0.1V to VCC. For the simplest operation, REF+ can be shorted to VCC and REF – can be shorted to GND. The converter output noise is determined by the thermal noise of the front end circuits. Since the transition noise is well below 1LSB (0.02LSB), a decrease in reference voltage will proportionally improve the converter resolution and improve INL. Input Voltage Range The analog inputs are truly differential with an absolute, common mode range for the CH0-CH3 and COM input pins extending from GND – 0.3V to VCC + 0.3V. Within these limits, the LTC2489 converts the bipolar differential input signal VIN = IN+ – IN– (where IN+ and IN – are the selected input channels), from –FS = –0.5 • VREF to +FS = 0.5 • VREF where VREF = REF+ - REF–. Outside this range, the converter indicates the overrange or the underrange condition using distinct output codes (see Table 1). In order to limit any fault current due to input ESD leakage current, resistors of up to 5k may be added in series with the input. The effect of series resistance on the converter accuracy can be evaluated from the curves presented in the Input Current/Reference Current sections. In addition, series resistors will introduce a temperature dependent error due to input leakage current. A 1nA input leakage current will develop a 1ppm offset error on a 5k resistor if VREF = 5V. This error has a very strong temperature dependency. I2C INTERFACE The LTC2489 communicates through an I2C interface. The I2C interface is a 2-wire open-drain interface supporting multiple devices and multiple masters on a single bus. The connected devices can only pull the data line (SDA) low and can never drive it high. SDA is required to be externally connected to the supply through a pull-up resistor. When the data line is not being driven, it is high. Data on the I2C bus can be transferred at rates up to 100kbits/s in the standard mode and up to 400kbits/s in the fast mode. Each device on the I2C bus is recognized by a unique address stored in that device and can operate either as a transmitter or receiver, depending on the function of the device. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. Devices addressed by the master are considered a slave. The LTC2489 can only be addressed as a slave. Once addressed, it can receive channel selection bits or transmit the last conversion result. The serial clock line, SCL, is always an input to the LTC2489 and the serial data line SDA is bidirectional. The device supports the standard mode and the fast mode for data transfer speeds up to 400kbits/s. Figure 2 shows the definition of the I2C timing. 2489f 10 LTC2489 APPLICATIONS INFORMATION SDA tf tLOW tr tSU(DAT) tf tHD(SDA) tSP tr tBUF SCL tHD(SDA) S tSU(STA) Sr tSU(STO) P S 2489 F02 tHD(DAT) tHIGH Figure 2. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus The Start and Stop Conditions A Start (S) condition is generated by transitioning SDA from high to low while SCL is high. The bus is considered to be busy after the Start condition. When the data transfer is finished, a Stop (P) condition is generated by transitioning SDA from low to high while SCL is high. The bus is free after a Stop is generated. Start and Stop conditions are always generated by the master. When the bus is in use, it stays busy if a Repeated Start (Sr) is generated instead of a Stop condition. The repeated Start timing is functionally identical to the Start and is used for writing and reading from the device before the initiation of a new conversion. Data Transferring After the Start condition, the I2C bus is busy and data transfer can begin between the master and the addressed slave. Data is transferred over the bus in groups of nine bits, one byte followed by one acknowledge (ACK) bit. The master releases the SDA line during the ninth SCL clock cycle. The slave device can issue an ACK by pulling SDA low or issue a Not Acknowledge (NAK) by leaving the SDA line high impedance (the external pull-up resistor will hold the line high). Change of data only occurs while the clock line (SCL) is low. DATA FORMAT After a Start condition, the master sends a 7-bit address followed by a read/write (R/W) bit. The R/W bit is 1 for a read request and 0 for a write request. If the 7-bit address matches the hard wired, LTC2489’s address (one of 9 pin-selectable addresses) the device is selected. When the device is addressed during the conversion state, it will not acknowledge R/W requests and will issue a NAK by leaving the SDA line high. If the conversion is complete, the LTC2489 issues an ACK by pulling the SDA line low. The LTC2489 has two registers. The output register (24 bits long) contains the last conversion result. The input register (8 bits long) sets the input channel. DATA OUTPUT FORMAT The output register contains the last conversion result. After each conversion is completed, the device automatically enters the sleep state where the supply current is reduced to 1μA. When the LTC2489 is addressed for a read operation, it acknowledges (by pulling SDA low) and acts as a transmitter. The master/receiver can read up to three bytes from the LTC2489. After a complete read operation (3 bytes), a new conversion is initiated. The device will NAK subsequent read operations while a conversion is being performed. The data output stream is 24 bits long and is shifted out on the falling edges of SCL (see Figure 3a). The first bit is the conversion result sign bit (SIG) (see Tables 1 and 2). This bit is high if VIN ≥ 0 and low if VIN < 0 (where VIN corresponds to the selected input signal IN+ – IN–). The second bit is the most significant bit (MSB) of the result. The first two bits (SIG and MSB) can be used to indicate over and under range conditions (see Table 2). If both bits are HIGH, the differential input voltage is equal to or above +FS. If both bits are set low, the input voltage is below –FS. The function of these bits is summarized in Table 2. The 16 bits following the MSB bit are the conversion 2489f 11 LTC2489 APPLICATIONS INFORMATION Table 1. Output Data Format Differential Input Voltage VIN* VIN* ≥ FS** FS** – 1LSB 0.5 • FS** 0.5 • FS** – 1LSB 0 –1LSB –0.5 • FS** –0.5 • FS** – 1LSB –FS** VIN* < –FS** Bit 23 SIG 1 1 1 1 1 0 0 0 0 0 Bit 22 MSB 1 0 0 0 0 1 1 1 1 0 Bit 21 0 1 1 0 0 1 1 0 0 1 Bit 20 0 1 0 1 0 1 0 1 0 1 Bit 19 0 1 0 1 0 1 0 1 0 1 … … … … … … … … … … … Bit 6 LSB 0 1 0 1 0 1 0 1 0 1 Bits 5-0 Always 0 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000 *The differential input voltage VIN = IN+ – IN–. **The full-scale voltage FS = 0.5 • VREF . result in binary two’s complement format. The remaining six bits are always 0. As long as the voltage on the selected input channels (IN+ and IN–) remains between –0.3V and VCC + 0.3V (absolute maximum operating range) a conversion result is generated for any differential input voltage VIN from –FS = –0.5 • VREF to +FS = 0.5 • VREF . For differential input voltages greater than +FS, the conversion result is clamped to the value corresponding to +FS. For differential input voltages below –FS, the conversion result is clamped to the value –FS – 1LSB. Table 2. LTC2489 Status Bits Input Range VIN ≥ FS 0V ≤ VIN < FS –FS ≤ VIN < 0V VIN < –FS Bit 23 SIG 1 1 0 0 Bit 22 MSB 1 0 1 0 conversion is complete, a new channel may be written into the device. The first three bits of the input word consist of two preamble bits and one enable bit. These three bits are used to enable the input channel selection. Valid settings for these three bits are 000, 100, and 101. Other combinations should be avoided. If the first three bits are 000 or 100, the following data is ignored (don’t care) and the previously selected input channel remains valid for the next conversion. If the first three bits shifted into the device are 101, then the next five bits select the input channel for the next conversion cycle (see Table 3). Table 3 Channel Selection MUX ADDRESS SGL *0 0 0 0 1 1 1 1 ODD/ SIGN 0 0 1 1 0 0 1 1 A2 0 0 0 0 0 0 0 0 A1 0 0 0 0 0 0 0 0 A0 0 1 0 1 0 1 0 1 IN+ IN+ IN+ IN+ IN– IN+ IN– IN+ IN– IN– IN– IN– 0 IN+ CHANNEL SELECTION 1 IN– IN+ IN– 2 3 COM INPUT DATA FORMAT The LTC2489 serial input is 8 bits long and is written into the device in one 8-bit word. SGL, ODD, A2, A1, A0 are used to select the input channel. After power-up, the device initiates an internal reset cycle which sets the input channel to CH0-CH1 (IN+ = CH0, IN– = CH1). The first conversion automatically begins at power-up using this default input channel. Once the *Default at power up 2489f 12 LTC2489 APPLICATIONS INFORMATION SCL 1 … 7 8 9 1 2 … 9 1 2 3 4 5 6 7 8 9 SDA 7-BIT ADDRESS R ACK BY LTC2489 SIG MSB D23 ACK BY MASTER LSB ALWAYS LOW NAK BY MASTER START BY MASTER SLEEP DATA OUTPUT 2489 F03a Figure 3a. Timing Diagram for Reading from the LTC2489 SCL 1 2 … 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SDA 7-BIT ADDRESS W ACK BY LTC2489 SLEEP 1 0 EN SGL ODD A2 A1 A0 ACK BY LTC2489 DATA INPUT X X X X X X X X NAK BY LTC2489 START BY MASTER 2489 F03b Figure 3b. Timing Diagram for Writing to the LTC2489 The first input bit (SGL) following the 101 sequence determines if the input selection is differential (SGL = 0) or single-ended (SGL = 1). For SGL = 0, two adjacent channels can be selected to form a differential input. For SGL = 1, one of 4 channels is selected as the positive input. The negative input is COM for all single-ended operations. The remaining four bits (ODD, A2, A1, A0) determine which channel(s) is/are selected and the polarity (for a differential input). Initiating a New Conversion When the LTC2489 finishes a conversion, it automatically enters the sleep state. Once in the sleep state, the device is ready for a read operation. After the device acknowledges a read request, the device exits the sleep state and enters the data output state. The data output state concludes and the LTC2489 starts a new conversion once a Stop condition is issued by the master or all 24 bits of data are read out of the device. During the data read cycle, a Stop command may be issued by the master controller in order to start a new conversion and abort the data transfer. This Stop command must be issued during the ninth clock cycle of a byte read when the bus is free (the ACK/NAK cycle). LTC2489 Address The LTC2489 has two address pins (CA0, CA1). Each may be tied high, low, or left floating enabling one of 9 possible addresses (see Table 4). In addition to the configurable addresses listed in Table 4, the LTC2489 also contains a global address (1110111) which may be used for synchronizing multiple LTC2489s or other LTC24XX delta-sigma I2C devices, (See Synchronizing Multiple LTC2489s with Global Address Call section). 2489f 13 LTC2489 APPLICATIONS INFORMATION Table 4. Address Assignment CA1 LOW LOW LOW HIGH HIGH HIGH FLOAT FLOAT FLOAT CA0 LOW HIGH FLOAT LOW HIGH FLOAT LOW HIGH FLOAT ADDRESS 0010100 0010110 0010101 0100110 0110100 0100111 0010111 0100101 0100100 Continuous Read In applications where the input channel does not need to change for each cycle, the conversion can be continuously performed and read without a write cycle (see Figure 5). The input channel remains unchanged from the last value written into the device. If the device has not been written to since power up, the channel selection is set to the default value of CH0 = IN+, CH1 = IN–. At the end of a read operation, a new conversion automatically begins. At the conclusion of the conversion cycle, the next result may be read using the method described above. If the conversion cycle is not concluded and a valid address selects the device, the LTC2489 generates a NAK signal indicating the conversion cycle is in progress. Continuous Read/Write Once the conversion cycle is concluded, the LTC2489 can be written to and then read from using the Repeated Start (Sr) command. Operation Sequence The LTC2489 acts as a transmitter or receiver, as shown in Figure 4. The device may be programmed to select an input channel, differential or single-ended mode, and channel polarity. S 7-BIT ADDRESS R/W ACK DATA Sr DATA TRANSFERRING P CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION 2489 F04 Figure 4. Conversion Sequence S 7-BIT ADDRESS R ACK READ P S 7-BIT ADDRESS R ACK READ P CONVERSION SLEEP DATA INPUT CONVERSION SLEEP DATA OUTPUT CONVERSION 2489 F05 Figure 5. Consecutive Reading with the Same Input/Configuration 2489f 14 LTC2489 APPLICATIONS INFORMATION Figure 6 shows a cycle which begins with a data Write, a repeated Start, followed by a Read and concluded with a Stop command. The following conversion begins after all 24 bits are read out of the device or after a Stop command. The following conversion will be performed using the newly programmed data. Discarding a Conversion Result and Initiating a New Conversion with Optional Write At the conclusion of a conversion cycle, a write cycle can be initiated. Once the write cycle is acknowledged, a Stop command will start a new conversion. If a new input channel is required, this data can be written into the device and a Stop command will initiate the next conversion (see Figure 7). Synchronizing Multiple LTC2489s with a Global Address Call In applications where several LTC2489s (or other I2C delta-sigma ADCs from Linear Technology Corporation) are used on the same I2C bus, all converters can be synchronized through the use of a global address call. Prior to issuing the global address call, all converters must have completed a conversion cycle. The master then issues a Start, followed by the global address 1110111, and a write request. All converters will be selected and acknowledge the request. The master then sends a write byte (optional) followed by the Stop command. This will update the channel selection (optional) and simultaneously initiate a start of conversion for all delta-sigma ADCs on the bus (see Figure 8). In order to synchronize multiple converters S 7-BIT ADDRESS W ACK WRITE Sr 7-BIT ADDRESS R ACK READ P CONVERSION SLEEP DATA INPUT ADDRESS DATA OUTPUT CONVERSION 2489 F06 Figure 6. Write, Read, Start Conversion S 7-BIT ADDRESS W ACK WRITE (OPTIONAL) P CONVERSION SLEEP DATA INPUT CONVERSION 2489 F07 Figure 7. Start a New Conversion Without Reading Old Conversion Result SCL SDA LTC2489 LTC2489 … LTC2489 S GLOBAL ADDRESS W ACK WRITE (OPTIONAL) P ALL LTC2489s IN SLEEP DATA INPUT CONVERSION OF ALL LTC2489s 2489 F08 Figure 8. Synchronize Multiple LTC2489s with a Global Address Call 2489f 15 LTC2489 APPLICATIONS INFORMATION without changing the channel, a Stop may be issued after acknowledgement of the global write command. Global read commands are not allowed and the converters will NAK a global read request. Driving the Input and Reference The input and reference pins of the LTC2489 are connected directly to a switched capacitor network. Depending on the relationship between the differential input voltage and the differential reference voltage, these capacitors are switched between these four pins. Each time a capacitor is switched between two of these pins, a small amount of charge is transferred. A simplified equivalent circuit is shown in Figure 9. When using the LTC2489’s internal oscillator, the input capacitor array is switched at 123kHz. The effect of the charge transfer depends on the circuitry driving the input/reference pins. If the total external RC time constant is less than 580ns the errors introduced by the sampling process are negligible since complete settling occurs. Typically, the reference inputs are driven from a low impedance source. In this case, complete settling occurs even with large external bypass capacitors. The inputs (CH0-CH3, COM), on the other hand, are typically driven from larger source resistances. Source resistances up to 10k may interface directly to the LTC2489 and settle INPUT MULTIPLEXER 100Ω INTERNAL SWITCH NETWORK 10kΩ completely; however, the addition of external capacitors at the input terminals in order to filter unwanted noise (antialiasing) results in incomplete settling. Automatic Differential Input Current Cancellation In applications where the sensor output impedance is low (up to 10kΩ with no external bypass capacitor or up to 500Ω with 0.001μF bypass), complete settling of the input occurs. In this case, no errors are introduced and direct digitization is possible. For many applications, the sensor output impedance combined with external input bypass capacitors produces RC time constants much greater than the 580ns required for 1ppm accuracy. For example, a 10kΩ bridge driving a 0.1μF capacitor has a time constant an order of magnitude greater than the required maximum. The LTC2489 uses a proprietary switching algorithm that forces the average differential input current to zero independent of external settling errors. This allows direct digitization of high impedance sensors without the need for buffers. The switching algorithm forces the average input current on the positive input (IIN+) to be equal to the average input current on the negative input (IIN–). Over the complete conversion cycle, the average differential input current (IIN+ – IIN–) is zero. While the differential input current is IIN+ IN+ I IN+ () ( AVG = I IN– ≈ () AVG = VIN(CM) − VREF(CM) 0.5 • REQ IIN– IN– 100Ω 10kΩ I REF + where : ) 1.5VREF + VREF(CM) – VIN(CM) 0.5 • REQ ( )– AVG VIN2 VREF • REQ VREF = REF + − REF − CEQ 12μF IREF+ REF+ 10kΩ ⎛ REF + – REF − ⎞ VREF(CM) = ⎜ ⎟ ⎜ ⎟ 2 ⎝ ⎠ VIN = IN+ − IN− , WHERE IN+ AND IN− ARE THE SELECTED INPUT CHANNELS ⎛ IN+ – IN− ⎞ VIN(CM) = ⎜ ⎟ ⎜ ⎟ 2 ⎝ ⎠ REQ = 2.98MΩ INTERNAL OSCILLATOR IREF– REF– 10kΩ 2489 F09 REQ = 0.833 • 1012 /fEOSC EXTERNAL OSCILLATOR ( ) SWITCHING FREQUENCY fSW = 123kHz INTERNAL OSCILLATOR fSW = 0.4 • fEOSC EXTERNAL OSCILLATOR Figure 9. Equivalent Analog Input Circuit 2489f 16 LTC2489 APPLICATIONS INFORMATION zero, the common mode input current (IIN+ + IIN–)/2 is proportional to the difference between the common mode input voltage (VIN(CM)) and the common mode reference voltage (VREF(CM)). In applications where the input common mode voltage is equal to the reference common mode voltage, as in the case of a balanced bridge, both the differential and common mode input current are zero. The accuracy of the converter is not compromised by settling errors. In applications where the input common mode voltage is constant but different from the reference common mode voltage, the differential input current remains zero while the common mode input current is proportional to the difference between VIN(CM) and VREF(CM). For a reference common mode voltage of 2.5V and an input common mode of 1.5V, the common mode input current is approximately 0.74μA. This common mode input current does not degrade the accuracy if the source impedances tied to IN+ and IN– are matched. Mismatches in source impedance lead to a fixed offset error but do not effect the linearity or full-scale reading. A 1% mismatch in a 1k source resistance leads to a 74μV shift in offset voltage. In applications where the common mode input voltage varies as a function of the input signal level (single-ended type sensors), the common mode input current varies proportionally with input voltage. For the case of balanced input impedances, the common mode input current effects are rejected by the large CMRR of the LTC2489, leading 90 80 70 +FS ERROR (ppm) 60 50 40 30 20 10 0 –10 0 10 1k 100 RSOURCE (Ω) 10k 100k 2489 F10 to little degradation in accuracy. Mismatches in source impedances lead to gain errors proportional to the difference between the common mode input and common mode reference. 1% mismatches in 1k source resistances lead to gain errors on the order of 15ppm. Based on the stability of the internal sampling capacitors and the accuracy of the internal oscillator, a one-time calibration will remove this error. In addition to the input sampling current, the input ESD protection diodes have a temperature dependent leakage current. This current, nominally 1nA (±10nA max), results in a small offset shift. A 1k source resistance will create a 1μV typical and a 10μV maximum offset voltage. Reference Current Similar to the analog inputs, the LTC2489 samples the differential reference pins (REF+ and REF–) transferring small amounts of charge to and from these pins, thus producing a dynamic reference current. If incomplete settling occurs (as a function the reference source resistance and reference bypass capacitance) linearity and gain errors are introduced. For relatively small values of external reference capacitance (CREF < 1nF), the voltage on the sampling capacitor settles for reference impedances of many kΩ (if CREF = 100pF up to 10kΩ will not degrade the performance) (see Figures 10 and 11). –FS ERROR (ppm) VCC = 5V VREF = 5V VIN+ = 3.75V VIN– = 1.25V FO = GND TA = 25°C CREF = 0.01μF CREF = 0.001μF CREF = 100pF CREF = 0pF 10 0 –10 –20 –30 –40 –50 VCC = 5V –60 VREF = 5V V + = 1.25V –70 VIN– = 3.75V IN –80 FO = GND TA = 25°C –90 10 0 CREF = 0.01μF CREF = 0.001μF CREF = 100pF CREF = 0pF 1k 100 RSOURCE (Ω) 10k 100k 2489 F11 Figure 10. +FS Error vs RSOURCE at VREF (Small CREF) Figure 11. –FS Error vs RSOURCE at VREF (Small CREF) 2489f 17 LTC2489 APPLICATIONS INFORMATION In cases where large bypass capacitors are required on the reference inputs (CREF > .01μF), full-scale and linearity errors are proportional to the value of the reference resistance. Every ohm of reference resistance produces a full-scale error of approximately 0.5ppm (while operating with the internal oscillator) (see Figures 12 and 13). If the input common mode voltage is equal to the reference common mode voltage, a linearity error of approximately 0.67ppm per 100Ω of reference resistance results (see Figure 14). In applications where the input and reference common mode voltages are different, the errors increase. A 1V difference in between common mode input and common mode reference results in a 6.7ppm INL error for every 100Ω of reference resistance. 500 VCC = 5V VREF = 5V VIN+ = 3.75V VIN– = 1.25V FO = GND TA = 25°C CREF = 1μF, 10μF –100 CREF = 0.1μF –FS ERROR (ppm) CREF = 0.01μF –200 CREF = 1μF, 10μF –300 VCC = 5V VREF = 5V VIN+ = 1.25V VIN– = 3.75V FO = GND TA = 25°C 0 200 600 400 RSOURCE (Ω) CREF = 0.1μF In addition to the reference sampling charge, the reference ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (±10nA max) results in a small, gain error. A 100Ω reference resistance will create a 0.5μV full-scale error. Normal Mode Rejection and Antialiasing One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversample ratio, the LTC2489 significantly simplifies antialiasing filter requirements. Additionally, the input current cancellation feature allows external low pass filtering without degrading the DC performance of the device. 0 400 +FS ERROR (ppm) 300 200 CREF = 0.01μF 100 –400 0 –500 0 200 600 400 RSOURCE (Ω) 800 1000 2489 F12 800 1000 2489 F13 Figure 12. +FS Error vs RSOURCE at VREF (Large CREF) Figure 13. –FS Error vs RSOURCE at VREF (Large CREF) 10 INL (ppm OF VREF) VCC = 5V 8 VREF = 5V VIN(CM) = 2.5V 6 T = 25°C A 4 CREF = 10μF 2 0 R = 1k R = 500Ω R = 100Ω –2 –4 –6 –8 –10 – 0.5 – 0.3 0.1 – 0.1 VIN/VREF 0.3 0.5 2489 F14 Figure 14. INL vs Differential Input Voltage and Reference Source Resistance for CREF > 1μF 2489f 18 LTC2489 APPLICATIONS INFORMATION The SINC4 digital filter provides excellent normal mode rejection at all frequencies except DC and integer multiples of the modulator sampling frequency (fS). The modulator sampling frequency is fS = 15,360Hz while operating with its internal oscillator and fS = fEOSC/20 when operating with an external oscillator of frequency fEOSC . When using the internal oscillator, the LTC2489 is designed to reject line frequencies. As shown in Figure 15, rejection nulls occur at multiples of frequency fN, where fN = 55Hz for simultaneous 50Hz/60Hz rejection. Multiples of the modulator sampling rate (fS = fN • 256) only reject noise to 15dB (see Figure 16); if noise sources are present at these frequencies antialiasing will reduce their effects. The user can expect to achieve this level of performance using the internal oscillator, as shown in Figure 17. Measured values of normal mode rejection are shown superimposed over the theoretical values. 0 INPUT NORMAL MODE REJECTION (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fN 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (Hz) 8fN fN = fEOSC/5120 Traditional high order delta-sigma modulators suffer from potential instabilities at large input signal levels. The proprietary architecture used for the LTC2489 third order modulator resolves this problem and guarantees stability with input signals 150% of full scale. In many industrial applications, it is not uncommon to have microvolt level signals superimposed over unwanted error sources with several volts if peak-to-peak noise. Figure 18 shows measurement results for the rejection of a 7.5V peak-to-peak noise source (150% of full scale) applied to the LTC2489. This curve shows that the rejection performance is maintained even in extremely noisy environments. Output Data Rate When using its internal oscillator, the LTC2489 produces up to 7.5 samples per second (sps) with a notch frequency of 60Hz. The actual output data rate depends upon the length of the sleep and data output cycles which are controlled 0 INPUT NORMAL MODE REJECTION (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 250fN 252fN 254fN 256fN 258fN 260fN 262fN INPUT SIGNAL FREQUENCY (Hz) 2489 F16 fN = fEOSC/5120 2489 F15 Figure 15. Input Normal Mode Rejection at DC Figure 16. Input Normal Mode Rejection at fS = 256 • fN 2489f 19 LTC2489 APPLICATIONS INFORMATION 0 NORMAL MODE REJECTION (dB) –20 –40 – 60 –80 –100 –120 MEASURED DATA CALCULATED DATA NORMAL MODE REJECTION (dB) VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25°C 0 –20 –40 – 60 –80 –100 –120 VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) VCC = 5V VREF = 5V VIN(CM) = 2.5V TA = 25°C 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz) 2489 F17 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz) 2489 F18 Figure 17. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% (50Hz/60Hz Notch) Figure 18. Measure Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% (60Hz Notch) by the user and can be made insignificantly short. When operating with an external conversion clock (fO connected to an external oscillator), the LTC2489 output data rate can be increased. The duration of the conversion cycle is 41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves as if the internal oscillator is used. An increase in fEOSC over the nominal 307.2kHz will translate into a proportional increase in the maximum output data rate (up to a maximum of 100sps). The increase in output rate leads to degradation in offset, full-scale error, and effective resolution as well as a shift in frequency rejection. A change in fEOSC results in a proportional change in the internal notch position. This leads to reduced differential mode rejection of line frequencies. The common mode rejection of line frequencies remains unchanged, thus fully differential input signals with a high degree of symmetry on both the IN+ and IN– pins will continue to reject line frequency noise. An increase in fEOSC also increases the effective dynamic input and reference current. External RC networks will continue to have zero differential input current, but the time required for complete settling (580ns for fEOSC = 307.2kHz) is reduced, proportionally. Once the external oscillator frequency is increased above 1MHz (a more than 3X increase in output rate) the effectiveness of internal auto calibration circuits begins to degrade. This results in larger offset errors, full-scale errors, and decreased resolution, as shown in Figures 19 to 26. 2489f 20 LTC2489 APPLICATIONS INFORMATION 50 40 30 20 10 0 TA = 25°C –10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2489 F19 OFFSET ERROR (ppm OF VREF) +FS ERROR (ppm OF VREF) –FS ERROR (ppm OF VREF) VIN(CM) = VREF(CM) VCC = VREF = 5V VIN = 0V FO = EXT CLOCK TA = 85°C 3500 3000 2500 VIN(CM) = VREF(CM) VCC = VREF = 5V FO = EXT CLOCK TA = 85°C 0 –500 –1000 TA = 25°C TA = 85°C –2000 2000 1500 1000 500 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2489 F20 –1500 TA = 25°C –2500 –3000 –3500 VIN(CM) = VREF(CM) VCC = VREF = 5V FO = EXT CLOCK 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2489 F21 Figure 19. Offset Error vs Output Data Rate and Temperature Figure 20. +FS Error vs Output Data Rate and Temperature Figure 21.–FS Error vs Output Data Rate and Temperature 18 TA = 25°C, 85°C RESOLUTION (BITS) RESOLUTION (BITS) 16 18 20 16 TA = 85°C 14 TA = 25°C OFFSET ERROR (ppm OF VREF) VIN(CM) = VREF(CM) VIN = 0V 15 FO = EXT CLOCK TA = 25°C 10 VCC = VREF = 5V 5 0 –5 VCC = 5V, VREF = 2.5V 14 12 VIN(CM) = VREF(CM) VCC = VREF = 5V VIN = 0V FO = EXT CLOCK RES = LOG 2 (VREF/NOISERMS) 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2489 F22 10 12 VIN(CM) = VREF(CM) VCC = VREF = 5V FO = EXT CLOCK RES = LOG 2 (VREF/INLMAX) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2489 F23 –10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2489 F24 Figure 22. Resolution (NoiseRMS ≤ 1LSB) vs Output Data Rate and Temperature Figure 23. Resolution (INLMAX ≤ 1LSB) vs Output Data Rate and Temperature Figure 24. Offset Error vs Output Data Rate and Temperature 18 18 RESOLUTION (BITS) 16 VCC = 5V, VREF = 2.5V, 5V 14 RESOLUTION (BITS) 16 VCC = 5V, VREF = 2.5V 14 VCC = VREF = 5V VIN(CM) = VREF(CM) 12 VIN = 0V FO = EXT CLOCK TA = 25°C RES = LOG 2 (VREF/NOISERMS) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2489 F25 VIN(CM) = VREF(CM) VIN = 0V 12 REF– = GND FO = EXT CLOCK TA = 25°C RES = LOG 2 (VREF/INLMAX) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2489 F26 Figure 25. Resolution (NoiseRMS ≤ 1LSB) vs Output Data Rate and Temperature Figure 26. Resolution (INLMAX ≤ 1LSB) vs Output Data Rate and Temperature 2489f 21 LTC2489 APPLICATIONS INFORMATION Easy Drive ADCs Simplify Measurement of High Impedance Sensors Delta-Sigma ADCs, with their high accuracy and high noise immunity, are ideal for directly measuring many types of sensors. Nevertheless, input sampling currents can overwhelm high source impedances or low-bandwidth, micropower signal conditioning circuits. The LTC2489 solves this problem by balancing the input currents, thus simplifying or eliminating the need for signal conditioning circuits. A common application for a delta-sigma ADC is thermistor measurement. Figure 27 shows two examples of thermistor digitization benefiting from the Easy Drive technology. The first circuit (applied to input channels CH0 and CH1) uses balanced reference resistors in order to balance the common mode input/reference voltage and balance the differential input source resistance. If reference resistors R1 and R4 are exactly equal, the input current is zero and no errors result. If these resistors have a 1% tolerance, the maximum error in measured resistance is 1.6Ω due to a shift in common mode voltage; far less than the 1% error of the reference resistors themselves. No amplifier is required, making this an ideal solution in micropower applications. Easy Drive also enables very low power, low bandwidth amplifiers to drive the input to the LTC2489. As shown in Figure 27, CH2 is driven by the LT1494. The LT1494 has excellent DC specs for an amplifier with 1.5μA supply current (the maximum offset voltage is 150μV and the open loop gain is 100,000). Its 2kHz bandwidth makes it unsuitable for driving conventional delta sigma ADCs. Adding a 1kΩ, 0.1μF filter solves this problem by providing a charge reservoir that supplies the LTC2489 instantaneous current, while the 1k resistor isolates the capacitive load from the LT1494. Conventional delta sigma ADCs input sampling current lead to DC errors as a result of incomplete settling in the external RC network. The Easy Drive technology cancels the differential input current. By balancing the negative input (CH3) with a 1kΩ, 0.1μF network errors due to the common mode input current are cancelled. 2489f 22 LTC2489 PACKAGE DESCRIPTION DE Package 14-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1708 Rev B) 0.70 ± 0.05 3.60 ± 0.05 2.20 ± 0.05 3.30 ± 0.05 1.70 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 3.00 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ± 0.10 (2 SIDES) R = 0.05 TYP R = 0.115 TYP 8 14 0.40 ± 0.10 3.00 ± 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 3.30 ± 0.10 1.70 ± 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER (DE14) DFN 0806 REV B 7 0.200 REF 0.75 ± 0.05 3.00 REF 0.00 – 0.05 1 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2489f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC2489 TYPICAL APPLICATION 5V R1 51.1k C4 0.1μF IIN+ = 0 R3 10k TO 100k 10μF 13 0.1μF C3 0.1μF 5V 102k 5V R4 IIN– = 0 51.1k 14 8 9 10 11 1k LT1494 0.1μF 1k 0.1μF 7 5V 12 VCC LTC2489 REF + REF– CH0 CH1 CH2 CH3 COM GND 2489 F38 FO 1 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR 1.7k SDA SCL 5 4 2-WIRE I2C INTERFACE CA0 CA1 6 2 3 9-PIN SELECTABLE ADDRESSES + 0.1μF 10k TO 100k – Figure 27. Easy Drive ADCs Simplify Measurement of High Impedance Sensors RELATED PARTS PART NUMBER LT1236A-5 LT1460 LT1790 LTC2400 LTC2410 LTC2440 LTC2442 LTC2449 DESCRIPTION Precision Bandgap Reference, 5V Micropower Series Reference Micropower SOT-23 Low Dropout Reference Family 24-bit, No Latency ΔΣ ADC in SO-8 24-bit, No Latency ΔΣ ADC with Differential Inputs High Speed, Low Noise 24-bit ΔΣ ADC 24-Bit, High Speed, 4-Channel/2-Channel ΔΣ ADC with Integrated Amplifier 24-Bit, High Speed, 8-Channel/16-Channel ΔΣ ADC COMMENTS 0.05% Max Initial Accuracy, 5ppm/°C Drift 0.075% Max Initial Accuracy, 10ppm/°C Max Drift 0.05% Max Initial Accuracy, 10ppm/°C Max Drift 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA 0.8μVRMS Noise, 2ppm INL 3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs 8kHz Output Rate, 220nV Noise, Simultaneous 50Hz/60Hz Rejection 8kHz Output Rate, 200nV Noise, Simultaneous 50Hz/60Hz Rejection Pin Compatible 16-Bit and 24-Bit Versions Pin Compatible 16-Bit and 24-Bit Versions LTC2480/LTC2482/ 16-/24-Bit ΔΣ ADCs with Easy Drive Inputs, 600nV Noise, LTC2484 Programmable Gain, and Temperature Sensor LTC2481/LTC2483/ 16-/24-Bit ΔΣ ADCs with Easy Drive Inputs, 600nV Noise, I2C Interface, Programmable Gain, and Temperature Sensor LTC2485 LTC2486/LTC2488/ 16-Bit/24-Bit 2-/4-Channel ΔΣ ADC with Easy Drive Inputs, SPI Pin-Compatible 16-Bit and 24-Bit Versions LTC2492 Interface, Programmable Gain, and Temperature Sensor LTC2487 LTC2493 16-Bit 2-/4-Channel ΔΣ ADC with Easy Drive Inputs and I2C Interface 24-Bit 2-/4-Channel ΔΣ ADC with Easy Drive Inputs, I2C Interface and Temperature Sensor Pin-Compatible LTC2493/LTC2489 Pin Compatible LTC2487/LTC2489 LTC2495/LTC2497/ 16-Bit/24-Bit 8-/16-Channel ΔΣ ADC with Easy Drive Inputs and Pin-Compatible 16-Bit and 24-Bit Versions LTC2499 I2C Interface, Programmable Gain, and Temperature Sensor LTC2496/LTC2498 16-Bit 8-/16-Channel ΔΣ ADC with Easy Drive Inputs and SPI Interface Pin-Compatible with LTC2449/LTC2494 2489f 24 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0307 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007