LTC2635

LTC2635 Quad 12-/10-/8-Bit I2C VOUT DACs with 10ppm/°C Reference FEATURES n DESCRIPTION The LTC®2635 is a family of quad 12-, 10-, and 8-bit voltage-output DACs with an integrated, high-accuracy, low-drift reference in a 16-pin QFN or a 10-lead MSOP package. It has rail-to-rail output buffers and is guaranteed monotonic. The LTC2635-L has a full-scale output of 2.5V, and operates from a single 2.7V to 5.5V supply. The LTC2635-H has a full-scale output of 4.096V, and operates from a 4.5V to 5.5V supply. Each DAC can also operate with an external reference, which sets the fullscale output to the external reference voltage. These DACs communicate via a 2-wire I2C-compatible serial interface. The LTC2635 operates in both the standard mode (clock rate of 100kHz) and the fast mode (clock rate of 400kHz). The LTC2635 incorporates a power-on reset circuit. Options are available for reset to zero-scale, reset to mid-scale in internal reference mode, reset to mid-scale in external reference mode, or reset with all DAC outputs in a high-impedance state after power-up. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5396245, 5859606, 6891433, 6937178, 7414561. n n n n n n n n n n Integrated Precision Reference 2.5V Full-Scale 10ppm/°C (LTC2635-L) 4.096V Full-Scale 10ppm/°C (LTC2635-H) Maximum INL Error: ±2.5 LSB (LTC2635-12) Power-On-Reset to Zero-Scale/Mid-Scale/Hi-Z Low Noise: 0.75mVP-P 0.1Hz to 200kHz Guaranteed Monotonic Over –40°C to 125°C Automotive Temperature Range Selectable Internal or External Reference 2.7V to 5.5V Supply Range (LTC2635-L) Ultralow Crosstalk Between DACs (3nV•s) Low Power: 0.6mA at 3V Double-Buffered Data Latches Small 16-Pin 3mm × 3mm QFN and 10-Lead MSOP Packages APPLICATIONS n n n n n Mobile Communications Process Control and Industrial Automation Power Supply Margining Portable Equipment Automotive BLOCK DIAGRAM GND INTERNAL REFERENCE SWITCH VREF (REFLO) REGISTER REGISTER REGISTER VOUTA REGISTER VCC VOUTD REF Integral Nonlinerity 2 VCC = 3V INTERNAL REF . 1 INL (LSB) DAC A DAC D VREF REGISTER REGISTER REGISTER VOUTB REGISTER DAC B DAC C VREF VOUTC 0 –1 (LDAC) DECODE CA0 (CA1) (CA2) I2C ADDRESS DECODE POWER-ON RESET –2 0 1024 2048 CODE 3072 4095 2635 TA01 SCL I2C INTERFACE SDA ( ) QFN PACKAGE ONLY 2635 BD 2635f 1 LTC2635 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VCC) ................................... –0.3V to 6V SCL, SDA, REFLO, LDAC.............................. –0.3V to 6V VOUTA-D, CA0, CA1, CA2...... –0.3V to Min (VCC + 0.3V, 6V) REF .................................... –0.3V to Min (VCC + 0.3V, 6V) Operating Temperature Range LTC2635C ................................................ 0°C to 70°C LTC2635H (Note 3) ............................ –40°C to 125°C Maximum Junction Temperature .......................... 150°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) MS Package ...................................................... 300°C PIN CONFIGURATION TOP VIEW REFLO GND VCC NC 16 15 14 13 VOUTA 1 VOUTB 2 LDAC 3 CA0 4 5 SCL 6 NC 7 CA2 8 SDA 17 GND 12 VOUTD 11 VOUTC 10 REF 9 CA1 VCC 1 VOUTA 2 VOUTB 3 CA0 4 SCL 5 TOP VIEW 10 9 8 7 6 GND VOUTD VOUTC REF SDA 11 GND MSE PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 35°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB UD PACKAGE 16-LEAD (3mm × 3mm) PLASTIC QFN TJMAX = 150°C, θJA = 68°C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB 2635f 2 LTC2635 ORDER INFORMATION LTC2635 C UD –L Z 12 #TR PBF LEAD FREE DESIGNATOR PBF = Lead Free TAPE AND REEL TR = 2,500-Piece Tape and Reel RESOLUTION 12 = 12-Bit 10 = 10-Bit 8 = 8-Bit POWER-0N RESET MI = Reset to Mid-Scale in Internal Reference Mode MX = Reset to Mid-Scale in External Reference Mode (LMX Only) MO = Reset to Mid-Scale in Internal Reference Mode, DAC Outputs Hi-Z (LMO Only) Z = Reset to Zero-Scale in Internal Reference Mode FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE L = 2.5V H = 4.096V PACKAGE TYPE UD = 16-Pin QFN MSE = 10-Lead MSOP TEMPERATURE GRADE C = Commercial Temperature Range (0°C to 70°C) H = Automotive Temperature Range (–40°C to 125°C) PRODUCT PART NUMBER Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2635f 3 LTC2635 PRODUCT SELECTION GUIDE PART MARKING* PART NUMBER LTC2635-LMI12 LTC2635-LMI10 LTC2635-LMI8 LTC2635-LMX12 LTC2635-LMX10 LTC2635-LMX8 LTC2635-LZ12 LTC2635-LZ10 LTC2635-LZ8 LTC2635-LMO12** LTC2635-LMO10** LTC2635-LMO8** LTC2635-HMI12 LTC2635-HMI10 LTC2635-HMI8 LTC2635-HZ12 LTC2635-HZ10 LTC2635-HZ8 QFN LDZB LDZJ LDZR LDYZ LDZH LDZQ LDYY LDZG LDZP LFBT LFBV LFBW LDZF LDZN LDZV LDZC LDZK LDZS MSOP LTDZY LTFBG LTFBP LTDZX LTFBF LTFBN LTDZW LTFBD LTFBM LTFBX LTFBY LTFBZ LTFBC LTFBK LTFBS LTDZZ LTFBH LTFBQ VFS WITH INTERNAL REFERENCE 2.5V • (4095/4096) 2.5V • (1023/1024) 2.5V • (255/256) 2.5V • (4095/4096) 2.5V • (1023/1024) 2.5V • (255/256) 2.5V • (4095/4096) 2.5V • (1023/1024) 2.5V • (255/256) 2.5V • (4095/4096) 2.5V • (1023/1024) 2.5V • (255/256) 4.096V • (4095/4096) 4.096V • (1023/1024) 4.096V • (255/256) 4.096V • (4095/4096) 4.096V • (1023/1024) 4.096V • (255/256) POWER-ON RESET TO CODE Mid-Scale Mid-Scale Mid-Scale Mid-Scale Mid-Scale Mid-Scale Zero-Scale Zero-Scale Zero-Scale High Impedance High Impedance High Impedance Mid-Scale Mid-Scale Mid-Scale Zero-Scale Zero-Scale Zero-Scale POWER-ON REFERENCE MODE Internal Internal Internal External External External Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal RESOLUTION 12-Bit 10-Bit 8-Bit 12-Bit 10-Bit 8-Bit 12-Bit 10-Bit 8-Bit 12-Bit 10-Bit 8-Bit 12-Bit 10-Bit 8-Bit 12-Bit 10-Bit 8-Bit VCC 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V MAXIMUM INL ±2.5LSB ±1LSB ±0.5LSB ±2.5LSB ±1LSB ±0.5LSB ±2.5LSB ±1LSB ±0.5LSB ±2.5LSB ±1LSB ±0.5LSB ±2.5LSB ±1LSB ±0.5LSB ±2.5LSB ±1LSB ±0.5LSB *Above options are available in a 16-pin QFN package (LTC2635xUD) or 10-lead MSOP package (LTC2635xMSE). **Contact Linear Technology for other Hi-Z options. 2635f 4 LTC2635 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2635-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8/-LMO12/-LMO10/-LM08 (VFS = 2.5V) LTC2635-8 SYMBOL PARAMETER DC Performance Resolution Monotonicity DNL INL ZSE VOS VOSTC GE GETC Integral Nonlinearity Zero-Scale Error Offset Error VOS Temperature Coefficient Gain Error Gain Temperature Coefficient Load Regulation VCC = 3V, Internal Ref. (Note 4) VCC = 3V, Internal Ref. (Note 4) VCC = 3V, Internal Ref., Code=0 VCC = 3V, Internal Ref. (Note 5) VCC = 3V, Internal Ref. VCC = 3V, Internal Ref. VCC = 3V, Internal Ref. (Note 10) C-Grade H-Grade Internal Ref., Mid-Scale, VCC = 3V ± 10%, –5mA ≤ IOUT ≤ 5mA VCC = 5V±10%, –10mA ≤ IOUT ≤ 10mA Internal Ref., Mid-Scale, VCC = 3V ± 10%, –5mA ≤ IOUT ≤ 5mA VCC = 5V±10%, –10mA ≤ IOUT ≤ 10mA l l l l l l l l l ELECTRICAL CHARACTERISTICS CONDITIONS LTC2635-10 MIN 10 10 TYP MAX MIN 12 12 ±0.5 ±0.2 0.5 ±0.5 ±10 ±1 5 ±5 LTC2635-12 TYP MAX UNITS Bits Bits ±1 ±1 0.5 ±0.5 ±10 ±2.5 5 ±5 LSB LSB mV mV μV/°C ±0.8 %FSR ppm/°C ppm/°C 0.256 LSB/mA 0.256 LSB/mA MIN 8 8 TYP MAX Differential Nonlinearity VCC = 3V, Internal Ref. (Note 4) ±0.5 ±0.05 0.5 ±0.5 ±10 ±0.2 10 10 0.009 0.016 0.009 0.016 ±0.8 ±0.5 5 ±5 ±0.2 10 10 ±0.8 ±0.2 10 10 0.14 0.14 0.035 0.064 0.035 0.064 ROUT DC Output Impedance l l 0.09 0.09 0.156 0.156 0.09 0.09 0.156 0.156 0.09 0.09 0.156 0.156 Ω Ω SYMBOL VOUT PSR ISC PARAMETER DAC Output Span Power Supply Rejection Short Circuit Output Current (Note 6) Sinking Sourcing CONDITIONS External Reference Internal Reference VCC = 3V ± 10% or 5V ± 10% VFS = VCC = 5.5V Zero-Scale; VOUT Shorted to VCC Full-Scale; VOUT Shorted to GND l l l l l l l l l l l MIN TYP 0 to VREF 0 to 2.5 –80 27 –28 0.05 –0.001 MAX UNITS V V dB 48 –48 2 –0.1 5.5 mA mA μA μA V mA mA mA mA μA μA DAC ISD DAC Output Current in High Impedance Mode MO Options Only Sinking Sourcing Positive Supply Voltage Supply Current (Note 7) For Specified Performance VCC = 3V, VREF = 2.5V, External Reference VCC = 3V, Internal Reference VCC = 5V VREF = 2.5V, External Reference VCC = 5V, Internal Reference VCC = 5V, C-Grade VCC = 5V, H-Grade Power Supply VCC ICC 2.7 0.5 0.6 0.6 0.7 1 1 0.7 0.8 0.8 0.9 20 30 ISD Supply Current in Power-Down Mode (Note 7) 2635f 5 LTC2635 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2635-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8/-LMO12/-LMO10/-LM08 (VFS = 2.5V) SYMBOL Reference Input Input Voltage Range Resistance Capacitance IREF Reference Output Output Voltage Reference Temperature Coefficient Output Impedance Capacitive Load Driving Short Circuit Current Digital I/O VIL VIH VIL(CAn) VIH(CAn) RINH RINL RINF VOL tOF tSP IIN CIN CB CCAn Low Level Input Voltage (SDA and SCL) High Level Input Voltage (SDA and SCL) Low Level Input Voltage on CAn (n = 0, 1,2) High Level Input Voltage on CAn (n = 0, 1,2) Resistance from CAn (n = 0, 1,2) to VCC to Set CAn = VCC Resistance from CAn (n = 0, 1,2) to GND to Set CAn = GND Resistance from CAn (n = 0, 1,2) to VCC or GND to Set CAn = Float Low Level Output Voltage Output Fall Time Pulse Width of Spikes Suppressed by Input Filter Input Leakage I/O Pin Capacitance Capacitive Load for Each Bus Line External Capacitive Load on Address Pin CAn (n = 0, 1,2) 0.1VCC ≤ VIN ≤ 0.9VCC (Note 8) (Note 14) (Note 11) See Test Circuit 1 See Test Circuit 1 See Test Circuit 2 See Test Circuit 2 See Test Circuit 2 Sink Current = 3mA VO = VIH(MIN) to VO = VIL(MAX), CB = 10pF to 400pF (Note 12) l l l l l l l l l l l l l l l l l l ELECTRICAL CHARACTERISTICS PARAMETER CONDITIONS MIN 1 120 TYP MAX VCC UNITS V kΩ pF μA V ppm/°C kΩ μF mA 160 14 0.005 200 1.5 1.26 Reference Current, Power-Down Mode DAC Powered Down 1.24 1.25 ±10 0.5 10 VCC = 5.5V, REF Shorted to GND –0.5 0.7VCC 2.5 0.3VCC V V 0.15VCC 0.85VCC 10 10 2 0 20 + 0.1CB 0 0.4 250 50 1 10 400 10 V V kΩ kΩ MΩ V ns ns μA pF pF pF 2635f 6 LTC2635 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2635-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8/-LMO12/-LMO10/-LM08 (VFS = 2.5V) SYMBOL AC Performance tS Settling Time VCC = 3V (Note 9) ±0.39% (±1LSB at 8 Bits) ±0.098% (±1LSB at 10 Bits) ±0.024% (±1LSB at 12 Bits) 3.5 4.1 4.4 1 500 At Mid-Scale Transition 1 DAC Held at FS, 1 DAC Switched 0 to FS External Reference At f = 1kHz, External Reference At f = 10kHz, External Reference At f = 1kHz, Internal Reference At f = 10kHz, Internal Reference 0.1Hz to 10Hz, External Reference 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, External Reference 0.1Hz to 200kHz, Internal Reference CREF = 0.1μF 2.1 2.6 320 180 160 200 180 35 40 680 730 μs μs μs V/μs pF nV • s nV • s kHz nV/√Hz nV/√Hz nV/√Hz nV/√Hz μVP-P μVP-P μVP-P μVP-P PARAMETER CONDITIONS MIN TYP MAX UNITS ELECTRICAL CHARACTERISTICS Voltage Output Slew Rate Capacitive Load Driving Glitch Impulse DAC-to-DAC Crosstalk Multiplying Bandwidth en Output Voltage Noise Density Output Voltage Noise TIMING CHARACTERISTICS SYMBOL fSCL tHD(STA) tLOW tHIGH tSU(STA) tHD(DAT) tSU(DAT) tr tf tSU(STO) tBUF t1 t2 PARAMETER SCL Clock Frequency Hold Time (Repeated) Start Condition Low Period of the SCL Clock Pin High Period of the SCL Clock Pin The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V. (See Figure 1) (Note 13) LTC2635-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8/-LMO12/-LMO10/-LM08 (VFS = 2.5V) CONDITIONS l l l l l l l l l l l l l MIN 0 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 1.3 400 20 TYP MAX 400 UNITS kHz μs μs μs μs Set-Up Time for a Repeated Start Condition Data Hold Time Data Set-Up Time Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals Set-Up Time for Stop Condition Bus Free Time Between a Stop and Start Condition Falling Edge of 9th Clock of the 3rd Input Byte to LDAC High or Low Transition LDAC Low Pulse Width (Note 12) (Note 12) 0.9 300 300 μs ns ns ns μs μs ns ns 2635f 7 LTC2635 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2635-HMI12/-HMI10/-HMI8/-HZ12/-HZ10/-HZ8 (VFS = 4.096V) LTC2635-8 SYMBOL PARAMETER DC Performance Resolution Monotonicity DNL INL ZSE VOS VOSTC GE GETC Integral Nonlinearity Zero-Scale Error Offset Error VOS Temperature Coefficient Gain Error Gain Temperature Coefficient Load Regulation VCC = 5V, Internal Ref. (Note 4) VCC = 5V, Internal Ref. (Note 4) VCC = 5V, Internal Ref., Code=0 VCC = 5V, Internal Ref. (Note 5) VCC = 5V, Internal Reference VCC = 5V, Internal Reference VCC = 5V, Internal Ref. (Note 10) C-Grade H-Grade Internal Reference, Mid-Scale, VCC = 5V ± 10%, –10mA ≤ IOUT ≤ 10mA Internal Reference, Mid-Scale, VCC = 5V ± 10%, –10mA ≤ IOUT ≤ 10mA l l l l l l l l ELECTRICAL CHARACTERISTICS LTC2635-10 MIN 10 10 TYP MAX MIN 12 12 ±0.5 ±0.2 0.5 ±0.5 ±10 ±1 5 ±5 LTC2635-12 TYP MAX UNITS Bits Bits ±1 ±1 0.5 ±0.5 ±10 ±2.5 5 ±5 LSB LSB mV mV μV/°C ±0.8 %FSR ppm/°C ppm/°C 0.16 LSB/mA CONDITIONS MIN 8 8 TYP MAX Differential Nonlinearity VCC = 5V, Internal Ref. (Note 4) ±0.5 ±0.05 0.5 ±0.5 ±10 ±0.2 10 10 0.006 0.01 ±0.8 ±0.5 5 ±5 ±0.2 10 10 0.022 ±0.8 ±0.2 10 10 0.04 0.09 ROUT DC Output l 0.09 0.156 0.09 0.156 0.09 0.156 Ω SYMBOL VOUT PSR ISC PARAMETER DAC Output Span Power Supply Rejection Short Circuit Output Current (Note 6) Sinking Sourcing Positive Supply Voltage Supply Current (Note 7) Supply Current in Power-Down Mode (Note 7) CONDITIONS External Reference Internal Reference VCC = 5V±10% VFS = VCC = 5.5V Zero-Scale; VOUT Shorted to VCC Full-Scale; VOUT Shorted to GND For Specified Performance VCC = 3V, VREF = 4.096V, External Reference VCC = 3V, Internal Reference VCC = 5V, C-Grade VCC = 5V, H-Grade l l l l l l l MIN TYP 0 to VREF 0 to 4.096 –80 27 –28 MAX UNITS V V dB 48 –48 5.5 mA mA V mA mA μA μA Power Supply VCC ICC ISD 4.5 0.6 0.7 1 1 0.8 0.9 20 30 2635f 8 LTC2635 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2635-HMI12/-HMI10/-HMI8/-HZ12/-HZ10/-HZ8 (VFS = 4.096V) SYMBOL Reference Input Input Voltage Range Resistance Capacitance IREF Reference Output Output Voltage Reference Temperature Coefficient Output Impedance Capacitive Load Driving Short Circuit Current Digital I/O VIL VIH VIL(CAn) VIH(CAn) RINH RINL RINF VOL tOF tSP IIN CIN CB CCAn Low Level Input Voltage (SDA and SCL) High Level Input Voltage (SDA and SCL) Low Level Input Voltage on CAn (n = 0, 1,2) High Level Input Voltage on CAn (n = 0, 1,2) Resistance from CAn (n = 0, 1,2) to VCC to Set CAn = VCC Resistance from CAn (n = 0, 1,2) to GND to Set CAn = GND Resistance from CAn (n = 0, 1,2) to VCC or GND to Set CAn = Float Low Level Output Voltage Output Fall Time Pulse Width of Spikes Suppressed by Input Filter Input Leakage I/O Pin Capacitance Capacitive Load for Each Bus Line External Capacitive Load on Address Pin CAn (n=0, 1,2) 0.1VCC ≤ VIN ≤ 0.9VCC (Note 8) (Note 14) (Note 11) See Test Circuit 1 See Test Circuit 1 See Test Circuit 2 See Test Circuit 2 See Test Circuit 2 Sink Current = 3mA VO = VIH(MIN) to VO = VIL(MAX), CB = 10pF to 400pF (Note 12) l l l l l l l l l l l l l l l l l l ELECTRICAL CHARACTERISTICS PARAMETER CONDITIONS MIN 1 120 TYP MAX VCC UNITS V kΩ pF μA V ppm/°C kΩ μF mA 160 14 0.005 200 1.5 2.064 Reference Current, Power-Down Mode DAC Powered Down 2.032 2.048 ±10 0.5 10 VCC = 5.5V, REF Shorted to GND –0.5 0.7VCC 4 0.3VCC V V 0.15VCC 0.85VCC 10 10 2 0 20 + 0.1CB 0 0.4 250 50 1 10 400 10 V V kΩ kΩ MΩ V ns ns μA pF pF pF 2635f 9 LTC2635 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2635-HMI12/-HMI10/-HMI8/-HZ12/-HZ10/-HZ8 (VFS = 4.096V) SYMBOL AC Performance tS Settling Time VCC = 5V (Note 9) ±0.39% (±1LSB at 8 Bits) ±0.098% (±1LSB at 10 Bits) ±0.024% (±1LSB at 12 Bits) 3.9 4.3 5 1 500 At Mid-Scale Transition 1 DAC Held at FS, 1 DAC Switched 0 to FS External Reference At f = 1kHz, External Reference At f = 10kHz, External Reference At f = 1kHz, Internal Reference At f = 10kHz, Internal Reference 0.1Hz to 10Hz, External Reference 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, External Reference 0.1Hz to 200kHz, Internal Reference CREF = 0.1μF 3 3 320 180 160 250 230 35 50 680 750 μs μs μs V/μs pF nV • s nV • s kHz nV/√Hz nV/√Hz nV/√Hz nV/√Hz μVP-P μVP-P μVP-P μVP-P PARAMETER CONDITIONS MIN TYP MAX UNITS ELECTRICAL CHARACTERISTICS Voltage Output Slew Rate Capacitive Load Driving Glitch Impulse DAC-to-DAC Crosstalk Multiplying Bandwidth en Output Voltage Noise Density Output Voltage Noise The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V. (See Figure 1) (Note 13) LTC2635-HMI12/-HMI10/-HMI8/-HZ12/-HZ10/-HZ8 (VFS = 4.096V) SYMBOL fSCL tHD(STA) tLOW tHIGH tSU(STA) tHD(DAT) tSU(DAT) tr tf tSU(STO) tBUF t1 t2 PARAMETER SCL Clock Frequency Hold Time (Repeated) Start Condition Low Period of the SCL Clock Pin High Period of the SCL Clock Pin Set-Up Time for a Repeated Start Condition Data Hold Time Data Set-Up Time Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals Set-Up Time for Stop Condition Bus Free Time Between a Stop and Start Condition Falling Edge of 9th Clock of the 3rd Input Byte to LDAC High or Low Transition LDAC Low Pulse Width l TIMING CHARACTERISTICS CONDITIONS l l l l l l l l l l l l MIN 0 0.6 1.3 0.6 0.6 0 100 20+0.1CB 20+0.1CB 0.6 1.3 400 20 TYP MAX 400 UNITS kHz μs μs μs μs 0.9 300 300 μs ns ns ns μs μs ns ns (Note 12) (Note 12) 2635f 10 LTC2635 ELECTRICAL CHARACTERISTICS Note 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. All voltages are with respect to GND. Note 3. High temperatures degrade operating lifetimes. Operating lifetime is derated at temperatures greater than 105°C. Note 4. Linearity and monotonicity are defined from code kL to code 2N – 1, where N is the resolution and kL is given by kL = 0.016 • (2N/ VFS), rounded to the nearest whole code. For VFS = 2.5V and N = 12, kL = 26 and linearity is defined from code 26 to code 4,095. For VFS = 4.096V and N = 12, kL = 16 and linearity is defined from code 16 to code 4,095. Note 5. Inferred from measurement at code 16 (LTC2635-12), code 4 (LTC2635-10) or code 1 (LTC2635-8), and at full-scale. Note 6. This IC includes current limiting that is intended to protect the device during momentary overload conditions. Junction temperature can exceed the rated maximum during current limiting. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 7. Digital inputs at 0V or VCC. Note 8. Guaranteed by design and not production tested. Note 9. Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 100pF to GND. Note 10. Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. Note 11. Maximum VIH = VCC(MAX) + 0.5V. . Note 12. CB = capacitance of one bus line in pF Note 13. All values refer to VIH = VIH(MIN) and VIL = VIL(MAX) levels. Note 14. Minimum VIL exceeds the Absolute Maximum rating. This condition won’t damage the IC, but could degrade performance. 2635f 11 LTC2635 TYPICAL PERFORMANCE CHARACTERISTICS LTC2635-L12 (Internal Reference, VFS = 2.5V) Integral Nonlinearity (INL) 1.0 VCC = 3V 0.5 DNL (LSB) INL (LSB) 0.5 1.0 VCC = 3V TA = 25°C, unless otherwise noted. Differential Nonlinearity (DNL) 0 0 –0.5 –0.5 –1.0 0 1024 2048 CODE 3072 4095 2635 G01 –1.0 0 1024 2048 CODE 3072 4095 2635 G02 INL vs Temperature 1.0 VCC = 3V 0.5 INL (LSB) 0.5 DNL (LSB) 1.0 DNL vs Temperature 1.260 VCC = 3V 1.255 DNL (POS) 0 DNL (NEG) –0.5 VREF (V) 1.250 Reference Output Voltage vs Temperature VCC = 3V INL (POS) 0 –0.5 INL (NEG) 1.245 –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2635 G03 –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2635 G04 1.240 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2635 G05 Settling to ±1 LSB Rising SCL 5V/DIV 9th CLOCK OF 3rd DATA BYTE Settling to ±1 LSB Falling 3/4 SCALE TO 1/4 SCALE STEP , VCC = 3V VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 4.4μs VOUT 1 LSB/DIV 3.3μs VOUT 1 LSB/DIV 1/4 SCALE TO 3/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 2μs/DIV 2635 G06 SCL 5V/DIV 9th CLOCK OF 3rd DATA BYTE 2μs/DIV 2635 G07 2635f 12 LTC2635 TYPICAL PERFORMANCE CHARACTERISTICS LTC2635-H12 (Internal Reference, VFS = 4.096V) Integral Nonlinearity (INL) 1.0 VCC = 5V 0.5 DNL (LSB) INL (LSB) 0.5 1.0 VCC = 5V TA = 25°C, unless otherwise noted. Differential Nonlinearity (DNL) 0 0 –0.5 –0.5 –1.0 0 1024 2048 CODE 3072 4095 2635 G08 –1.0 0 1024 2048 CODE 3072 4095 2635 G09 INL vs Temperature 1.0 VCC = 5V INL (POS) DNL (LSB) 1.0 DNL vs Temperature 2.068 VCC = 5V 0.5 DNL (POS) 0 DNL (NEG) –0.5 VREF (V) 2.048 2.058 Reference Output Voltage vs Temperature VCC = 5V 0.5 INL (LSB) 0 INL (NEG) –0.5 2.038 –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2635 G10 –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2635 G11 2.028 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2635 G12 Settling to ±1 LSB Rising SCL 5V/DIV 9th CLOCK OF 3rd DATA BYTE VOUT 1 LSB/DIV 3.9μs Settling to ±1 LSB Falling 3/4 SCALE TO 1/4 SCALE STEP VCC = 5V, VFS = 4.095V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 5μs 9th CLOCK OF 3rd DATA BYTE VOUT 1 LSB/DIV 1/4 SCALE TO 3/4 SCALE STEP , VCC = 5V VFS = 4.095V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 2μs/DIV 2635 G13 SCL 5V/DIV 2μs/DIV 2635 G14 2635f 13 LTC2635 TYPICAL PERFORMANCE CHARACTERISTICS LTC2635-10 Integral Nonlinearity (INL) 1.0 VCC = 3V VFS = 2.5V INTERNAL REF 0.5 DNL (LSB) INL (LSB) 0.5 1.0 TA = 25°C, unless otherwise noted. Differential Nonlinearity (DNL) VCC = 3V VFS = 2.5V INTERNAL REF 0 0 –0.5 –0.5 –1.0 0 256 512 CODE 768 1023 2635 G15 –1.0 0 256 512 CODE 768 1023 2635 G16 LTC2635-8 Integral Nonlinearity (INL) 0.50 VCC = 3V VFS = 2.5V INTERNAL REF 0.50 Differential Nonlinearity (DNL) VCC = 3V VFS = 2.5V INTERNAL REF 0.25 DNL (LSB) 0 64 128 CODE 192 255 2635 G17 0.25 INL (LSB) 0 0 –0.25 –0.25 –0.50 –0.50 0 64 128 CODE 192 255 2635 G18 LTC2635 Load Regulation 10 8 6 4 ΔVOUT (mV) ΔVOUT (V) 2 0 –2 –4 –6 –8 –10 –30 –20 –10 INTERNAL REF. CODE = MID-SCALE 0 10 IOUT (mA) 20 30 2635 G19 Current Limiting 0.20 3 VCC = 5V (LTC2635-H) VCC = 5V (LTC2635-L) VCC = 3V (LTC2635-L) OFFSET ERROR (mV) INTERNAL REF. CODE = MID-SCALE –20 –10 0 10 IOUT (mA) 20 30 2635 G20 Offset Error vs Temperature VCC = 5V (LTC2635-H) VCC = 5V (LTC2635-L) VCC = 3V (LTC2635-L) 0.15 0.10 0.05 0 –0.05 –0.01 –0.15 2 1 0 –1 –2 –3 –50 –25 –0.20 –30 0 25 50 75 100 125 150 TEMPERATURE (°C) 2635 G21 2635f 14 LTC2635 TYPICAL PERFORMANCE CHARACTERISTICS LTC2635 Large-Signal Response Mid-Scale Glitch Impulse Power-On Reset Glitch LTC2635-L 9th CLOCK OF 3rd DATA BYTE TA = 25°C, unless otherwise noted. SCL 5V/DIV VOUT 0.5V/DIV VOUT 5mV/DIV VFS = VCC = 5V 1/4 SCALE to 3/4 SCALE 2μs/DIV 2635 G22 VCC 2V/DIV LTC2635-H12, VCC = 5V 3nV • s TYP VOUT 5mV/DIV LTC2635-L12, VCC = 3V 2.1nV • s TYP 2μs/DIV 2635 G23 ZERO SCALE 200μs/DIV 2635 G24 Headroom at Rails vs Output Current 5.0 4.5 4.0 3.5 VOUT (V) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 5V SINKING 3V (LTC2635-L) SINKING 1 2 3 456 IOUT (mA) 7 8 9 10 VOUT 0.5V/DIV 3V (LTC2635-L) SOURCING SCL 5V/DIV 5V SOURCING Exiting Power-Down to Mid-Scale VCC = 5V INTERNAL REFERENCE 9th CLOCK OF 3rd DATA BYTE Power-On Reset to Mid-Scale VCC 2V/DIV LTC2635-H DACs A-C IN POWER-DOWN MODE LTC2635-H 5μs/DIV 2635 G26 VOUT 0.5V/DIV LTC2635-L 200μs/DIV 2635 G27 2635 G25 Supply Current vs Logic Voltage 1.6 1.4 1.2 ICC(mA) VCC = 5V 1.0 0.8 0.6 0.4 VCC = 3V (LTC2635-L) VOUT 500mV/DIV SWEEP SDA, SCL BETWEEN 0V AND VCC SCL 5V/DIV Exiting Power-Down for Hi-Z Option 9th CLOCK OF 3rd DATA BYTE DAC OUTPUT SET TO MID-SCALE HIGH-IMPEDANCE (POWER-DOWN) MODE 0 1 2 3 4 5 2635 G28 2μs/DIV LTC2635-LMO, VCC = 3V DAC OUTPUT DRIVEN BY 1V SOURCE THROUGH 15k RESISTOR 2635 G29 LOGIC VOLTAGE (V) 2635f 15 LTC2635 TYPICAL PERFORMANCE CHARACTERISTICS LTC2635 Mulitplying Bandwidth 2 0 NOISE VOLTAGE (nV/√Hz) –2 –4 –6 dB –8 –10 –12 –14 –16 –18 1k VCC = 5V VREF(DC) = 2V VREF(AC) = 0.2VP-P CODE = FULL-SCALE 10k 100k FREQUENCY (Hz) 1M 2635 G31 TA = 25°C, unless otherwise noted. Noise Voltage vs Frequency 500 VCC = 5V CODE = MID-SCALE INTERNAL REF GAIN ERROR (%FSR) 1.0 Gain Error vs Reference Input VCC = 5.5V 0.8 GAIN ERROR OF 4 CHANNELS 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 400 300 LTC2635-H 200 LTC2635-L 100 0 100 –1.0 1k 10k 100k FREQUENCY (Hz) 1M 2634 G32 1 1.5 2 2.5 3 3.5 4 4.5 REFERENCE VOLTAGE (V) 5 5.5 2635 G33 0.1Hz to 10Hz Voltage Noise VCC = 5V, VFS = 2.5V CODE = MID-SCALE INTERNAL REF SCL 5V/DIV 1 DAC SWITCH 0-FS 2V/DIV DAC-to-DAC Crosstalk (Dynamic) 1.0 9th CLOCK OF 3rd DATA BYTE GAIN ERROR (%FSR) LTC2635-H12, VCC = 5V 3nV • s TYPICAL CREF = 0.1μF 2μs/DIV 2635 G34 2635 G35 Gain Error vs Temperature 0.5 10μV/DIV 0 VOUT 2mV/DIV –0.5 1s/DIV –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2635 G36 2635f 16 LTC2635 PIN FUNCTIONS (MSOP/QFN) VCC (Pin 1/Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V (LTC2635-L) or 4.5V ≤ VCC ≤ 5.5V (LTC2635-H). Bypass to GND with a 0.1μF capacitor. VOUTA to VOUTD (Pins 2, 3, 8, 9/Pins 1, 2, 11, 12): DAC Analog Voltage Outputs. LDAC (Pin 3, QFN only): Asynchronous DAC Update. A falling edge on this input after four bytes (slave address byte plus three data bytes) have been written into the part immediately updates the DAC registers with the contents of the input registers (similar to a software update). A low on this input without a complete 32-bit (four bytes including the slave address) data write transfer to the part does not update the DAC output. A low on the LDAC pin powers up the DACs. A software power down command is ignored if LDAC is low. CA0 (Pin 4/Pin 4): Chip Address Bit 0. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (see Tables 1 and 2). SCL (Pin 5/Pin 5): Serial Clock Input Pin. Data is shifted into the SDA pin at the rising edges of the clock. This high-impedance pin requires a pull-up resistor or current source to VCC. SDA (Pin 6/Pin 8): Serial Data Bidirectional Pin. Data is shifted into the SDA pin and acknowledged by the SDA pin. This pin is high impedance while data is shifted in. Open drain N-channel output during acknowledgment. SDA requires a pull-up resistor or current source to VCC. REF (Pin 7/Pin 10): Reference Voltage Input or Output. When External Reference mode is selected, REF is an input (1V ≤ VREF ≤ VCC) where the voltage supplied sets the full-scale DAC output voltage. When Internal Reference is selected, the 10ppm/°C 1.25V (LTC2635-L) or 2.048V (LTC2635-H) internal reference (half full-scale) is available at the pin. This output may be bypassed to GND with up to 10μF, and must be buffered when driving an external DC load current. CA2 (Pin 7, QFN only): Chip Address Bit 2. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (see Table 1). CA1 (Pin 9, QFN only): Chip Address Bit 1. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (see Table 1). GND (Pin 10, Exposed Pad Pin 11/Pin 14, Exposed Pad Pin 17): Ground. Must be soldered to PCB ground. REFLO (Pin 13, QFN only): Reference Low Pin. The voltage at this pin sets the zero-scale voltage of all DACs. This pin must be tied to GND. 2635f 17 LTC2635 BLOCK DIAGRAM GND INTERNAL REFERENCE SWITCH VREF (REFLO) REGISTER REGISTER REGISTER VOUTA REGISTER VCC VOUTD REF DAC A DAC D VREF REGISTER REGISTER REGISTER VOUTB REGISTER DAC B DAC C VREF VOUTC (LDAC) DECODE CA0 (CA1) (CA2) I2C ADDRESS DECODE POWER-ON RESET SCL I2C INTERFACE SDA ( ) QFN PACKAGE ONLY 2635 BD 2635f 18 LTC2635 TEST CIRCUITS Test Circuits for I2C Digital I/O (See Electrical Characteristics) Test Circuit 1 Test Circuit 2 VDD 100Ω CAn VIH(CAn)/VIL(CAn) 2635 TC01 2635 TC02 RINH/RINL/RINF CAn GND TIMING DIAGRAMS SDA tf SCL tHD(STA) S tHD(DAT) tHIGH Sr tSU(STA) tSU(STO) P S 2635 F01 tSU(DAT) tLOW tr tr tHD(STA) tSP tr tBUF ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS Figure 1. I2C Timing 2635f 19 LTC2635 TIMING DIAGRAMS SLAVE ADDRESS START SDA SCL A6 1 A5 2 A4 3 A3 4 A2 5 A1 6 A0 7 W ACK C3 8 9 1 C2 2 1ST DATA BYTE C1 C0 3 4 A3 5 A2 6 A1 7 A0 ACK 8 9 1 2 2ND DATA BYTE ACK 3 4 5 6 7 8 9 1 2 3RD DATA BYTE X 3 4 5 X 6 X 7 X ACK 8 9 t1 t2 LDAC 2635 F02a Figure 2a. Typical LTC2635 Write Transaction 9TH CLOCK OF 3RD DATA BYTE SCL t1 LDAC 2635 F02b Figure 2b. LTC2635 LDAC Timing (QFN Package Only) 2635f 20 LTC2635 OPERATION The LTC2635 is a family of quad voltage output DACs in 16-pin QFN and 10-lead MSOP packages. Each DAC can operate rail-to-rail using an external reference, or with its full-scale voltage set by an integrated reference. Eighteen combinations of accuracy (12-, 10-, and 8-bit), power-on reset value (zero-scale, mid-scale in internal reference mode, or mid-scale in external reference mode), DAC power-down output load (high impedance or 200kΩ), and full-scale voltage (2.5V or 4.096V) are available. The LTC2635 is controlled using a 2-wire I2C interface. Power-On Reset The LTC2635-HZ/-LZ clear the output to zero-scale when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2635 contains circuitry to reduce the power-on glitch: the analog output typically rises less than 5mV above zeroscale during power on. In general, the glitch amplitude decreases as the power supply ramp time is increased. See “Power-On Reset Glitch” in the Typical Performance Characteristics section. The LTC2635-HMI/-LMI/-LMX provide an alternative reset, setting the output to mid-scale when power is first applied. The LTC2635-LMI and LTC2635-HMI power up in internal reference mode, with the output set to a mid-scale voltage of 1.25V and 2.048V, respectively. The LTC2635-LMX power-up in external reference mode, with the output set to mid-scale of the external reference. The LTC2635-LMO powers up in in-ternal reference mode with all the DAC channels placed in the high-impedance state (powered-down). Input and DAC registers are set to the mid-scale code, and only the internal reference is powered up, causing supply current to be typically 100μA upon power up. Default reference mode selection is described in the Reference Modes section. Power Supply Sequencing The voltage at REF (Pin 10 – QFN, Pin 7 – MSOP) must be kept within the range –0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turnon and turn-off sequences, when the voltage at VCC is in transition. Transfer Function The digital-to-analog transfer function is VOUT(IDEAL) = k 2N ( VREF – VREFLO ) + VREFLO where k is the decimal equivalent of the binary DAC input code, N is the resolution, and VREF is either 2.5V (LTC2635LMI/-LMX/-LMO/-LZ) or 4.096V (LTC2635-HMI/-HZ) when in Internal Reference mode, and the voltage at REF when in External Reference mode. I2C Serial Interface The LTC2635 communicates with a host using the standard 2-wire I2C interface. The timing diagrams (Figures 1 and 2) show the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The value of these pull-up resistors is dependent on the power supply and can be obtained from the I2C specifications. For an I2C bus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pF. The LTC2635 is a receive-only (slave) device. The master can write to the LTC2635. The LTC2635 will not acknowledge (NAK) a read request from the master. START (S) and STOP (P) Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a communication to a slave device by transmitting a START condition. A START condition is generated by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition. A STOP condition is generated by transitioning SDA from low to high while SCL is high. The bus is then free for communication with another I2C device. 2635f 21 LTC2635 OPERATION Acknowledge The Acknowledge (ACK) signal is used for handshaking between the master and the slave. An ACK (active LOW) generated by the slave lets the master know that the latest byte of information was properly received. The ACK related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the ACK clock pulse. The slave-receiver must pull down the SDA bus line during the ACK clock pulse so that it remains a stable LOW during the HIGH period of this clock pulse. The LTC2635 responds to a write by a master in this manner but does not acknowledge a read operation; in that case, SDA is retained HIGH during the period of the ACK clock pulse. Chip Address The state of pins CA0, CA1 and CA2 (CA1 and CA2 are only available on the QFN package) determines the slave address of the part. These pins can be each set to any one of three states: VCC, GND or float. This results in 27 (QFN Package) or 3 (MSOP Package) selectable addresses for the part. The slave address assignments are shown in Tables 1 and 2. In addition to the address selected by the address pins, the part also responds to a global address. This address allows a common write to all LTC2635 parts to be accomplished using one 3-byte write transaction on the I2C bus. The global address, listed at the end of Tables 1 and 2, is a 7-bit hardwired address not selectable by CA0, CA1 or CA2. If another address is required, please consult the factory. The maximum capacitive load allowed on the address pins (CA0, CA1 and CA2) is 10pF, as these pins are driven during address detection to determine if they are floating. Table 1. Slave Address Map (QFN Package) CA2 GND GND GND GND GND GND GND GND GND FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT VCC VCC VCC VCC VCC VCC VCC VCC VCC CA1 GND GND GND FLOAT FLOAT VCC VCC VCC GND GND GND FLOAT FLOAT VCC VCC VCC GND GND GND FLOAT FLOAT VCC VCC VCC CA0 GND FLOAT VCC GND VCC GND FLOAT VCC GND FLOAT VCC GND VCC GND FLOAT VCC GND FLOAT VCC GND VCC GND FLOAT VCC A6 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A5 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A4 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT GLOBAL ADDRESS Table 2. Slave Address Map (MSOP Package) CA0 GND FLOAT VCC GLOBAL ADDRESS A6 0 0 0 1 A5 0 0 0 1 A4 1 1 1 1 A3 0 0 0 0 A2 0 0 0 0 A1 0 0 1 1 A0 0 1 0 1 2635f 22 LTC2635 OPERATION Write Word Protocol The master initiates communication with the LTC2635 with a START condition and a 7-bit slave address followed by the Write bit (W) = 0. The LTC2635 acknowledges by pulling the SDA pin low at the 9th clock if the 7-bit slave address matches the address of the part (set by CA0, CA1 or CA2) or the global address. The master then transmits three bytes of data. The LTC2635 acknowledges each byte of data by pulling the SDA line low at the 9th clock of each data byte transmission. After receiving three complete bytes of data, the LTC2635 executes the command specified in the 24-bit input word. If more than three data bytes are transmitted after a valid 7-bit slave address, the LTC2635 does not acknowledge (NAK) the extra bytes of data (SDA is high during the 9th clock). The format of the three data bytes is shown in Figure 3. The first byte of the input word consists of the 4-bit command, followed by the 4-bit DAC address. The next two bytes contain the 16-bit data word, which consists of the 12-, 10- or 8-bit input code, MSB to LSB, followed by 4, 6 or 8 don’t-care bits (LTC2635-12, -10 and -8, respectively). A typical LTC2635 write transaction is shown in Figure 4. The command bit assignments (C3-C0) and address (A3A0) assignments are shown in Tables 3 and 4. The first four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register. In an update operation, the data word is copied from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 12-, 10-, or 8-bit input code, and is converted to an analog voltage at the DAC output. Write to and Update combines the first two commands. The Update operation also powers up the DAC if it had been in power-down mode. The data path and registers are shown in the Block Diagram. Table 3. Command Codes COMMAND* C3 0 0 0 0 0 0 0 0 1 C2 0 0 0 0 1 1 1 1 1 C1 0 0 1 1 0 0 1 1 1 C0 0 1 0 1 0 1 0 1 1 Write to Input Register n Update (Power Up) DAC Register n Write to Input Register n, Update (Power Up) All Write to and Update (Power Up) DAC Register n Power Down n Power Down Chip (All DAC’s and Reference) Select Internal Reference (Power Up Reference) Select External Reference (Power Down Internal Reference) No Operation *Command codes not shown are reserved and should not be used. Table 4. Address Codes ADDRESS (n)* A3 0 0 0 0 1 A2 0 0 0 0 1 A1 0 0 1 1 1 A0 0 1 0 1 1 DAC A DAC B DAC C DAC D ALL DACs * Address codes not shown are reserved and should not be used. Reference Modes For applications where an accurate external reference is either not available, or not desirable due to limited space, the LTC2635 has a user-selectable, integrated reference. The integrated reference voltage is internally amplified by 2x to provide the full-scale DAC output voltage range. The LTC2635-LMI/-LMX/-LMO/-LZ provides a full-scale output of 2.5V. The LTC2635-HMI/-HZ provides a full-scale output of 4.096V. The internal reference can be useful in applications where the supply voltage is poorly regulated. Internal Reference mode can be selected by using command 0110b, and is the power-on default for LTC2635-HZ/-LZ, as well as for LTC2635-HMI/-LMI/-LMO. 2635f 23 LTC2635 OPERATION Write Word Protocol for LTC2635 S SLAVE ADDRESS W ACK 1ST DATA BYTE ACK 2ND DATA BYTE ACK 3RD DATA BYTE ACK P INPUT WORD Input Word (LTC2635-12) C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X 1ST DATA BYTE Input Word (LTC2635-10) C3 C2 C1 C0 A3 A2 A1 A0 D9 D8 D7 2ND DATA BYTE 3RD DATA BYTE D6 D5 D4 D3 D2 D1 D0 X X X X X X 1ST DATA BYTE Input Word (LTC2635-8) C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 2ND DATA BYTE 3RD DATA BYTE D4 D3 D2 D1 D0 X X X X X X X X 1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE 2635 F03 Figure 3. Command and Data Input Format The 10ppm/°C, 1.25V (LTC2635-LMI/-LMX/-LMO/-LZ) or 2.048V (LTC2635-HMI/-HZ) internal reference is available at the REF pin. Adding bypass capacitance to the REF pin will improve noise performance; and up to 10μF can be driven without oscillation. This output must be buffered when driving an external DC load current. Alternatively, the DAC can operate in External Reference mode using command 0111b. In this mode, an input voltage supplied externally to the REF pin provides the reference (1V ≤ VREF ≤ VCC) and the supply current is reduced. The external reference voltage supplied sets the full-scale DAC output voltage. External Reference mode is the power-on default for LTC2635-LMX. The reference mode of LTC2635-HZ/-LZ/-HMI/-LMI/-LMO (Internal Reference power-on default), can be changed by software command after power up. The same is true for LTC2635-LMX (External Reference power-on default). Power-Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than four DAC outputs are needed. When in power-down, the buffer amplifiers, bias circuits, and integrated reference circuits are disabled, and draw essentially zero current. The DAC amplifier outputs are put into a high-impedance state, and the output pins are passively pulled to ground through individual 200k resistors (LTC2635-LMI/-LMX/ -LMO/-LZ/-HMI/-HZ). For the LTC2635-LMO options, the output pins are not passively pulled to ground, but are also placed in a high-impedance state (open-circuited state) during power-down, typically drawing less than 0.1μA. The LTC2635-LMO options power-up with all DAC outputs in this high-impedance state. They remain that way until given a software or hardware update command. For all LTC2635 options, input- and DAC-register contents are not disturbed during power-down. 2635f 24 LTC2635 OPERATION Any channel or combination of channels can be put into power-down mode by using command 0100b in combination with the appropriate DAC address, (n). The supply current is reduced approximately 20% for each DAC powered down. The integrated reference is automatically powered down when external reference is selected using command 0111b. In addition, all the DAC channels and the integrated reference together can be put into power-down mode using Power Down Chip command 0101b. When the integrated reference is in power-down mode, the REF pin becomes high impedance (typically > 1GΩ). For all powerdown commands the 16-bit data word is ignored. Normal operation resumes after executing any command that includes a DAC update, (as shown in Table 1) or pulling the asynchronous LDAC pin low (QFN package only). The selected DAC is powered up as its voltage output is updated. When a DAC which is in a powered-down state is powered up and updated, normal settling is delayed. If less than four DACs are in a powered-down state prior to the update command, the power-up delay time is 10μs. However, if all four DACs and the integrated reference are powered down, then the main bias generation circuit block has been automatically shut down in addition to the DAC amplifiers and reference buffers. In this case, the power up delay time is 12μs. The power-up of the integrated reference depends on the command that powered it down. If the reference is powered down using the Select External Reference Command (0111b), then it can only be powered back up using Select Internal Reference Command (0110b). However, if the reference was powered down using Power Down Chip Command (0101b), then in addition to Select Internal Reference Command (0110b), any command (in software or using the LDAC pin) that powers up the DACs will also power up the integrated reference. Voltage Output The LTC2635’s integrated rail-to-rail amplifier has guaranteed load regulation when sourcing or sinking up to 10mA at 5V, and 5mA at 3V. Load regulation is a measure of the amplifier’s ability to maintain the rated voltage accuracy over a wide range of load current. The measured change in output voltage per change in forced load current is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to Ω. The amplifier’s DC output impedance is 0.1Ω when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 50Ω typical channel resistance of the output devices (e.g., when sinking 1mA, the minimum output voltage is 50Ω • 1mA, or 50mV). See the graph Headroom at Rails vs. Output Current in the Typical Performance Characteristics section. The amplifier is stable driving capacitive loads of up to 500pF. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog output of the DAC cannot go below ground, it may limit for the lowest codes as shown in Figure 5b. Similarly, limiting can occur near full-scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC, as shown in Figure 5c. No full-scale limiting can occur if VREF is less than VCC – FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. Board Layout The PC board should have separate areas for the analog and digital sections of the circuit. A single, solid ground plane should be used, with analog and digital signals carefully routed over separate areas of the plane. This keeps digital signals away from sensitive analog signals and minimizes the interaction between digital ground currents and the analog section of the ground plane. The resistance from the LTC2635 GND pin to the ground plane should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.1Ω). Note that the LTC2635 is no more susceptible to 2635f 25 LTC2635 OPERATION this effect than any other parts of this type; on the contrary, it allows layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. Another technique for minimizing errors is to use a separate power ground return trace on another board layer. The trace should run between the point where the power supply is connected to the board and the DAC ground pin. Thus the DAC ground pin becomes the common point for analog ground, digital ground, and power ground. When the LTC2635 is sinking large currents, this current flows out the ground pin and directly to the power ground trace without affecting the analog ground plane voltage. It is sometimes necessary to interrupt the ground plane to confine digital ground currents to the digital portion of the plane. When doing this, make the gap in the plane only as long as it needs to be to serve its purpose and ensure that no traces cross over the gap. 2635f 26 LTC2635 OPERATION SLAVE ADDRESS A6 START SDA SCL VOUT X = DON’T CARE A6 1 A5 2 A4 3 A3 4 A2 5 A1 6 A0 7 W ACK C3 8 9 1 C2 2 A5 A4 A3 A2 A1 A0 W C3 C2 COMMAND/ADDRESS C1 C0 C1 C0 3 4 A3 A3 5 A2 A2 6 A1 A1 7 A0 A0 ACK 8 9 1 2 3 MS DATA D11 D10 D9 D8 D7 D6 D5 D4 ACK 4 5 6 7 8 9 1 2 3 D3 D2 LS DATA D1 D0 X X X X STOP ACK 4 5 6 7 8 9 FULL-SCALE VOLTAGE ZERO-SCALE VOLTAGE 2635 F04 Figure 4. Typical LTC2635 Input Waveform—Programming DAC Output for Full-Scale 2635f 27 LTC2635 OPERATION POSITIVE FSE VREF = VCC VREF = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE OUTPUT VOLTAGE 0V 0 2,048 INPUT CODE (a) INPUT CODE (b) 4,095 (c) 2635 F05 0V NEGATIVE OFFSET Figure 5. Effects of Rail-to-Rail On a DAC Transfer Curve (Shown for 12 Bits). (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero (c) Effect of Positive Full-Scale Error for Codes Near Full-Scale 2635f 28 LTC2635 APPLICATION INFORMATION Voltage Margining Application with LTC3850 (1.2V ±5%) –LTC2635– LMO Option Only VIN 6.5V TO 14V 0.1μF 2.2Ω 0.1μF VIN ILIM 10k BOOST1 FREQ SW1 1nF 3.32k LTC3850EUF BG1 PGND ITH1 SENSE+ RUN1 SENSE– VFB1 1nF 10Ω 10Ω 2.2μH PGOOD INTVCC TG1 0.1μF 100k 4.7μF 0.008Ω VOUT 1.2V ±5% 1nF 100pF 10k 500kHz MODE/PLLIN TK/SS1 10nF SGND 15pF 63.4k 5V VOUT 1.26V 1.2V 1.14V DAC D OUTPUT 0.5V 0.8V 1.1V 7 DAC CODE 819 1311 1802 0.1μF 2 REF LTC2635CMSE-LMOI2 DAC A DAC D 9 10k 15k 0.22μF 3 DAC B DAC C 8 VCC 1 20k 2635 TA02 TO I2C BUS 4 5 6 CAO SCL SDA GND 10 2635 TA02 2635f 29 LTC2635 PACKAGE DESCRIPTION UD Package 16-Lead Plastic QFN (3mm × 3mm) (Reference LTC DWG # 05-08-1691) 0.70 0.05 3.50 0.05 2.10 1.45 0.05 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.75 0.05 BOTTOM VIEW—EXPOSED PAD R = 0.115 TYP 15 16 0.40 1 1.45 0.10 (4-SIDES) 2 0.10 PIN 1 NOTCH R = 0.20 TYP OR 0.25 45 CHAMFER 3.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) (UD16) QFN 0904 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 0.05 0.50 BSC 2635f 30 LTC2635 PACKAGE DESCRIPTION MSE Package 10-Lead Plastic MSOP Exposed Die Pad , (Reference LTC DWG # 05-08-1664 Rev C) BOTTOM VIEW OF EXPOSED PAD OPTION 2.794 (.110 0.102 .004) 0.889 (.035 0.127 .005) 1 2.06 0.102 (.081 .004) 1.83 0.102 (.072 .004) 0.29 REF 5.23 (.206) MIN 2.083 (.082 0.102 3.20 – 3.45 .004) (.126 – .136) 0.05 REF DETAIL “B” CORNER TAIL IS PART OF DETAIL “B” THE LEADFRAME FEATURE. FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 0.497 0.076 (.0196 .003) REF 10 0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 3.00 0.102 (.118 .004) (NOTE 3) 10 9 8 7 6 4.90 0.152 (.193 .006) 0.254 (.010) GAUGE PLANE 0.53 0.152 (.021 .006) DETAIL “A” 0.18 (.007) SEATING PLANE 1.10 (.043) MAX DETAIL “A” 0 – 6 TYP 12345 3.00 0.102 (.118 .004) (NOTE 4) 0.86 (.034) REF 0.17 – 0.27 (.007 – .011) TYP NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.50 (.0197) BSC 0.1016 (.004 0.0508 .002) MSOP (MSE) 0908 REV C 2635f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC2635 RELATED PARTS PART NUMBER LTC1660/LTC1665 LTC1664 LTC1821 LTC2600/LTC2610/ LTC2620 LTC2601/LTC2611/ LTC2621 LTC2602/LTC2612/ LTC2622 LTC2604/LTC2614/ LTC2624 LTC2605/LTC2615/ LTC2625 LTC2606/LTC2616/ TC2626 LTC2609/LTC2619/ LTC2629 LTC2630 LTC2631 LTC2634 LTC2636 LTC2637 LTC2640 DESCRIPTION Octal 10-/8-Bit VOUT DACs in 16-Pin Narrow SSOP COMMENTS VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output Quad 10-Bit VOUT DAC in 16-Pin Narrow VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output SSOP Parallel 16-Bit Voltage Output DAC Octal 16-/14-/12-Bit VOUT DACs in 16-Lead Narrow SSOP Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP Precision 16-Bit Settling in 2μs for 10V Step 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface Octal 16-/14-/12-Bit VOUT DACs with I2C 250μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, I2C Interface Interface Single 16-/14-/12-Bit VOUT DACs with I2C Interface 270μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, I2C Interface Quad 16-/14-/12-Bit VOUT DACs with I2C 250μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output with Separate VREF Pins Interface for Each DAC Single 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference in SC70 180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, Rail-to-Rail Output, SPI Serial Interface Single 12-/10-/8-Bit I2C VOUT DACs with 180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, 10ppm/°C Reference in ThinSOT™ Rail-to-Rail Output, I2C Interface Quad 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference Octal 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference Octal 12-/10-/8-Bit I2C VOUT DACs with 10ppm/°C Reference Single 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference in ThinSOT 125μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail Output, SPI Interface 125μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail Output, SPI Interface 125μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail Output, I2C Interface 180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail Output, SPI Interface 2635f 32 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 1109 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2009