LTC2637-HMX10

FEATURES n n n n n n n n n n n LTC2637 Octal 12-/10-/8-Bit I2C VOUT DACs with 10ppm/°C Reference DESCRIPTION The LTC®2637 is a family of octal 12-, 10-, and 8-bit voltage-output DACs with an integrated, high-accuracy, low-drift 10ppm/°C reference in 14-lead DFN and 16-lead MSOP packages. It has a rail-to-rail output buffer and is guaranteed monotonic. The LTC2637-L has a full-scale output of 2.5V, and operates from a single 2.7V to 5.5V supply. The LTC2637-H has a full-scale output of 4.096V, and operates from a 4.5V to 5.5V supply. Each DAC can also operate with an external reference, which sets the DAC full-scale output to the external reference voltage. These DACs communicate via a 2-wire I2C-compatible serial interface. The LTC2637 operates in both the standard mode (clock rate of 100kHz) and the fast mode (clock rate of 400kHz). The LTC2637 incorporates a power-on reset circuit. Options are available for reset to zero-scale or reset to mid-scale in internal reference mode, or reset to mid-scale in external reference mode after power-up. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5396245, 5859606, 6891433, 6937178, 7414561. Integrated Precision Reference: 2.5V Full-Scale 10ppm/°C (LTC2637-L) 4.096V Full-Scale 10ppm/°C (LTC2637-H) Maximum INL Error: 2.5LSB (LTC2637-12) Low Noise: 0.75mVP-P 0.1Hz to 200KHz Guaranteed Monotonic Over –40°C to 125°C Temperature Range Selectable Internal or External Reference 2.7V to 5.5V Supply Range (LTC2637-L) Ultralow Crosstalk Between DACs ( 4V requires VCC slew rates to be no greater than 110mV/ms. Note 4: Linearity and monotonicity are defined from code kL to code 2N–1, where N is the resolution and kL is given by kL = 0.016•(2N/ VFS), rounded to the nearest whole code. For VFS = 2.5V and N = 12, kL = 26 and linearity is defined from code 26 to code 4,095. For VFS = 4.096V and N = 12, kL = 16 and linearity is defined from code 16 to code 4,095. Note 5: Inferred from measurement at code 16 (LTC2637-12), code 4 (LTC2637-10) or code 1 (LTC2637-8), and at full-scale. Note 6: This IC includes current limiting that is intended to protect the device during momentary overload conditions. Junction temperature can exceed the rated maximum during current limiting. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 7: Digital inputs at 0V or VCC. Note 8: Guaranteed by design and not production tested. Note 9: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 100pF to GND. Note 10: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. Note 11: Maximum VIH = VCC(MAX) + 0.5V. Note 12: CB = Capacitance of one bus line in pF. Note 13: All values refer to VIH = VIN(MIN) and VIL = VIL(MAX) levels. Note 14: Minimum VIL exceeds Absolute Maximum rating. This condition won’t damage the IC, but could degrade performance. Note 15: Thermal resistance of MSOP package limits IOUT to –5mA ≤ IOUT ≤ 5mA for H-grade MSOP parts and VCC = 5V ±10%. 2637fb 10 LTC2637 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2637-L12 (Internal Reference, VFS = 2.5V) Integral Nonlinearity (INL) 1.0 VCC = 3V 0.5 DNL (LSB) INL (LSB) 0.5 1.0 VCC = 3V Differential Nonlinearity (DNL) 0 0 –0.5 –0.5 –1.0 0 1024 2048 CODE 3072 4095 2637 G01 –1.0 0 1024 2048 CODE 3072 4095 2637 G02 INL vs Temperature 1.0 VCC = 3V 0.5 INL (LSB) INL (POS) DNL (LSB) 0.5 1.0 DNL vs Temperature 1.260 VCC = 3V 1.255 VREF (V) DNL (POS) 0 DNL (NEG) –0.5 1.245 Reference Output Voltage vs Temperature VCC = 3V 0 INL (NEG) –0.5 1.250 –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2637 G03 –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2637 G04 1.240 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2637 G05 Settling to ±1LSB Rising 9TH CLOCK OF 3RD DATA BYTE Settling to ±1LSB Falling 3/4 SCALE TO 1/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 4.5μs SCL 5V/DIV VOUT 1LSB/DIV 3.6μs VOUT 1LSB/DIV 1/4 SCALE TO 3/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 2μs/DIV 2637 G06 SCL 5V/DIV 9TH CLOCK OF 3RD DATA BYTE 2μs/DIV 2637 G07 2637fb 11 LTC2637 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2637-H12 (Internal Reference, VFS = 4.096V) Integral Nonlinearity (INL) 1.0 VCC = 5V 0.5 DNL (LSB) INL (LSB) 0.5 1.0 VCC = 5V Differential Nonlinearity (DNL) 0 0 –0.5 –0.5 –1.0 0 1024 2048 CODE 3072 4095 2637 G08 –1.0 0 1024 2048 CODE 3072 4095 2637 G09 INL vs Temperature 1.0 VCC = 5V 0.5 INL (LSB) INL (POS) DNL (LSB) 0.5 1.0 DNL vs Temperature 2.068 VCC = 5V 2.058 VREF (V) DNL (POS) 0 DNL (NEG) –0.5 2.038 Reference Output Voltage vs Temperature VCC = 5V 0 INL (NEG) –0.5 2.048 –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2637 G10 –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2637 G11 2.028 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2637 G12 Settling to ±1LSB Rising SCL 5V/DIV 9TH CLOCK OF 3RD DATA BYTE VOUT 1LSB/DIV Settling to ±1LSB Falling 3/4 SCALE TO 1/4 SCALE STEP VCC = 5V, VFS = 4.095V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 5μs 4.1μs SCL 5V/DIV 9TH CLOCK OF 3RD DATA BYTE VOUT 1LSB/DIV 1/4 SCALE TO 3/4 SCALE STEP VCC = 5V, VFS = 4.095V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 2μs/DIV 2637 G13 2μs/DIV 2637 G14 2637fb 12 LTC2637 TYPICAL PERFORMANCE CHARACTERISTICS LTC2637-10 Integral Nonlinearity (INL) 1.0 VCC = 3V VFS = 2.5V INTERNAL REF . 0.5 DNL (LSB) INL (LSB) 0.5 1.0 VCC = 3V VFS = 2.5V INTERNAL REF . TA = 25°C, unless otherwise noted. Differential Nonlinearity (DNL) 0 0 –0.5 –0.5 –1.0 0 256 512 CODE 768 1023 2637 G15 –1.0 0 256 512 CODE 768 1023 2637 G16 LTC2637-8 Integral Nonlinearity (INL) 0.50 VCC = 3V VFS = 2.5V INTERNAL REF . 0.25 DNL (LSB) INL (LSB) 0.25 0.50 VCC = 3V VFS = 2.5V INTERNAL REF . Differential Nonlinearity (DNL) 0 0 –0.25 –0.25 –0.50 0 64 128 CODE 192 255 2637 G17 –0.50 0 64 128 CODE 192 255 2637 G18 LTC2637 Load Regulation 10 8 6 4 VOUT (mV) VOUT (V) 2 0 –2 –4 –6 –8 –10 –30 –20 –10 INTERNAL REF. CODE = MID-SCALE 0 10 IOUT (mA) 20 30 2637 G19 Current Limiting 0.20 3 VCC = 5V (LTC2637-H) VCC = 5V (LTC2637-L) VCC = 3V (LTC2637-L) OFFSET ERROR (mV) INTERNAL REF. CODE = MID-SCALE –20 –10 0 10 IOUT (mA) 20 30 2637 G20 Offset Error vs Temperature VCC = 5V (LTC2637-H) VCC = 5V (LTC2637-L) VCC = 3V (LTC2637-L) 0.15 0.10 0.05 0 –0.05 –0.01 –0.15 2 1 0 –1 –2 –3 –50 –25 –0.20 –30 0 25 50 75 100 125 150 TEMPERATURE (°C) 2637 G21 2637fb 13 LTC2637 TYPICAL PERFORMANCE CHARACTERISTICS LTC2637 Large-Signal Response Mid-Scale Glitch Impulse 9TH CLOCK OF 3RD DATA BYTE SCL 5V/DIV VOUT 0.5V/DIV VOUT 5mV/DIV VFS = VCC = 5V 1/4 SCALE to 3/4 SCALE 2μs/DIV 2637 G22 TA = 25°C, unless otherwise noted. Power-On Reset Glitch LTC2637-L VCC 2V/DIV LTC2637-H12 VCC = 5V, 3nV•s TYP VOUT 5mV/DIV LTC2637-L12 VCC = 3V, 2.1nV•s TYP 2μs/DIV 2637 G23 ZERO-SCALE 200μs/DIV 2637 G24 Headroom at Rails vs Output Current 5.0 4.5 4.0 3.5 VOUT (V) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 3V (LTC2637-L) SINKING 1 2 3 456 IOUT (mA) 7 8 9 10 5V SINKING VOUT 0.5V/DIV 3V (LTC2637-L) SOURCING 5V SOURCING SCL 5V/DIV Exiting Power-Down to Mid-Scale 9TH CLOCK OF 3RD DATA BYTE VCC 2V/DIV Power-On Reset to Mid-Scale LTC2637-H DACs A TO G IN POWER-DOWN MODE LTC2637H VCC = 5V INTERNAL REF 5μs/DIV 2637 G26 VOUT 0.5V/DIV LTC2637-L 200μs/DIV 2637 G27 2637 G25 Supply Current vs Logic Voltage 1.8 1.6 1.4 ICC (mA) VCC = 5V 1.2 1.0 0.8 0.6 VCC = 3V (LTC2637-L) SWEEP SDA, SCL, BETWEEN 0V AND VCC DAC to DAC Crosstalk (Dynamic) 2 9TH CLOCK OF 3RD DATA BYTE SCL LTC2637-H12 5V/DIV VCC = 5V, 3nV•s TYP CREF = 0.1μF 1 DAC SWITCH 0 TO FS 2V/DIV VOUT 2mV/DIV 0 –2 –4 –6 dB –8 –10 –12 –14 –16 Multiplying Bandwidth 0 1 2 3 LOGIC VOLTAGE (V) 4 5 2637 G28 2μs/DIV 2637 G29 –18 VCC = 5V VREF(DC) = 2V VREF(AC) = 0.2VP-P CODE = FULL-SCALE 1k 10k 100k FREQUENCY (Hz) 1M 2637 G30 2637fb 14 LTC2637 TYPICAL PERFORMANCE CHARACTERISTICS LTC2637 Gain Error vs. Temperature 1.0 500 TA = 25°C, unless otherwise noted. Noise Voltage vs. Frequency VCC = 5V CODE = MID-SCALE INTERNAL REF . GAIN ERROR (%FSR) 0.5 NOISE VOLTAGE (nV/√Hz) 400 300 LTC2637-H 200 LTC2637-L 100 0 –0.5 –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2637 G31 0 100 1k 100k 10k FREQUENCY (Hz) 1M 2637 G32 Gain Error vs Reference Input 1.0 VCC = 5.5V 0.8 GAIN ERROR OF 8 CHANNELS 0.6 GAIN ERROR (%FSR) 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 1 1.5 2 2.5 3 3.5 4 4.5 REFERENCE VOLTAGE (V) 5 5.5 10μV/DIV 0.1Hz to 10Hz Voltage Noise VCC = 5V, VFS = 2.5V CODE = MID-SCALE INTERNAL REF . 1s/DIV 2637 G35 2637 G34 2637fb 15 LTC2637 PIN FUNCTIONS (DFN/MSOP) VCC (Pin 1/Pin 1): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V (LTC2637-L) or 4.5V ≤ VCC ≤ 5.5V (LTC2637-H). Bypass to GND with a 0.1μF capacitor. VOUTA to VOUTH (Pins 2–5, 10–13/Pins 2–5, 12–15): DAC Analog Voltage Outputs. CAO (Pin 6/Pin 7): Chip Address Bit 0. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (See Tables 1 and 2). SCL (Pin 7/Pin 8): Serial Clock Input Pin. Data is shifted into the SDA pin at the rising edges of the clock. This high impedance pin requires a pull-up resistor or current source to VCC. SDA (Pin 8/Pin 9): Serial Data Bidirectional Pin. Data is shifted into the SDA pin and acknowledged by the SDA pin. This pin is high impedance while data is shifted in. Open drain N-channel output during acknowledgment. SDA requires a pull-up resistor or current source to VCC. REF (Pin 9/Pin 11): Reference Voltage Input or Output. When External Reference mode is selected, REF is an input (1V ≤ VREF ≤ VCC) where the voltage supplied sets the full-scale DAC output voltage. When Internal Reference is selected, the 10ppm/°C 1.25V (LTC2637-L) or 2.048V (LTC2637-H) internal reference (half full-scale) is available at the pin. This output may be bypassed to GND with up to 10μF and must be buffered when driving external DC , load current. GND (Pin 14/Pin 16): Ground. CA2 (Pin 6, MSOP only): Chip Address Bit 2. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (See Table 1). CA1 (Pin 10, MSOP only): Chip Address Bit 1. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (See Table 1). Exposed Pad (Pin 15, DFN Only): Ground. Must be soldered to PCB Ground. 2637fb 16 LTC2637 BLOCK DIAGRAM INTERNAL REFERENCE GND SWITCH VREF VCC REGISTER REGISTER REGISTER REGISTER REF VOUTA VREF DAC A DAC H VREF VOUTH REGISTER REGISTER REGISTER VOUTB VREF DAC B REGISTER DAC G VREF VOUTG REGISTER REGISTER REGISTER VOUTC VREF REGISTER DAC C DAC F VREF VOUTF REGISTER REGISTER REGISTER VOUTD REGISTER DAC D DAC E VOUTE CAO (CA1) (CA2) I2C ADDRESS DECODE I2C INTERFACE DECODE POWER-ON RESET SCL SDA 2637 BD ( ) MSOP PACKAGE ONLY TEST CIRCUITS Test Circuit 1 Test Circuit 2 VDD 100Ω VIH(CAn)/VIL(CAn) 2637 TC01 CAn RINH/RINL/RINF CAn GND 2637 TC01b 2637fb 17 LTC2637 TIMING DIAGRAM 18 SDA tSU(DAT) tf tHD(STA) tSP tr tBUF tf tLOW tr SCL tHD(STA) S 2637 F01 tHD(DAT) tHIGH Sr P S tSU(STA) tSU(STO) ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS Figure 1. I2C Timing SLAVE ADDRESS 1ST DATA BYTE A1 6 7 8 9 1 2 3 4 5 6 7 8 9 A0 W ACK C3 C2 C1 C0 A3 A2 A1 A0 ACK 2ND DATA BYTE ACK 3RD DATA BYTE X X X X ACK START A6 A5 A4 A3 A2 SCL 1 2 3 4 5 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 2637 F02 Figure 2. Typical LTC2637 Write Transaction 2637fb LTC2637 OPERATION The LTC2637 is a family of octal voltage output DACs in 14-lead DFN and 16-lead MSOP packages. Each DAC can operate rail-to-rail using an external reference, or with its full-scale voltage set by an integrated reference. Eighteen combinations of accuracy (12-, 10-, and 8-bit), power-on reset value (zero-scale, mid-scale in internal reference mode, or mid-scale in external reference mode), and fullscale voltage (2.5V or 4.096V) are available. The LTC2637 is controlled using a 2-wire I2C interface. Power-On Reset The LTC2637-HZ/ LTC2637-LZ clear the output to zero-scale when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2637 contains circuitry to reduce the power-on glitch: the analog output typically rises less than 5mV above zeroscale during power on. In general, the glitch amplitude decreases as the power supply ramp time is increased. See “Power-On Reset Glitch” in the Typical Performance Characteristics section. The LTC2637-HMI/LTC2637-HMX/LTC2637-LMI/ LTC2637-LMX provide an alternative reset, setting the output to mid-scale when power is first applied. The LTC2637-LMI and LTC2637-HMI power up in internal reference mode, with the output set to a mid-scale voltage of 1.25V and 2.048V, respectively. The LTC2637-LMX and LTC2637-HMX power-up in external reference mode, with the output set to mid-scale of the external reference. Default reference mode selection is described in the Reference Modes section. Power Supply Sequencing The voltage at REF (Pin 9, DFN; Pin 11, MSOP) must be kept within the range –0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turnon and turn-off sequences, when the voltage at VCC is in transition. Transfer Function The digital-to-analog transfer function is: ⎛k⎞ VOUT(IDEAL) = ⎜ N ⎟ VREF ⎝2 ⎠ where k is the decimal equivalent of the binary DAC input code, N is the resolution, and VREF is either 2.5V (LTC2637-LMI/LTC2637-LMX/LTC2637-LZ) or 4.096V (LTC2637-HMI/LTC2637-HMX/LTC2637-HZ) when in Internal Reference mode, and the voltage at REF when in External Reference mode. I2C Serial Interface The LTC2637 communicates with a host using the standard 2-wire I2C interface. The timing diagrams (Figures 1 and 2) show the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The value of these pull-up resistors is dependent on the power supply and can be obtained from the I2C specifications. For an I2C bus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pF . The LTC2637 is a receive-only (slave) device. The master can write to the LTC2637. The LTC2637 will not acknowledge (NAK) a read request from the master. START (S) and STOP (P) Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a communication to a slave device by transmitting a START condition. A START condition is generated by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition. A STOP condition is generated by transitioning SDA from low to high while SCL is high. The bus is then free for communication with another I2C device. 2637fb 19 LTC2637 OPERATION Acknowledge The Acknowledge (ACK) signal is used for handshaking between the master and the slave. An ACK (active LOW) generated by the slave lets the master know that the latest byte of information was properly received. The ACK related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the ACK clock pulse. The slave-receiver must pull down the SDA bus line during the ACK clock pulse so that it remains a stable LOW during the HIGH period of this clock pulse. The LTC2637 responds to a write by a master in this manner but does not acknowledge a read operation; in that case, SDA is retained HIGH during the period of the ACK clock pulse. Chip Address The state of pins CA0, CA1 and CA2 (CA1 and CA2 are only available on the MSOP package) determines the slave address of the part. These pins can each be set to any one of three states: VCC, GND or float. This results in 27 (MSOP Package) or 3 (DFN Package) selectable addresses for the part. The slave address assignments are shown in Tables 1 and 2. In addition to the address selected by the address pins, the part also responds to a global address. This address allows a common write to all LTC2637 parts to be accomplished using one 3-byte write transaction on the I2C bus. The global address, listed at the end of Tables 1 and 2, is a 7-bit hardwired address not selectable by CA0, CA1 or CA2. If another global address is required, please consult the factory. The maximum capacitive load allowed on the address pins (CA0, CA1 and CA2) is 10pF as these pins are driven during , address detection to determine if they are floating. Table 1. Slave Address Map (MSOP Package) CA2 GND GND GND GND GND GND GND GND GND FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT VCC VCC VCC VCC VCC VCC VCC VCC VCC CA1 GND GND GND FLOAT FLOAT FLOAT VCC VCC VCC GND GND GND FLOAT FLOAT FLOAT VCC VCC VCC GND GND GND FLOAT FLOAT FLOAT VCC VCC VCC CA0 GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC A6 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A5 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A4 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 GLOBAL ADDRESS Table 2. Slave Address Map (DFN Package) CA0 GND FLOAT VCC GLOBAL ADDRESS A6 0 0 0 1 A5 0 0 0 1 A4 1 1 1 1 A3 0 0 0 0 A2 0 0 0 0 A1 0 0 1 1 A0 0 1 0 1 2637fb 20 LTC2637 OPERATION Write Word Protocol The master initiates communication with the LTC2637 with a START condition and a 7-bit slave address followed by the Write bit (W) = 0. The LTC2637 acknowledges by pulling the SDA pin low at the 9th clock if the 7-bit slave address matches the address of the part (set by CA0, CA1 or CA2) or the global address. The master then transmits three bytes of data. The LTC2637 acknowledges each byte of data by pulling the SDA line low at the 9th clock of each data byte transmission. After receiving three complete bytes of data, the LTC2637 executes the command specified in the 24-bit input word. If more than three data bytes are transmitted after a valid 7-bit slave address, the LTC2637 does not acknowledge the extra bytes of data (SDA is high during the 9th clock). The format of the three data bytes is shown in Figure 3. The first byte of the input word consists of the 4-bit command, followed by the 4-bit DAC address. The next two bytes contain the 16-bit data word, which consists of the 12-, 10- or 8-bit input code, MSB to LSB, followed by 4, 6 or 8 don’t-care bits (LTC2637-12, LTC2637-10 and LTC2637-8, respectively). A typical LTC2637 write transaction is shown in Figure 4. The command bit assignments (C3-C0) and address (A3A0) assignments are shown in Tables 3 and 4. The first four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register. In an update operation, the data word is copied from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 12-, 10-, or 8-bit input code, and is converted to an analog voltage at the DAC output. Write to and Update combines the first two commands. The Update operation also powers up the DAC if it had been in power-down mode. The data path and registers are shown in the Block Diagram. Table 3. Command Codes COMMAND* C3 0 0 0 0 0 0 0 0 1 C2 0 0 0 0 1 1 1 1 1 C1 0 0 1 1 0 0 1 1 1 C0 0 1 0 1 0 1 0 1 1 Write to Input Register n Update (Power Up) DAC Register n Write to Input Register n, Update (Power Up) All Write to and Update (Power Up) DAC Register n Power Down n Power Down Chip (All DAC’s and Reference) Select Internal Reference (Power Up Reference) Select External Reference (Power Down Internal Reference) No Operation *Command codes not shown are reserved and should not be used. Table 4. Address Codes ADDRESS (n)* A3 0 0 0 0 0 0 0 0 1 A2 0 0 0 0 1 1 1 1 1 A1 0 0 1 1 0 0 1 1 1 A0 0 1 0 1 0 1 0 1 1 DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H All DACs *Address codes not shown are reserved and should not be used. Reference Modes For applications where an accurate external reference is either not available, or not desirable due to limited space, the LTC2637 has a user-selectable, integrated reference. The integrated reference voltage is internally amplified by 2x to provide the full-scale DAC output voltage range. 2637fb 21 LTC2637 OPERATION Write Word Protocol for LTC2637 S SLAVE ADDRESS W ACK 1ST DATA BYTE ACK 2ND DATA BYTE ACK 3RD DATA BYTE ACK INPUT WORD P Input Word (LTC2637-12) C3 C2 C1 C0 A3 A2 A1 A1 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X 1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE Input Word (LTC2637-10) C3 C2 C1 C0 A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE Input Word (LTC2637-8) C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X 2637 F03 1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE Figure 3. Command and Data Input Format The LTC2637-LMI/ LTC2637-LMX/ LTC2637-LZ provides a full-scale output of 2.5V. The LTC2637-HMI/ LTC2637HMX/ LTC2637-HZ provides a full-scale output of 4.096V. The internal reference can be useful in applications where the supply voltage is poorly regulated. Internal Reference mode can be selected by using command 0110b, and is the power-on default for LTC2637-HZ/ LTC2637-LZ, as well as for LTC2637-HMI/ LTC2637-LMI. The 10ppm/°C, 1.25V (LTC2637-LMI/ LTC2637-LMX/ LTC2637-LZ) or 2.048V (LTC2637-HMI/ LTC2637-HMX/ LTC2637-HZ) internal reference is available at the REF pin. Adding bypass capacitance to the REF pin will improve noise performance; and up to 10μF can be driven without oscillation. The REF output must be buffered when driving an external DC load current. Alternatively, the DAC can operate in External Reference mode using command 0111b. In this mode, an input voltage supplied externally to the REF pin provides the reference (1V ≤ VREF ≤ VCC) and the supply current is reduced. The external reference voltage supplied sets the full-scale DAC output voltage. External Reference mode is the power-on default for LTC2637-HMX/ LTC2637-LMX. The reference mode of LTC2637-HZ/ LTC2637-LZ/ LTC2637HMI/ LTC2637-LMI (internal reference power-on default), can be changed by software command after power up. The same is true for LTC2637-HMX/ LTC2637-LMX (external reference power-on default). Power-Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than eight DAC outputs are needed. When in power-down, the buffer amplifiers, bias circuits, and integrated reference circuits are disabled, and draw essentially zero current. The DAC outputs are put into a high-impedance state, and the output pins are passively pulled to ground through individual 200kΩ resistors. Input and DAC register contents are not disturbed during power down. Any DAC channel or combination of channels can be put into power-down mode by using command 0100b in combination with the appropriate DAC address, (n). The supply current is reduced approximately 10% for each DAC powered down. The integrated reference is automatically powered down when external reference is selected using 2637fb 22 LTC2637 OPERATION command 0111b. In addition, all the DAC channels and the integrated reference together can be put into powerdown mode using Power Down Chip command 0101b. When the integrated reference and all DAC channels are in power-down mode, the REF pin becomes high impedance (typically > 1GΩ). For all power-down commands the 16-bit data word is ignored. Normal operation resumes after executing any command that includes a DAC update, (as shown in Table 1). The selected DAC is powered up as its voltage output is updated. When a DAC which is in a powered-down state is powered up and updated, normal settling is delayed. If less than eight DACs are in a powered-down state prior to the update command, the power-up delay time is 10μs. However, if all eight DACs and the integrated reference are powered down, then the main bias generation circuit block has been automatically shut down in addition to the DAC amplifiers and reference buffers. In this case, the power up delay time is 12μs. The power-up of the integrated reference depends on the command that powered it down. If the reference is powered down using the Select External Reference Command (0111b), then it can only be powered back up using Select Internal Reference Command (0110b). However, if the reference was powered down using Power Down Chip Command (0101b), then in addition to Select Internal Reference Command (0110b), any command that powers up the DACs will also power up the integrated reference. Voltage Output The LTC2637’s DAC output integrated rail-to-rail amplifiers have guaranteed load regulation when sourcing or sinking up to 10mA at 5V, and 5mA at 3V. Load regulation is a measure of the amplifier’s ability to maintain the rated voltage accuracy over a wide range of load current. The measured change in output voltage per change in forced load current is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to ohms. The amplifier’s DC output impedance is 0.1Ω when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 50Ω typical channel resistance of the output devices (e.g., when sinking 1mA, the minimum output voltage is 50Ω • 1mA, or 50mV). See the graph “Headroom at Rails vs. Output Current” in the Typical Performance Characteristics section. The amplifier is stable driving capacitive loads of up to 500pF . Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog output of the DAC cannot go below ground, it may limit for the lowest codes as shown in Figure 5b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC, as shown in Figure 5c. No full-scale limiting can occur if VREF is less than VCC–FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. Board Layout The PC board should have separate areas for the analog and digital sections of the circuit. A single, solid ground plane should be used, with analog and digital signals carefully routed over separate areas of the plane. This keeps digital signals away from sensitive analog signals and minimizes the interaction between digital ground currents and the 2637fb 23 LTC2637 OPERATION analog section of the ground plane. The resistance from the LTC2637 GND pin to the ground plane should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.1Ω). Note that the LTC2637 is no more susceptible to this effect than any other parts of this type; on the contrary, it allows layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. Another technique for minimizing errors is to use a separate power ground return trace on another board layer. The trace should run between the point where the power supply is connected to the board and the DAC ground pin. Thus the DAC ground pin becomes the common point for analog ground, digital ground, and power ground. When the LTC2637 is sinking large currents, this current flows out the ground pin and directly to the power ground trace without affecting the analog ground plane voltage. It is sometimes necessary to interrupt the ground plane to confine digital ground currents to the digital portion of the plane. When doing this, make the gap in the plane only as long as it needs to be to serve its purpose and ensure that no traces cross over the gap. SLAVE ADDRESS A6 START SDA SCL VOUT X = DON’T CARE A6 1 A5 2 A4 3 A3 4 A2 5 A1 6 A0 7 8 ACK C3 9 1 C2 2 A5 A4 A3 A2 A1 A0 W C3 C2 COMMAND/ADDRESS C1 C1 3 C0 C0 4 A3 A3 5 A2 A2 6 A1 A1 7 A0 A0 ACK 8 9 1 2 3 D11 D10 D9 MS DATA D8 D7 D6 D5 D4 ACK 4 5 6 7 8 9 1 2 3 D3 D2 D1 LS DATA D0 X X X X STOP ACK 4 5 6 7 8 9 FULL-SCALE VOLTAGE ZERO-SCALE VOLTAGE 2637 F04 Figure 4. Typical LTC2637 Input Waveform—Programming DAC Output for Full-Scale VREF = VCC POSITIVE FSE VREF = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (c) 0V 0 2,048 INPUT CODE (a) INPUT CODE (b) 4,095 2637 F04 OUTPUT VOLTAGE 0V NEGATIVE OFFSET Figure 5. Effects of Rail-to-Rail Operation On a DAC Transfer Curve (Shown for 12 Bits). (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero (c) Effect of Positive Full-Scale Error for Codes Near Full-Scale 2637fb 24 LTC2637 TYPICAL APPLICATION LTC2637 DACs Adjust LTC2755-16 Offsets, Amplified with LT1991 PGA to ±5V 5V 15 15V 0.1μF VDD LTC2755 RFBA 60 15V LTC6240 61 ROFSA 64 RIN1 63 RCOM1 DAC A 0.1μF 8 7 0.1μF + – 1/2 LT1469 6 4 0.1μF –15V OUTD LT1634-1.25 62 REFA RVOSA 58 –15V DAC D 30k –15V –15V OUTC LT1634-1.25 DAC C DAC B 30k GND –15V 19 9 SDA 8 SCL 7 CA0 10 CA1 CA2 6 16 GND 2637 TA02 + IOUT2A 2 3 – 30k 5 IOUT1A 59 2 + – 15V OUTA 11 REF LTC2637MS-LMI12 DAC A DAC H 15 VCC 1 0.1μF 5V 8 M9 9 M3 10 M1 1 P1 2 P3 3 P9 0.1μF 7 VCC LT1991 REF VEE 5 4 0.1μF –15V 4 DAC C DAC F 13 OUT 6 VOUT = ±5V 8 1 1/2 LT1469 4 0.1μF 0.1μF 2 + – + – + – LT1634-1.25 3 LT1634-1.25 30k OUTB –15V 5 12 14 DAC B DAC G DAC D DAC E I2C BUS 2637fb 25 LTC2637 PACKAGE DESCRIPTION DE Package 14-Lead (4mm × 3mm) Plastic DFN (Reference LTC DWG # 05-08-1708 Rev B) 4.00 0.10 (2 SIDES) 0.70 3.30 0.05 1.70 0.05 PIN 1 PACKAGE TOP MARK OUTLINE (SEE NOTE 6) 7 0.25 0.05 0.50 BSC 3.00 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.00 – 0.05 0.200 REF 0.75 0.05 3.00 REF BOTTOM VIEW—EXPOSED PAD 0.05 0.05 R = 0.05 TYP R = 0.115 TYP 8 14 0.40 0.10 3.60 0.05 2.20 3.00 0.10 (2 SIDES) 3.30 1.70 0.10 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 45 CHAMFER (DE14) DFN 0806 REV B 1 0.25 0.05 0.50 BSC NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE MS Package 16-Lead (4mm × 5mm) Plastic MSOP (Reference LTC DWG # 05-08-1669 Rev Ø) 0.889 (.035 0.127 .005) 4.039 0.102 (.159 .004) (NOTE 3) 16151413121110 9 0.280 0.076 (.011 .003) REF 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) GAUGE PLANE 0.254 (.010) DETAIL “A” 0 – 6 TYP 4.90 0.152 (.193 .006) 3.00 0.102 (.118 .004) (NOTE 4) 0.305 0.038 (.0120 .0015) TYP 0.50 (.0197) BSC 0.18 (.007) 0.53 0.152 (.021 .006) DETAIL “A” 12345678 1.10 (.043) MAX 0.86 (.034) REF RECOMMENDED SOLDER PAD LAYOUT SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC 0.1016 (.004 0.0508 .002) MSOP (MS16) 1107 REV Ø 2637fb 26 LTC2637 REVISION HISTORY REV A B DATE 10/09 06/10 DESCRIPTION Update LTC2637-12 Maximum Limits Added details to Note 3 Revised Typical Application circuit Added Typical Application drawing and revised Related Parts PAGE NUMBER 5, 6, 8 10 25 28 2637fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC2637 TYPICAL APPLICATION LTC2637 DACs Adjust LTC2755-16 Offsets, Amplified with LT1991 PGA to ±5V 5V 15 15V 0.1μF VDD LTC2755 RFBA 60 15V LTC6240 61 ROFSA 64 RIN1 63 RCOM1 DAC A 6 IOUT2A 2 3 0.1μF 8 7 0.1μF + – 1/2 LT1469 4 0.1μF –15V OUTD LT1634-1.25 62 REFA RVOSA 58 –15V DAC D 30k –15V –15V OUTC LT1634-1.25 DAC C DAC B 30k GND –15V 19 I2C BUS 9 SDA 8 SCL RELATED PARTS PART NUMBER LTC2636 DESCRIPTION Octal 12-/10-/8-Bit, SPI VOUT DACs with 10ppm/°C Reference COMMENTS 125μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail Output, 14-Lead 4mm × 3mm DFN and 16-Lead MSOP Packages VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output 250μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, I2C Interface 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface ±4LSB INL max at 16-Bits and ±2mV Offset Error, Rail-to-Rail Output, 20-Lead 4mm × 5mm QFN and 16-Lead TSSOP Packages ±4LSB INL max at 16-Bits and ±2mV Offset Error, Rail-to-Rail Output, 20-Lead 4mm × 4mm QFN and 16-Lead Narrow SSOP Packages ±2.5 LSB INL, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, 16-Pin 3mm × 3mm QFN and 10-Lead MSOP Packages 180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, Rail-to-Rail Output, in SC70 (LTC2630)/ ThinSOT™(LTC2631) 180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail Output, in ThinSOT Gain Accuracy of 0.04%, Gains from –13 to 14, 100μA Precision Op-Amp 90MHz Gain Bandwidth, 125μV offset, 900ns , 22V/μs Slew Rate Precision Op-Amp 2637fb LT 0610 REV B • PRINTED IN USA LTC1660/LTC1665 LTC2605/LTC2615/ LTC2625 LTC2600/LTC2610/ LTC2620 LTC2656/LTC2657 LTC2654/LTC2655 Octal 10/8-Bit VOUT DACs in 16-Pin Narrow SSOP Octal 16-/14-/12-Bit VOUT DACs with I2C Interface Octal 16-/14-/12-Bit VOUT DACs in 16-Lead Narrow SSOP Octal 16-/12 Bit, SPI/I2C VOUT DACs with 10ppm/°C Max Reference Quad 16-/12 Bit, SPI/I2C VOUT DACs with 10ppm/°C Max Reference Quad 12-/10-/8-Bit SPI/I2C VOUT DACs with 10ppm/°C Reference Single 12-/10-/8-Bit, SPI/ I2C VOUT DACs with 10ppm/°C Reference Single 12-/10-/8-Bit, SPI VOUT DACs with 10ppm/°C Reference LTC2634/LTC2635 LTC2630/LTC2632 LTC2640 Amplifiers LT1991 LT1469 Precision, 100μA Gain Selectable Amplifier Dual 90MHz, 22V/μs 16-Bit Accurate Operational Amplifier 28 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2009 + – 30k 5 IOUT1A 59 2 + – 15V OUTA 11 REF LTC2637MS-LMI12 DAC A DAC H 15 VCC 1 0.1μF 5V 8 M9 9 M3 10 M1 1 P1 2 P3 3 P9 0.1μF 7 VCC LT1991 REF VEE 5 4 0.1μF –15V 4 DAC C DAC F 13 OUT 6 VOUT = ±5V 8 1 1/2 LT1469 4 0.1μF 0.1μF 2 + – + – + – LT1634-1.25 3 LT1634-1.25 30k OUTB –15V 5 12 7 CA0 10 CA1 CA2 6 16 GND 2637 TA03 DAC B DAC G 14 DAC D DAC E