LTC2640AITS8-LZ10

FEATURES n LTC2640 Single 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference DESCRIPTION The LTC®2640 is a family of 12-, 10-, and 8-bit voltageoutput DACs with an integrated, high-accuracy, low-drift reference in an 8-lead TSOT-23 package. It has a rail-to-rail output buffer that is guaranteed monotonic. The LTC2640-L has a full-scale output of 2.5V, and operates from a single 2.7V to 5.5V supply. The LTC2640-H has a full-scale output of 4.096V, and operates from a 4.5V to 5.5V supply. A 10ppm/°C reference output is available at the REF pin. Each DAC can also operate in External Reference mode, in which a voltage supplied to the REF pin sets the fullscale output. The LTC2640 DACs use a SPI/MICROWIRE™ compatible 3-wire serial interface which operates at clock rates up to 50MHz. The LTC2640 incorporates a power-on reset circuit. Options are available for Reset to Zero-Scale or Reset to Mid-Scale after power-up. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5396245, 5859606, 6891433, 6937178 and 7414561. n n n n n n n n n n n n Integrated Precision Reference 2.5V Full-Scale 10ppm/°C (LTC2640-L) 4.096V Full-Scale 10ppm/°C (LTC2640-H) Maximum INL Error: 1LSB (LTC2640A-12) Bidirectional Reference: Input or 10ppm/°C Output Low Noise (0.7mVpp, 0.1Hz to 200kHz) Guaranteed Monotonic Over Temperature 2.7V to 5.5V Supply Range (LTC2640-L) Low Power Operation: 180μA at 3V Power Down to 1.8μA Maximum (C and I Grades) Asynchronous DAC Clear Pin (LTC2640-Z) Power-On Reset to Zero or Mid-Scale options Double-Buffered Data Latches Guaranteed Operation from –40°C to 125°C (H-Grade) 8-Lead TSOT-23 (ThinSOT™) Package APPLICATIONS n n n n n n Mobile Communications Process Control and Industrial Automation Automatic Test Equipment Portable Equipment Automotive Optical Networking BLOCK DIAGRAM VCC (LTC2640-Z) REF INTERNAL REFERENCE Integral Nonlinearity (LTC2640A-LZ12) 1.0 VCC = 3V VFS = 2.5V SDI SWITCH 0.5 INL (LSB) VOUT –1.0 GND 2640 TA01 SCK 24-BIT SHIFT REGISTER CONTROL DECODE LOGIC RESISTOR DIVIDER 0 DACREF CS/LD INPUT REGISTER DAC REGISTER DAC –0.5 0 1024 2048 CODE 3072 4095 2640 TA01b CLR 2640fb 1 LTC2640 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VCC) ................................... –0.3V to 6V CLR, CS/LD, REF_SEL, SCK, SDI ................. –0.3V to 6V VOUT, REF ......................... –0.3V to Min(VCC + 0.3V, 6V) Operating Temperature Range LTC2640C ................................................ 0°C to 70°C LTC2640I.............................................. –40°C to 85°C LTC2640H (Note 3) ............................ –40°C to 125°C Maximum Junction Temperature........................... 150°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) .................. 300°C PIN CONFIGURATION LTC2640-Z CS/LD 1 SCK 2 SDI 3 GND 4 TOP VIEW 8 CLR 7 VOUT 6 REF 5 VCC LTC2640-M CS/LD 1 SCK 2 SDI 3 GND 4 TOP VIEW 8 REF_SEL 7 VOUT 6 REF 5 VCC TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 TJMAX = 150°C (NOTE 6), θJA = 195°C/W TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 TJMAX = 150°C (NOTE 6), θJA = 195°C/W 2640fb 2 LTC2640 ORDER INFORMATION LTC2640 A C TS8 –L M 12 #TRM PBF LEAD FREE DESIGNATOR TAPE AND REEL TR = 2,500-Piece Tape and Reel TRM = 500-Piece Tape and Reel RESOLUTION 12 = 12-Bit 10 = 10-Bit 8 = 8-Bit POWER-ON RESET M = Reset to Mid-Scale Z = Reset to Zero-Scale FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE L = 2.5V H = 4.096V PACKAGE TYPE TS8 = 8-Lead Plastic TSOT-23 TEMPERATURE GRADE C = Commercial Temperature Range (0°C to 70°C) I = Industrial Temperature Range (–40°C to 85°C) H = Automotive Temperature Range (–40°C to 125°C) ELECTRICAL GRADE (OPTIONAL) A = ±1LSB Maximum INL (12-Bit) PRODUCT PART NUMBER Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2640fb 3 LTC2640 PRODUCT SELECTION GUIDE PART NUMBER LTC2640A-LM12 LTC2640A-LZ12 LTC2640A-HM12 LTC2640A-HZ12 LTC2640-LM12 LTC2640-LM10 LTC2640-LM8 LTC2640-LZ12 LTC2640-LZ10 LTC2640-LZ8 LTC2640-HM12 LTC2640-HM10 LTC2640-HM8 LTC2640-HZ12 LTC2640-HZ10 LTC2640-HZ8 VFS WITH INTERNAL PART MARKING* REFERENCE LTDHV LTDHW LTDHX LTDHY LTDHV LTDHZ LTDJF LTDHW LTDJB LTDJG LTDHX LTDJC LTDJH LTDHY LTDJD LTDJJ 2.5V • (4095/4096) 2.5V • (4095/4096) 4.096V • (4095/4096) 4.096V • (4095/4096) 2.5V • (4095/4096) 2.5V • (1023/1024) 2.5V • (255/256) 2.5V • (4095/4096) 2.5V • (1023/1024) 2.5V • (255/256) 4.096V • (4095/4096) 4.096V • (1023/1024) 4.096V • (255/256) 4.096V • (4095/4096) 4.096V • (1023/1024) 4.096V • (255/256) POWER-ON RESET TO CODE PIN 8 Mid-Scale Zero Mid-Scale Zero Mid-Scale Mid-Scale Mid-Scale Zero Zero Zero Mid-Scale Mid-Scale Mid-Scale Zero Zero Zero REF_SEL CLR REF_SEL CLR REF_SEL REF_SEL REF_SEL CLR CLR CLR REF_SEL REF_SEL REF_SEL CLR CLR CLR RESOLUTION 12-Bit 12-Bit 12-Bit 12-Bit 12-Bit 10-Bit 8-Bit 12-Bit 10-Bit 8-Bit 12-Bit 10-Bit 8-Bit 12-Bit 10-Bit 8-Bit VCC 2.7V – 5.5V 2.7V – 5.5V 4.5V – 5.5V 4.5V – 5.5V 2.7V – 5.5V 2.7V – 5.5V 2.7V – 5.5V 2.7V – 5.5V 2.7V – 5.5V 2.7V – 5.5V 4.5V – 5.5V 4.5V – 5.5V 4.5V – 5.5V 4.5V – 5.5V 4.5V – 5.5V 4.5V – 5.5V MAXIMUM INL ±1LSB ±1LSB ±1LSB ±1LSB ±2.5LSB ±1LSB ±0.5LSB ±2.5LSB ±1LSB ±0.5LSB ±2.5LSB ±1LSB ±0.5LSB ±2.5LSB ±1LSB ±0.5LSB *The temperature grade is identified by a label on the shipping container. 2640fb 4 LTC2640 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2640-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2640A-LM12/-LZ12 (VFS = 2.5V) LTC2640-8 SYMBOL PARAMETER DC Performance Resolution Monotonicity DNL INL ZSE VOS VOSTC FSE VFSTC Differential Nonlinearity Integral Nonlinearity Zero-Scale Error Offset Error l LTC2640-10 LTC2640-12 LTC2640A-12 UNITS Bits Bits ±1 ±0.5 0.5 ±0.5 ±10 ±0.08 ±0.4 ±10 ±10 ±10 ±1 5 ±5 LSB LSB mV mV μV/°C %FSR ppm/°C ppm/°C ppm/°C CONDITIONS MIN 8 8 TYP MAX MIN TYP MAX MIN TYP 10 10 ±0.5 ±0.5 ±0.2 0.5 ±0.5 ±10 ±0.08 ±0.4 ±10 ±10 ±10 0.035 0.064 0.035 0.064 ±1 5 ±5 ±1 0.5 ±0.5 ±10 12 12 MAX MIN TYP MAX 12 12 ±1 ±2.5 5 ±5 VCC = 3V, Internal Ref. (Note 4) l VCC = 3V, Internal Ref. (Note 4) l VCC = 3V, Internal Ref. (Note 4) l VCC = 3V, Internal Ref., Code = 0 l ±0.05 ±0.5 0.5 ±0.5 ±10 5 ±5 VCC = 3V, Internal Ref. (Note 5) l VOS Temperature VCC = 3V, Internal Ref. (Note 5) Coefficient Full-Scale Error VCC = 3V, Internal Ref. (Note 11) l ±0.08 ±0.4 ±10 ±10 ±10 ±0.08 ±0.4 ±10 ±10 ±10 0.14 0.256 0.14 0.256 Full-Scale Voltage VCC = 3V, Internal Ref. (Note 10) Temperature C-Grade Coefficient I-Grade H-Grade Load Regulation Internal Ref., Mid-Scale, VCC = 3V ±10%, –5mA ≤ IOUT ≤ 5mA, VCC = 5V ±10%, –10mA ≤ IOUT ≤ 10mA Internal Ref., Mid-Scale, VCC = 3V ±10%, –5mA ≤ IOUT ≤ 5mA, VCC = 5V ±10%, –10mA ≤ IOUT ≤ 10mA l l 0.009 0.016 0.009 0.016 0.14 0.256 LSB/mA 0.14 0.256 LSB/mA ROUT DC Output Impedance l l 0.09 0.156 0.09 0.156 0.09 0.156 0.09 0.156 0.09 0.156 0.09 0.156 0.09 0.156 0.09 0.156 Ω Ω SYMBOL VOUT PSR ISC PARAMETER DAC Output Span Power Supply Rejection Short-Circuit Output Current (Note 6) Sinking Sourcing Positive Supply Voltage Supply Current (Note 7) CONDITIONS External Reference Internal Reference VCC = 3V ±10% or 5V ±10% VFS = VCC = 5.5V Zero-Scale; VOUT shorted to VCC Full-Scale; VOUT shorted to GND For Specified Performance VCC = 3V, VREF = 2.5V, External Reference VCC = 3V, Internal Reference VCC = 5V, VREF = 2.5V, External Reference VCC = 5V, Internal Reference VCC = 5V, C-Grade, I-Grade VCC = 5V, H-Grade l l l l l l l l l MIN TYP 0 to VREF 0 to 2.5 –80 27 –28 MAX UNITS V V dB 48 –48 5.5 mA mA V μA μA μA μA μA μA Power Supply VCC ICC 2.7 150 180 160 190 0.6 0.6 200 240 210 260 1.8 4 ISD Supply Current in Power-Down Mode (Note 7) 2640fb 5 LTC2640 ELECTRICAL CHARACTERISTICS SYMBOL Reference Input Input Voltage Range Resistance Capacitance IREF Reference Output Output Voltage Reference Temperature Coefficient Output Impedance Capacitive Load Driving Short-Circuit Current Digital I/O VIH VIL ILK CIN AC Performance tS Settling Time VCC = 3V (Note 9) ±0.39% (±1LSB at 8-Bits) ±0.098% (±1LSB at 10-Bits) ±0.024% (±1LSB at 12-Bits) 3.2 3.8 4.1 1 500 At Mid-Scale Transition External Reference At f = 1kHz, External Reference At f = 10kHz, External Reference At f = 1kHz, Internal Reference At f = 10kHz, Internal Reference 0.1Hz to 10Hz, External Reference 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, External Reference 0.1Hz to 200kHz, Internal Reference, CREF = 0.33μF 2.1 300 140 130 160 150 20 20 650 670 μs μs μs V/μs pF nV•s kHz nV√Hz nV√Hz nV√Hz nV√Hz μVP-P μVP-P μVP-P μVP-P Digital Input High Voltage Digital Input Low Voltage Digital Input Leakage Digital Input Capacitance VCC = 3.6V to 5.5V VCC = 2.7V to 3.6V VCC = 4.5V to 5.5V VCC = 2.7V to 4.5V VIN = GND to VCC (Note 8) l l l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2640-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2640A-LM12/-LZ12 (VFS = 2.5V) PARAMETER CONDITIONS MIN 0 160 190 7.5 DAC Powered Down l TYP MAX VCC 220 0.1 1.260 UNITS V kΩ pF μA V ppm/°C kΩ μF mA V V Reference Current, Power-Down Mode 0.005 1.240 1.250 ±10 0.5 10 VCC = 5.5V; REF Shorted to GND 2.4 2 2.5 0.8 0.6 ±1 2.5 V V μA pF Voltage Output Slew Rate Capacitance Load Driving Glitch Impulse Multiplying Bandwidth en Output Voltage Noise Density Output Voltage Noise 2640fb 6 LTC2640 TIMING CHARACTERISTICS SYMBOL t1 t2 t3 t4 t5 t6 t7 t9 t10 PARAMETER SDI Valid to SCK Setup SDI Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK High to CS/LD High CS/LD Low to SCK High CLR Pulse Width CS/LD High to SCK Pos. Edge SCK Frequency 50% Duty Cycle The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V. (See Figure 1) (Note 8). LTC2640-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2640A-LM12/-LZ12 (VFS = 2.5V) CONDITIONS l l l l l l l l l l MIN 4 4 9 9 10 7 7 20 7 TYP MAX UNITS ns ns ns ns ns ns ns ns ns 50 MHz ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2640-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2640A-HM12/-HZ12 (VFS = 4.096V) LTC2640-8 SYMBOL PARAMETER DC Performance Resolution Monotonicity l LTC2640-10 LTC2640-12 LTC2640A-12 MAX UNITS Bits Bits ±1 ±0.5 0.5 ±0.5 ±10 ±0.08 ±0.4 ±10 ±10 ±10 ±1 5 ±5 LSB LSB mV mV μV/°C %FSR ppm/°C ppm/°C ppm/°C 0.16 LSB/mA CONDITIONS MIN 8 8 TYP MAX MIN TYP MAX MIN TYP 10 10 ±0.5 ±0.5 ±0.2 0.5 ±0.5 ±10 ±0.08 ±0.4 ±10 ±10 ±10 0.022 0.04 ±1 5 ±5 ±1 0.5 ±0.5 ±10 12 12 MAX MIN TYP 12 12 ±1 ±2.5 5 ±5 VCC = 5V, Internal Ref. (Note 4) l VCC = 5V, Internal Ref. (Note 4) l VCC = 5V, Internal Ref. (Note 4) l VCC = 5V, Internal Ref., Code = 0 l DNL INL ZSE VOS VOSTC FSE VFSTC Differential Nonlinearity Integral Nonlinearity Zero-Scale Error Offset Error ±0.05 ±0.5 0.5 ±0.5 ±10 ±0.08 ±0.4 ±10 ±10 ±10 5 ±5 VCC = 5V, Internal Ref. (Note 5) l VOS Temperature VCC = 5V, Internal Ref. (Note 5) Coefficient Full-Scale Error VCC = 5V, Internal Ref. (Note 11) l Full-Scale Voltage VCC = 5V, Internal Ref. (Note 10) Temperature C-Grade Coefficient I-Grade H-Grade Load Regulation VCC = 5V ±10%, Internal Ref. Mid-Scale, –10mA ≤ IOUT ≤ 10mA VCC = 5V ±10%, Internal Ref. Mid-Scale, –10mA ≤ IOUT ≤ 10mA l ±0.08 ±0.4 ±10 ±10 ±10 0.09 0.16 0.006 0.01 0.09 ROUT DC Output Impedance l 0.09 0.156 0.09 0.156 0.09 0.156 0.09 0.156 Ω 2640fb 7 LTC2640 ELECTRICAL CHARACTERISTICS SYMBOL VOUT PSR ISC PARAMETER DAC Output Span Power Supply Rejection Short-Circuit Output Current (Note 6) Sinking Sourcing Positive Supply Voltage Supply Current (Note 7) Supply Current in Power-Down Mode (Note 7) Input Voltage Range Resistance Capacitance IREF Reference Output Output Voltage Reference Temperature Coefficient Output Impedance Capacitive Load Driving Short-Circuit Current Digital I/O VIH VIL ILK CIN AC Performance tS Settling Time VCC = 5V (Note 9) ±0.39% (±1LSB at 8 Bits) ±0.098% (±1LSB at 10 Bits) ±0.024% (±1LSB at 12 Bits) 3.7 4.2 4.6 1 500 At Mid-Scale Transition External Reference 3.0 300 μs μs μs V/μs pF nV•s kHz Digital Input High Voltage Digital Input Low Voltage Digital Input Leakage Digital Input Capacitance VIN = GND to VCC (Note 8) l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2640-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2640A-HM12/-HZ12 (VFS = 4.096V) CONDITIONS External Reference Internal Reference VCC = 5V ±10% VFS = VCC = 5.5V Zero-Scale; VOUT shorted to VCC Full-Scale; VOUT shorted to GND For Specified Performance VCC = 5V, VREF = 4.096V, External Reference VCC = 5V, Internal Reference VCC = 5V, C-Grade, I-Grade VCC = 5V, H-Grade l l l l l l l l l l MIN TYP 0 to VREF 0 to 4.096 –80 27 –28 MAX UNITS V V dB 48 –48 5.5 mA mA V μA μA μA μA V kΩ pF μA V ppm/°C kΩ μF mA V Power Supply VCC ICC ISD Reference Input 0 160 190 7.5 0.005 2.032 2.048 ±10 0.5 10 VCC = 5.5V; REF Shorted to GND 2.4 0.8 ±1 2.5 4.3 0.1 2.064 VCC 220 4.5 160 200 0.6 0.6 220 270 1.8 4 Reference Current, Power-Down Mode DAC Powered Down V μA pF Voltage Output Slew Rate Capacitance Load Driving Glitch Impulse Multiplying Bandwidth 2640fb 8 LTC2640 ELECTRICAL CHARACTERISTICS SYMBOL en PARAMETER Output Voltage Noise Density The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2640-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2640A-HM12/-HZ12 (VFS = 4.096V) CONDITIONS At f = 1kHz, External Reference At f = 10kHz, External Reference At f = 1kHz, Internal Reference At f = 10kHz, Internal Reference 0.1Hz to 10Hz, External Reference 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, External Reference 0.1Hz to 200kHz, Internal Reference, CREF = 0.33μF MIN TYP 140 130 210 200 20 20 650 670 MAX UNITS nV√Hz nV√Hz nV√Hz nV√Hz μVP-P μVP-P μVP-P μVP-P Output Voltage Noise TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V. (See Figure 1) (Note 8). LTC2640-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2640A-HM12/-HZ12 (VFS = 4.096V) SYMBOL t1 t2 t3 t4 t5 t6 t7 t9 t10 PARAMETER SDI Valid to SCK Setup SDI Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK High to CS/LD High CS/LD Low to SCK High CLR Pulse Width CS/LD High to SCK Pos. Edge SCK Frequency 50% Duty Cycle CONDITIONS l l l l l l l l l l MIN 4 4 9 9 10 7 7 20 7 TYP MAX UNITS ns ns ns ns ns ns ns ns ns 50 MHz Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages are with respect to GND. Note 3: High temperatures degrade operating lifetimes. Operating lifetime is derated at temperatures greater than 105°C. Note 4: Linearity and monotonicity are defined from code kL to code 2N – 1, where N is the resolution and kL is given by kL = 0.016 • (2N/ VFS), rounded to the nearest whole code. For VFS = 2.5V and N = 12, kL = 26 and linearity is defined from code 26 to code 4,095. For VFS = 4.096V and N = 12, kL = 16 and linearity is defined from code 16 to code 4,095. Note 5: Inferred from measurement at code 16 (LTC2640-12), code 4 (LTC2640-10) or code 1 (LTC2640-8), and at full-scale. Note 6: This IC includes current limiting that is intended to protect the device during momentary overload conditions. Junction temperature can exceed the rated maximum during current limiting. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 7: Digital inputs at 0V or VCC. Note 8: Guaranteed by design and not production tested. Note 9: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. Load is 2k in parallel with 100pF to GND. Note 10: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. Note 11: Full-scale error is determined using the reference voltage measured at the REF pin. 2640fb 9 LTC2640 TYPICAL PERFORMANCE CHARACTERISTICS LTC2640-L12 (Internal Reference, VFS = 2.5V) Integral Nonlinearity (INL) 1.0 VCC = 3V 0.5 DNL (LSB) INL (LSB) 0.5 VREF (V) 1.0 VCC = 3V 1.255 TA = 25°C, unless otherwise noted. Reference Output Voltage vs Temperature 1.260 VCC = 3V Differential Nonlinearity (DNL) 0 0 1.250 –0.5 –0.5 1.245 –1.0 0 1024 2048 CODE 3072 4095 2640 G01 –1.0 0 1024 2048 CODE 3072 4095 2640 G02 1.240 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2640 G03 INL vs Temperature 1.0 VCC = 3V 0.5 INL (POS) DNL (LSB) INL (LSB) 0.5 1.0 DNL vs Temperature 2.52 VCC = 3V FS OUTPUT VOLTAGE (V) 2.51 Full-Scale Output Voltage vs Temperature VCC = 3V DNL (POS) 0 DNL (NEG) –0.5 0 INL (NEG) –0.5 2.50 2.49 –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2640 G04 –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2640 G05 2.48 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2640 G06 Settling to ±1LSB Settling to ±1LSB 3/4 SCALE TO 1/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS CS/LD 2V/DIV VOUT 1LSB/DIV 4.1μs 3.6μs VOUT 1LSB/DIV 1/4 SCALE TO 3/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 2μs/DIV 2640 G07 CS/LD 2V/DIV 2μs/DIV 2640 G08 2640fb 10 LTC2640 TYPICAL PERFORMANCE CHARACTERISTICS LTC2640-H12 (Internal Reference, VFS = 4.096V) Integral Nonlinearity (INL) 1.0 VCC = 5V 0.5 DNL (LSB) INL (LSB) 0.5 VREF (V) 1.0 VCC = 5V 2.058 TA = 25°C, unless otherwise noted. Reference Output Voltage vs Temperature 2.068 VCC = 5V Differential Nonlinearity (DNL) 0 0 2.048 –0.5 –0.5 2.038 –1.0 0 1024 2048 CODE 3072 4095 2640 G09 –1.0 0 1024 2048 CODE 3072 4095 2640 G10 2.028 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2640 G11 INL vs Temperature 1.0 VCC = 5V 0.5 INL (POS) DNL (LSB) INL (LSB) 0.5 1.0 DNL vs Temperature 4.115 VCC = 5V FS OUTPUT VOLTAGE (V) 4.105 Full-Scale Output Voltage vs Temperature VCC = 5V DNL (POS) 0 DNL (NEG) –0.5 0 INL (NEG) –0.5 4.095 4.085 –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2640 G12 –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2640 G13 4.075 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2640 G14 Settling to ±1LSB Settling to ±1LSB CS/LD 5V/DIV VOUT 1LSB/DIV 4.6μs 3.9μs VOUT 1LSB/DIV 1/4 SCALE TO 3/4 SCALE STEP VCC = 5V, VFS = 4.095V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 2μs/DIV 2640 G15 CS/LD 5V/DIV 3/4 SCALE TO 1/4 SCALE STEP VCC = 5V, VFS = 4.095V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 2μs/DIV 2640 G16 2640fb 11 LTC2640 TYPICAL PERFORMANCE CHARACTERISTICS LTC2640-10 Integral Nonlinearity (INL) 1.0 VCC = 5V VFS = 4.096V INTERNAL REF . 0.5 DNL (LSB) INL (LSB) 0.5 1.0 VCC = 5V VFS = 4.096V INTERNAL REF . TA = 25°C, unless otherwise noted. Differential Nonlinearity (DNL) 0 0 –0.5 –0.5 –1.0 0 256 512 CODE 768 1023 2640 G17 –1.0 0 256 512 CODE 768 1023 2640 G18 LTC2640-8 Integral Nonlinearity (INL) 1.0 VCC = 3V VFS = 2.5V INTERNAL REF . 0.5 DNL (LSB) INL (LSB) 0.25 0.50 VCC = 3V VFS = 2.5V INTERNAL REF . Differential Nonlinearity (DNL) 0 0 –0.5 –0.25 –1.0 –0.50 0 64 128 CODE 2640 G19 192 255 0 64 128 CODE 192 255 2640 G20 LTC2640 Load Regulation 10 8 6 4 ΔVOUT (mV) VOUT (V) 2 0 –2 –4 –6 –8 –10 –30 –20 –10 INTERNAL REF . CODE = MIDSCALE 0 10 IOUT (mA) 20 30 2630 G21 Current Limiting 0.20 0.15 0.10 0.05 0 3 VCC = 5V (LTC2640-H) VCC = 5V (LTC2640-L) VCC = 3V (LTC2640-L) OFFSET ERROR (mV) 2 1 0 –1 –2 INTERNAL REF . CODE = MIDSCALE –20 –10 0 10 IOUT (mA) 20 30 2630 G22 Offset Error vs Temperature VCC = 5V (LTC2640-H) VCC = 5V (LTC2640-L) VCC = 3V (LTC2640-L) –0.05 –0.10 –0.15 –0.20 –30 –3 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2640 G23 2640fb 12 LTC2640 TYPICAL PERFORMANCE CHARACTERISTICS LTC2640 Gain Error vs VCC 0.4 0.3 GAIN ERROR (%FSR) 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 2.5 3 3.5 4 VCC (V) 2640 G24 TA = 25°C, unless otherwise noted. Gain Error vs Temperature EXTERNAL REF . VREF = 2.5V GAIN ERROR (%FSR) 0.4 0.3 0.2 0.1 0.0 –0.1 –0.2 –0.3 4.5 5 5.5 –0.4 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2640 G25 Large-Signal Response EXTERNAL REF . VREF = 2.5V VOUT 0.5V/DIV VFS = VCC = 5V 1/4 SCALE TO 3/4 SCALE 2μs/DIV 2640 G26 Mid-Scale-Glitch Impulse Power-On Reset Glitch 5.0 LTC2640-L 4.5 4.0 Headroom at Rails vs Output Current 5V SOURCING CS/LD 5V/DIV LTC2640-H12, VCC = 5V: 3.0nV-s TYP VOUT 5mV/DIV LTC2640-L12, VCC = 3V: 2.1nV-s TYP 2μs/DIV 2640 G27 VCC 2V/DIV VOUT (V) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 200μs/DIV 2640 G28 3V (LTC2640-L) SOURCING ZERO-SCALE VOUT 2mV/DIV 5V SINKING 3V (LTC2640-L) SINKING 0 1 2 3 456 IOUT (mA) 7 8 9 10 0 2640 G29 Exiting Power-Down to Mid-Scale 1.4 CS/LD 2V/DIV ICC (mA) 1.2 1.0 0.8 0.6 0.4 0.2 LTC2640-H 0.0 4μs/DIV 2640 G30 Supply Current vs Logic Voltage SWEEP SCK, SDI, CS/LD AND CLR BETWEEN 0V AND VCC VOUT 1V/DIV Hardware CLR VOUT 0.5V/DIV VCC = 5V VCC = 3V (LTC2640-L) CLR 5V/DIV LTC2640-LZ 4 5 2640 G31 0 1 3 2 LOGIC VOLTAGE (V) 1μs/DIV 2640 G32 2640fb 13 LTC2640 TYPICAL PERFORMANCE CHARACTERISTICS LTC2640 Multiplying Bandwidth 0 –2 NOISE VOLTAGE (nV/√Hz) –4 –6 dB –8 –10 –12 –14 VCC = 5V VREF(DC) = 2V –16 VREF(AC) = 0.2VP-P CODE = FULL SCALE –18 100k 10k 1k FREQUENCY (Hz) 400 500 TA = 25°C, unless otherwise noted. Noise Voltage vs Frequency INTERNAL REF . CODE = MIDSCALE 0.1Hz to 10Hz Voltage Noise LTC2640-L, VCC = 4V INTERNAL REF . CODE = MIDSCALE 300 LTC2640-H (VCC = 5V) 10μV/DIV 200 100 LTC2640-L (VCC = 4V) 1000k 2640 G33 0 100 1k 10k FREQUENCY (Hz) 100k 1M 2640 G34 1s/DIV 2640 G35 PIN FUNCTIONS CS/LD (Pin 1): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on SDI into the register. When CS/LD is taken high, SCK is disabled and the specified command (see Table 1) is executed. SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL compatible. SDI (Pin 3): Serial Interface Data Input. Data on SDI is clocked into the DAC on the rising edge of SCK. The LTC2640 accepts input word lengths of either 24- or 32-bits. GND (Pin 4): Ground. VCC (Pin 5): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V (LTC2640-L) or 4.5V ≤ VCC ≤ 5.5V (LTC2640-H). Bypass to GND with a 0.1μF capacitor. REF (Pin 6): Reference Voltage Input or Output. When External Reference mode is selected, REF is an input (0V ≤ VREF ≤ VCC) where the voltage supplied sets the full-scale voltage. When Internal Reference is selected, the 10ppm/°C 1.25V (LTC2640-L) or 2.048V (LTC2640-H) internal reference is available at the pin. This output may be bypassed to GND with up to 10μF (0.33μF is recommended), and must be buffered when driving external DC load current. VOUT (Pin 7): DAC Analog Voltage Output. CLR (Pin 8, LTC2640-Z): Asynchronous Clear Input. A logic low at this level-triggered input clears all registers and causes the DAC voltage output to reset to Zero. CMOS and TTL compatible. REF_SEL (Pin 8, LTC2640-M): Selects default Reference at power-up. Tie to VCC to select the Internal Reference, or GND to select an External Reference. After power-up, the logic state at this pin is ignored and the reference may be changed only by software command. 2640fb 14 LTC2640 BLOCK DIAGRAMS LTC2640-Z VCC INTERNAL REFERENCE SDI REF SWITCH SCK CONTROL DECODE LOGIC 24-BIT SHIFT REGISTER RESISTOR DIVIDER DACREF CS/LD INPUT REGISTER DAC REGISTER DAC VOUT CLR GND LTC2640-M VCC INTERNAL REFERENCE SDI REF REF_SEL SWITCH SCK CONTROL DECODE LOGIC 24-BIT SHIFT REGISTER RESISTOR DIVIDER DACREF CS/LD INPUT REGISTER DAC REGISTER DAC VOUT GND 2640 BD 2640fb 15 LTC2640 TIMING DIAGRAM t1 t2 SCK 1 t3 2 t4 3 23 t6 24 t10 SDI t5 CS/LD 2640 F01 t7 Figure 1. Serial Interface Timing 2640fb 16 LTC2640 OPERATION The LTC2640 is a family of single voltage-output DACs in 8-lead ThinSOT packages. Each DAC can operate railto-rail using an external reference, or with its full-scale voltage set by an integrated reference. 12 combinations of accuracy (12-, 10-, and 8-bit), power-on reset value (zero or mid-scale), and full-scale voltage (2.5V or 4.096V) are available. The LTC2640 is controlled using a 3-wire SPI/MICROWIRE compatible interface. Power-On Reset The LTC2640-HZ/LTC2640-LZ clear the output to zero-scale when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2640 contains circuitry to reduce the power-on glitch: the analog output typically rises less than 5mV above zeroscale during power on if the power supply is ramped to 5V in 1ms or more. In general, the glitch amplitude decreases as the power supply ramp time is increased. See “Power-On Reset Glitch” in the Typical Performance Characteristics section. The LTC2640-HM/LTC2640-LM provide an alternative reset, setting the output to mid-scale when power is first applied. Default reference mode selection is described in the Reference Modes section. Power Supply Sequencing The voltage at REF (Pin 6) should be kept within the range –0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 5) is in transition. Transfer Function The digital-to-analog transfer function is: VOUT(IDEAL) = k 2N VREF where k is the decimal equivalent of the binary DAC input code, N is the resolution, and VREF is either 2.5V (LTC2640LM/LTC2640-LZ) or 4.096V (LTC2640-HM/LTC2640-HZ) when in Internal Reference mode, and the voltage at REF (Pin 6) when in External Reference mode. INPUT WORD (LTC2640-12) COMMAND C3 C2 C1 C0 4 DON'T-CARE BITS X X X X D11 D10 MSB INPUT WORD (LTC2640-10) COMMAND C3 C2 C1 C0 4 DON'T-CARE BITS X X X X D9 MSB INPUT WORD (LTC2640-8) COMMAND C3 C2 C1 C0 4 DON'T-CARE BITS X X X X D7 MSB D6 D5 D4 D3 DATA (8 BITS + 8 DON'T-CARE BITS) D2 D1 D0 LSB X X X X X X X X 2640 F02 DATA (12 BITS + 4 DON'T-CARE BITS) D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB X X X X DATA (10 BITS + 6 DON'T-CARE BITS) D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB X X X X X X Figure 2. Command and Data Input Format 2640fb 17 LTC2640 OPERATION Serial Interface The CS/LD input is level triggered. When this input is taken low, it acts as a chip-select signal, enabling the SDI and SCK buffers and the input shift register. Data (SDI input) is transferred at the next 24 rising SCK edges. The 4-bit command, C3-C0, is loaded first, followed by 4 don’t-cares bits, and finally the 16-bit data word. The data word comprises the 12-, 10- or 8-bit input code, ordered MSB-to-LSB, followed by 4, 6 or 8 don’t-cares bits (LTC2640-12, LTC2640-10 and LTC2640-8 respectively; see Figure 2). Data can only be transferred to the device when the CS/LD signal is low, beginning on the first rising edge of SCK. SCK may be high or low at the falling edge of CS/LD. The rising edge of CS/LD ends the data transfer and causes the device to execute the command specified in the 24-bit input sequence. The complete sequence is shown in Figure 3a. The command (C3-C0) assignments are shown in Table 1. The first three commands in the table consist of write and update operations. A Write operation loads a 16-bit data word from the 24-bit shift register into the input register. In an Update operation, the input register is copied to the DAC register and converted to an analog voltage at the DAC output. Write to and Update combines the first two commands. The Update operation also powers up the DAC if it had been in power-down mode. The data path and registers are shown in the Block Diagram. Table 1. Command Codes COMMAND* C3 0 0 0 0 0 0 C2 0 0 0 1 1 1 C1 0 0 1 0 1 1 C0 0 1 1 0 0 1 Write to Input Register Update (Power-Up) DAC Register Write to and Update (Power-Up) DAC Register Power Down Select Internal Reference Select External Reference While the minimum input sequence is 24-bits, it may optionally be extended to 32-bits to accommodate microprocessors that have a minimum word width of 16-bits (2-bytes). To use the 32-bit width, 8 don’t-cares bits are transferred to the device first, followed by the 24-bit sequence described. Figure 3b shows the 32-bit sequence. The 16-bit data word is ignored for all commands that do not include a Write operation. Reference Modes For applications where an accurate external reference is not available, the LTC2640 has a user-selectable, integrated reference. The LTC2640-LM/LTC2640-LZ provide a fullscale output of 2.5V. The LTC2640-HM/LTC2640-HZ provide a full-scale output of 4.096V. The internal reference can be useful in applications where the supply voltage is poorly regulated. Internal Reference mode can be selected by using command 0110, and is the power-on default for LTC2640HZ/LTC2640-LZ, as well as for LTC2640-HM/LTC2640-LM when REF_SEL is tied high. The 10ppm/°C, 1.25V (LTC2640-LM/LTC2640-LZ) or 2.048V (LTC2640-HM/LTC2640-HZ) internal reference is available at the REF pin. Adding bypass capacitance to the REF pin will improve noise performance; 0.33μF is recommended, and up to 10μF can be driven without oscillation. This output must be buffered when driving an external DC load current. Alternatively, the DAC can operate in External Reference mode using command 0111. In this mode, an input voltage supplied externally to the REF pin provides the reference (0V ≤ VREF ≤ VCC) and the supply current is reduced. External Reference mode is the power-on default for LTC2640-HM/LTC2640-LM when REF_SEL is tied low. The reference mode of LTC2640-HZ/LTC2640-LZ can be changed only by software command. The same is true for LTC2640-HM/LTC2640-LM after power-on, after which the logic state on REF_SEL is ignored. *Command codes not shown are reserved and should not be used 2640fb 18 LTC2640 OPERATION Power-Down Mode For power-constrained applications, the LTC2640’s powerdown mode can be used to reduce the supply current whenever the DAC output is not needed. When in powerdown, the buffer amplifier, bias circuit, and reference circuit are disabled and draw essentially zero current. The DAC output is put into a HIGH-impedance state, and the output pin is passively pulled to ground through a 200k resistor. Input and DAC register contents are not disturbed during power-down. The DAC can be put into power-down mode by using command 0100. The supply current is reduced to 1.8μA maximum (C and I grades) and the REF pin becomes HIGH impedance (typically > 1GΩ). Normal operation resumes after executing any command that includes a DAC update, as shown in Table 1. The DAC is powered up and its voltage output is updated. Normal settling is delayed while the bias, reference, and amplifier circuits are re-enabled. When the REF pin output is bypassed to GND with 1nF or less, the power-up delay time is 20μs for settling to 12-bits. This delay increases to 200μs for 0.33μF, and 10ms for 10μF. Voltage Output The LTC2640’s integrated rail-to-rail amplifier has guaranteed load regulation when sourcing or sinking up to 10mA at 5V, and 5mA at 3V. Load regulation is a measure of the amplifier’s ability to maintain the rated voltage accuracy over a wide range of load current. The measured change in output voltage per change in forced load current is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to ohms. The amplifier’s DC output impedance is 0.1Ω when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 50Ω typical channel resistance of the output devices (e.g., when sinking 1mA, the minimum output voltage is 50Ω • 1mA, or 50mV). See the graph “Headroom at Rails vs. Output Current” in the Typical Performance Characteristics section. The amplifier is stable driving capacitive loads of up to 500pF. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog output of the DAC cannot go below ground, it may limit the lowest codes, as shown in Figure 4b. Similarly, limiting can occur near full-scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC, as shown in Figure 4c. No full-scale limiting can occur if VREF is less than VCC – FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. Board Layout The PC board should have separate areas for the analog and digital sections of the circuit. A single, solid ground plane should be used, with analog and digital signals carefully routed over separate areas of the plane. This keeps digital signals away from sensitive analog signals and minimizes the interaction between digital ground currents and the analog section of the ground plane. The resistance from the LTC2640 GND pin to the ground plane should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.1Ω). Note that the LTC2640 is no more susceptible to 2640fb 19 LTC2640 OPERATION this effect than any other parts of this type; on the contrary, it allows layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. Another technique for minimizing errors is to use a separate power ground return trace on another board layer. The trace should run between the point where the power supply is connected to the board and the DAC ground pin. Thus the DAC ground pin becomes the common point for analog ground, digital ground, and power ground. When the LTC2640 is sinking large currents, this current flows out the ground pin and directly to the power ground trace without affecting the analog ground plane voltage. It is sometimes necessary to interrupt the ground plane to confine digital ground currents to the digital portion of the plane. When doing this, make the gap in the plane only as long as it needs to be to serve its purpose and ensure that no traces cross over the gap. 2640fb 20 OPERATION CS/LD 1 2 7 13 14 17 D3 D2 D1 D0 X X X X 2640 F03a SCK 3 4 10 21 23 D10 DATA WORD D9 D8 D7 D6 D5 D4 11 12 18 24 16 20 22 C0 4 DON’T-CARE BITS X X X X D11 5 6 8 9 15 19 C1 C3 COMMAND WORD C2 SDI 24-BIT INPUT WORD Figure 3a. LTC2640-12 24-Bit Load Sequence (Minimum Input Word). LTC2640-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Cares Bits; LTC2640-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Cares Bits CS/LD 6 7 13 14 17 D11 D10 D9 X X X X 4 DON’T-CARE BITS X COMMAND WORD X C3 C2 C1 C0 8 9 10 11 12 18 16 15 19 X 20 D8 21 D7 22 D6 23 D5 24 D4 25 D3 DATA WORD 2640 F03b SCK 1 2 3 4 5 26 D2 27 D1 28 D0 29 X 30 X 31 X 32 X SDI X X X X X 8 DON’T-CARE BITS 32-BIT INPUT WORD Figure 3b. LTC2640-12 32-Bit Load Sequence LTC2640-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Cares Bits; LTC2640-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Cares Bits LTC2640 21 2640fb LTC2640 OPERATION VREF = VCC POSITIVE FSE VREF = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (c) 0V 0 2,048 INPUT CODE (a) 4,095 2640 F04 OUTPUT VOLTAGE 0V NEGATIVE OFFSET INPUT CODE (b) Figure 4. Effects of Rail-to-Rail Operation on a DAC Transfer Curve (Shown for 12-Bits) (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero (c) Effect of Positive Full-Scale Error for Codes Near Full-Scale 2640fb 22 LTC2640 PACKAGE DESCRIPTION TS8 Package 8-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1637) 0.52 MAX 0.65 REF 2.90 BSC (NOTE 4) 1.22 REF 3.85 MAX 2.62 REF 1.4 MIN 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.65 BSC 0.22 – 0.36 8 PLCS (NOTE 3) 0.80 – 0.90 0.20 BSC 1.00 MAX DATUM ‘A’ 0.01 – 0.10 0.30 – 0.50 REF NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 0.09 – 0.20 (NOTE 3) 1.95 BSC TS8 TSOT-23 0802 2640fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC2640 TYPICAL APPLICATION Programmable ±5V Output 5V 5V 4 0.1μF 3 56 VCC REF 8 REF_SEL 3 SDI LTC2640A VOUT 7 2 SCK -LM12 1 CS/LD GND 4 5 0.1μF 1 8 M9 9 M3 10 M1 1 P1 2 P3 3 P9 10V 7 VCC LT1991 REF VEE 4 0.1μF 6 – LTC2054 + 2 SERIAL BUS OUT 5 VOUT = ±5V 0.1μF –10V 2640 TA03 RELATED PARTS PART NUMBER LTC1663 LTC1669 LTC2360-LTC2362/ LTC2365-LTC2366 LTC2450/LTC2452 LTC2451/LTC2453 LTC2600/LTC2610/LTC2620 LTC2601/LTC2611/LTC2621 LTC2602/LTC2612/LTC2622 LTC2604/LTC2614/LTC2624 LTC2605/LTC2615/LTC2625 LTC2606/LTC2616/LTC2626 LTC2609/LTC2619/LTC2629 LTC2630 LTC2631 DESCRIPTION Single 10-Bit VOUT DAC in SOT-23 Single 10-Bit VOUT DAC in SOT-23 12-Bit SAR ADCs in TSOT23-6/TSOT23-8 Packages 16-Bit Single-Ended/Differential Delta Sigma ADCs 16-Bit Single-Ended/Differential Delta Sigma ADCs Octal 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP Octal 16-/14-/12-Bit VOUT DACs with I2C Interface Single 16-/14-/12-Bit VOUT DACs with I2C Interface Quad 16-/14-/12-Bit VOUT DACs with I2C Interface Single 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference in SC70 Single 12-/10-/8-Bit I2C VOUT DACs with 10ppm/°C Reference in ThinSOT COMMENTS VCC = 2.7V to 5.5V, 60μA, Internal Reference, SMBus Interface VCC = 2.7V to 5.5V, 60μA, Internal Reference, I2C Interface 100ksps/250ksps/500ksps/1Msps/3Msps Output Rates SPI Interface, Tiny DFN Packages, 60Hz Output Rate I2C Interface, Tiny DFN and TSOT23-8 Packages, 60Hz Output Rate 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, I2C Interface 270μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, I2C Interface 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output with Separate VREF Pins for Each DAC 180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, Rail-to-Rail Output, SPI Interface 180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, Selectable External Ref. Mode, Rail-to-Rail Output, I2C Interface 2640fb 24 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 1108 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008