LTC3823IGNPBF

FEATURES n n n n n n n n n n n n n n n n n n LTC3823 Fast No RSENSETM Step-Down Synchronous DC/DC Controller with Differential Output Sensing, Tracking and PLL DESCRIPTION The LTC®3823 is a synchronous step-down switching regulator controller with true remote differential output sensing and output voltage up/down tracking capability. Its advanced functions and high accuracy reference are ideal for powering high performance server, ASIC and computer memory systems. The LTC3823 uses a constant on-time, valley current mode control architecture to deliver very low duty factors without requiring a sense resistor. The operating frequency is selected by an external resistor and is compensated for variations in input supply voltage. An internal phase-locked loop allows the IC to be synchronized to an external clock. Fault protection is provided by an overvoltage comparator and input undervoltage lockout. The regulator current limit is user programmable. A wide supply range allows voltages as high as 36V to be stepped down to as low as a 0.6V output. When using remote sense, output voltages up to 3.3V can be developed, and up to 90% of VIN without remote sense. Power supply sequencing is accomplished using an external soft-start timing capacitor. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611. Wide VIN Range: 4.5V to 36V ± 0.67%, 0.6V Reference Voltage Output Voltage Tracking Capability True Remote Sensing Differential Amplifier Sense Resistor Optional True Current Mode Control 2% to 90% Duty Cycle at 200kHz tON(MIN) < 100ns Phase-Locked Loop Frequency Synchronization Powerful Dual N-Channel MOSFET Driver Adjustable Cycle-by-Cycle Current Limit Adjustable Switching Frequency Programmable Soft-Start Current Foldback Protection (Disabled at Start-Up) Output Overvoltage Protection Micropower Shutdown: 30μA Power Good Output Voltage Monitor Tracks the Reference Input Pin Available in (5mm × 5mm) 32-Lead QFN and 28-Lead SSOP Narrow Packages APPLICATIONS n n Distributed Power Systems Server Power Supplies TYPICAL APPLICATION High Efficiency Step-Down Converter PGOOD 0.01μF 10k PLLFLTR PLLIN 0.1μF TRACK/SS ITH 1000pF 10k SGND RUN VON VRNG VDIFFOUT 9.5k VFB 3k LTC3823 INTVCC DRVCC BG SENSE+ SENSE– PGND VOUTSENSE+ VOUTSENSE– 3823 TA01a Efficiency and Power Loss vs Load Current 97 10 VIN = 5V VOUT = 2.5V FIGURE 12 CIRCUIT POWER LOSS (W) EFFICIENCY 1 10μF 35V 3 VIN 5V TO 28V VOUT 2.5V 10A ION VIN TG SW 68k Si4884 1.8μH 0.22μF 96 95 EFFICIENCY (%) 94 93 92 91 90 BOOST CMDSH-3 + 180μF 4V 2 POWER LOSS 0.1 VOUT Si4874 10μF B340A 89 88 87 0.1 1 LOAD CURRENT (A) 10 3823 TA01b 0.01 3823fd 1 LTC3823 ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltages Input Supply Voltage VIN , VINSNS.................................................... –0.3V to 36V DRVCC, (BOOST – SW) ............................–0.3V to 7V BOOST ................................................... –0.3V to 42V SENSE+, SW Voltage .................................–5V to 36V TRACK/SS, FCB, Z0, Z1/SSENABLE, Z2, PLLIN, VOUTSENSE+, VOUTSENSE– Voltages .................................. –0.3V to (INTVCC + 0.3)V VON , VRNG , PGOOD Voltages .. –0.3V to (INTVCC + 0.3)V VDIFFOUT ................................................–0.3V to INTVCC RUN, ION .................................................... –0.3V to 12V PLLFLTR, ITH , VFB Voltages ...................... –0.3V to 2.7V INTVCC , ZVCC Voltages ................................–0.3V to 7V TG, BG, INTVCC Peak Currents ....................................4A TG, BG, INTVCC RMS Currents...............................50mA Operating Temperature Range .................–40°C to 85°C Junction Temperature (Note 2) ............................. 125°C Storage Temperature Range .................. –65°C to 125°C Lead Temperature (Soldering, 10 sec) SSOP ................................................................ 300°C PIN CONFIGURATION PGOOD TOP VIEW FCB RUN VON PGOOD VRNG VFB ITH SGND ION VOUTSENSE+ 1 2 3 4 5 6 7 8 9 28 Z0 27 BOOST 26 TG 25 SW 24 SENSE+ 23 SENSE– 22 PGND 21 BG 20 INTVCC 19 Z2 18 Z1/SSENABLE 17 ZVCC 16 VIN 15 PLLIN VRNG 1 VFB 2 ITH 3 SGND 4 ION 5 VDIFFOUT 6 NC 7 VOUTSENSE+ 8 9 10 11 12 13 14 15 16 VOUTSENSE– NC TRACK/SS PLLFLTR PLLIN VIN VINSNS ZVCC 33 SGND TOP VIEW BOOST RUN VON FCB SW 24 SENSE+ 23 SENSE– 22 PGND 21 BG 20 DRVCC 19 INTVCC 18 Z2 17 Z1/SSENABLE TG Z0 32 31 30 29 28 27 26 25 VDIFFOUT 10 11 VOUTSENSE– 12 TRACK/SS 13 PLLFLTR 14 GN PACKAGE 28-LEAD PLASTIC SSOP NARROW TJMAX = 125°C, θJA = 80°C/W UH PACKAGE 32-LEAD (5mm 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD (PIN 33) IS SGND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LTC3823EGN#PBF LTC3823IGN#PBF LTC3823EUH#PBF LTC3823IUH#PBF TAPE AND REEL LTC3823EGN#TRPBF LTC3823IGN#TRPBF LTC3823EUH#TRPBF LTC3823IUH#TRPBF PART MARKING* LTC3823EGN LTC3823IGN 3823 3823 PACKAGE DESCRIPTION 28-Lead Plastic SSOP Narrow 28-Lead Plastic SSOP Narrow 32-Lead (5mm × 5mm) Plastic QFN 32-Lead (5mm × 5mm) Plastic QFN TEMPERATURE RANGE –40°C to 85°C –40°C to 85°C –40°C to 85°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3823fd 2 LTC3823 ELECTRICAL CHARACTERISTICS SYMBOL IQ VFB VFB(LINEREG) VFB(LOADREG) VRUN ISS/TRACK IFB gm(EA) VFCB IFCB tON tON(MIN) tOFF(MIN) VSENSE(MAX) PARAMETER Input DC Supply Current Feedback Voltage Accuracy (Note 3) Feedback Voltage Line Regulation Feedback Voltage Load Regulation RUN Pin On Threshold Soft-Start Charge Current Feedback Pin Input Current Error Amplifier Transconductance Forced Continuous Threshold Forced Continuous Pin Current On-Time Minimum On-Time Minimum Off-Time Maximum Current Sense Threshold VRNG = 1V, VFB = 570mV (0°C to 85°C) VRNG = 0V, VFB = 570mV (0°C to 85°C) VRNG = INTVCC , VFB = 570mV (0°C to 85°C) VRNG = 1V, VFB = 630mV VRNG = 0V, VFB = 630mV VRNG = INTVCC , VFB = 630mV 8 VIN Falling VIN Rising TG High TG Low BG High BG Low CLOAD = 3300pF CLOAD = 3300pF CLOAD = 3300pF CLOAD = 3300pF 6V < VIN < 36V ICC = 0mA to 20mA l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 15V unless otherwise specified. CONDITIONS Normal Operation Shutdown Supply Current ITH = 1.2V (0°C to 85°C) ITH = 1.2V VIN = 4.5V to 30V, ITH = 1.2V (Note 3) ITH = 0.5V to 1.9V (Note 3) VRUN Rising VSS/TRACK = 0V ITH = 1.2V (Note 3) VFCB = 0V ION = –60μA, VON = 1.5V ION = –60μA, VON = 0V ION = –180μA, VON = 0V 120 50 240 210 80 l l l MIN TYP 1400 30 MAX 2200 50 0.604 0.606 –0.3 1.9 –2.3 100 0.63 –2 290 150 100 400 160 85 320 UNITS μA μA V V %/V % V μA nA mS V μA ns ns ns ns mV mV mV mV mV mV Main Control Loop 0.596 0.594 0.6 0.6 0.002 –0.04 1 –1.3 –100 0.57 1.5 –1.7 –20 1.65 0.6 –1 250 115 50 280 140 70 280 – 60 – 30 –120 11 3.1 3.9 1.9 1.2 1.9 0.7 20 20 20 20 VSENSE(MIN) Minimum Current Sense Threshold ΔVFB(OV) VIN(UVLO+) VIN(UVLO–) TG RUP TG RDOWN BG RUP BG RDOWN TG tr TG tf BG tr BG tf VINTVCC ΔVLDO(LOADREG) RPLLIN IPLLFLTR Output Overvoltage Fault Threshold Offset Undervoltage Lockout Undervoltage Lockout TG Driver Pull-Up On-Resistance TG Driver Pull-Down On-Resistance BG Driver Pull-Up On-Resistance BG Driver Pull-Down On-Resistance TG Rise Time TG Fall Time BG Rise Time BG Fall Time Internal VCC Voltage Internal VCC Load Regulation PLLIN Input Resistance Phase Detector Sink Current Phase Detector Source Current fPLLIN < fO fPLLIN > fO 14 3.4 4.1 2.5 2.5 3 1.5 % V V Ω Ω Ω Ω ns ns ns ns Internal VCC Regulation 4.75 5 – 0.1 50 –15 15 5.45 ±2 V % kΩ μA μA Phase-Locked Loop 3823fd 3 LTC3823 ELECTRICAL CHARACTERISTICS SYMBOL PGOOD Output ΔVFBH ΔVFBL ΔVFB(HYS) VPGL ADA RIN VOS PSRROA ICL VOUT(MAX) GBW TSD THYST PGOOD Upper Threshold PGOOD Lower Threshold PGOOD Hysteresis PGOOD Low Voltage Gain Input Resistance Input Offset Voltage Power Supply Rejection Ratio Maximum Output Current Maximum Output Voltage Gain Bandwidth Product Shutdown Temperature Thermal Hysteresis IDIFFOUT = 300μA IDIFFOUT = 1mA Rising l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 15V unless otherwise specified. PARAMETER CONDITIONS VFB Rising VFB Falling VFB Returning IPGOOD = 5mA l MIN 8 –8 TYP 11 –11 1.5 0.15 MAX 14 –14 3 0.4 1.0035 2 UNITS % % % V V/V kΩ mV dB mA V MHz °C °C Differential Sensing Amplifier 0.9965 1.000 80 Measured at VOUTSENSE+ Input VOUTSENSE+ = VDIFFOUT = 1.5V, IDIFFOUT = 1mA 6V < VIN < 30V 3.775 90 3 4 3.5 170 15 Thermal Shutdown Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC3823GN: TJ = TA + (PD • 80°C/W) LTC3823UH: TJ = TA + (PD • 34°C/W) Note 3: The LTC3823 is tested in a feedback loop that servos VFB to achieve a specified error amplifier output voltage (ITH). Note 4: The LTC3823E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3823I is guaranteed over the full –40°C to 85°C operating temperature range. TYPICAL PERFORMANCE CHARACTERISTICS Current Sense Threshold vs ITH Voltage 300 CURRENT SENSE THRESHOLD (mV) 250 200 ON-TIME (ns) ON-TIME (ns) 150 100 50 0 –50 0.5V 1V 0.7V 1000 VRNG = 2V 1.4V 10000 On-Time vs ION Current VON = 0V 800 700 600 500 400 300 200 100 10 0 0 10 20 30 40 50 60 70 80 90 100 ION CURRENT (μA) 3823 G02 On-Time vs VON Voltage IION = 60μA 100 –100 0 0.5 1.5 1 ITH VOLTAGE (V) 2 2.5 2823 G01 –150 0 0.5 1 1.5 2 2.5 3 3.5 VON VOLTAGE (V) 4 4.5 5 3823 G03 3823fd 4 LTC3823 TYPICAL PERFORMANCE CHARACTERISTICS On-Time vs Temperature 250 245 240 235 ON-TIME (ns) 230 225 220 215 210 205 200 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 MAX CURRENT SENSE THRESHOLD (mV) IION = 30μA VON = 0V 300 MAX CURRENT SENSE THRESHOLD (mV) Maximum Current Sense Threshold vs VRNG Voltage 150 145 140 135 130 125 120 115 110 105 Maximum Current Sense Threshold vs Temperature VRNG = 1V 250 200 150 100 50 0.5 0.75 1 1.25 1.5 VRNG VOLTAGE (V) 1.75 2 100 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3823 G04 3823 G05 3823 G06 Error Amplifier gm vs Temperature 1.8 2.5 Input Current vs Input Voltage 60 50 Shutdown Current vs Input Voltage 1.7 gm (mS) SHUTDOWN CURRENT (μA) INPUT CURRENT (mA) 2.0 40 30 20 10 1.6 1.5 1.5 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 1.0 0 5 25 10 15 20 INPUT VOLTAGE, VIN (V) 30 3823 G08 0 0 5 25 10 15 20 INPUT VOLTAGE, VIN (V) 30 3823 G09 3823 G07 INTVCC Load Regulation 0 –0.1 –0.2 –0.3 ΔINTVCC (%) –0.4 –0.5 –0.6 –0.7 –0.8 –0.9 –1.0 0 5 10 15 20 25 30 35 40 45 50 INTVCC LOAD CURRENT (mA) 3823 G10 FCB Pin Current vs Temperature –1.00 –1.05 –1.10 FCB PIN CURRENT (μA) –1.15 –1.20 –1.25 –1.30 –1.35 –1.40 –1.45 –1.50 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 TRACK/SS AND VFB 500mV/DIV VOUT 2V/DIV Track Up FIGURE 12 CIRCUIT TRACK/SS VFB VOUT 250ms/DIV 3823 G12 3823 G11 3823fd 5 LTC3823 TYPICAL PERFORMANCE CHARACTERISTICS Track Down FIGURE 12 CIRCUIT TRACK/SS TRACK/SS AND VFB 500mV/DIV VFB VOUT IL 5A/DIV STEP 0A TO 10A 250ms/DIV 3823 G13 Transient Response FIGURE 12 CIRCUIT VOUT 100mV/DIV EFFICIENCY (%) 100 95 90 85 80 75 70 65 20μs/DIV 3823 G14 Efficiency vs Load Current FIGURE 12 CIRCUIT DISCONTINUOUS MODE CONTINUOUS MODE VOUT 2V/DIV 60 55 50 0.1 1 LOAD CURRENT (A) 10 3823 G15 ITH Voltage vs Load Current 1400 FIGURE 12 CIRCUIT 1200 ITH VOLTAGE (mV) FREQUENCY (kHz) 1000 CONTINUOUS MODE 800 600 DISCONTINUOUS MODE 400 200 0 0 1 2 7 3 456 LOAD CURRENT (A) 8 9 360 340 320 Frequency vs Input Voltage 100 ILOAD = 10A Efficiency vs Input Voltage FCB = 5V 98 FIGURE 12 CIRCUIT 96 EFFICIENCY (%) 94 92 90 88 86 84 ILOAD = 1A ILOAD = 10A ILOAD = 1A 300 280 260 240 FCB = 0V FIGURE 12 CIRCUIT 0 5 10 15 INPUT VOLTAGE (V) 20 25 3823 G17 82 80 0 5 15 10 INPUT VOLTAGE (V) 20 25 3823 G18 10 3823 G16 Frequency vs Load Current MAXIMUM CURRENT SENSE THRESHOLD (mV) 400 350 300 FREQUENCY (kHz) DISCONTINUOUS MODE 250 200 150 100 50 0 0 1 2 34567 LOAD CURRENT (A) 8 9 10 CONTINUOUS MODE FIGURE 12 CIRCUIT 160 140 120 100 80 60 40 20 0 Current Limit Foldback VRNG = 1V 140 120 ION CURRENT (μA) 100 80 60 40 20 0 0 0.1 0.2 0.3 VFB (V) 0.4 0.5 0.6 3823 G20 ION Current vs VIN RON = 82k 0 5 20 15 25 10 INPUT VOLTAGE, VIN (V) 30 35 3823 G21 3823 G19 3823fd 6 LTC3823 PIN FUNCTIONS (UH/GN) VRNG (Pin 1/Pin 5): Sense Voltage Range Input. The voltage at this pin is ten times the nominal sense voltage at maximum output current and can be set from 0.5V to 2V by a resistive divider from INTVCC . The nominal sense voltage defaults to 50mV when this pin is tied to ground and 200mV when tied to INTVCC . Do not set this voltage between 0.5V to ground and 2V to INTVCC . VFB (Pin 2/Pin 6): Error Amplifier Feedback Input. This pin connects the error amplifier input to an external resistive divider from VOUT. ITH (Pin 3/Pin 7): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V with 0.75V corresponding to zero sense voltage (zero current). SGND (Pin 4/Pin 8): Signal Ground. All small-signal components and compensation components should connect to this ground, which in turn, connects to PGND at one point. ION (Pin 5/Pin 9): On-Time Current Input. Tie a resistor from this pin to ground to set the one-shot timer current and thereby, set the switching frequency. VDIFFOUT (Pin 6/Pin 10): Output of Remote Sensing Differential Amplifier. Connect this to VFB directly or through a resistive divider. VOUTSENSE + (Pin 8/Pin 11): This is the positive sense pin for the remote sense differential amplifier. Connect this pin to the positive terminal of the output load capacitor. VOUTSENSE – (Pin 9/Pin 12): This is the negative sense pin for the remote sense differential amplifier. Connect this pin to the negative terminal of the output load capacitor. NC (Pins 7, 10, UH Package): No Connect. TRACK/SS (Pin 11/Pin 13): Output Voltage Tracking and Soft-Start Input. When the IC is configured to be the master of two outputs, a capacitor to ground at this pin sets the ramp rate for the output voltage. When the IC is configured to be the slave of two outputs, the VFB voltage of the master IC is reproduced by a resistive divider and applied to this pin during the soft-start phase. An internal 1.7μA soft-start current is charging this pin during the soft-start phase. PLLFLTR (Pin 12/Pin 14): The phase-locked loop’s lowpass filter is tied to this pin. The voltage at this pin defaults to 1.180V when the IC is not synchronized with an external clock at the PLLIN pin. PLLIN (Pin 13/Pin 15): External Synchronization Input to Phase Detector. This pin is internally terminated to SGND with a 50k resistor. VIN (Pin 14/Pin 16): Main Input Supply. Decouple this to PGND with a capacitor (0.1μF to 1μF). VINSNS (Pin 15, UH Package): VIN Voltage Sense Input. Normally this pin is tied to VIN. However, in certain applications when the IC is powered from a separate supply, VINSNS is tied to the upper MOSFET supply to sense the VIN voltage. This pin is co-bonded with VIN in the GN package. ZVCC (Pin 16/Pin 17): Post-Package Zener Trim Supply. Under normal conditions this pin should always be connected to INTVCC . Z1/SSENABLE (Pin 17/Pin 18): Post-Package Zener Trim Control. This pin is a multifunctional pin used in production for post-package trimming and tracking. Ground this pin under normal soft-start operation. Connecting this pin to INTVCC will turn off the soft-start current during tracking. Z2 (Pin 18/Pin 19): Post-Package Zener Trim Control. This pin is used in production for post-package trimming. Ground this pin under normal operation. INTVCC (Pin 19/Pin 20): Internal 5V Regulated Output. The control circuits are powered from this voltage. Decouple this pin to PGND with a minimum of 4.7μF low ESR tantalum or ceramic capacitor. DRVCC (Pin 20, UH Package): Driver Voltage Input. Must be connected to INTVCC externally. Do not exceed 7V at this pin. This pin is co-bonded to INTVCC internally in the GN package. BG (Pin 21/Pin 21): Bottom Gate Driver Output. This pin drives the gate of the bottom N-channel MOSFET between ground and INTVCC . 3823fd 7 LTC3823 PIN FUNCTIONS (UH/GN) PGND (Pin 22/Pin 22): Power Ground. Connect this pin closely to the source of the bottom N-channel MOSFET, the (–) terminal of CVCC and CIN . SENSE – (Pin 23/Pin 23): Current Sense Comparator Input. The negative input to the current comparator is used to accurately Kelvin sense the bottom side of the sense resistor or MOSFET. SENSE + (Pin 24/Pin 24): Current Sense Comparator Input. The positive input to the current comparator is normally connected to the SW node unless using a sense resistor. SW (Pin 25/Pin 25): Switch Node. The (–) terminal of the bootstrap capacitor, CB , connects here. This pin swings from a diode drop below ground up to VIN . TG (Pin 26/Pin 26): Top Gate Drive Output. This pin drives the top N-channel MOSFET with a voltage swing equal to INTVCC , superimposed on the switch node voltage SW. BOOST (Pin 27/Pin 27): Boosted Floating Driver Supply. The (+) terminal of the bootstrap capacitor, CB , connects here. This pin swings from a diode voltage drop below INTVCC up to VIN + INTVCC . Z0 (Pin 28/Pin 28): Dead Time Control Input. Applying a DC voltage at this pin will vary the dead time between TG low and BG high transition. Do not force a voltage higher than INTVCC on this pin. FCB (Pin 29/Pin 1): Forced Continuous Input. Connect this pin to SGND to forced continuous synchronization operation at low load, to INTVCC to enable discontinuous mode operation at low load, or to a resistive divider from a secondary output when using a secondary winding. RUN (Pin 30/Pin 2): Run Control Input. A voltage above 1.5V turns on the IC. Forcing this pin below 1.5V shuts down the device. VON (Pin 31/Pin 3): On-Time Input. Connecting this pin to the output voltage makes the on-time proportional to VOUT. The comparator input defaults to 0.6V when the pin is grounded and defaults to 4.8V when the pin is tied to INTVCC . PGOOD (Pin 32/Pin 4): Power Good Output. Open-drain logic that is pulled to ground when the output voltage is not within ±11% of the regulation point after the internal 20μs power bad mask timer expires. SGND (Exposed Pad Pin 33, UH Package): The exposed pad is signal ground. It must be soldered to PCB ground for electrical contact and for rated thermal performance. 3823fd 8 LTC3823 FUNCTIONAL DIAGRAM PLLFLTR VOUT VON 4.8V ION RON FCB INTVCC 1μA R R PLL-SYNC R VINSNS 5V REG VIN + CIN VIN 0.6V ZVCC 0.6V Z0 Z1/SSENABLE Z2 BOOST CB M1 SW SWITCH LOGIC AND ANTISHOOT THROUGH SENSE+ SENSE– DRVCC BG M2 CVCC PGND RSENSE (OPTIONAL) – F + INTVCC PLLIN tON VVON = (10pF) IION R S Q FCNT ON TG + ICMP 20k + IREV DB L1 VOUT – 2.0V VRNG (0.5~2) – RUN + COUT OV FOLDBACK DISABLED AT START-UP 0.5V 3.3μA + FOLDBACK 0.25V SENSE+ PGOOD BG SENSE– SW – M2 1 240k Q2 Q4 ITHB Q6 OV – VFB PGND R2 (EXT) R1 (EXT) *CONNECTION W/O SENSE RESISTOR + SGND Q1 40k VOUTSENSE– UV – + + RUN VOUTSENSE+ 40k 0.6V VDIFFOUT ITH RC CC1 TRACK/SS CSS –++ + 40k EA 0.5V 1.5V EXTERNAL TO CHIP – + – – 40k SS RUN INTVCC 1.7μA 3823 FD 3823fd 9 LTC3823 OPERATION Main Control Loop The LTC3823 is a current mode controller for DC/DC step-down converters. In normal operation, the top MOSFET is turned on for a fixed interval determined by a one-shot timer, OST. When the top MOSFET is turned off, the bottom MOSFET is turned on until the current comparator ICMP trips, restarting the one-shot timer and initiating the next cycle. Inductor current is determined by sensing the voltage between the SENSE – and SENSE + pins using a sense resistor or the bottom MOSFET onresistance . The voltage on the ITH pin sets the comparator threshold corresponding to inductor valley current. The error amplifier EA adjusts this voltage by comparing the feedback signal, VFB , to an internal reference voltage. If the load current increases, it causes a drop in the feedback voltage relative to the reference. The ITH voltage then rises until the average inductor current again matches the load current. At low load currents, the inductor current can drop to zero and become negative. This is detected by current reversal comparator IREV which then shuts off M2, resulting in discontinuous operation. Both switches will remain off with the output capacitor supplying the load current until the ITH voltage rises above the zero current level (0.75V) to initiate another cycle. Discontinuous mode operation is disabled by comparator F when the FCB pin is brought below 0.6V, forcing continuous synchronous operation. The operating frequency is determined implicitly by the top MOSFET on-time and the duty cycle required to maintain regulation. The one-shot timer generates an on time that is proportional to the ideal duty cycle, thus holding frequency approximately constant with changes in VIN. The nominal frequency can be adjusted with an external resistor, RON . For applications with stringent constant frequency requirements, the LTC3823 can be synchronized with an external clock. By programming the nominal frequency of the LTC3823 the same as the external clock frequency, the LTC3823 behaves as a constant frequency part against the load and supply variations. Overvoltage and undervoltage comparators OV and UV pull the PGOOD output low if the output feedback voltage exits a ±10% window around the regulation point after the internal 20μs power bad mask timer expires. Furthermore, in an overvoltage condition, M1 is turned off and M2 is turned on immediately and held on until the overvoltage condition clears. Foldback current limiting is provided if the output is shorted to ground. As VFB drops, the buffered current threshold voltage, ITHB, is pulled down and clamped to 0.9V. This reduces the inductor valley current level to one-tenth of its maximum value as VFB approaches 0V. Foldback current limiting is disabled at start-up. Pulling the RUN pin low forces the controller into its shutdown state, turning off both M1 and M2. Forcing a voltage above 1.5V will turn on the device. INTVCC Power Power for the top and bottom MOSFET drivers and most of the internal controller circuitry is derived from the INTVCC pin. The top MOSFET driver is powered from a floating bootstrap capacitor, CB . This capacitor is recharged from INTVCC through an external Schottky diode, DB , when the top MOSFET is turned off. If the input voltage is low and INTVCC drops below 3V, undervoltage lockout circuitry prevents the power switches from turning on. 3823fd 10 LTC3823 APPLICATIONS INFORMATION The basic LTC3823 application circuit is shown in Figure 12. External component selection is primarily determined by the maximum load current and begins with the selection of the sense resistance and power MOSFET switches. The LTC3823 uses either a sense resistor or the on-resistance of the synchronous power MOSFET for determining the inductor current. The desired amount of ripple current and operating frequency largely determines the inductor value. Finally, CIN is selected for its ability to handle the large RMS current into the converter and COUT is chosen with low enough ESR to meet the output voltage ripple and transient specification. Maximum Sense Voltage and VRNG Pin Inductor current is determined by measuring the voltage across a sense resistance that appears between the SENSE – and SENSE + pins. The maximum sense voltage is set by the voltage applied to the VRNG pin and is equal to approximately (0.133)VRNG . The current mode control loop will not allow the inductor current valleys to exceed (0.133)VRNG/RSENSE. In practice, one should allow some margin for variations in the LTC3823 and external component values and a good guide for selecting the sense resistance is: RSENSE = VRNG 10 • IOUT(MAX) MOSFET as the current sense element by simply connecting the SENSE + pin to the SW pin and SENSE – pin to PGND. This improves efficiency, but one must carefully choose the MOSFET on-resistance as discussed below. Power MOSFET Selection The LTC3823 requires two external N-channel power MOSFETs, one for the top (main) switch and one for the bottom (synchronous) switch. Important parameters for the power MOSFETs are the breakdown voltage V(BR)DSS, threshold voltage V(GS)TH, on-resistance RDS(ON), reverse transfer capacitance CRSS and maximum current IDS(MAX). The gate drive voltage is set by the 5V INTVCC supply. Consequently, logic-level threshold MOSFETs must be used in LTC3823 applications. If the input voltage is expected to drop below 5V, then sub-logic level threshold MOSFETs should be considered. When the bottom MOSFET is used as the current sense element, particular attention must be paid to its on-resistance. MOSFET on-resistance is typically specified with a maximum value RDS(ON)(MAX) at 25°C. In this case, additional margin is required to accommodate the rise in MOSFET on-resistance with temperature: RDS(ON)(MAX) = RSENSE ρT An external resistive divider from INTVCC can be used to set the voltage of the VRNG pin between 0.5V and 2V resulting in nominal sense voltages of 50mV to 200mV. Additionally, the VRNG pin can be tied to SGND or INTVCC in which case the nominal sense voltage defaults to 50mV or 200mV, respectively. The maximum allowed sense voltage is about 1.33 times this nominal value. Connecting the SENSE+ and SENSE– Pins The IC can be used with or without a sense resistor. When using a sense resistor, place it between the source of the bottom MOSFET, M2, and PGND. Connect the SENSE + and SENSE – pins to the top and bottom of the sense resistor. Using a sense resistor provides a well defined current limit, but adds cost and reduces efficiency. Alternatively, one can eliminate the sense resistor and use the bottom The ρT term is a normalization factor (unity at 25°C) accounting for the significant variation in on-resistance with temperature, typically about 0.4%/°C as shown in Figure 1. For a maximum junction temperature of 100°C, using a value ρT = 1.3 is reasonable. The power dissipated by the top and bottom MOSFETs strongly depends upon their respective duty cycles and the load current. When the LTC3823 is operating in continuous mode, the duty cycles for the MOSFETs are: DTOP = DBOT VOUT VIN V –V = IN OUT VIN 3823fd 11 LTC3823 APPLICATIONS INFORMATION 2.0 T NORMALIZED ON-RESISTANCE 1.5 improves efficiency by reducing MOSFET switching losses but requires larger inductance and/or capacitance in order to maintain low output ripple voltage. The operating frequency of LTC3823 applications is determined implicitly by the one-shot timer that controls the on-time, tON , of the top MOSFET switch. The on-time is set by the current out of the ION pin and the voltage at the VON pin according to: 50 100 0 JUNCTION TEMPERATURE (°C) 150 3823 F01 1.0 0.5 0 –50 tON = VVON (10pF) IION Figure 1. RDS(ON) vs Temperature The resulting power dissipation in the MOSFETs at maximum output current are: PTOP = DTOP IOUT(MAX) PBOT = DBOT IOUT(MAX) 2ρ T(TOP) RDS(ON)(MAX) Tying a resistor RON to SGND from the ION pin yields an on-time inversely proportional to 1/3 VIN . The current out of the ION pin is: IION = VIN 3 RON + k VIN2 IOUT(MAX) CRSS f 2ρ T(BOT) RDS(ON)(MAX) For a step-down converter, this results in approximately constant frequency operation as the input supply varies: f= VOUT [ HZ ] VVON • 3 RON(10pF) Both MOSFETs have I2R losses and the top MOSFET includes an additional term for transition losses, which are largest at high input voltages. The constant k = 1.7A–1 can be used to estimate the amount of transition loss. The bottom MOSFET losses are greatest when the bottom duty cycle is near 100%, during a short-circuit or at high input voltage. Operating Frequency The choice of operating frequency is a tradeoff between efficiency and component size. Low frequency operation 1000 VOUT = 3.3V VOUT = 2.5V VOUT = 1.5V To hold frequency constant during output voltage changes, tie the VON pin to VOUT. The VON pin has internal clamps that limit its input to the one-shot timer. If the pin is tied below 0.6V, the input to the one-shot is clamped at 0.6V. Similarly, if the pin is tied above 4.8V, the input is clamped at 4.8V. In high VOUT applications, tie VON to INTVCC . Figures 2a and 2b show how RON relates to switching frequency for several common output voltages. 1000 VOUT = 12V SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) VOUT = 3.3V VOUT = 5V 100 100 RON (kΩ) 1000 3823 F02a 100 10 100 RON (kΩ) 1000 3823 F02b Figure 2a. Switching Frequency vs RON (VON = 0V) Figure 2b. Switching Frequency vs RON (VON = INTVCC) 3823fd 12 LTC3823 APPLICATIONS INFORMATION When there is no RON resistor connected to the ION pin, the on-time tON is theoretically infinite, which in turn could damage the converter. To prevent this, the LTC3823 detects this fault condition and provides a minimum ION current of 5μA to 10μA. Changes in the load current magnitude will cause frequency shift. Parasitic resistance in the MOSFET switches and inductor reduce the effective voltage across the inductance, resulting in increased duty cycle as the load current increases. By lengthening the on-time slightly as current increases, constant frequency operation can be maintained. This is accomplished with a resistive divider from the ITH pin to the VON pin and VOUT. The values required will depend on the parasitic resistances in the specific application. A good starting point is to feed about 25% of the voltage change at the ITH pin to the VON pin as shown in Figure 3a. Place capacitance on the VON pin to filter out the ITH variations at the switching frequency. The resistor load on ITH reduces the DC gain of the error amp and degrades load regulation, which can be avoided by using the PNP emitter follower of Figure 3b. RVON1 30k VOUT RVON2 100k RC ITH CC CVON 0.01μF VON LTC3823 MOSFET back off. This time is generally about 280ns. The minimum off-time limit imposes a maximum duty cycle of tON/(tON + tOFF(MIN)). If the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation. The minimum input voltage to avoid dropout is: VIN(MIN) = VOUT tON + tOFF(MIN) tON A plot of maximum duty cycle vs frequency is shown in Figure 4. 2.0 SWITCHING FREQUENCY (MHz) 1.5 DROPOUT REGION 1.0 0.5 0 0 0.25 0.50 0.75 DUTY CYCLE (VOUT/VIN) 1.0 3823 F04 Figure 4. Maximum Switching Frequency vs Duty Cycle Inductor Selection (3a) RVON1 3k VOUT INTVCC 10k Q1 2N5087 RVON2 10k CVON 0.01μF RC ITH CC 3823 F03 VON LTC3823 Given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: ⎛V ⎞⎛ V ⎞ ΔIL = ⎜ OUT ⎟ ⎜1− OUT ⎟ VIN ⎠ ⎝ f•L ⎠⎝ Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors and output voltage ripple. Highest efficiency operation is obtained at low frequency with small ripple current. However, achieving this requires a large inductor. There is a tradeoff between component size, efficiency and operating frequency. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX) . The largest ripple current occurs at the highest VIN . To guarantee that ripple current 3823fd (3b) Figure 3. Correcting Frequency Shift with Load Current Changes Minimum Off-Time and Dropout Operation The minimum off-time tOFF(MIN) is the smallest amount of time that the LTC3823 is capable of turning on the bottom MOSFET, tripping the current comparator and turning the 13 LTC3823 APPLICATIONS INFORMATION does not exceed a specified maximum, the inductance should be chosen according to: ⎛V ⎞⎛ ⎞ OUT ⎟ ⎜1− VOUT ⎟ ⎜ L =⎜ ⎟ ⎟⎜ ⎝ f ΔIL(MAX ) ⎠ ⎝ VIN(MAX ) ⎠ Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or Kool Mμ® cores. A variety of inductors designed for high current, low voltage applications are available from manufacturers such as Sumida, Panasonic, Coiltronics, Coilcraft and Toko. Schottky Diode D1 Selection The Schottky diode D1 shown in Figure 12 conducts during the dead time between the conduction of the power MOSFET switches. It is intended to prevent the body diode of the bottom MOSFET from turning on and storing charge during the dead time, which can cause a modest (about 1%) efficiency loss. The diode can be rated for about one half to one fifth of the full load current since it is on for only a fraction of the duty cycle. In order for the diode to be effective, the inductance between it and the bottom MOSFET must be as small as possible, mandating that these components be placed adjacently. The diode can be omitted if the efficiency loss is tolerable. CIN and COUT Selection The input capacitance CIN is required to filter the square wave current at the drain of the top MOSFET. Use a low ESR capacitor sized to handle the maximum RMS current. IRMS ≅ IOUT(MAX) VOUT VIN VIN –1 VOUT The selection of COUT is primarily determined by the ESR required to minimize voltage ripple and load step transients. The output ripple ΔVOUT is approximately bounded by: ⎛ 1⎞ ΔVOUT ≤ ΔIL ⎜ESR + ⎟ 8 fCOUT ⎠ ⎝ Since ΔIL increases with input voltage, the output ripple is highest at maximum input voltage. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the necessary RMS current rating. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-sensitive applications providing that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. When used as input capacitors, care must be taken to ensure that ringing from inrush currents and switching does not pose an overvoltage hazard to the power switches and controller. To dampen input voltage transients, add a small 5μF to 50μF aluminum electrolytic capacitor with an ESR in the range of 0.5Ω to 2Ω. High performance through-hole capacitors may also be used, but an additional ceramic capacitor in parallel is recommended to reduce the effect of their lead inductance. Top MOSFET Driver Supply (CB, DB) An external bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. This capacitor is charged through diode DB from INTVCC when the switch node is low. When the top MOSFET turns 3823fd This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT(MAX)/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. 14 LTC3823 APPLICATIONS INFORMATION on, the switch node rises to VIN and the BOOST pin rises to approximately VIN + INTVCC . The boost capacitor needs to store about 100 times the gate charge required by the top MOSFET. In most applications 0.1μF to 0.47μF, X5R or X7R dielectric capacitor is adequate. Discontinuous Mode Operation and FCB Pin The FCB pin determines whether the bottom MOSFET remains on when current reverses in the inductor. Tying this pin above its 0.6V threshold enables discontinuous operation where the bottom MOSFET turns off when inductor current reverses. The load current at which current reverses and discontinuous operation begins depends on the amplitude of the inductor ripple current and will vary with changes in VIN. Tying the FCB pin below the 0.6V threshold forces continuous synchronous operation, allowing current to reverse at light loads and maintaining high frequency operation. To prevent forcing current back into the main power supply, potentially boosting the input supply to a dangerous voltage level, forced continuous mode of operation is disabled when the TRACK/SS voltage is 20% below the reference voltage during soft-start or tracking up. Forced continuous mode of operation is also disabled when the TRACK/SS voltage is below 0.1V during tracking down operation. During these two periods, the PGOOD signal is forced low. In addition to providing a logic input to forced continuous operation, the FCB pin provides a mean to maintain a flyback winding output when the primary is operating in discontinuous mode. The secondary output VOUT2 is normally set as shown in Figure 5 by the turns ratio N + VIN LTC3823 TG VIN CIN 1N4148 of the transformer. However, if the controller goes into discontinuous mode and halts switching due to a light primary load current, then VOUT2 will droop. An external resistor divider from VOUT2 to the FCB pin sets a minimum voltage VOUT2(MIN) below which continuous operation is forced until VOUT2 has risen above its minimum. ⎛ R4 ⎞ VOUT2(MIN) = 0.6 V⎜ 1 + ⎟ ⎝ R3 ⎠ Fault Conditions: Current Limit and Foldback The maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. In the LTC3823, the maximum sense voltage is controlled by the voltage on the VRNG pin. With valley current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. The corresponding output current limit is: ILIMIT = VSNS(MAX ) RDS(ON) 1 + ΔIL ρT 2 The current limit value should be checked to ensure that ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit generally occurs with the largest VIN at the highest ambient temperature, conditions that cause the largest power loss in the converter. Note that it is important to check for self-consistency between the assumed MOSFET junction temperature and the resulting value of ILIMIT which heats the MOSFET switches. Caution should be used when setting the current limit based upon the RDS(ON) of the MOSFETs. The maximum current limit is determined by the minimum MOSFET on-resistance. Data sheets typically specify nominal and maximum values for RDS(ON), but not a minimum. A reasonable assumption is that the minimum RDS(ON) lies the same percentage below the typical value as the maximum lies above it. Consult the MOSFET manufacturer for further guidelines. To further limit current in the event of a short circuit to ground, the LTC3823 includes foldback current limiting. If the output falls by more than 60%, then the maximum sense voltage is progressively lowered to about one tenth of its full value. 3823fd + T1 1:N R4 FCB R3 SGND SW • + VOUT2 COUT2 1μF VOUT1 COUT BG PGND 3823 F05 Figure 5. Secondary Output Loop • 15 LTC3823 APPLICATIONS INFORMATION INTVCC Regulator An internal P-channel low dropout regulator produces the 5V supply that powers the drivers and internal circuitry within the LTC3823. The INTVCC pin can supply up to 50mA RMS and must be bypassed to ground with a minimum of 4.7μF low ESR tantalum capacitor or other low ESR capacitor. Good bypassing is necessary to supply the high transient currents required by the MOSFET gate drivers. Applications using large MOSFETs with a high input voltage and high frequency of operation may cause the LTC3823 to exceed its maximum junction temperature rating or RMS current rating. Most of the supply current drives the MOSFET gates. In continuous mode operation, this current is IGATECHG = f(Qg(TOP) + Qg(BOT)). The junction temperature can be estimated from the equations given in Note 2 of the Electrical Characteristics. For example, the GN package is limited to less than 23mA from a 30V supply: TJ = 70°C + (23mA)(30V)(80°C/W) = 125°C For applications where more current is needed than INTVCC can supply, INTVCC can be driver by an external supply with a voltage higher than 5.35V. However, the INTVCC pin should not exceed its absolute maximum voltage of 7V. External Gate Drive Buffers The LTC3823 drivers are adequate for driving up to about 50nC into MOSFET switches with RMS currents of 50mA. Applications with larger MOSFET switches or operating at frequencies requiring greater RMS currents will benefit from using external gate drive buffers such as the LTC1693. Alternately, the external buffer circuit shown in Figure 6 can be used. BOOST Q1 FMMT619 GATE OF M1 Q2 FMMT720 SW INTVCC Q3 FMMT619 GATE OF M2 Q4 FMMT720 PGND 3823 F06 Soft-Start and Tracking The LTC3823 has the ability to either soft start by itself with a capacitor or track the output of another supply. When the device is configured to soft start by itself, a capacitor should be connected to the TRACK/SS pin. The LTC3823 is put in a low quiescent current shutdown state (30μA) if the RUN pin voltage is below 1.5V. The TRACK/SS pin is actively pulled to ground in this shutdown state. Once the RUN pin voltage is above 1.5V, the LTC3823 is powered up. A soft-start current of 1.7μA then starts to charge the soft-start capacitor CSS . Pin Z1/SSENABLE must be grounded for soft-start operation. Note that soft-start is achieved not by limiting the maximum output current of the controller but by controlling the ramp rate of the output voltage. Current foldback is disabled during this soft-start phase. During the soft-start phase, the LTC3823 is ramping the reference voltage until it is 20% below the voltage set by the VREFIN pin. The forced continuous mode is also disabled and PGOOD signal is forced low during this phase. The total soft-start time can be calculated as: tSOFTSTART = 0.5V • CSS /1.7μA When the device is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the TRACK/SS pin. Pin Z1/SSENABLE should be tied to INTVCC to turn off the softstart current in this mode. Therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supply output voltage. Output Voltage Tracking The LTC3823 allows the user to program how its output ramps up and down by means of the TRACK/SS pin. Through this pin, the output can be set up to either coincidentally or ratiometrically track with another supply’s output, as shown in Figure 7. In the following discussions, VOUT1 refers to the master LTC3823’s output and VOUT2 refers to the slave LTC3823’s output. To implement the coincident tracking in Figure 7a, connect an additional resistive divider to VOUT1 and connect its midpoint to the TRACK/SS pin of the slave IC. The ratio of this divider should be selected the same as that of the slave IC’s feedback divider shown in Figure 8. In this tracking 3823fd 10Ω TG 10Ω BG Figure 6. Optional External Gate Driver 16 LTC3823 APPLICATIONS INFORMATION VOUT1 OUTPUT VOLTAGE OUTPUT VOLTAGE VOUT1 VOUT2 VOUT2 3823 F07 TIME TIME (7a) Coincident Tracking (7b) Ratiometric Tracking Figure 7. Two Different Modes of Output Voltage Tracking VOUT1 R3 TO TRACK/SS2 PIN R4 R2 R1 TO VFB1 PIN TO VFB2 PIN R4 R3 TO TRACK/SS2 PIN R2 VOUT2 VOUT1 R1 TO VFB1 PIN TO VFB2 PIN R4 3823 F08 VOUT2 R3 (8a) Coincident Tracking Setup (8b) Ratiometric Tracking Setup Figure 8. Setup for Coincident and Ratiometric Tracking I I + D1 TRACK/SS2 0.6V VFB2 D3 D2 EA2 – 3823 F09 Figure 9. Equivalent Input Current of Error Amplifier mode, VOUT1 must be set higher than VOUT2 . To implement the ratiometric tracking, the ratio of the divider should be exactly the same as the master IC’s feedback divider. Note that the pin Z1/SSENABLE of the slave IC should be tied to INTVCC so that the internal soft-start current is disabled in both tracking modes or it will introduce a small error on the tracking voltage depending on the absolute values of the tracking resistive divider. By selecting different resistors, the LTC3823 can achieve different modes of tracking including the two in Figure 7. So which mode should be programmed? While either mode in Figure 7 satisfies most practical applications, there do exist some tradeoffs. The ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. This can be better understood with the help of Figure 9. At the input stage of the slave IC’s error amplifier, two common anode diodes are used to clamp the equivalent reference voltage and an additional diode is used to match the shifted common mode voltage. The top two current sources are of the same amplitude. In the coincident mode, the TRACK/SS voltage is substantially higher than 0.6V at steady state and effectively turns off D1. D2 and D3 will therefore conduct the same current and offer tight matching between VFB2 and the internal precision 0.6V reference. In the ratiometric mode, however, TRACK/SS equals 0.6V at steady state. D1 will divert part of the bias current to make VFB2 slightly lower than 0.6V. Although this error is minimized by the exponential I-V characteristic of the diode, it does impose a finite amount of output voltage deviation. Furthermore, when the master IC’s output experiences dynamic excursion (under load transient, for example), the slave IC output will be affected as well. For better output regulation, use the coincident tracking mode instead of ratiometric. 3823fd 17 LTC3823 APPLICATIONS INFORMATION Differential Amplifier This amplifier provides true differential output voltage sensing. Sensing both the positive and negative terminals of the output voltage benefits regulation in high current applications and/or applications having electrical interconnection losses. Precision feedback resistors are integrated in the IC with the amplifier already configured as a unity-gain differential amplifier. It has a GBW product of 3.5MHz and an open-loop gain of >120dB. The amplifier can source >2mA of current, and can be used in applications with up to 3.3V output voltage. The amplifier is not capable of sinking significant current, and must be resistively loaded. A load of 20kΩ or less is recommended for stability. The amplifier is not designed to drive capacitive loads. Phase-Locked Loop and Frequency Synchronization The LTC3823 has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. This allows the top MOSFET turn-on to be locked to the rising edge of an external source. The frequency range of the voltage controlled oscillator is ±30% around the center frequency, fO . The center frequency is the operating frequency discussed in the previous section. The LTC3823 incorporates a pulse detection circuit that will detect a clock on the PLLIN pin. In turn, it will turn on the phase-locked loop function. The pulse width of the clock has to be greater than 400ns and the amplitude of the clock should be greater than 2V. During the start-up phase, phase-locked loop function is disabled. When LTC3823 is not in synchronization mode, PLLFLTR pin voltage is set to around 1.18V. Frequency synchronization is accomplished by changing the internal on-time current according to the voltage on the PLLFLTR pin. The phase detector used is an edge sensitive digital type which provides zero degrees phase shift between the external and internal pulses. This type of phase detector will not lock up on input frequencies close to the harmonics of the VCO center frequency. The PLL hold-in range, ΔfH , is equal to the capture range, ΔfC : ΔfH = ΔfC = ±0.3 fO 2.4V RLP CLP PLLFLTR PLLIN DIGITAL PHASE/ FREQUENCY DETECTOR VCO 3823 F10 Figure 10. Phase-Locked Loop Block Diagram The output of the phase detector is a complementary pair of current sources charging or discharging the external filter network on the PLLFLTR pin. A simplified block diagram is shown in Figure 10. If the external frequency (fPLLIN) is greater than the oscillator frequency fO , current is sourced continuously, pulling up the PLLFLTR pin. When the external frequency is less than fO , current is sunk continuously, pulling down the PLLFLTR pin. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. Thus the voltage on the PLLFLTR pin is adjusted until the phase and frequency of the external and internal oscillators are identical. At this stable operating point the phase comparator output is open and the filter capacitor CLP holds the voltage. The LTC3823 PLLIN pin must be driven from a low impedance source such as a logic gate located close to the pin. The loop filter components (CLP , RLP) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP =10k and CLP is 0.01μF to 0.1μF. Dead Time Control To further optimize the efficiency, the LTC3823 gives users some control over the dead time of the Top gate low and Bottom gate high transition. By applying a DC voltage on the Z0 pin, the TG low BG high dead time can be programmed. Because the dead time is a strong function of 3823fd 18 LTC3823 APPLICATIONS INFORMATION the load current and the type of MOSFET used, users need to be careful to optimize the dead time for their particular applications. Figure 11 shows the relation between the TG Low BG High dead time by varying the Z0 voltages. For an application using LTC3823 with load current of 5A and IR7811W MOSFETs, the dead time could be optimized. To make sure that there is no shoot-through under all conditions, a dead time of 70ns is selected. This corresponds to a DC voltage about 2.4V on Z0 pin. This voltage can easily be generated with a resistor divider off INTVCC . 200 TG LOW TO BG HIGH DEADTIME (ns) 180 160 140 120 100 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 Z0 VOLTAGE (V) 4 4.5 5 IOUT = 2A FIGURE 12 CIRCUIT 2. Transition loss. This loss arises from the brief amount of time the top MOSFET spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at input voltages above 20V and can be estimated from: Transition Loss ≅ (1.7A–1) VIN2 IOUT CRSS f 3. INTVCC current. This is the sum of the MOSFET driver and control currents. 4. CIN loss. The input capacitor has the difficult job of filtering the large RMS input current to the regulator. It must have a very low ESR to minimize the AC I2R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries. Other losses, including COUT ESR loss, Schottky diode D1 conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. 3823 F11 Figure 11. TG Low BG High Dead Time vs Z0 Voltage Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC3823 circuits: 1. DC I2R losses. These arise from the resistances of the MOSFETs, inductor and PC board traces and cause the efficiency to drop at high output currents. In continuous mode the average output current flows through L, but is chopped between the top and bottom MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and the board traces to obtain the DC I2R loss. For example, if RDS(ON) = 0.01Ω and RL = 0.005Ω, the loss will range from 15mW to 1.5W as the output current varies from 1A to 10A. When making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If you make a change and the input current decreases, then the efficiency has increased. If there is no change in input current, then there is no change in efficiency. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD (ESR), where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The ITH pin external components shown in Figure 12 will provide adequate compensation for most applications. For a detailed explanation of switching control loop theory see Application Note 76. 3823fd 19 LTC3823 APPLICATIONS INFORMATION Design Example As a design example, take a supply with the following specifications: VIN = 5V to 28V (15V nominal), VOUT = 2.5V ±5%, IOUT(MAX) = 10A, f = 320kHz. First, calculate the timing resistor with VON = VOUT : RON = 2.5V = 104kΩ 3 (2.5V)(320kHz)(10pF) Because the top MOSFET is on for such a short time, an Si7342DP R DS(ON)(MAX) = 0 .010Ω, C RSS = 1 20pF, θJA = 53°C/W will be sufficient. Checking its power dissipation at current limit with ρ100°C = 1.4: PTOP = 2.5V (14A)2 (1.4)(0.010Ω) + 28 V and choose the inductor for about 40% ripple current at the maximum VIN : L= ⎛ 2.5V ⎞ 2.5V ⎟ = 1.77µH ⎜1− (320kHz)(0.4)(10A) ⎝ 28V ⎠ (1.7)(28V)2 (14A)(120pF)(320kHz) = 0.25W + 0.72W = 0.97 W TJ = 70°C + (0.97W)(53°C/W) = 121°C The junction temperature will be significantly less at nominal current, but this analysis shows that careful attention to heat sinking on the board will be necessary in this circuit. CIN is chosen for an RMS current rating of about 3A at 85°C. The output capacitors are chosen for a low ESR of 0.013Ω to minimize output voltage changes due to inductor ripple current and load steps. The ripple voltage will be only: ΔVOUT(RIPPLE) = ΔIL(MAX) (ESR) = (5.9A) (0.013Ω) = 77mV However, a 0A to 10A load step will cause an output change of up to: ΔVOUT(STEP) = ΔILOAD (ESR) = (10A) (0.013Ω) = 130mV An optional 22μF ceramic output capacitor is included to minimize the effect of ESL in the output ripple. The complete circuit is shown in Figure 12. PC Board Layout Checklist When laying out a PC board follow one of two suggested approaches. The simple PC board layout requires a dedicated ground plane layer. Also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. • The ground plane layer should not have any traces and it should be as close as possible to the layer with power MOSFETs. 3823fd Selecting a standard value of 1.2μH results in a maximum ripple current of: ΔIL = ⎛ 2.5V ⎞ 2.5V ⎜1 – ⎟ = 5.9 A (320kHz)(1.2μH) ⎝ 28V ⎠ Next, choose the synchronous MOSFET switch. Choosing a Si7892ADP (RDS(ON) = 0.005Ω (NOM) 0.006Ω (MAX), θJA = 50°C/W) yields a nominal sense voltage of: VSNS(NOM) = (7A)(1.3)(0.005Ω) = 45mV Tying VRNG to 0.75V will set the current sense voltage range for a nominal value of 75mV with current limit occurring at 100mV. To check if the current limit is acceptable, assume a junction temperature of about 80°C above a 70°C ambient with ρ150°C = 1.5: 100mV 1 ILIMIT ≥ + (5.9 A) = 14A (1.5)(0.006Ω) 2 and double check the assumed TJ in the MOSFET: PBOT = 28 V – 2 .5V 2 (14A) (1.5)(0.006Ω) = 1.6 W 28 V TJ = 70°C + (1.6W)(50°C/W) = 150°C 20 LTC3823 APPLICATIONS INFORMATION R8 27.1k INTVCC R7 23.2k CIN 10μF 50V 3 VOUT 2.5V 10A COUT1 220μF 4V VIN 5V TO 28V RPG 100k GND RUN R5 42.5k R6 7.5k PGOOD 1 2 3 4 VRNG FB VITH ION DIFFOUT C4 220pF R2 16.2k R1 5.11k TRACK/SS RC 1.5k CC2 100pF CC1 6800pF CSS 0.1μF 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 M1 Si7342DP L1 1.2μH FCB RUN VON LTC3823GN Z0 TG SW BOOST PGOOD VRNG VFB ITH SGND ION VDIFFOUT VOUTSENSE+ VOUTSENSE– TRACK/SS PLLFLTR 10k 1000pF 0.01μF 23 SENSE– 22 PGND 21 BG 20 INTVCC 19 Z2 18 Z1/SSENABLE 17 ZVCC 16 VIN 15 PLLIN SENSE+ + CB 0.22μF DB CMDSH-3 D1 B320A M2 Si7892ADP + + CVCC 4.7μF COUT3 47μF X5R 3 PLLIN RON 100k 3823 F12 Figure 12. Design Example: 2.5V/7A at 320kHz • Place CIN , COUT, MOSFETs, D1 and inductor all in one compact area. It may help to have some components on the bottom side of the board. • Use an immediate via to connect the components to ground plane including SGND and PGND of LTC3823. Use several bigger vias for power components. • Use compact plane for switch node (SW) to improve cooling of the MOSFETs and to keep EMI down. • Use planes for VIN and VOUT to maintain good voltage filtering and to keep power losses low. • Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power component. You can connect the copper areas to any DC net (VIN , VOUT, GND or to any other DC rail in your system). When laying out a printed circuit board, without a ground plane, use the following checklist to ensure proper operation of the controller. • Segregate the signal and power grounds. All smallsignal components should return to the SGND pin at one point which is then tied to the PGND pin close to the source of M2. • Place M2 as close to the controller as possible, keeping the PGND, BG and SW traces short. • Connect the input capacitor(s) CIN close to the power MOSFETs. This capacitor carries the MOSFET AC current. • Keep the high dV/dt SW, BOOST and TG nodes away from sensitive small-signal nodes. • Connect the INTVCC decoupling capacitor CVCC closely to the INTVCC and PGND pins. • Connect the top driver boost capacitor CB closely to the BOOST and SW pins. • Connect the VIN pin decoupling capacitor CIN closely to the VIN and PGND pins. 3823fd 21 LTC3823 TYPICAL APPLICATION 22 Design Example: 1.2V/10A at 450kHz with Light Load Discontinuous Mode Operation INTVCC R2 R1 23.2k 26.7k 1% 1% RRUN 100k VIN E1 INTVCC E3 VIN 4.5V TO 16V RPG 100k RBOOST 0Ω C2 10μF 16V E5 3 GND DB CMDSH-3-LTC 32 PGOOD RUN FCB Z0 BOOST TG SW VON 31 30 29 28 27 26 Q1 Si4884 L1 1μH IHLP-2525CZ-01 R7 100Ω 1% E14 VOUT E7 VOUT 1.2V/10A C5 0.22μF E6 VOUTSENSE+ LTC3823UH 1 2 3 4 5 6 7 8 VRNG VFB ITH SGND ION VDIFFOUT NC VOUTSENSE+ VOUTSENSE– NC TRACK/SS PLLFLTR PLLIN VIN VINSNS ZVCC 9 RVIN 10Ω CSS 0.1μF RPL 10k CPL 0.01μF CP 1000pF CVIN 0.1μF 10 11 12 13 14 15 16 CVCC 10μF 6.3V SENSE+ SENSE– PGND BG DRVCC INTVCC Z2 Z1/SSENABLE 24 23 22 21 20 19 18 17 D1 B320A Q2 Si4874 C11 47μF 6.3V 3 C12 10μF 6.3V E8 GND R8 100Ω 1% E15 GND E9 VOUTSENSE– 3823 TA02 E2 RUN E4 PGOOD R3 39k R4 5.11k 1% R5 5.11k 1% R6 11k RC 1.5k 1% CC1 6800pF C6 220pF CC2 RON 100pF 66.5k 1% E10 TRACK/SS E11 PLLIN E12 GND E13 GND 3823fd LTC3823 PACKAGE DESCRIPTION GN Package 28-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .386 – .393* (9.804 – 9.982) 28 27 26 25 24 23 22 21 20 19 18 17 1615 .045 ± .005 .033 (0.838) REF .254 MIN .150 – .165 .229 – .244 (5.817 – 6.198) .150 – .157** (3.810 – 3.988) .0165 ± .0015 RECOMMENDED SOLDER PAD LAYOUT .0250 BSC 1 .0532 – .0688 (1.35 – 1.75) 23 4 56 7 8 9 10 11 12 13 14 .004 – .0098 (0.102 – 0.249) .015 ± .004 × 45° (0.38 ± 0.10) .0075 – .0098 (0.19 – 0.25) 0° – 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .008 – .012 (0.203 – 0.305) TYP .0250 (0.635) BSC GN28 (SSOP) 0204 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 3823fd 23 LTC3823 PACKAGE DESCRIPTION UH Package 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693 Rev D) 0.70 0.05 5.50 0.05 4.10 0.05 3.50 REF (4 SIDES) 3.45 0.05 3.45 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 0.75 0.05 R = 0.05 TYP 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD R = 0.115 TYP 31 32 0.40 1 2 3.45 0.10 0.10 PIN 1 NOTCH R = 0.30 TYP OR 0.35 45° CHAMFER 3.50 REF (4-SIDES) 3.45 0.10 (UH32) QFN 0406 REV D 0.200 REF NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 0.05 0.50 BSC 3823fd 24 LTC3823 REVISION HISTORY REV D DATE 10/09 DESCRIPTION Text Change to Title Patent Numbers Added I-Grade Parts Added to Order Information Text Changes to Notes 2, 3, 4 Text Changes to Pin Functions Text Changes to Applications Information Section Updated Related Parts (Revision history begins at Rev D) PAGE NUMBER 1 1 2 4 8 16 24 3823fd Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 25 LTC3823 TYPICAL APPLICATION Design Example: 1.8V/10A with Synchronization INTVCC R2 R1 23.2k 27.1k 1% 1% E1 INTVCC RRUN 100k E3 VIN 4.5V TO 16V C2 10μF 16V E5 3 GND DB CMDSH-3-LTC 32 PGOOD 1 2 3 4 5 6 7 8 VRNG VFB ITH SGND ION VDIFFOUT NC VOUTSENSE+ 31 VON 30 RUN 29 FCB 28 27 26 SW SENSE+ SENSE– PGND BG DRVCC INTVCC Z2 Z1/SSENABLE 24 23 22 21 20 19 18 17 Q1 Si4884 L1 1μH IHLP-2525CZ-01 D1 B320A CVCC 10μF 6.3V Q2 Si4874 R7 100Ω 1% E14 VOUT E7 VOUT 1.8V/10A Z0 BOOST TG C5 0.22μF E6 VOUTSENSE+ E2 RUN E4 PGOOD RPG 100k VIN RBOOST 0Ω R3 39k R6 11k RC 1.5k 1% CC1 6800pF R4 5.11k 1% R5 10.2k 1% C6 220pF CC2 RON 100pF 90k 1% E10 TRACK/SS LTC3823UH C9 47μF 6.3V 3 + C7 180μF E8 GND E15 GND E9 VOUTSENSE– VOUTSENSE– NC TRACK/SS PLLFLTR PLLIN VIN VINSNS ZVCC 9 10 11 12 13 14 15 16 RVIN 10Ω 300kHz E11 PLLIN E12 GND R8 100Ω 1% CSS 0.1μF CP RPL 1000pF 10k CPL 0.01μF CVIN 0.1μF E13 GND 3823 TA03 RELATED PARTS COMMENTS Fixed 400kHz Operating Frequency, 4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5.25V, 2mm × 3mm QFN-12 Phase-Lockable Fixed Operating Frequency 250kHz to 750kHz, LTC3851A/ 4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5.25V, MSOP-16E, 3mm × 3mm LTC3851A-1 QFN-16, SSOP-16 LTC3878 No RSENSE Constant On-Time Synchronous Step-Down DC/DC Very Fast Transient Response, tON(MIN) = 43ns, 4V ≤ VIN ≤ 38V, Controller 0.8V ≤ VOUT ≤ 0.9VIN, SSOP-16 LTC3879 No RSENSE Constant On-Time Synchronous Step-Down DC/DC Very Fast Transient Response, tON(MIN)= 43ns, 4V ≤ VIN ≤ 38V, Controller 0.6V ≤ VOUT ≤ 0.9VIN, MSOP-16E, 3mm × 3mm QFN-16 LTC3850/LTC3850-1/ Dual 2-Phase, High Efficiency Synchronous Step-Down DC/DC Phase-Lockable Fixed Operating Frequency 250kHz to 780kHz, 4V ≤ VIN ≤ 30V, 0.8V ≤ VOUT ≤ 5.25V LTC3850-2 Controllers, RSENSE or DCR Current Sensing and Tracking LTC3855 Dual, Multiphase Synchronous Step-Down DC/DC with Phase-Lockable Fixed Operating Frequency 250kHz to 770kHz, Differential Remote Sense 4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 12.5V ® High Efficiency, Compact Size, Ultrafast Transient Response, LTM4600HV 10A DC/DC μModule Complete Power Supply 4.5V ≤ VIN ≤ 28V, 0.8V ≤ VOUT ≤ 5V, 15mm × 15mm × 2.8mm LTM4601AHV 12A DC/DC μModule Complete Power Supply High Efficiency, Compact Size, Ultrafast Transient Response, 4.5V ≤ VIN ≤ 28V, 0.8V ≤ VOUT ≤ 5V, 15mm × 15mm × 2.8mm LTC3610 12A, 1MHz, Monolithic Synchronous Step-Down DC/DC High Efficiency, Adjustable Constant On-Time, 4V ≤ VIN ≤ 24V, VOUT(MIN) 0.6V, 9mm × 9mm QFN-64 Converter LTC3611 10A, 1MHz, Monolithic Synchronous Step-Down DC/DC High Efficiency, Adjustable Constant On-Time, 4V ≤ VIN ≤ 32V, VOUT(MIN) 0.6V, 9mm × 9mm QFN-64 Converter μModule is a registered trademark of Linear Technology Corporation. PART NUMBER LTC3854 DESCRIPTION Small Footprint Wide VIN Range Synchronous Step-Down DC/DC Controller No RSENSE Wide VIN Range Synchronous Step-Down DC/DC Controller 3823fd 26 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 1209 REV D • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006