LTC4222IUH-TRPBF

FEATURES n n n n n n n n n n n n LTC4222 Dual Hot Swap Controller with I2C Compatible Monitoring DESCRIPTION The LTC®4222 Hot Swap™ controller allows two power paths to be safely inserted and removed from a live backplane. Using external N-channel pass transistors, board supply voltages and inrush currents are ramped up at an adjustable rate. An I2C interface and onboard ADC allows for monitoring of current, voltage and fault status for each channel. The device features adjustable, analog, foldback current limit circuits and a Soft-Start circuit that sets the dI/dt of the inrush currents. An I2C interface may configure the part to latch off or automatically restart after the LTC4222 detects a fault on either channel. The controller has additional features to interrupt the host when a fault has occurred, notify when output power is good, detect insertion of a load card and power-up either automatically upon insertion or wait for an I2C command to turn on. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 7330065. Allows Safe Insertion Into a Live Backplane 10-Bit ADC Monitors Currents and Voltages I2C/SMBus Interface Wide Operating Voltage Range: 2.9V to 29V dI/dt Controlled Soft-Start High Side Drive for External N-Channel MOSFETs No External Gate Capacitors Required Input Overvoltage/Undervoltage Protection Optional Latchoff or Auto-Retry After Faults Alert Host After Faults Inrush Current Limit with Foldback Available in 32-Pin (5mm × 5mm) QFN and 36-Pin SSOP Packages APPLICATIONS n n n n Live Board Insertion Electronic Circuit Breakers Computers, Servers Platform Management TYPICAL APPLICATION Advanced Mezzanine Card Application 6mΩ 12V 34k 0.1μF 10Ω 1.02k 3.4k ON SDA SCL ALERT UV1 VDD1 OV1 ON SDA SCL ALERT CONFIG ADR0 ADR1 ADR2 INTVCC GND 3.4k 1.02k 0.1μF 3.3V 300mΩ Si1046R 4222 TA01a Si7336ADP 10.2k 10Ω 12V 7.4A 3.57k SENSE1– GATE1 SOURCE1 FB1 GPIO1 EN1 ADIN1 TIMER LTC4222 SS ADIN2 EN2 GPIO2 FB2 – SENSE2 GATE2 SOURCE2 10Ω 10nF 3.57k 4.99k 68nF 1μF Start-Up Waveform with Sequencing VIN1/2 10V/DIV CONTACT BOUNCE 12PGOOD VOUT2 10V/DIV VOUT1 10V/DIV NC 0.1μF OV2 UV2 VDD2 AUXPGOOD GPIO PGOOD 10V/DIV 10Ω 50ms/DIV 4222 TA01b 6.55k 3.3V 150mA BACKPLANE PLUG-IN CARD 4222f 1 LTC4222 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltages (VDDn) .............................. –0.3V to 35V Supply Voltage (INTVCC) ........................... –0.3V to 6.5V Input Voltages GATEn – SOURCEn (Note 3) .................... –0.3V to 5V SENSE+n ..........................VDDn – 6.5V to VDDn + 0.3V SENSE–n .............................–0.3V to SENSE+n + 0.3V SOURCEn.................................................. –5V to 35V UVn.....................................–0.3V to SENSE+n + 0.3V ENn, FBn, ON, OVn ................................ –0.3V to 12V ADR0-2, TIMER, SS ............... –0.3V to INTVCC + 0.3V ADINn, CONFIG...................................... –0.3V to 12V ALERT, SCL, SDA, SDAI, SDAO ............ –0.3V to 6.5V Output Voltages GATEn, GPIOn........................................ –0.3V to 35V Operating Temperature Range LTC4222C ................................................ 0°C to 70°C LTC4222I.............................................. –40°C to 85°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) SSOP ................................................................ 300°C PIN CONFIGURATION TOP VIEW SENSE1– TOP VIEW SOURCE1 SENSE1– GATE1 VDD1 GPIO1 SENSE1+ FB1 VDD1 UV1 OV1 24 EN1 23 ADIN1 22 ON 33 21 ALERT 20 SCL 19 SDA 18 ADIN2 17 EN2 9 10 11 12 13 14 15 16 SOURCE2 SENSE2– OV2 UV2 VDD2 GATE2 FB2 GPIO2 SS CONFIG INTVCC GND 1 2 3 4 5 6 7 8 9 36 GATE1 25 SOURCE1 34 FB1 33 GPIO1 32 EN1 31 ADIN1 30 ON1 29 ON2 28 ALERT 27 SCL 26 SDAI 25 SDAO 24 ADIN2 23 EN2 22 GPIO2 21 FB2 20 SOURCE2 19 GATE2 OV1 SS 1 CONFIG 2 INTVCC 3 GND 4 ADR0 5 ADR1 6 ADR2 7 TIMER 8 32 31 30 29 28 27 26 25 UV1 ADR0 10 ADR1 11 ADR2 12 TIMER 13 OV2 14 UV2 15 VDD2 16 SENSE2+ 17 SENSE2– 18 UH PACKAGE 32-LEAD (5mm 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD (PIN 33), PCB GND CONNECTION OPTIONAL G PACKAGE 36-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 95°C/W 4222f 2 LTC4222 ORDER INFORMATION LEAD FREE FINISH TC4222CG#PBF LTC4222IG#PBF LTC4222CUH#PBF LTC4222IUH#PBF TAPE AND REEL LTC4222CG#TRPBF LTC4222IG#TRPBF LTC4222CUH#TRPBF LTC4222IUH#TRPBF PART MARKING* LTC4222CG LTC4222IG LTC4222 LTC4222 PACKAGE DESCRIPTION 36-Lead Plastic SSOP 36-Lead Plastic SSOP 32-Lead (5mm × 5mm) Plastic QFN 32-Lead (5mm × 5mm) Plastic QFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted. SYMBOL Supplies VDDn IDD1 IDD2 VDDn(UVL) VDDn(HYST) INTVCC INTVCC(UVL) INTVCC(HYST) ΔVSENSE(TH) ΔVSENSE Input Supply Range VDD1 Input Supply Current VDD2 Input Supply Current Input Supply Undervoltage Lockout Input Supply Undervoltage Lockout Hysteresis Internal Regulator Voltage INTVCC Undervoltage Lockout INTVCC Undervoltage Lockout Hysteresis Circuit Breaker Threshold (VDD – VSENSE) Current Limit Voltage (VDD – VSENSE) VFB = 1.3V VFB = 0V Start-Up Timer Expired ΔVSENSE = 100mV VSENSE = 12V VDD = 2.9V to 29V Gate On, VGATE = 0V Gate Off, VGATE = 15V VGATE = 15V, (VDD – VSENSE)n = 200mV VDD – SENSE = 200mV, CGATE = 10nF VSOURCE = 2.9V to 29V VIN Rising IINTVCC = 0mA INTVCC Rising VDD1 = 12V VDD2 = 12V, IINTVCC = 0mA VDD Rising l l l l l l l l l l l l l l l l l l l l l l l ELECTRICAL CHARACTERISTICS PARAMETER CONDITIONS MIN 2.9 TYP MAX 29 UNITS V mA mA V mV V V mV mV mV mV mV mV μs μA V μA mA mA 0.85 3 2.34 60 3.15 2.55 35 47.5 48.75 46 14 130 10 0 4.7 –8 0.8 2.43 80 3.3 2.64 50 50 50 50 16.6 150 20 20 5.9 –12 1 450 0.5 3.8 1.215 80 2 4.3 1.235 128 7 1.2 4 2.53 100 3.45 2.73 65 52.5 51.25 54 19 165 30 40 6.5 –18 1.5 Current Limit and Circuit Breaker (Both Channels) tD(OC) ISENSE(IN) Gate Drive ΔVGATE IGATE(UP) IGATE(DN) IGATE(LIM) tPHL(SENSE) VGS(POWERBAD) Comparator Inputs VINPUT(TH) OC Fault Filter SENSE+/ – Pin Input Current External N-Channel Gate Drive (VGATE – VSOURCE) (Note 3) External N-Channel Gate Pull-Up Current External N-Channel Gate Pull-Down Current Pull-Down Current from GATE to SOURCE During OC/UVLO (VDD – SENSE) High to GATE Low (GATE-SOURCE) Voltage for Power Bad Fault CONFIG, EN, FB, ON, OV and UV Input Threshold FB Power Good Hysteresis 1 4.7 1.255 180 20 μs V V mV mV 4222f ΔVCONFIG,EN,ON(HYST) CONFIG, EN, ON Hysteresis ΔVFB(HYST) 3 LTC4222 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted. SYMBOL ΔVOV(HYST) ΔVUV(HYST) I(IN) IEN(UP) VUV(RTH) ΔVUV(RHYST) VGPIO(TH) Other Pin Functions VGPIO(OL) IGPIO(OH) ISOURCE tP(GATE) tD(GATE) GPIO Output Low Voltage GPIO Input Leakage Current SOURCE Input Current Input (ON, OV, UV, EN) to GATE Off Propagation Delay GATE Turn-On Delay ON UV, OV, EN Overcurrent Auto-Retry IGPIO = 5mA, VDD2 = 2.9V VGPIO = 15V SOURCE = 15V l l l l l l l l l l l l ELECTRICAL CHARACTERISTICS PARAMETER OV Hysteresis UV Hysteresis CONFIG, FB, ON, OV and UV Input Current EN Pull-Up Current UV Reset Threshold Voltage UV Reset Threshold Hysteresis GPIO Input Threshold CONDITIONS l l l l l l l MIN 16 60 5 0.36 60 0.8 TYP 24 90 0 10 0.4 125 1 0.25 0 MAX 32 110 ±1 20 0.46 180 1.2 0.4 ±1 170 5 8 125 6.7 0.22 1.255 110 2.6 58 12.5 0.95 UNITS mV mV μA μA V mV V V μA μA μs μs ms s V V μA μA N/A μA μA Bits VIN = 3V VEN = 0V VUV Falling VGPIO Rising 70 115 3 4 100 5 0.2 1.235 100 2.15 50 10 0.75 75 4.2 0.18 1.215 90 1.6 38 7.5 0.5 10 VTIMERL(TH) VTIMERH(TH) ITIMER(UP) ITIMER(DOWN) ITIMER(UP/DOWN) ISS ADC RES VFS Timer Low Threshold Timer High Threshold TIMER Pull-Up Current TIMER Pull-Down Current for OC Auto-Retry TIMER Pin OC Auto-Retry Duty Cycle Soft-Start Ramp Pull-Up Current Ramping Waiting for GATE to Slew l l l Resolution (No Missing Codes) Full-Scale Voltage (1023 • VLSB) (VDD – SENSE) SOURCE ADIN (VDD – SENSE) SOURCE ADIN (VDD – SENSE) SOURCE ADIN (Note 5) (VDD – SENSE) SOURCE ADIN VADIN = 1.28V VADIN = 1.28V l l l l l l l l l l l l l l l 64 32 1.28 62.5 31.25 1.25 ±3 ±2 ±2 ±0.5 ±1.5 ±1 ±1 1 2 0 15 ±0.1 mV V V μV mV mV LSB LSB LSB LSB % % % MΩ μA Hz LSB LSB Step Size VOS Offset Error INL TUE Integral Nonlinearity Total Unadjusted Error/Full-Scale Error RADIN IADIN ADIN Sampling Resistance ADIN Input Current Conversion Rate 4222f 4 LTC4222 ELECTRICAL CHARACTERISTICS SYMBOL I2C Interface VADR(H) IADR(IN,Z) VADR(L) IADR(IN) VALERT(OL) IALERT(OH) VSDA,SCL(TH) ISDA,SCL(OH) VSDA(OL) I2C Interface Timing fSCL(MAX) tBUF(MIN) tHD,STA(MIN) tSU,STA(MIN) tSU,STO(MIN) tHD,DAT(MIN) tHD,DATO tSU,DAT(MIN) tSP tRST CX SCL Clock Frequency Bus Free Time Between Stop/Start Condition Hold Time After (Repeated) Start Condition Repeated Start Condition Set-Up Time Stop Condition Set-Up Time Data Hold Time (Input) Data Hold Time (Output) Data Set-Up Time Suppressed Spike Pulse Width Stuck-Bus Reset Time SCL, SDA Input Capacitance SCL or SDA Held Low SDAI Tied to SDAO (Note 5) 50 25 300 Operates with fSCL ≤ fSCL(MAX) 400 1000 0.12 100 30 140 30 600 30 110 32 1.3 600 600 600 100 900 600 250 40 10 kHz μs ns ns ns ns ns ns ns ms pF ADR0, ADR1, ADR2 Input High Voltage ADR0, ADR1, ADR2 Hi-Z Input Current ADR0, ADR1, ADR2 Input Low Voltage ADR0, ADR1, ADR2 Input Current ALERT Output Low Voltage ALERT Input Current SDA, SCL Input Threshold SDA, SCL Input Current SDA Output Low Voltage SCL, SDA = INTVCC ISDA = 3mA ADR0, ADR1, ADR2 = 0V, INTVCC IALERT = 3mA ALERT = INTVCC ADR0, ADR1, ADR2 = 0.8V, INTVCC – 0.8V l l l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted. PARAMETER CONDITIONS MIN INTVCC – 0.8 5 0.2 –80 0.2 1.5 1.7 0.2 TYP INTVCC – 0.4 0 0.4 MAX INTVCC – 0.2 –5 0.8 80 0.4 ±1 1.9 ±1 0.4 UNITS V μA V μA V μA V μA V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive, all voltages are referenced to GND unless otherwise specified. Note 3: An internal clamp limits the GATE pin to a minimum of 5V above SOURCE. Driving this pin to voltages beyond the clamp may damage the device. Note 4: Integral Nonlinearity is defined as the deviation of a code from a precise analog input voltage. Maximum specifications are limited by the LSB step size and the single shot measurement. Typical specifications are measured from 1/4, 1/2, 3/4 areas of the quantization band. Note 5: Guaranteed by design and not subject to test. 4222f 5 LTC4222 TYPICAL PERFORMANCE CHARACTERISTICS IDD1 vs VDD1 1.0 0.9 3.5 0.8 0.7 0.6 2.5 0.5 0.4 2.0 2.9 2.8 2.5 3.0 INTVCC (V) 0 5 15 VDD2 (V) 4222 G01 4222 G02 TA = 25°C. VDDn = 12V unless otherwise noted. IDD2 vs VDD2 4.0 3.4 3.3 3.2 IDD2 (mA) 3.1 3.0 INTVCC vs VDD2 IDD1 (mA) 0 5 10 15 VDD1 (V) 20 25 30 10 20 25 30 3.0 3.5 4.0 VDD2 (V) 4.5 5.0 4222 G03 INTVCC vs ILOAD 3.50 1.250 1.245 3.25 VTH(UV) vs Temperature 100 VHYST(UV) vs Temperature 95 VHYST(UV) (mV) –25 25 0 50 TEMPERATURE (°C) 75 100 4222 G05 3.00 VTH(UV) (V) INTVCC (V) VDD2 = 2.9V VDD2 = 3.3V VDD2 = 5V VDD2 = 12V 1.240 1.235 1.230 90 2.75 1.225 2.50 1.220 –50 85 0 2.5 5.0 7.5 10.0 ILOAD (mA) 12.5 15.0 4222 G04 80 –50 –25 25 0 50 TEMPERATURE (°C) 75 100 4222 G06 4222f 6 LTC4222 TYPICAL PERFORMANCE CHARACTERISTICS ITIMER vs Temperature 110 60 50 CURRENT LIMIT (mV) 105 ITIMER (μA) 40 30 20 10 90 –50 0 TA = 25°C. VDDn = 12V unless otherwise noted. VTH Circuit Breaker vs Temperature 53 52 51 50 49 48 47 –50 Current Limit vs VFB 100 95 –25 25 0 50 TEMPERATURE (°C) 75 100 4222 G07 0 0.2 0.4 0.6 0.8 VFB (V) 1.0 1.2 1.4 VTH CIRCUIT BREAKER (mV) –25 25 0 50 TEMPERATURE (°C) 75 100 4222 G09 4222 G08 ΔVGATE vs Temperature 6.1 6.0 6.0 5.9 ΔVGATE (V) ΔVGATE (V) 5.8 5.7 5.6 5.5 5.4 –50 VDD2 = 2.9V VDD2 = 3.3V VDD2 = 5V VDD2 = 12V –25 25 0 50 TEMPERATURE (°C) 75 100 4222 G10 ΔVGATE vs IGATE 6.5 VDD2 = 2.9V VDD2 = 3.3V VDD2 = 5V VDD2 = 12V IGATE (μA) 12.0 IGATE vs Temperature 11.9 5.5 11.8 5.0 11.7 4.5 11.6 4.0 0 2 4 8 6 IGATE (A) 10 12 14 4222 G11 11.5 –50 –25 25 0 50 TEMPERATURE (°C) 75 100 4222 G12 4222f 7 LTC4222 TYPICAL PERFORMANCE CHARACTERISTICS VOL(GPIO) vs IGPIO 0.6 0.5 0.4 ERROR (%) VGPIO (V) 0.3 0.2 0.1 0 1.0 0.9 0.8 0.7 INL (LSB) 0.6 0.5 0.4 0.3 0.2 0.1 0 2 4 6 IGPIO (mA) 8 10 4222 G13 TA = 25°C. VDDn = 12V unless otherwise noted. ADC Total Unadjusted Error vs CODE (ADIN1) 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 256 512 CODE 768 1024 4222 G14 ADC INL vs CODE (ADIN1) 0 –0.5 0 256 512 CODE 768 1024 4222 G15 ADC DNL vs CODE (ADIN1) 0.5 0.4 0.3 0.2 DNL (LSB) 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 256 512 CODE 768 1024 4222 G16 ADC Full-Scale Error vs Temperature 4 3 FULL-SCALE ERROR (LSB) 2 1 0 –1 –2 –3 –4 –50 0.1 –25 0 50 25 TEMPERATURE (°C) 75 100 4222 G17 TPHL VGATE vs VSENSE Overdrive 100 TPHL VGATE (μs) 10 1 0 50 100 150 200 250 300 350 400 VSENSE (mV) 4222 G18 4222f 8 LTC4222 PIN FUNCTIONS ADIN: ADC Input. A voltage between 0 and 1.28V applied to this pin is measured by the on-board ADC. Tie to ground if unused. ADR0, ADR1, ADR2: Serial Bus Address Inputs. Tying these pins to ground, open, or INTVCC configures one of 27 possible addresses. See Table 1 in Applications Information. ALERT: Fault Alert Output. Open drain logic output that is pulled to ground when a fault occurs to alert the host controller. A fault alert is enabled by setting the corresponding bit in the ALERT register as shown in Table 4. See Applications Information. Tie to ground if unused. CONFIG: Configuration Input. Configures the part to control the two channels together or independently. When CONFIG is tied to GND both channels start up at the same time. A fault, EN or ON turn-off command on either channel will shut down both channels. When CONFIG is tied to INTVCC, either channel can start up independently. A fault, EN or ON turn-off command will result in the associated channel turning off, while the other channel remains on. If one channel is commanded to turn on while another channel is in the turn-on sequence, the 4222 waits until the first channel has finished its turn-on sequence before turning on the second channel. EN1, EN2: Enable Input. Ground this pin to indicate a board is present and enable the N-channel MOSFET to turn-on. When this pin is high, the MOSFET is not allowed to turn on. An internal 10μA current source pulls up this pin. Transitions on this pin are recorded in the FAULT register. A high-to-low transition activates the logic to read the state of the ON pin and clear faults. See Applications Information. EXPOSED PAD: (Pin 33, QFN Package) Exposed Pad. May be left open or connected to device ground. FB1, FB2: Foldback Current Limit and Power-Good Input. A resistive divider from the output is tied to this pin. When the voltage at this pin drops below 1.235V, power is not considered good. The power bad condition may result in the GPIO pin pulling low or going high impedance depending on the configuration of CONTROL register bits 6 and 7. Also a power bad fault is logged when the FB pin is low, the LTC4222 has finished the startup cycle and the GATE pin is high. See Applications Information. The startup current limit folds back from 50mV sense voltage to 16.6mV as the FB voltage drops from 0.8V to 0.2V. Foldback is not active once the part leaves startup and the current limit is increased to 150mV. GATE1, GATE2: Gate Drive for External N-Channel MOSFET. An internal 12μA current source charges the gate of the MOSFET. No compensation capacitor is required on the GATE pin, but a resistor and capacitor network from this pin to ground may be used to set the turn-on output voltage slew rate. During turn-off there is a 1mA pull-down current. During a short circuit or under-voltage lockout (VDD or INTVCC), a 450mA pull-down current source between GATE and SOURCE is activated. GND: Device Ground. GPIO1, GPIO2: General Purpose Input/Output. Open drain logic output or logic input. Defaults to an output set to pull low to indicate power is not good. Configure according to Table 3. INTVCC: Low Voltage Supply Decoupling Output. Connect a 0.1μF capacitor from this pin to ground. ON: (QFN Package) On Control Input. Formed by internally tying the ON1 and ON2 lines together. ON1, ON2: (SSOP Package) On Control Inputs. A rising edge turns on the external N-channel FET and a falling edge turns it off. This pin also configures the state of the FET ON register bit (and hence the external FET) at power up. For example, if the ON pin is tied high, then the FET ON bit (Control bit 3 in Table 3) goes high 100ms after power-up. Likewise if the ON pin is tied low then the channel remains off after power-up until the FET ON bit is set high using the I2C bus. A high-to-low transition on this pin clears the fault register for the related channel. The two ON pins are tied together internally on the QFN package. OV1, OV2: Overvoltage Comparator Input. Connect this pin to an external resistive divider from VDD. If the voltage at this pin rises above 1.235V, an overvoltage fault is detected and the GATE turns off. Tie to GND if unused. 4222f 9 LTC4222 SCL: Serial Bus Clock Input. Data at the SDA pin is shifted in or out on rising edges of SCL. This is a high impedance pin that is generally driven by an open collector output from a master controller. An external pull-up resistor or current source is required. SDAO: (SSOP Package) Serial Bus Data Output. Opendrain output for sending data back to the master controller or acknowledging a write operation. Normally tied to SDAI to form the SDA line. An external pull-up resistor or current source is required. Internally tied to SDAI in QFN package. SDAI: (SSOP Package) Serial Bus Data Input. A high impedance input for shifting in address, command or data bits. Normally tied to SDAO to form the SDA line. Internally tied to SDAO in QFN package. SDA: (QFN Package) Serial Bus Data Input/Output Line. Formed by internally tying the SDAO and SDAI lines together. An external pull-up resistor or current source is required. SENSE1–, SENSE2–: Negative Current Sense Input. Connect this pin to the output of the current sense resistor. The current limit circuit controls the corresponding GATE pin voltage to limit the sense voltage between the SENSE+ and SENSE– pins to the level set by the soft-start and foldback characteristic, with a maximum of 50mV during start-up and to 150mV independent of soft-start and foldback after the start-up timer has expired. A circuit breaker, enabled after start-up, trips when the sense voltage exceeds 50mV for 20μs. SENSE1+, SENSE2+: (SSOP Package) Positive Current Sense Input. Connect this pin to the input of the current sense resistor. It must be connected to the same trace as VDDn. Internally tied to VDDn in the QFN package. SOURCE1, SOURCE2: N-Channel MOSFET Source and ADC Input. Connect this pin to the source of the external N-Channel MOSFET switch for gate drive return. This pin also serves as the ADC input to monitor output voltage. The pin provides a return for the gate pull-down circuit. SS: Soft-Start Input. Sets the inrush current slew rate at startup. Connect a 68nF capacitor to provide 5mV/ms as the slew rate for the sense voltage in startup. This corresponds to 1A/ms with a 5mΩ sense resistor. Note that a large Soft-Start capacitor and a small TIMER capacitor may result in a condition where the timer expires before the inrush current has started. Allow an additional 2nF of timer capacitance per 1nF of Soft-Start capacitor to ensure proper startup. TIMER: Startup Timer Input. Connect a capacitor between this pin and ground to set a 12.3ms/μF duration for startup, after which an overcurrent fault is logged if the inrush is still current limited. The duration of the off time is 600ms/μF when overcurrent auto-retry is enabled, resulting in a 1:50 duty cycle. An internal timer provides a 100ms startup time and 5s auto-retry time if this pin is tied to INTVCC. Allow an additional 2nF of timer capacitance per 1nF of Soft-Start (SS) capacitor to ensure proper startup. UV1, UV2: Undervoltage Comparator Input. Connect this pin to an external resistive divider from VDD. If the voltage at this pin falls below 1.145V, an undervoltage fault is detected and the GATE turns off. Pulling this pin below 0.4V resets the fault register for that channel except for the UV fault bit. Tie to INTVCC if unused. VDD1, VDD2: Supply Voltage Input and Positive Current Sense Input. This pin has an undervoltage lockout threshold of 2.43V. In the QFN package this pin is also the positive current sense input. 4222f 10 LTC4222 FUNCTIONAL DIAGRAM FB SENSE– 0.2V 0.6V 1.235V UV FOLDBACK and DIDT 0mV TO 150mV SENSE+ (SSOP) + UV – CS UVS CB 50mV – 0.4V +– + CHARGE PUMP AND GATE DRIVER FET ON GATE SOURCE + RST RESET FAULT – OV + OV1 INTVCC 1.235V 1.235V + OVS 1.235V PG PWRGD – – 10 A EN + EN EN – 2.43V + UVLO1 LOGIC VDD UVLO VDD – SS SOFT-START 0.2V + TM1 INTVCC 100 A TIMER 2A VDD2 TM2 3.3V GEN INTVCC CONFIG – + 1.235V COUPLE – 1.235V + – SDAI (SSOP) SDAO (SSOP) SDA (QFN) SCL ALERT I2C ADDR I2C 5 VCC UVLO ADIN1 SOURCE1 A/D CONVERTER 10 BIT VDDA – SENSE1 ADIN2 SOURCE2 VDDB – SENSE2 4222 BD 1 OF 27 ADR2 +– – + + GP GPIO – 1V + ONS ON ON – 1.235V 2x 1x + UVLO2 – 2.64V ADR0 ADR1 4222f 11 LTC4222 TIMING DIAGRAM SDAI/SDAO tSU, DAT tHD, DATO, tHD, DATI tSU, STA tSP tHD, STA tSP tBUF tSU, STO 4222 TD01 SCL tHD, STA START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION OPERATION The LTC4222 is designed to turn two supply voltages on and off in a controlled manner, allowing boards to be safely inserted or removed from a live backplane. During normal operation, the charge pump and gate drivers turn on external N-channel MOSFET gates to pass power to the loads. The gate driver circuits use a charge pump that derives its power from the VDD1 or VDD2 pin, whichever is higher. Also included in the gate driver circuits are internal 6.5V GATE to SOURCE clamps to protect the oxide of logic level MOSFETs. During start-up the inrush currents are tightly controlled by using current limit foldback, soft start dI/dt limiting and output dI/dt limiting. The LTC4222 is capable of controlling both channels independently, or coupling control signals so that both channels start up and turn off together. The current sense (CS) amplifiers monitor the load currents using the difference between the SENSE+ (VDD for QFN) and SENSE– pin voltages. A CS amplifier limits the current in the load by pulling back on the GATE-to-SOURCE voltage in an active control loop when the sense voltage exceeds the commanded value. The CS amplifiers require 20μA input bias current from both the SENSE+ and the SENSE– pins. A short circuit on an output to ground results in excessive power dissipation during active current limiting. To limit this power, the corresponding CS amplifier regulates the voltage between the SENSE+ and SENSE– pins at 150mV. If an overcurrent condition persists, the internal circuit breaker (CB) registers a fault when the sense voltage exceeds 50mV for more than 20μs. This indicates to the logic that it is time to turn off the GATE to prevent overheating. At this point the TIMER capacitor starts to discharge with the 2μA current source until the voltage drops below 0.2V (comparator TM1) which tells the logic that the pass transistor has cooled and it is safe to turn on again if overcurrent auto-retry is enabled. If the TIMER pin is tied to INTVCC, the cool-down time defaults to 5 seconds using an internal system timer. The output voltages are monitored using the FB resistive divider and the Power Good (PG) comparators to determine when output voltages are acceptable for the loads. The power good conditions are signaled by the GPIO1 and GPIO2 pins using open-drain pull-down transistors. The GPIO pins may also be independently configured to signal power bad, or as general purpose inputs (GP comparators), or general purpose open drain outputs. The Functional Diagram shows the monitoring blocks of the LTC4222. The group of comparators on the left side includes the undervoltage (UV), overvoltage (OV), reset (RST), enable (EN) and on (ON) comparators for channel 1 or 2. These comparators determine if the external conditions are valid prior to turning on their corresponding GATE. The two undervoltage lockout circuits, UVLO1 and UVLO2, validate the input supplies and the internally generated 3.3V supply, INTVCC. UVLO2 also generates the power-up initialization to the logic circuits as INTVCC crosses this rising threshold. The CONFIG pin is used to select the desired startup behavior of the LTC4222. When the CONFIG pin is low, both channels will start up and turn off simultaneously and a fault on either channel will result in both channels turning off, or prevent both channels from starting up. When the 4222f 12 LTC4222 OPERATION CONFIG pin is high the two channels work completely independently and ignore the behavior of the other channel. This allows for the channels to start up in sequence by connecting the GPIO (power good) output of one channel to the UV pin of the other channel. The two channels share the TIMER and SS (soft-start) pins that control startup behavior. If the CONFIG pin is high and one channel is enabled while the other channel is starting up, the LTC4222 will wait for the startup cycle to end before starting up the second channel to ensure that it gets a full timer cycle. The exception to this is the ON pins, which turn on the corresponding channel immediately. When both channels startup simultaneously, the inrush current for both channels is limited by whichever FB pin is lowest. Included in the LTC4222 is a 10-bit A/D signal. The 6-input multiplexer ahead of the A/D converter allows to select between the two ADIN pins, the two SOURCE pins and the two current sense devices. An I2C interface is provided to read the A/D registers. It also allows the host to poll the device and determine if faults have occurred. If the ALERT line is configured as an interrupt, the host is enabled to respond to faults in real time. The SDA line is divided into an SDAI (input) and SDAO (output). This simplifies applications using an optoisolator driven directly from the SDAO output. The I2C device address is forwarded to the address decoder from the ADR0, ADR1 and ADR2 pins. These inputs have three states each that decode into a total of 27 device addresses. APPLICATIONS INFORMATION A typical LTC4222 application is in a high availability system in which two positive voltage supplies are distributed to one or more cards. The device measures card voltages and currents and records past and present fault conditions for both channels. The system queries each LTC4222 over the I2C periodically and reads status and measurement information. A basic LTC4222 application circuit is shown in Figure 1. The following sections cover turn-on, turn-off and acts upon various faults that the LTC4222 detects. External component selection is discussed in detail in the Design Example section. Turn-On Sequence The power supplies on a board are controlled by using external N-channel pass transistors (Q1 and Q2) placed in the power path. Note that resistor RSn provides current detection. Resistors R1n, R2n and R3n define undervoltage and overvoltage levels for the two channels. R5n prevents high frequency oscillations in Qn and R6n. C1n forms an optional network that may be used to provide an output dV/dt limited start-up. Several conditions must be present before the external MOSFET for a given channel turns on. First the external supplies, VDDn, must exceed their 2.44V undervoltage lockout levels. Next the internally generated supply, INTVCC, must cross its 2.64V undervoltage threshold. This generates a 60μs to 120μs power-on-reset pulse. During reset the fault registers are cleared and the control registers are set or cleared as described in the register section. After a power-on-reset pulse, the LTC4222 goes through the following turn-on sequence for one or both channels. First the UV and OV comparators indicate that input power is within the acceptable range, which is indicated by STATUS bits 0 to 1 in Table 5. Second, the EN pin is externally pulled low. Finally, all of these conditions must be satisfied for the duration of 100ms to ensure that any contact bounce during insertion has ended. Additionally, if the CONFIG pin is low all initial conditions for both channels must be met before the pair are allowed to turn on together. When these initial conditions are satisfied, the ON pin is checked and it’s state written to bit 3 in the CONTROL register (Table 3). If it is high, the external MOSFET is turned on. If the ON pin is low, the external MOSFET is turned on when the ON pin is brought high or if a serial bus turn-on command is sent by setting CONTROL bit 3. If the CONFIG pin is low, either both ON pins must be high or both CONTROL registers third bits must be set in order for the external MOSFETs to be turned on simultaneously. 4222f 13 LTC4222 APPLICATIONS INFORMATION VIN1 12V RS1 0.01Ω Z1 SA14A R11 140k Q1 FDD3706 R71 10.2k R81 3.57k R5-1 10Ω RG1 15k CG1 3.9nF CF1 0.1μF R21 4.53k R31 13.7k UV1 VDD1 OV1 ON SDA SCL ALERT CONFIG ADR0 ADR1 ADR2 INTVCC GND R32 13.7k R22 3.32k OV2 UV2 VDD2 R41 100k SENSE1– GATE1 ON SDA SCL ALERT SOURCE1 FB1 GPIO1 EN1 ADIN1 TIMER SS CTIMER 0.68μF CSS 68nF NC LTC4222 ADIN2 EN2 GPIO2 FB2 SOURCE2 C3 0.1μF GND SENSE2– GATE2 RG2 15k R5-2 10Ω CG2 3.9nF CF2 0.1μF VIN2 3.3V BACKPLANE PLUG-IN CARD R82 3.57k R72 4.99k R42 100k R12 23.7k Z2 SA14A RS2 0.01Ω Q2 FDD3706 4222 TA01a Figure 1. Typical Application A MOSFET is turned on by charging up the GATE with a 12μA current source. When the GATE voltage reaches the MOSFET threshold voltage, the MOSFET begins to turn on and the SOURCE voltage then follows the GATE voltage as it increases. While the MOSFET is turning on, the inrush current increases linearly at a dI/dt rate selected by capacitor CSS. This is accomplished using the current limit amplifier controlling the GATE pin voltage. Once the inrush current reaches the limit set by the FB pin, the dI/dt ramp stops and the inrush current follows the foldback profile as shown in Figure 2. When both channels turn on simultaneously, the foldback current limit is set by the lower of the two FB pins. A start-up timer is used to prevent damaging the MOSFET when starting up into a short-circuit. The TIMER capacitor integrates at 100μA during start-up and once the TIMER pin reaches threshold of 1.235V, the part checks to see if it is in current limit. If this is the case, the overcurrent fault bit, FAULT bit 2 in Table 6, is set and the part turns off. If the part is not in current limit, the 50mV circuit breaker is armed and the current limit is switched to 150mV. Alternately an internal 100ms start-up timer may be selected by tying the TIMER pin to INTVCC. As the SOURCE voltage rises, the FB pin voltage follows as set by R7 and R8. Once FB crosses its 1.235V threshold, and the start-up timer has expired, the corresponding GPIO pin, in the default power good configuration, ceases to pull low and indicates that power is now good. Alternately STATUS bit 3 can be read to check power-good status, where a zero indicates that power is good. If a series resistor and capacitor from GATE to GROUND (R6 and C1) are employed to provide a constant inrush current during start-up, which provides a constant dV/dt at 4222f 14 LTC4222 APPLICATIONS INFORMATION VDD + 6V VGATE drive voltage is 4.7V. The GATE-to-SOURCE voltage is clamped below 6.5V to protect the gates of logic level N-channel MOSFETs. Turn-Off Sequence One or both GATE pins are turned off by a variety of conditions. A normal turn-off is initiated by an ON pin going low or a serial bus turn-off command. Additionally, several fault conditions cause a GATE to turn off. These include an input overvoltage (OV pin), input undervoltage (UV pin), overcurrent circuit breaker (SENSE– pin), or EN transitioning high. Writing a logic one into the UV, OV or OC fault bits (FAULT register bits 0 to 2 in Table 6) also latches off the associated GATE if their auto-retry bits are set to false. A MOSFET is turned off with a 1mA current pulling down the GATE pin to ground. With the MOSFET turned off, the SOURCE and FB voltages drop as CL discharges. When the FB voltage crosses below its threshold, GPIO may be configured to pull low to indicate that the output power is no longer good. If the INTVCC pin drops below 2.60V for greater than 1μs, or the associated VDD pin falls below 2.35V for greater than 2μs, a fast shut down of the MOSFET is initiated. In this case the GATE pin is pulled down with a 450mA current to the SOURCE pin. Overcurrent Fault The LTC4222 has different current limiting behavior during start-up, when the output supply ramps up under TIMER, SS and FB control, and normal operation. As such it can generate an overcurrent fault during both phases of operation. Both set the faulting supply’s overcurrent fault bit (FAULT register bit 2) and shut off the faulting GATE, or both GATEs if the CONFIG pin is low. During start-up when both TIMER and SS are ramping, the current limit is a function of SS pin voltage and the voltage on the FB pins. A supply could power up entirely in current limit depending on the bypass capacitor at the outputs of the ramping supplies. The TIMER pin sets the time duration for current limit during startup, either 12.3ms/μF when using a timer capacitor, or 100ms when the TIMER pin is tied to INTVCC. If the supply is still in current limit at the end of the timing cycle, an overcurrent fault is declared for that 4222f VDD VOUT GPIO (POWER GOOD) VSENSE 25mV tSTARTUP 10mV ILOAD • RSENSE 4222 F02 SS LIMITED FB LIMITED TIMER EXPIRES Figure 2. Power-Up Waveform the output, a 12μA pull-up current (IGATE) from the GATE pin slews the gate upwards and resulting current is less than the current limit. Because the inrush current is less than the current limit, the start-up timer can expire without producing an overcurrent fault and a small timer capacitor may be used. After the timer has expired power-good will not be signaled until the FB pin crosses its threshold and the GATE to SOURCE voltage crosses the 4.3V threshold that indicates the MOSFET is fully enhanced. When both those conditions are met the output voltage is suitable for the load to be turned on and the impedance back to the supply through the MOSFET is low. Power-good is then asserted with the GPIO pin or read via the interface, signaling that it is safe to turn on downstream loads. A power-bad fault is not generated when starting up in this manner because the FB pin will cross its threshold before the GATE to SOURCE threshold is crossed. RG should be chosen such that IGATE • RG is less than the threshold of the MOSFET to avoid a current spike at the beginning of startup. Reducing RG degrades the stability of the current limit circuit, see applications information on current limit stability. GATE Pin Voltage A curve of GATE-to-SOURCE voltage vs VDD is shown in the Typical Performance Characteristics. At minimum input supply voltage of 2.9V, the minimum GATE-to-SOURCE 15 LTC4222 APPLICATIONS INFORMATION supply and the MOSFET is turned off. If the CONFIG pin is low, then both channels will turn off together. After the switch has turned off due to an OC fault the part will wait for a cool-down period before allowing the switch to turn on again. If the TIMER pin is tied to VCC the cool-down period will be 5s on the internal timer. Otherwise if using a TIMER capacitor, the capacitor will discharge at 2μA and the internal 100ms timer is started, when the 100ms timer expires and the TIMER pin reaches its 0.2V lower threshold the part is allowed to restart if the overcurrent fault bit (FAULT register bit 2) has been cleared or the overcurrent auto-retry bit (CONTROL register bit 2) has been set. After start-up, a supply has dual-level glitch-tolerant protection against overcurrent faults. The sense resistor voltage drop is monitored by a 50mV electronic circuit breaker and a 150mV active current limit. In the event that a supply’s current exceeds the circuit breaker threshold, an internal 20μs timer is started. If the supply is still overcurrent after 20μs the circuit breaker trips and the switch is turned off. An analog current limit loop prevents the supply current from exceeding exceeding the 150mV current limit in the event of a short circuit. The 20μs filter delay and the higher current limit threshold prevent unnecessary resets of the board due to minor current surges. The LTC4222 will stay in the latched off state unless the overcurrent auto-retry bit (CONTROL register bit 2) is set, in which case the switch turns on again after 100ms when using the external TIMER capacitor to set the startup time, or 5s when using the internal timer. Note that current limit foldback is not active after start-up. Overvoltage Fault An overvoltage fault occurs when an OV pin rises above its 1.235V threshold for more than 2μs. This shuts off the corresponding GATE with a 1mA current to ground and sets the overvoltage present STATUS bit 0 and the overvoltage FAULT bit 0. If the pin subsequently falls back below the threshold for 100ms, the GATE is allowed to turn on again unless overvoltage auto-retry has been disabled by clearing CONTROL bit 0. If the CONFIG pin is tied low, an OV fault on either channel will shut off both channels simultaneously. Undervoltage Fault An undervoltage fault occurs when a UV pin falls below its 1.235V threshold for more than 2μs. This turns off the corresponding GATE with a 1mA current to ground and sets undervoltage present STATUS bit 1 and undervoltage FAULT bit 1. If the UV pin subsequently rises above the threshold for 100ms, the GATE is turned on again unless undervoltage auto-retry has been disabled by clearing CONTROL bit 1. When power is applied to the device, if UV is below its 1.235V threshold after INTVCC crosses its 2.64V undervoltage lockout threshold, an undervoltage fault is logged in the FAULT register. If the CONFIG pin is tied low, an UV fault on either channel will shut off both channels simultaneously. ON Signals and the CONFIG Pin Turn-on commands are issued from the ON pins or the I2C interface. Internally, rising and falling edges of the ON pins set and reset the FET_ON register bits. Unlike the other control signals such as UV, OV and EN, the rising edge of the ON signal is not filtered by the 100ms internal timer and instead turns on the corresponding channel immediately. Cycling an ON signal cancels the corresponding channel’s overcurrent auto-retry cool-down period, allowing the channel to restart after a 100ms delay. To start up and shut down both channels at the same time set the CONFIG pin low. Both channels then start up when all the UV, OV, EN and ON signals are in the correct state to turn on both channels, and when any of these signals turns one channel off, both channels turn off. Setting the CONFIG pin high allows the two channels to 4222f LOAD CURRENT 5A/DIV VGATE 10V/DIV VSOURCE 10V/DIV VGPIO 5V/DIV 10μs/DIV CL = 0F RSHORT = 5mΩ RS = 20mΩ RG = 1k CG = 1μF 4222 F03 Figure 3. Short-Circuit Waveform 16 LTC4222 APPLICATIONS INFORMATION start up and turn off independently. When both ON signals are brought high sequentially, the channel turned on first immediately begins to start up and the second channel has a 200ns window to assert it’s ON signal in order to start up in the same timer period. If the second ON signal is asserted after the 200ns window but before the end of the first channel’s startup time, the second channel startup is delayed. The second channel will then start 100ms after the first channel’s start up timer has expired and the TIMER pin, if used, reaches its 200mV low threshold. When an external TIMER capacitor is used, the TIMER capacitor voltage ramps up with a 100μA current. Once the TIMER pin reaches its 1.235V threshold the TIMER begins to discharge. While the TIMER capacitor is discharging, the ON signal for the second channel should not be asserted for 2ms/μF of TIMER capacitance. This allows the TIMER capacitor to return to its low state and ensures that the next channel to start receives a full timer cycle. This wait time is unnecessary when using the internal 100ms timer. Board Present Change of State 4222 F04 is reinserted the fault register is cleared except for FAULT bit 4. After 100ms the state of the ON pin is latched into bit 3 of the CONTROL register. At this point the channel starts up again. If a connection sense on the plug-in card is driving an EN pin, insertion or removal of the card may cause the pin voltage to bounce. This results in clearing the fault register when the card is removed. The pin may be debounced using a filter capacitor, CEN, on the EN pin as shown in Figure 4. The filter time is given by: tFILTER = CEN • 123 (ms/μF) OUT LTC4222 SOURCE 10μA EN CEN + – GND 1.235V LOAD The EN pins may be used to detect the presence of one or two downstream cards. Whenever an EN pin toggles, FAULT bit 4 is set to indicate a change of state. When the EN pin goes high, indicating board removal, the corresponding GATE turns off immediately (with a 1mA current to ground) and the board present STATUS bit 4, is cleared. If the EN pin is pulled low, indicating a board insertion, all fault bits for that channel except FAULT bit 4 are cleared and enable STATUS bit 4, is set. If the EN pin remains low for 100ms the state of the ON pin is captured in ‘FET On’ CONTROL bit 3. This turns the switch on if the ON pin is tied high. There is an internal 10μA pull-up current source on the EN pin. If the CONFIG pin is tied low, both EN pins must be low for 100ms for the two channels to be enabled and if either EN pin goes high both channels will turn off. If a channel shuts down due to a fault, it may be desirable to restart that channel simply by removing and reinserting the related load card. In cases where the LTC4222 and the switch reside on a backplane or midplane and the load resides on a plug-in card, the EN pin detects when the plug-in card is removed. Figure 4 shows an example where the EN pin is used to detect insertion. Once the plug-in card MOTHERBOARD CONNECTOR PLUG-IN CARD Figure 4. Plug-In Card Insertion/Removal FET Short Fault A FET short fault is reported if the data converter measures a current sense voltage greater than or equal to 2mV while the corresponding GATE is turned off. This condition sets FET short bit, Fault bit 5. Power Bad Fault A power bad fault is reported if a FB pin voltage drops below its 1.235V threshold for more than 2μs when the corresponding GATE is above the 4.3V gate to source threshold. This pulls the GPIO pin low immediately in the default power good configuration, and sets power-bad present bit, STATUS bit 3, and power bad bit, FAULT bit 3. A circuit prevents power-bad faults if the GATE-to-SOURCE voltage is low, eliminating false power-bad faults during power-up or power-down. If the FB pin voltage subsequently rises back above the threshold, a power-good configured GPIO pin returns to a high impedance state and STATUS bit 3 is reset. 4222f 17 LTC4222 APPLICATIONS INFORMATION Fault Alerts When any of the fault bits in a FAULT register (see Table 4) are set, an optional bus alert is generated if the appropriate bit in the ALERT register has been set. This allows only selected faults to generate alerts. At power-up the default state is to not alert on faults and the ALERT pin is high. If an alert is enabled, the corresponding fault causes the ALERT pin to pull low. After the bus master controller broadcasts the Alert Response Address, the LTC4222 responds with its address on the SDA line and releases ALERT as shown in Table 7. If there is a collision between two LTC4222s responding with their addresses simultaneously, then the device with the lower address wins arbitration and responds first. The ALERT line is also released if the device is addressed by the bus master if ALERT is pulled low due to an alert. Once the ALERT signal has been released for one fault, it is not pulled low again until the FAULT register indicates a different fault has occurred or the original fault is cleared and it occurs again. Note that this means repeated or continuing faults do not generate alerts until the associated FAULT register bit has been cleared. Resetting Faults Faults are reset with any of the following conditions on a given channel. First, a serial bus command writing zeros to the FAULT register bits 0 to 5 clears the associated faults. Second, FAULT register bits 0 to 5 are cleared when the corresponding switch is turned off by the ON pin or STATUS bit 3 going from high to low, if the corresponding UV pin is brought below its 0.4V reset threshold for 2μs, or if INTVCC falls below its 2.64V undervoltage lockout threshold. Finally, when EN is brought from high to low, only corresponding FAULT bits 0-3 and 5 are cleared, and bit 4, which indicates a EN change of state, is set. Note that faults that are still present, as indicated in the STATUS registers, cannot be cleared. The FAULT registers are not cleared when auto-retrying. When auto-retry is disabled the existence of an overvoltage, undervoltage, or overcurrent fault keeps the switch off. As soon as the fault is cleared, the switch turns on. If auto-retry is enabled, then a high value in STATUS register bits 0 or 1 holds the switch off and the fault register is ignored. Subsequently, when STATUS register bits 0 and 1 are cleared by removal of the fault condition, the switch is allowed to turn on again. The LTC4222 will set FAULT bit 2 and turn off in the event of an overcurrent fault, preventing it from remaining in an overcurrent condition. If configured to auto-retry, the LTC4222 will continually attempt to restart after cool-down cycles until it succeeds in starting up without generating an overcurrent fault. Note that if a switch is on after an auto-retry and the FAULT bit has not been reset, clearing the corresponding auto-retry bit will turn the channel off. Data Converter The LTC4222 incorporates a 10-bit A/D converter that continuously scans six different voltages. The SOURCE pins have a 1/24 resistive divider to monitor a full scale voltage of 32V with 31.25mV resolution. The ADIN pins are monitored with a 1.28V full scale and 1.25mV resolution, and the voltage between the VDD and SENSE pins is monitored with a 64mV full scale and 62.5μV resolution. Results from each conversion are stored, left justified, in registers as seen in Tables 7 and 8, and are updated 15 times per second. Setting ADC_CONTROL register bit 0 invokes a test mode that halts the data converter so that the data converter result registers may be written to and read from for software testing. The data converter also has a direct address mode that allows the user to take a specific measurement at a specific time and hold that value for later readback. Direct address mode is entered by setting the Halt bit, bit 0, in the ADC_CONTROL register (see Table 9). Then when the channel address bits, ADC_CONTROL bits 1 to 3, are written to, the ADC will make a single measurement on the channel indicated by those bits, then stop. Setting the ADC Alert bit, ADC_CONTROL bit 4, will enable an interrupt when the data converter finishes the conversion, resulting in the ALERT pin pulling low when the data is ready. Alternately, the ADC Busy bit, ADC_CONTROL bit 5, can be polled to check for the end of the conversion, after a direct address conversion the ADC Busy bit will go low. In normal mode ADC Busy is always high. Resetting the Halt bit returns the data converter to the scan mode. 4222f 18 LTC4222 APPLICATIONS INFORMATION Configuring the GPIO Pins Table 3 describes the possible states of the GPIO pins using the CONTROL registers bits 6 and 7. At power-up, the default state is for a GPIO pin to go high impedance when power is good (FB pin greater than 1.235V). Other applications for a GPIO pin are to pull down when power is good, a general purpose output and a general purpose input. A simple application of the GPIO pin in the power good configuration is to connect it to the UV pin of the other channel with the CONFIG pin high. This will result in the second channel being turned on after the first channel has started up and signaled power-good. Current Limit Stability For many applications the LTC4222 current limit will be stable without additional components. However there are certain conditions where additional components may be needed to improve stability. The dominant pole of the current limit circuit is set by the capacitance and resistance at the gate of the external MOSFET, and larger gate capacitance makes the current limit loop more stable. Usually a total of 8nF gate to source capacitance is sufficient for stability and is typically provided by inherent MOSFET CGS, however the stability of the loop is degraded by increasing RSENSE or by reducing the size of the resistor on a gate RC network if one is used, which may require additional gate to source capacitance. Board level short-circuit testing is highly recommended as board layout can also affect transient performance, for stability testing the worst case condition for current limit stability occurs when the output is shorted to ground after a normal startup. There are two possible parasitic oscillations when the MOSFET operates as a source follower when ramping at power-up or during current limiting. The first type of oscillation occurs at high frequencies, typically above 1MHz. This high frequency oscillation is easily damped with R5 as shown in Figure 1. In some applications, one may find that R5 helps in short-circuit transient recovery as well. However, too large of an R5 value will slow down the turn-off time. The recommended R5 range is between 5Ω and 500Ω. The second type of source follower oscillation occurs at frequencies between 200kHz and 800kHz due to the load capacitance being between 0.2μF and 9μF the presence , of R5 resistance, the absence of a drain bypass capacitor, a combination of bus wiring inductance and bus supply output impedance. To prevent this second type of oscillation avoid load capacitance below 10μF alternately connect an , external capacitor from the MOSFET gate to ground with a value greater than 1.5nF . Supply Transients The LTC4222 is designed to ride through supply transients caused by load steps. If there is a shorted load and the parasitic inductance back to the supply is greater than 0.5μH, there is a chance that the supply collapses before the active current limit circuit brings down the GATE pin. If this occurs, the undervoltage monitors pull the corresponding GATE pin low. The undervoltage lockout circuit has a 2μs filter time after VDD drops below 2.35V. The UV pin reacts in 2μs to shut the GATE off, but it is recommended to add a filter capacitor CF to prevent unwanted shutdown caused by a transient. Eventually either the UV pin or undervoltage lockout responds to bring the current under control before the supply completely collapses. Supply Transient Protection The LTC4222 is safe from damage with supply voltages up to 35V. However, spikes above 35V may damage the part. During a short-circuit condition, large changes in current flowing through power supply traces may cause inductive voltage spikes which exceed 35V. To minimize such spikes, the power trace inductance should be minimized by using wider traces or heavier trace plating. Also, a snubber circuit dampens inductive voltage spikes. Build a snubber by using a 100Ω resistor in series with a 0.1μF capacitor between VDD and GND. A surge suppressor, Z1 in Figure 1, at the input can also prevent damage from voltage surges. Design Example As a design example, take the following specifications for channel 1: VIN = 12V, IMAX = 5A, IINRUSH = 1A, dI/dtINRUSH , = 10A/ms, CL = 330μF VUV(RISING) = 10.75V, VOV(FALLING) = 14.0V, VPWRGD(UP) = 11.6V, and I2C ADDRESS = 1000111. This completed design is shown in Figure 1. 4222f 19 LTC4222 APPLICATIONS INFORMATION Selection of the sense resistor, RS, is set by the overcurrent threshold of 50mV: RS = 50mV = 0.01Ω IMAX The inrush dI/dt is set to 10A/ms using CSS: CSS = ISS 1 • 0.0429 • RSENSE ⎛ A⎞ dl/dt ⎜ ⎟ ⎝ s⎠ 10μA • 0.0429 • 1 = = 4.3nF choose 4.7nF 10000 • 0.01Ω The MOSFET is sized to handle the power dissipation during inrush when output capacitor COUT is being charged. A method to determine power dissipation during inrush is based on the principle that: Energy in CL = Energy in Q1 This uses: Energy in CL = 1 1 CV 2 = (0.33mF)(12)2 2 2 For a start-up time of 4ms with a 2x safety margin we choose: 2 • t STARTUP + CSS • 2 12.3ms/μF 8ms + 4.7nF • 2 = 0.68μF CTIMER = 12.3ms/μF CTIMER = Note the minimum value of CTIMER is 10nF . The UV and OV resistor string values can be solved in the following method. First pick R3 based on ISTRING being 1.235V/R3 at the edge of the OV rising threshold. Then solve the following equations: R2 = VOV(OFF ) VUV(ON) • R3 • UVTH(RISING) OVTH(FALLING) – R3 – R2 – R3 or 0.024 joules. Calculate the time it takes to charge up COUT: C •V I 0.33mF • 12V t STARTUP = L DD INRUSH = = 4ms IINRUSH 1A The power dissipated in the MOSFET: PDISS = Energy in CL = 6W t STARTUP The SOA (safe operating area) curves of candidate MOSFETs must be evaluated to ensure that the heat capacity of the package tolerates 6W for 4ms. The SOA curves of the Fairchild FDC653N provide for 2A at 12V (24W) for 10ms, satisfying this requirement. Since the FDC653N has less than 8nF of gate capacitance and we are using a GATE RC network, the short circuit stability of the current limit should be checked and improved by adding a capacitor from GATE to SOURCE if needed. The inrush current is set to 1A using C1: C •I C1= L GATE IINRUSH 0.33mF • 12μA C1= or C1= 3.9nF 1A R1= VUV(ON) •(R3 + R2) UVTH(RISING) In our case we choose R3 to be 3.4k to give a resistor string current below 100μA. Then solving the equations results in R2 = 1.16 kΩ and R1 = 34.6kΩ. The FB divider is solved by picking R8 and solving for R7, choosing 3.57k for R8 we get: R7 = VPWRGD(UP) • R8 FBTH(RISING) – R8 Resulting in R7 = 30k A 0.1μF capacitor, CF, is placed on the UV pins to prevent supply glitches from turning off the GATE via UV or OV. 4222f 20 LTC4222 APPLICATIONS INFORMATION The address is set with the help of Table 1, which indicates binary address 1000111 corresponds to address 4. Address 4 is set by setting ADR2 low, ADR1 open and ADR0 high. Next the value of R5 and R6 are chosen to be the default values 10Ω and 15kΩ as discussed previously. In addition a 0.1μF ceramic bypass capacitor is placed on the INTVCC pin. Layout Considerations To achieve accurate current sensing, a Kelvin connection is required. The minimum trace width for 1oz copper foil is 0.02" per amp to make sure the trace stays at a reasonable temperature. Using 0.03" per amp or wider is recommended. Note that 1oz copper exhibits a sheet resistance of about 530μΩ. Small resistances add up quickly in high current applications. To improve noise immunity, put the resistive dividers to the UV, OV and FB pins close to the device and keep traces to VDD and GND short. It is also important to put the bypass capacitor for the INTVCC pin, C3, as close as possible between INTVCC and GND. 0.1μF capacitors from the UV pins (and OV pins through resistor R2) to GND also helps reject supply noise. Figure 5 shows a layout that addresses these issues. Note that surge suppressor, Z1 is placed between supply and ground using wide traces. SENSE RESISTOR RS ILOAD Digital Interface The LTC4222 communicates with a bus master using a 2-wire interface compatible with I2C Bus and SMBus, an I2C extension for low power devices. The LTC4222 is a read-write slave device and supports SMBus bus Read Byte, Write Byte, Read Word and Write Word commands. A complete list of the resistors of the LTC4222 is shown in Table 2. The second word in a Read Word command is the contents of the subsequent 8 bit register. The second word in a Write Word command is ignored. Data formats for these commands are shown in Figures 6 to 11. The LTC4222 interface also features a 25ms timeout feature to prevent the bus being stuck low if a communication error occurs. If either the SCL or SDA lines remain low for more than 25ms the LTC4222 will reset it’s interface and release the SDAO pin, freeing the bus to resume communication. The LTC4222 also features PMBus compatibility, the interface will not acknowledge unsupported commands and the internal addresses are in the manufacturer specified address space under the PMBus specification. START and STOP Conditions When the bus is idle, both SCL and SDA are high. A bus master signals the beginning of a transmission with a start condition by transitioning SDA from high to low while SCL is high, as shown in Figure 6. When the master has finished communicating with the slave, it issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. I2C Device Addressing Twenty seven distinct bus addresses are available using three 3-state address pins, ADR0, ADR1 and ADR2. Table 1 shows the correspondence between pin states and addresses. In addition, the LTC4222 responds to two special addresses. Address (1100 0110) is a mass write address that writes to all LTC4222s, regardless of their individual address settings. Mass write can be disabled by setting register bit 4 in the CONTROL register of channel 2 to zero. Address (0001 100) is the SMBus Alert Response Address. If the LTC4222 is pulling low on the ALERT pin due to an 4222f R1 Z1 CF VIAS TO GROUND PLANE CSS R3 OV UV VDD SENSE+ SENSE– R2 SS CONFIG C3 INTVCC GND VIA TO GROUND PLANE LTC4222UHD 4222 F05 Figure 5. Recommended Layout 21 LTC4222 APPLICATIONS INFORMATION SDA a6 - a0 b7 - b0 b7 - b0 SCL S 1-7 8 9 1-7 8 9 1-7 8 9 P START CONDITION ADDRESS R/W ACK DATA ACK DATA ACK STOP CONDITION 4222 F06 Figure 6. Data Transfer Over I2C or SMBus alert, it acknowledges this address by broadcasting its address and releasing the ALERT pin. Acknowledge The acknowledge signal is used in handshaking between transmitter and receiver to indicate that the last byte of data was received. The transmitter always releases the SDA line during the acknowledge clock pulse. When the slave is the receiver, it pulls down the SDA line so that it remains LOW during this pulse to acknowledge receipt of the data. If the slave fails to acknowledge by leaving SDA high, then the master may abort the transmission by generating a STOP condition. When the master is receiving data from the slave, the master pulls down the SDA line during the clock pulse to indicate receipt of the data. After the last byte has been received the master leaves the SDA line HIGH (not acknowledge) and issues a stop condition to terminate the transmission. Write Protocol The master begins communication with a START condition followed by the seven bit slave address and the R/W bit set to zero, as shown in Figure 7. The addressed LTC4222 acknowledges this and then the master sends a command byte which indicates which internal register the master wishes to write. The LTC4222 acknowledges this and then latches the lower three bits of the command byte into its internal Register Address pointer. The master then delivers the data byte and the LTC4222 acknowledges once more and latches the data into its control register. The transmission is ended when the master sends a STOP condition. If the master continues sending a second data byte, as in a Write Word command, the second data byte is acknowledged by the LTC4222 but ignored, as shown in Figure 8. Read Protocol The master begins a read operation with a START condition followed by the seven bit slave address and the R/W bit set to zero, as shown in Figure 9. The addressed LTC4222 acknowledges this and then the master sends a command byte which indicates which internal register the master wishes to read. The LTC4222 acknowledges this and then latches the lower three bits of the command byte into its internal Register Address pointer. The master then sends a repeated START condition followed by the S ADDRESS W A a7:a0 00 COMMAND b7:b0 A DATA A 0 b7:b0 0 DATA XXXXXXXX AP 0 4222 F08 S ADDRESS W A a7:a0 00 COMMAND b7:b0 A DATA A P 0 b7:b0 0 FROM MASTER TO SLAVE FROM SLAVE TO MASTER A: ACKNOWLEDGE (LOW) A: NOT ACKNOWLEDGE (HIGH) R: READ BIT (HIGH) W: WRITE BIT (LOW) S: START CONDITION P: STOP CONDITION 4222 F07 Figure 8. LTC4222 Serial Bus SDA Write Word Protocol S ADDRESS W A a7:a0 00 COMMAND b7:b0 AS 0 ADDRESS a7:a0 R A DATA A P 1 0 b7:b0 1 4222 F09 Figure 7. LTC4222 Serial Bus SDA Write Byte Protocol Figure 9. LTC4222 Serial Bus SDA Read Byte Protocol 4222f 22 LTC4222 APPLICATIONS INFORMATION same seven bit address with the R/W bit now set to one. The LTC4222 acknowledges and send the contents of the requested register. The transmission is ended when the master sends a STOP condition. If the master acknowledges the transmitted data byte, as in a Read Word command, Figure 10, the LTC4222 repeats the requested register as the second data byte. Alert Response Protocol When any of the fault bits in the FAULT register are set, an optional bus alert is generated if the appropriate bit in the ALERT register is also set. If an alert is enabled, the corresponding fault causes the ALERT pin to pull low. After the bus master controller broadcasts the Alert Response Address, the LTC4222 responds with its address on the SDA line and then release ALERT as shown in Figure 11. The ALERT line is also released if the device is addressed by the bus master. The ALERT signal is not pulled low again until the FAULT register indicates a different fault has occurred or the original fault is cleared and it occurs again. Note that this means repeated or continuing faults do not generate alerts until the associated FAULT register bit has been cleared. ADDRESS a7:a0 R A DATA A DATA A P 1 0 b7:b0 0 b7:b0 1 4222 F10 S ADDRESS W A a7:a0 00 COMMAND b7:b0 AS 0 Figure 10. LTC4222 Serial Bus SDA Read Word Protocol ALERT S RESPONSE R A ADDRESS 0001100 1 0 DEVICE ADDRESS a7:a0 AP 1 4222 F11 Figure 11. LTC4222 Serial Bus SDA Alert Response Protocol 4222f 23 LTC4222 APPLICATIONS INFORMATION Table 1. LTC4222 I2C Device Addressing DESCRIPTION Mass Write Alert Response 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 DEVICE ADDRESS h C6 19 88 8A 8C 8E 98 9A 9C 9E A8 AA AC AE B8 BA BC BE C8 CA CC CE D8 DA DC DE E8 EA EC 7 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 5 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 DEVICE ADDRESS 4 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 3 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X L L L L L L L L NC NC NC NC NC NC NC NC H H H H H H H H L NC H LTC4222 ADDRESS PINS ADR2 ADR1 X X NC H NC NC L H L L NC H NC NC L H L L NC H NC NC L H L L H H H ADR0 X X L NC NC H L H NC H L NC NC H L H NC H L NC NC H L H NC H L L L 4222f 24 LTC4222 APPLICATIONS INFORMATION Table 2. LTC4222 Register Addresses and Contents REGISTER ADDRESS Decimal 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 Hex D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h REGISTER NAME Control1 (A1) Alert1 (B1) Status1 (C1) Fault1 (D1) Control2 (A2) Alert2 (B2) Status2 (C2) Fault2 (D2) SOURCE1 MSB SOURCE1 LSB SOURCE2 MSB SOURCE2 LSB ADIN1 MSB ADIN1 LSB ADIN2 MSB ADIN2 LSB SENSE1 MSB SENSE1 LSB SENSE2 MSB SENSE2 LSB ADC CONTROL DESCRIPTION Sets Behavior for Channel 1 Selects Which Channel 1 Faults Generate Alerts Displays the Status of Channel 1 Fault Log for Channel 1 Sets Behavior for Channel 2 Selects which Channel 2 Faults Generate Alerts Displays the Status of Channel 2 Fault Log for Channel 2 ADC SOURCE1 MSB data ADC SOURCE1 LSB data ADC SOURCE2 MSB data ADC SOURCE2 LSB data ADC ADIN1 MSB ADC ADIN1 LSB ADC ADIN2 MSB ADC ADIN2 LSB ADC SENSE1 MSB ADC SENSE1 LSB ADC SENSE2 MSB ADC SENSE2 LSB Configures Behavior of the ADC + Set bit ADC_CONTROL(0) before writing 4222f 25 LTC4222 APPLICATIONS INFORMATION Table 3. CONTROL Registers A – Read/Write BIT 7:6 CONTROL 1 (D0h) GPIO1 Configure CONTROL 2 (D4h) GPIO2 Configure OPERATION FUNCTION Power Good (Default) Power⎯Good General Purpose Output General Purpose Input 5 4 3 GPIO1 Output Reserved Channel 1 FET On Control GPIO2 Output Mass Write Enable Channel 2 FET On Control A6 0 0 1 1 A7 0 1 0 1 GPIO PIN GPIO = C3 GPIO = C3 GPIO = A5 C6 = GPIO Output Data for GPIO Pins When Configured as General Purpose Output 1 = High Impedance, 0 = Pulled Low Allows Mass Write Addressing 1 = Mass Write Enabled (Default), 0 = Mass Write Disabled On Control Bit, Latches the State of the On Pin at the End of the Debounce Delay 1 = FET On, 0 = FET Off Overcurrent Auto-Retry Bit 1 = Auto-Retry After Overcurrent, 0 = Latch Off After Overcurrent (Default) 2 Channel 1 Overcurrent Auto-Retry Channel 2 Overcurrent Auto-Retry 1 Channel 1 Undervoltage Auto-Retry Channel 2 Undervoltage Auto-Retry Undervoltage Auto-retry 1 = Auto-Retry After Undervoltage (Default), 0 = Latch Off After Undervoltage 0 Channel 1 Overvoltage Auto-Retry Channel 2 Overvoltage Auto-Retry Overvoltage Auto-retry 1 = Auto-Retry After Overvoltage (Default), 0 = Latch Off After Overvoltage Table 4. ALERT Registers B – Read/Write BIT 7 6 5 4 3 2 1 0 ALERT 1 (D1h) Reserved Reserved Channel 1 FET Short Alert EN1 State Change Alert Channel 1 Power Bad Alert Channel 1 Overcurrent Alert Channel 1 Undervoltage Alert Channel 1 Overvoltage Alert ALERT 2 (D5h) Reserved Reserved Channel 2 FET Short Alert EN2 State Change Alert Channel 2 Power Bad Alert Channel 2 Overcurrent Alert Channel 2 Undervoltage Alert Channel 2 Overvoltage Alert OPERATION Not Used Not Used Enables Alert for FET Short Condition 1 = Enable Alert, 0 = Disable Alert (Default) Enables Alert When EN Changes State 1 = Enable Alert, 0 = Disable Alert (Default) Enables Alert When Output Power is Bad 1 = Enable Alert, 0 = Disable Alert (Default) Enables Alert for Overcurrent Condition 1 = Enable Alert, 0 = Disable Alert (Default) Enables Alert for Undervoltage Condition 1 = Enable Alert, 0 = Disable Alert (Default) Enables Alert for Overvoltage Condition 1 = Enable Alert, 0 = Disable Alert (Default) 4222f 26 LTC4222 APPLICATIONS INFORMATION Table 5. STATUS Registers C – Read BIT 7 6 5 4 3 2 1 0 STATUS 1 (D2h) FET On GPIO1 Input Channel 1 FET Short Status EN1 Status Channel 1 Power Bad Channel 1 Overcurrent Channel 1 Undervoltage Channel 1 Overvoltage STATUS 2 (D6h) FET On GPIO2 Input Channel 2 FET Short Status EN2 Status Channel 2 Power Bad Channel 2 Overcurrent Channel 2 Undervoltage Channel 2 Overvoltage OPERATION 1 = FET On, 0 = FET Off Reports the State of the GPIO1 Pin 1 = GPIO1 High, 0 = GPIO1 Low Reports the State of the GPIO2 Pin 1 = GPIO2 High, 0 = GPIO2 Low Indicates If the Channel is Enabled When EN is Low 1 = EN pin Low, 0 = EN pin High Indicates Power is Bad When FB is Low 1 = FB Low, 0 = FB High Indicates Overcurrent Condition; 1 = Overcurrent, 0 = Not Overcurrent Indicates Input Undervoltage When UV is Low 1 = UV Low, 0 = UV High Indicates Input Overvoltage When OV is High 1 = OV High, 0 = OV Low Table 6. FAULT Registers D – Read/Write BIT 7 6 5 FAULT 1 (D3h) Reserved Reserved Channel 1 FET Short Fault Occurred Channel 1 EN Changed State FAULT 2 (D7h) Reserved Reserved Channel 2 FET Short Fault Occurred Channel 2 EN Changed State OPERATION Reserved Reserved Indicates Potential FET Short was Detected When Measured Current Sense Voltage Exceeded 1mV While FET was Off 1 = FET was Shorted, 0 = FET is Good 4 Indicates That the LTC4215-1 was Enabled or Disabled When EN Changed State 1 = EN Changed State, 0 = EN Unchanged 3 2 1 0 Channel 1 Power Bad Fault Occurred Channel 1 Overcurrent Fault Occurred Channel 1 Undervoltage Fault Occurred Channel 1 Overvoltage Fault Occurred Channel 2 Power Bad Fault Occurred Channel 2 Overcurrent Fault Occurred Channel 2 Undervoltage Fault Occurred Channel 2 Overvoltage Fault Occurred Indicates Power was Bad When FB Went Low 1 = FB was Low, 0 = FB was High Indicates Overcurrent Fault Occurred 1 = Overcurrent Fault Occurred, 0 = No Overcurrent Faults Indicates Input Undervoltage Fault Occurred When UV Went Low 1 = UV was Low, 0 = UV was High Indicates Input Overvoltage Fault Occurred When OV Went High 1 = OV was High, 0 = OV was Low 4222f 27 LTC4222 APPLICATIONS INFORMATION Table 7. ADC Register Data Format: ADINn, SOURCEn, SENSEn MSB Bytes – Read/Write* BIT (7) Data (9) BIT (6) Data (8) BIT (5) Data (7) BIT (4) Data (6) BIT (3) Data (5) BIT (2) Data (4) BIT (1) Data (3) BIT (0) Data (2) *Set bit ADC_CONTROL(0) before writing Table 8. ADC Register Data Format: ADINn, SOURCEn, SENSEn LSB Bytes – Read/Write* BIT (7) Data (1) **Read as zero BIT (6) Data (0) BIT (5) Reserved** BIT (4) Reserved** BIT (3) Reserved** BIT (2) Reserved** BIT (1) Reserved** BIT (0) Reserved** *Set bit ADC_CONTROL(0) before writing Table 9. ADC CONTROL Register E – Read/Write BIT 7 6 5 4 3 2 1 ADC_CONTROL (E4h) Reserved Reserved ADC Busy ADC Alert ADC Channel Address OPERATION Reserved Reserved Status Bit That is High When the ADC is Converting. Always High in Free-Run Mode, Low When ADC is Halted or After a Point and Shoot Conversion. Read Only Enables the ALERT Pin to Pull Low When the ADC Finishes a Measurement These Bits May Be Written to Cause the ADC to Make a Single Measurement of the Desired Channel When the Halt Bit is High FUNCTION SOURCE1 SOURCE2 ADIN1 ADIN2 SENSE1 SENSE2 0 Halt SF2-0 000 001 010 011 100 101 Stops the Data Converter and Enables Point and Shoot Mode 4222f 28 LTC4222 TYPICAL APPLICATIONS VIN1 12V R10 3.3k 5V 2 RS1 0.01Ω INTVCC 5V 8 R9 10k 6 CF1 0.1μF Z1 SA14A R1-1 34k Q1 FDD3706 R7-1 10.2k R8-1 3.57k R5-1 10Ω R6-1 15k C1-1 22nF UV1 VDD1 OV1 SDA1 SDA0 SCL ALERT CONFIG ADR0 ADR1 ADR2 INTVCC GND R3-2 3.4k R2-2 1.02k HCPL-0300 3 GND VIN2 3.3V BACKPLANE PLUG-IN CARD 5 CF2 0.1μF R1-2 6.55k Z2 SA14A R5-2 10Ω C1-2 22nF OV2 UV2 VDD2 SENSE2– GATE2 R6-2 15k SENSE1– GATE1 SOURCE1 FB1 GPIO1 EN1 ADIN1 TIMER ON2 LTC4222 ON1 SS ADIN2 EN2 GPIO2 FB2 SOURCE2 CSS 68nF INTVCC R2-1 1.02k R3-1 3.4k R4-1 100k HCPL-0300 3 SDA INTVCC 6 8 2 BAT 254 HCPL-0300 5 R10 3.3k SCL 2 INTVCC 5V 8 3 R12 10k 6 C3 0.1μF 5 NC R8-2 3.57k R7-2 4.99k RS2 0.01Ω Q2 FDD3706 4222 TA03 Figure 12. 3.3V and 12V Application with Sequenced Turn-On Optically Isolated I2C Communication and 5A Current Limits. Schottky Diode Allows 3.3V Switch to Turn On When 12V is Absent 4222f 29 LTC4222 PACKAGE DESCRIPTION UH Package 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693) 0.75 ± 0.05 0.00 – 0.05 5.00 ± 0.10 (4 SIDES) 0.70 ± 0.05 PIN 1 TOP MARK (NOTE 6) R = 0.05 TYP R = 0.115 TYP BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER 31 32 0.40 ± 0.10 1 2 3.45 ± 0.05 3.50 REF (4-SIDES) 3.45 ± 0.10 5.50 ± 0.05 4.10 ± 0.05 3.50 REF (4 SIDES) 3.45 ± 0.05 3.45 ± 0.10 0.25 ± 0.05 0.50 BSC PACKAGE OUTLINE 0.200 REF NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 ± 0.05 0.50 BSC (UH32) QFN 0406 REV D RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4222f 30 LTC4222 PACKAGE DESCRIPTION G Package 36-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 12.50 – 13.10* (.492 – .516) 1.25 ± 0.12 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 7.8 – 8.2 5.3 – 5.7 7.40 – 8.20 (.291 – .323) 0.42 ± 0.03 RECOMMENDED SOLDER PAD LAYOUT 5.00 – 5.60** (.197 – .221) 0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2.0 (.079) MAX 0° – 8° 0.09 – 0.25 (.0035 – .010) 0.55 – 0.95 (.022 – .037) 0.65 (.0256) BSC NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE 0.22 – 0.38 (.009 – .015) TYP 0.05 (.002) MIN G36 SSOP 0204 4222f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC4222 TYPICAL APPLICATION 6mΩ 12V 93.1k 0.1μF 2k 10.2k UV1 VDD1 OV1 ON SDA SCL ALERT CONFIG ADR0 ADR1 ADR2 INTVCC GND 10.2k OV2 UV2 VDD2 2k 10Ω 0.1μF 12V 6mΩ Si7336ADP BACKPLANE 4222 TA02a Si7336ADP 93.1k 10Ω 12.1k 100k μTCA PLUG-IN CARD 1 12V SENSE1– GATE1 SOURCE1 FB1 GPIO1 EN1 ADIN1 TIMER LTC4222 SS ADIN2 EN2 GPIO2 FB2 SENSE2– GATE2 SOURCE2 12.1k 100k 68nF PWR GOOD 1 LOAD 1 1μF NC 0.1μF PWR GOOD 2 μTCA PLUG-IN CARD 2 LOAD 2 93.1k 93.1k 12V Figure 13. μTCA Application Supplying 12V Payload Power to Two μTCA Slots RELATED PARTS PART NUMBER LTC1642A LTC1645 DESCRIPTION Single Channel, Hot Swap Controller Dual Channel, Hot Swap Controller COMMENTS Operates from 3V to 16.5V, Overvoltage Protection up to 33V, SSOP-16 Operates from 3V to 12V, Power Sequencing, SO-8 or SO-14 Operates from 2.7V to 16.5V, SO-8 or SSOP-16 Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6 Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8 or MSOP-10 Operates from 2.5V to 16.5V, Power-Up Timeout, MSOP-10 Operates from –6V to –16V, MSOP-10 Operates from 29V to 15V, 8-Bit ADC Monitors Current and Voltage Operates from 0V to 6V, MSOP-10 or 12-Lead (4mm × 3mm) DFN Operates from 2.9V to 26.5V, Integrated MOSFET, TSSOP-20 or DFN-16 Operates from 2.9V to 26.5V, 5% Accurate Current Limit, SSOP-16 or DFN-16 Operates from ±2.7V to ±16.5V, SSOP-16 Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16 Operates from 1V to 6V, Compact, MSOP-10 or (3mm × 2mm) DFN-10 LTC1647-1/LTC1647-2/ Dual Channel, Hot Swap Controller LTC1647-3 LTC4210 LTC4211 LTC4212 LTC4214 LTC4215 LTC4216 LTC4217 LTC4218 LT4220 LTC4221 LTC4224 Single Channel, Hot Swap Controller Single Channel, Hot Swap Controller Single Channel, Hot Swap Controller Negative Voltage, Hot Swap Controller Single Channel, Hot Swap Controller with I2C Monitoring Single Channel, Hot Swap Controller Single Channel, Hot Swap Controller Single Channel, Hot Swap Controller Positive and Negative Voltage, Dual Channel, Hot Swap Controller Dual Hot Swap Controller/Sequencer Dual Channel, Hot Swap Controller 4222f 32 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 1008 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008