LTC4258

LTC4258 Quad IEEE 802.3af Power over Ethernet Controller with Integrated Detection FEATURES ■ ■ DESCRIPTIO ■ ■ ■ ■ ■ Controls Four Independent – 48V Powered Ethernet Ports Each Port Includes: – IEEE 802®.3af Compliant PD Detection and Classification – Output Current Limit with Foldback – Short-Circuit Protection with Fast Gate Pull-Down – PD Disconnect Using DC Sensing – Power Good Indication Operates Autonomously or by I2CTM Control 4-Bit Programmable Digital Address Allows Control of Up to 64 Ports Programmable INT Pin Eliminates Software Polling Current and Duty Cycle Limits Protect External FETs Available in a 36-Pin SSOP Package The LTC®4258 is a quad –48V Hot SwapTM controller designed for use in IEEE 802.3af compliant Power Sourcing Equipment (PSE). It consists of four independent ports, each with output current limit, short-circuit protection, complete Powered Device (PD) detection and classification capability, and programmable PD disconnect using DC sensing. Used with power MOSFETs and passives as in Figure 1, the LTC4258 can implement a complete IEEE 802.3af-compliant PSE. The LTC4258 can operate autonomously or be controlled by an I2C serial interface. Up to 16 LTC4258s may coexist on the same data bus, allowing up to 64 powered Ethernet ports to be controlled with only two digital lines. Fault conditions are optionally signaled with the INT pin to eliminate software polling. External power MOSFETs, current sense resistors and diodes allow easy scaling of current and power dissipation levels and provide protection against voltage and current spikes and ESD events. The LTC4258 is available in a 36-pin SSOP package. Linear Technology also provides solutions for 802.3af PD applications with the LTC4257, LTC4257-1, and LTC4267. APPLICATIO S ■ ■ ■ IEEE 802.3af Compliant Endpoint and Midspan Power Sources IP Phone Systems DTE Power Distribution , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Hot Swap is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATIO INT SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 3.3V 0.1µF 0.1µF 100V X7R SHDN1 SHDN2 SHDN3 SHDN4 VDD AUTO BYP RESET DETECT1 DETECT2 DETECT3 DETECT4 LTC4258 CMPD3003 ×4 DGND AGND VEE SENSE1 GATE1 OUT1 SENSE2 GATE2 OUT2 SENSE3 GATE3 OUT3 SENSE4 GATE4 OUT4 RS1 –48V 0.1µF Q1 10k RS2 PORT2 Q2 RS3 PORT3 Q3 RS1 TO RS4: 0.5Ω Q1 TO Q4: IRFM120A RS4 Q4 PORT4 4258 F01 10k 10k 10k PORT1 Figure 1. Complete 4-Port Powered Ethernet Power Source 4258fb U 0.1µF 100V ×4 SMAJ58A ×4 U U 1 LTC4258 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW RESET BYP INT SCL SDAOUT SDAIN AD3 AD2 AD1 Supply Voltages VDD to DGND .......................................... – 0.3V to 5V VEE to AGND ......................................... 0.3V to – 70V DGND to AGND (Note 2) ................................. ±0.3V Digital Pins SCL, SDAIN, SDAOUT, INT, AUTO, RESET SHDNn, ADn ................. DGND – 0.3V to DGND + 5V Analog Pins GATEn (Note 3) ................... VEE – 0.3V to VEE + 12V DETECTn .................... DGND – 21V to DGND + 0.3V SENSEn ................................. VEE – 0.3V to VEE + 1V OUTn .................................... VEE – 70V to VEE + 70V BYP Current ................................................. ±0.1mA Operating Ambient Temperature Range ...... 0°C to 70°C Junction Temperature (Note 4) ............................ 150°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C 1 2 3 4 5 6 7 8 9 36 NC 35 AUTO 34 OUT1 33 GATE1 32 SENSE1 31 OUT2 30 GATE2 29 SENSE2 28 VEE 27 OUT3 26 GATE3 25 SENSE3 24 OUT4 23 GATE4 22 SENSE4 21 AGND 20 SHDN4 19 SHDN3 ORDER PART NUMBER LTC4258CGW AD0 10 DETECT1 11 DETECT2 12 DETECT3 13 DETECT4 14 DGND 15 VDD 16 SHDN1 17 SHDN2 18 GW PACKAGE 36-LEAD PLASTIC SSOP TJMAX = 150°C, θJA = 80°C/W Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND = DGND = 0V, VDD = 3.3V, VEE = – 48V unless otherwise noted (Note 5). SYMBOL PARAMETER Power Supplies VDD VDD Supply Voltage VEE VEE Supply Voltage IDD VDD Supply Current IEE VEE Supply Current VDDMIN VEEMINON VEEMINOFF Detection IDET VDD UVLO Voltage VEE UVLO Voltage (Turning On) VEE UVLO Voltage (Turning Off) Detection Current CONDITIONS ● ELECTRICAL CHARACTERISTICS MIN 3 –47 TYP 3.3 2.5 –2 2.7 –31 –28 MAX 4 –57 5 –5 100 UNITS V V mA mA mA V V V µA µA V kΩ kΩ V mA 4258fb To Maintain IEEE Compliant Output (Note 6) Normal Operation Classification Into a Short (VDETECTn = 0V) (Note 8) VEE – AGND VEE – AGND First Point, VDETECTn = – 10V Second Point, VDETECTn = – 3.5V Open Circuit, Measured at DETECTn Pin ● ● ● ● ● ● ● ● ● 235 145 15.2 26.7 –16.4 55 –20 17 29 VDET Detection Voltage Compliance RDETMIN Minimum Valid Signature Resistance RDETMAX Maximum Valid Signature Resistance Classification VCLASS Classification Voltage ICLASS Classification Current Compliance 300 190 –23 19 33 –21 75 0mA < ICLASS < 31mA Into Short (VDETECT = 0V) ● ● 2 U W U U WW W LTC4258 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND = DGND = 0V, VDD = 3.3V, VEE = – 48V unless otherwise noted (Note 5). SYMBOL ITCLASS PARAMETER Classification Threshold Current CONDITIONS Class 0-1 Class 1-2 Class 2-3 Class 3-4 Class 4-Overcurrent Gate On, VGATEn = VEE Gate Off, VGATEn = VEE + 5V VGATEn = VEE + 2V IGATEn = – 1µA (Note 3) VOUTn – VEE 0V > VOUTn > –10V –10V > VOUTn > –30V VOUTn = –48V VSENSEn – VEE, VOUT = VEE (Note 7) VSENSEn – VEE, VOUTn = VEE VSENSEn – VEE, VOUTn = AGND – 30V VSENSEn – VEE, VOUTn = AGND – 10V VSENSEn – VEE VSENSEn = VEE ISDAOUT = 3mA, IINT = 3mA ISDAOUT = 5mA, IINT = 5mA SCL, SDAIN, RESET, SHDNn, AUTO, ADn SCL, SDAIN, RESET, SHDNn, AUTO, ADn ADn, RESET, SHDNn AUTO From Detect Command or Application of PD to Port to Detect Complete (Figure 2) Time to Measure PD Signature Resistance (Figure 2) From Successful Detect in Auto or Semiauto Mode to Class Complete From Classify Command in Manual Mode (Figure 2) (Figure 2) From Valid Detect to Port On in Auto Mode (Figure 2) From Port On Command to GATE Pin Current = IGON (Note 9) ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ELECTRICAL CHARACTERISTICS MIN 5.5 13 21 31 45 –20 30 10 1 TYP 6.5 14.5 23 33 48 –50 50 13 2 MAX 7.5 16 25 35 51 –70 300 15 3 –6 –18 UNITS mA mA mA mA mA µA µA mA V V µA µA µA mV mV mV mV mV mV µA V V V V kΩ kΩ Gate Driver IGON GATE Pin Current IGOFF GATE Pin Current IGPD GATE Pin Short-Circuit Pull-Down ∆VGATE External Gate Voltage (VGATEn – VEE) Output Voltage Sense VPG Power Good Threshold Voltage IVOUT Out Pin Bias Current –20 166 201 201 30.2 2.52 187.5 212.5 199 224 224 4.97 Current Sense VCUT Overcurrent Detection Sense Voltage VLIM Current Limit Sense Voltage VMIN DC Disconnect Sense Voltage VSC Short-Circuit Sense Voltage ISENSE SENSE Pin Bias Current Digital Interface VOLD Digital Output Low Voltage VILD VIHD RPU Digital Input Low Voltage Digital Input High Voltage Pull-Up Resistor to VDD 3.75 275 –50 0.4 0.7 0.8 2.4 50 50 170 170 10.1 10.1 10.1 590 230 52 420 13 130 1 RPD Pull-Down Resistor to DGND AC Characteristics tDETDLY Detection Delay tDET tCLSDLY Detection Duration Classification Delay ms ms ms ms ms ms ms tCLASS tPON Classification Duration Power On Delay, Auto Mode 4258fb 3 LTC4258 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND = DGND = 0V, VDD = 3.3V, VEE = – 48V unless otherwise noted (Note 5). SYMBOL tSTART PARAMETER Maximum Current Limit Duration During Port Start-Up CONDITIONS tSTART1 = 0, tSTART0 = 0 (Figure 3) tSTART1 = 0, tSTART0 = 1 (Figure 3) tSTART1 = 1, tSTART0 = 0 (Figure 3) tSTART1 = 1, tSTART0 = 1 (Figure 3) tICUT1 = 0, tICUT0 = 0 (Figure 3) tICUT1 = 0, tICUT0 = 1 (Figure 3) tICUT1 = 1, tICUT0 = 0 (Figure 3) tICUT1 = 1, tICUT0 = 1 (Figure 3) Reg16h = 00h tDIS1 = 0, tDIS0 = 0 (Figure 4) tDIS1 = 0, tDIS0 = 1 (Figure 4) tDIS1 = 1, tDIS0 = 0 (Figure 4) tDIS1 = 1, tDIS0 = 1 (Figure 4) VSENSEn – VEE > 5mV, VOUTn = – 48V (Figure 4) (Note 9) (Note 9) Figure 5 (Notes 9, 10) Figure 5 (Notes 9, 10) Figure 5 (Notes 9, 10) Figure 5 (Notes 9, 10) Figure 5 (Notes 9, 10) Figure 5 (Notes 9, 10) Figure 5 (Notes 9, 10) Figure 5 (Notes 9, 10) Figure 5 (Notes 9, 10) Figure 5 (Notes 9, 10) (Notes 9, 10, 11) (Notes 9, 10, 11) (Notes 9, 10) ● ● ● ● ● ● ● ● ● ● ● ● ● ● ELECTRICAL CHARACTERISTICS tICUT Maximum Current Limit Duration After Port Start-Up DCCLMAX tDIS Maximum Current Limit Duty Cycle Disconnect Delay MIN 50 25 100 200 50 25 100 200 5.8 300 75 150 600 tVMIN I2C Timing fSCLK t1 t2 t3 t4 t5 t6 t7 t8 tr tf tFLTINT tSTOPINT tARAINT DC Disconnect Minimum Pulse Width Sensitivity Clock Frequency Bus Free Time Start Hold Time SCL Low Time SCL High Time Data Hold Time Data Set-Up Time Start Set-Up Time Stop Set-Up Time SCL, SDAIN Rise Time SCL, SDAIN Fall Time Fault Present to INT Pin Low Stop Condition to INT Pin Low ARA to INT Pin High Time TYP 60 30 120 240 60 30 120 240 6.3 360 90 180 720 0.02 MAX 70 35 140 280 70 35 140 280 6.7 400 100 200 800 1 UNITS ms ms ms ms ms ms ms ms % ms ms ms ms ms ● ● ● ● ● ● ● ● ● ● ● ● ● ● 400 1.3 600 1.3 600 150 200 600 600 20 20 20 60 20 300 150 150 200 300 kHz µs ns µs ns ns ns ns ns ns ns ns ns ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: DGND and AGND should be tied together in normal operation. Note 3: An internal clamp limits the GATE pins to a minimum of 12V above VEE. Driving this pin beyond the clamp may damage the part. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 5: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground (AGND and DGND) unless otherwise specified. Note 6: The LTC4258 is designed to maintain a port voltage of –46.6V to –57V. The VEE supply voltage range accounts for the drop across the MOSFET and sense resistor. Note 7: The LTC4258 implements overload current detection per IEEE 802.3af. The minimum overload current (ICUT) is dependent on port voltage; ICUT_MIN = 15.4W/VPORT_MIN. An IEEE compliant system using the LTC4258 should maintain port voltage above –46.6V. Note 8: VEE supply current while classifying a short is measured indirectly by measuring the DETECTn pin current while classifying a short. Note 9: Guaranteed by design, not subject to test. Note 10: Values measured at VILD and VIHD. Note 11: If fault occurs during an I2C transaction, the INT pin will not be pulled down until a stop condition is present on the I2C bus. 4258fb 4 LTC4258 TYPICAL PERFOR A CE CHARACTERISTICS Power On Sequence in Auto Mode PORT 1 VDD = 3.3V VEE = – 48V GND POWER ON PORT VOLTAGE 20V/DIV VEE VEE GATE +14V VOLTAGE 10V/DIV VEE PORT CURRENT 0mA 500mA/DIV GND PORT VOLTAGE 10V/DIV DETECTION DETECTION PHASE 1 PHASE 2 CLASSIFICATION VEE Current Limit Foldback 225 200 175 VSENSEn (mV) PULL-DOWN VOLTAGE (V) 150 125 100 75 50 25 VDD = 3.3V VEE = – 48V TA = 25°C –40 –32 –24 –16 –8 0 4258 G03 0 –48 VOUTn-AGND (V) Classification Transient Response to 40mA Load Step 0 VDD = 3.3V VEE = – 48V TA = 25°C –18V CLASSIFICATION VOLTAGE (V) –6 –8 –10 –12 –14 –16 –18 –20 PORT VOLTAGE WITH TYPICAL CMPD3003 DETECTn PIN VOLTAGE 0 10 20 30 40 50 60 CLASSIFICATION CURRENT (mA) 70 SUPPLY CURRENT (mA) PORT VOLTAGE 1V/DIV 40mA PORT CURRENT 20mA/DIV 0mA 50µs/DIV 4258 G07 UW 50ms/DIV Powering On a 180µF Load VDD = 3.3V VEE = – 48V FET ON LOAD FULLY CHARGED FOLDBACK 425mA CURRENT LIMIT 5ms/DIV 4258 G01 4258 G02 INT and SDAOUT Pull Down Voltage vs Load Current 450 400 ILIMIT WITH RSENSE = 0.5Ω (mA) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 5 15 20 10 LOAD CURRENT (mA) 25 4258 G06 VDD = 3.3V TA = 25°C 350 300 250 200 150 100 50 0 Classification Current Compliance VDD = 3.3V –2 VEE = – 48V T = 25°C –4 A 3.0 2.5 2.0 1.5 1.0 0.5 VEE DC Supply Current vs Supply Voltage VDD = 3.3V REG 12h = 00h –50 –40 –30 –20 –10 VEE SUPPLY VOLTAGE (V) 0 0 –70 –60 4258 G08 4258 G09 4258fb 5 LTC4258 TEST TI I G PD INSERTED VPORTn 0V tDET VCLASS VGATEn INT tCLSDLY tDETDLY tPON tCLASS 4258 F02 VSENSEn TO VEE 0V TI I G DIAGRA S SCL SDA 0 1 START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE SCL SDA 0 1 0 AD3 AD2 AD1 AD0 R/W ACK A7 START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE 6 W UW INT VT VEE PORT TURN ON (AUTO MODE) Figure 2. Detect, Class and Turn-On Timing in Auto or Semiauto Modes VLIM VCUT tSTART, tICUT VSENSEn TO VEE VMIN INT tVMIN 4258 F03 tDIS 4258 F04 Figure 3. Current Limit Timing t3 tr Figure 4. DC Disconnect Timing t4 SCL t2 SDA t1 t5 tf t6 t7 t8 4258 F05 Figure 5. I2C Interface Timing UW 0 AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK ACK BY SLAVE ACK BY SLAVE FRAME 3 DATA BYTE ACK BY SLAVE STOP BY MASTER FRAME 2 REGISTER ADDRESS BYTE 4258 F06 Figure 6. Writing to a Register A6 A5 A4 A3 A2 A1 A0 ACK 0 1 0 AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK ACK BY SLAVE ACK BY SLAVE REPEATED START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE ACK BY SLAVE FRAME 2 DATA BYTE NO ACK BY MASTER STOP BY MASTER FRAME 2 REGISTER ADDRESS BYTE 4258 F07 Figure 7. Reading from a Register 4258fb LTC4258 TI I G DIAGRA S SCL SDA SCL SDA PI FU CTIO S RESET (Pin 1): Chip Reset, Active Low. When the RESET pin is low, the LTC4258 is held inactive with all ports off and all internal registers reset to their power-up states. When RESET is pulled high, the LTC4258 begins normal operation. RESET can be connected to an external capacitor or RC network to provide a power turn-on delay. Internal filtering of the RESET pin prevents glitches less than 1µs wide from resetting the LTC4258. Pull RESET high with ≤ 10k or tie to VDD. BYP (Pin 2): Bypass Output. The BYP pin is used to connect the internally generated – 20V supply to an external 0.1µF bypass capacitor. Use a 100V rated 0.1µF, X7R capacitor. Do not connect the BYP pin to any other external circuitry. INT (Pin 3): Interrupt Output, Open Drain. INT will pull low when any one of several events occur in the LTC4258. It will return to a high impedance state when bits 6 or 7 are set in the Reset PB register (1Ah). The INT signal can be used to generate an interrupt to the host processor, eliminating the need for continuous software polling. Individual INT events can be disabled using the Int Mask register (01h). See Register Functions and Applications Information for more information. The INT pin is only updated between I2C transactions. SCL (Pin 4): Serial Clock Input. High impedance clock input for the I2C serial interface bus. The SCL pin should be connected directly to the I2C SCL bus line. SDAOUT (Pin 5): Serial Data Output, Open Drain Data Output for the I2C Serial Interface Bus. The LTC4258 uses two pins to implement the bidirectional SDA function to simplify optoisolation of the I2C bus. To implement a standard bidirectional SDA pin, tie SDAOUT and SDAIN together. See Applications Information for more information. SDAIN (Pin 6): Serial Data Input. High impedance data input for the I2C serial interface bus. The LTC4258 uses two pins to implement the bidirectional SDA function to simplify optoisolation of the I2C bus. To implement a standard bidirectional SDA pin, tie SDAOUT and SDAIN together. See Applications Information for more information. AD3 (Pin 7): Address Bit 3. Tie the address pins high or low to set the I2C serial address to which the LTC4258 responds. This address will be (010A3A2A1A0)b. Pull AD3 high or low with ≤10k or tie to VDD or DGND. AD2 (Pin 8): Address Bit 2. See AD3. AD1 (Pin 9): Address Bit 1. See AD3. AD0 (Pin 10): Address Bit 0. See AD3. 4258fb W U U UW 0 1 0 AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE ACK BY SLAVE FRAME 2 DATA BYTE NO ACK BY MASTER STOP BY MASTER 4258 F08 Figure 8. Reading the Interrupt Register (Short Form) 0 0 0 1 1 0 0 R/W ACK 0 1 0 AD3 AD2 AD1 AD0 1 ACK START BY MASTER FRAME 1 ALERT RESPONSE ADDRESS BYTE ACK BY SLAVE NO ACK BY MASTER STOP BY MASTER 4258 F09 FRAME 2 SERIAL BUS ADDRESS BYTE Figure 9. Reading from Alert Response Address U 7 LTC4258 PI FU CTIO S DETECT1 (Pin 11): Detect Sense, Port 1. The LTC4258 Powered Device (PD) detection and classification hardware monitors port 1 with this pin. Connect DETECT1 to the output port via a low leakage diode (see Figure 1). If the port is unused, the DETECT1 pin can be tied to AGND or allowed to float. DETECT2 (Pin 12): Detection Sense, Port 2. See DETECT1. DETECT3 (Pin 13): Detection Sense, Port 3. See DETECT1. DETECT4 (Pin 14): Detection Sense, Port 4. See DETECT1. DGND (Pin 15): Digital Ground. DGND should be connected to the return from the 3.3V supply. DGND and AGND should be tied together. VDD (Pin 16): Logic Power Supply. Connect to a 3.3V power supply relative to DGND. VDD must be bypassed to DGND near the LTC4258 with at least a 0.1µF capacitor. SHDN1 (Pin 17): Shutdown Port 1, Active Low. When pulled low, SHDN1 shuts down port 1, regardless of the state of the internal registers. Pulling SHDN1 low is equivalent to setting the Reset Port 1 bit in the Reset Pushbutton register (1Ah). Internal filtering of the SHDN1 pin prevents glitches less than 1µs wide from reseting the LTC4258. Pull SHDN1 high with ≤10k or tie to VDD. SHDN2 (Pin 18): Shutdown Port 2, Active Low. See SHDN1. SHDN3 (Pin 19): Shutdown Port 3, Active Low. See SHDN1. SHDN4 (Pin 20): Shutdown Port 4, Active Low. See SHDN1. AGND (Pin 21): Analog Ground. AGND should be connected to the return from the – 48V supply. AGND and DGND should be tied together. SENSE4 (Pin 22): Port 4 Current Sense Input. SENSE4 monitors the external MOSFET current via a 0.5Ω sense resistor between SENSE4 and VEE. Whenever the voltage across the sense resistor exceeds the overcurrent detection threshold VCUT, the current limit fault timer counts up. If the voltage across the sense resistor reaches the current limit threshold VLIM (typically 25mV/50mA higher), the GATE4 pin voltage is lowered to maintain constant current in the external MOSFET. See Applications Information for further details. If the port is unused, the SENSE4 pin must be tied to VEE. GATE4 (Pin 23): Port 4 Gate Drive. GATE4 should be connected to the gate of the external MOSFET for port 4. When the MOSFET is turned on, a 50µA pull-up current source is connected to the pin. The gate voltage is clamped to 13V (typ) above VEE. During a current limit condition, the voltage at GATE4 will be reduced to maintain constant current through the external MOSFET. If the fault timer expires, GATE4 is pulled down with 50µA, turning the MOSFET off and recording a tICUT or tSTART event. If the port is unused, float the GATE4 pin or tie it to VEE. OUT4 (Pin 24): Port 4 Output Voltage Monitor. OUT4 should be connected to the output port through a 10k series resistor. A current limit foldback circuit limits the power dissipation in the external MOSFET by reducing the current limit threshold when the port voltage is within 18V of AGND. The port 4 Power Good bit is set when the voltage from OUT4 to VEE drops below 2V (typ). A 2.5MΩ resistor is connected internally from OUT4 to AGND. If the port is unused, the OUT4 pin can be tied to AGND or allowed to float. SENSE3 (Pin 25): Port 3 Current Sense Input. See SENSE4. GATE3 (Pin 26): Port 3 Gate Drive. See GATE4. OUT3 (Pin 27): Port 3 Output Voltage Monitor. See OUT4. VEE (Pin 28): – 48V Supply Input. Connect to a – 48V to – 57V supply, relative to AGND. SENSE2 (Pin 29): Port 2 Current Sense Input. See SENSE4. GATE2 (Pin 30): Port 2 Gate Drive. See GATE4. OUT2 (Pin 31): Port 2 Output Voltage Monitor. See OUT4. SENSE1 (Pin 32): Port 1 Current Sense Input. See SENSE4. GATE1 (Pin 33): Port 1 Gate Drive. See GATE 4. OUT1 (Pin 34): Port 1 Output Voltage Monitor. See OUT4. AUTO (Pin 35): Auto Mode Input. Auto mode allows the LTC4258 to detect and power up a PD even if there is no host controller present on the I2C bus. The voltage of the AUTO pin determines the state of the internal registers when the LTC4258 is reset or comes out of VDD UVLO (see the Register map in Table 1). The states of these register bits can subsequently be changed via the I2C interface. The real-time state of the AUTO pin is read at bit 0 in the Pin Status register (11h). Pull AUTO high or low with ≤10k or tie to VDD or DGND. NC (Pin 36): No Internal Connection. 4258fb 8 U U U ADDRESS REGISTER NAME Auto Pin Low Supply Event Mask 7 Pwr Good Change 4 0000,0000 0000,0000 0000,0000 0011,0000* Change 3 Change 2 Change 1 Change 4 Change 3 Change 2 Change 1 0000,0000 0000,0000 0000,0000 0011,0000* Pwr Good Pwr Good Pwr Good Pwr Enable Pwr Enable Pwr Enable Pwr Enable 0000,0000 0000,0000 Mask 6 Mask 5 Mask 4 Mask 3 Mask 2 Mask 1 Mask 0 1000,0000 1110,0100 tSTART Fault tICUT Fault Class Complete Detect Complete Disconnect Pwr Good Event Pwr Enable Event 1000,0000 1000,0000 Auto Pin High R/W PORT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET STATE RESET STATE Interrupts 00h Interrupt RO Global 01h Int Mask R/W Global Events 02h Power Event RO 4321 03h Power Event CoR CoR 04h Detect Event Disconnect 4 Reserved Over Temp Reserved VDD UVLO VEE UVLO Reserved Reserved Reserved Reserved Reserved Reserved Reserved tSTART Fault 4 tSTART Fault 3 tSTART Fault 2 tSTART Fault 1 Disconnect 3 Disconnect 2 Disconnect 1 tICUT Fault 4 tICUT Fault 3 tICUT Fault 2 tICUT Fault 1 RO 4321 Class Complete 4 Class Complete 3 Class Complete 2 Class Complete 1 Detect Complete 4 Detect Complete 3 Detect Complete 2 Detect Complete 1 05h Detect Event CoR CoR 06h Fault Event RO 4321 TABLE 1. REGISTER 07h Fault Event CoR CoR RO 4321 0Ah Supply Event RO 4321 AP 0Bh Supply Event CoR Reserved Reserved Reserved Reserved Power Good 4 Reserved Port 4 Mode 1 Reserved Class Enable 4 Reserved Reserved Interrupt Pin Enable Restart Class 4 Power Off 4 Clear All Interrupts Clear Interrupt Pin Reserved Reset All Power Off 3 Power Off 2 Power Off 1 Restart Class 3 Restart Class 2 Restart Class 1 Restart Detect 4 Power On 4 Reset Port 4 Reserved Reserved Reserved Reserved Reserved tSTART1 tSTART0 tICUT1 Reserved Reserved Reserved Reserved Class Enable 3 Class Enable 2 Class Enable 1 Detect Enable 4 Reserved tICUT0 Reserved Reserved Reserved Reserved DC Discon En 4 DC Discon En 3 Detect Enable 3 Port 4 Mode 0 Port 3 Mode 1 Port 3 Mode 0 Port 2 Mode 1 Port 2 Mode 0 Reserved AD3 Pin Status AD2 Pin Status AD1 Pin Status AD0 Pin Status Power Good 3 Power Good 2 Power Good 1 Power Enable 4 Power Enable 3 Reserved Port 1 Mode 1 DC Discon En 2 Detect Enable 2 Reserved tDIS1 Reserved Class Status 2 Class Status 1 Class Status 0 Reserved Detect Status 2 Detect Status 1 Power Enable 2 Class Status 2 Class Status 1 Class Status 0 Reserved Detect Status 2 Detect Status 1 Class Status 2 Class Status 1 Class Status 0 Reserved Detect Status 2 Detect Status 1 Class Status 2 Class Status 1 Class Status 0 Reserved Detect Status 2 Detect Status 1 CoR Detect Status 0 Detect Status 0 Detect Status 0 Detect Status 0 Power Enable 1 Auto Pin Status Port 1 Mode 0 DC Discon En 1 Detect Enable 1 Reserved tDIS0 Reserved 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 00A3A2,A1A000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 1000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 00A3A2,A1A001 1111,1111 0000,1111 1111,1111 0000,0000 0000,0000 1000,0000 Status 0Ch Port 1 Status RO 1 0Dh Port 2 Status RO 2 0Eh Port 3 Status RO 3 0Fh Port 4 Status RO 4 10h Power Status RO 4321 11h Pin Status RO Global Configuration 12h Operating Mode R/W 4321 13h Disconnect Enable R/W 4321 14h Detect/Class Enable R/W 4321 15h Reserved R/W 16h Timing Config R/W Global 17h Misc Config R/W Global Pushbuttons Restart Detect 3 Power On 3 Reset Port 3 Restart Detect 2 Power On 2 Reset Port 2 Restart Detect 1 Power On 1 Reset Port 1 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 18h Det/Class Restart PB WO 4321 19h Power Enable PB WO 4321 1Ah Reset PB WO Global Encoding DETECT STATUS CLASS STATUS Detect Status Unknown 000 000 Class Status Unknown Short Circuit (275mV, >550mA with a 0.5Ω sense resistor) and pulls the GATE pin down immediately if such an event occurs, shutting off the MOSFET in less than 1µs (with no external capacitor on GATE). Approximately 100µs later, GATE is allowed to rise back up and the normal current limit circuit will take over, allowing ILIM current to flow and causing the tICUT timer to count up. During a short circuit, ILIM will be reduced by the foldback feature to 1/7th of the nominal value. Figures 14 and 15 show the LTC4258 controlling port current during short circuits. In Figure 14, the MOSFET is turned off 0.5µs after the port is shorted with 1Ω. The spike in port voltage and current at the moment the MOSFET turns off is the response of inductance in the system, such as the magnetics and the Ethernet cable; see Surge Suppressors and Circuit Protection for further details. The 0.1µF port bypass cap (see Figure 1) provides some port current for 0.25µs after the MOSFET is off. In Figure 15, the LTC4258 quickly turns the port off and the 18 U spike above ground is again due to inductance. It then ramps the MOSFET gate up, similar to applying power after a PD is detected, bringing the port into a controlled 425mA (typ) ILIM current limit. When the short is removed, the port current no longer needs to be limited and LTC4258 ramps up its GATE pin to fully enhance the MOSFET. Short-circuit protection quickly stops excessive current and limits the energy delivered to a short or faulty PD. Yet the LTC4258 only stops current briefly, so momentary faults typically do not cause the PD to lose power and PDs receive at least 50ms of 400mA to 450mA peak current as required by the 802.3af standard. GND PORT VOLTAGE 20V/DIV VEE VEE GATE +15V VOLTAGE 10V/DIV VEE PORT CURRENT 0mA 20A/DIV VDD = 3.3V VEE = – 48V FAST PULL-DOWN ACTIVATED FET OFF SHORT APPLIED 250ns/DIV 4258 G04 W UU Figure 14. Rapid Response to 1Ω Short GND PORT VOLTAGE 20V/DIV VEE VEE +15V VEE CURRENT LIMIT VDD = 3.3V VEE = – 48V GATE VOLTAGE 10V/DIV FAST PULL-DOWN SHORT REMOVED SHORT APPLIED 100µs/DIV 4258 G05 PORT CURRENT 0mA 500mA/DIV Figure 15. Rapid Response to Momentary 100Ω Short 4258fb LTC4258 APPLICATIO S I FOR ATIO Choosing External MOSFETs Power delivery to the ports is regulated with external power MOSFETs. These MOSFETs are controlled as previously described to meet the IEEE 802.3af specification. Under normal operation, once the port is powered and the PD’s bypass capacitor is charged to the port voltage, the external MOSFET dissipates very little power. This suggests that a small MOSFET is adequate for the job. Unfortunately, other requirements of the IEEE 802.3af mandate a MOSFET capable of dissipating significant power. When the port is being powered up, the port voltage must reach 30V or more before the PD turns on. The port voltage can then drop to 0V as the PD’s bypass capacitor is charged. According to the IEEE, the PD can directly connect a 180µF capacitor to the port and the PSE must charge that capacitor with a current limit of 400mA to 450mA for at least 50ms. An even more extreme example is a noncompliant PD that provides the proper signature during detection but then behaves like a low valued resistor, say 50Ω, in parallel with a 1µF capacitor. When the PSE has charged this noncompliant PD up to 20V, the 50Ω resistor will draw 400mA (the minimum IEEE prescribed ILIM current limit) keeping the port voltage at 20V for the remainder of tSTART. The external MOSFET sees 24V to 37V VDS at 400mA to 450mA, dissipating 9.6W to 16.7W for 60ms (typ). The LTC4258 implements foldback to reduce the current limit when the MOSFET VDS is high; see the Foldback section. Without foldback, the MOSFET could see as much as 25.7W for 60ms (typ) when powering a shorted or a noncompliant PD with only a few ohms of resistance. With foldback, the MOSFET sees a maximum of 18W for the duration of tSTART. The LTC4258’s duty cycle protection enforces 15 times longer off time than on time, preventing successive attempts to power a defective PD from damaging the MOSFET. System software can enforce even longer wait times. When the LTC4258 is operated in semiauto or manual mode—described in more detail under Operating Modes— U it will not power on a port until commanded to do so by the host controller. By keeping track of tSTART and tICUT faults, the host controller can delay turning on the port again after one of these faults even if the LTC4258 reports a Detect Good. In this way the host controller implements a MOSFET cooling off period which may be programmed to protect smaller MOSFETs from repeated thermal cycling. The LTC4258 has built-in duty cycle protection for tICUT and tSTART (see tICUT Timing and tSTART Timing sections) that is sufficient to protect the MOSFETs shown in Figure 1. Before designing a MOSFET into your system, carefully compare its safe operating area (SOA) with the worst case conditions (like powering up a defective PD) the device will face. Using transient suppressors, polyfuses and extended wait times after disconnecting a PD are effective strategies to reduce the extremes applied to the external MOSFETs. Surge Suppressors and Circuit Protection IEEE 802.3af Power over Ethernet is a challenging Hot Swap application because it must survive the (probably unintentional) abuse of everyone in the building. While hot swapping boards in a networking or telecom card cage is done by a trained technician or network administrator, anyone in the building can plug a device into the network. Moreover, in a card cage the physical domain being powered is confined to the card cage. With Power over Ethernet, the PSE supplies power to devices up to 100 meters away. Ethernet cables could potentially be cut, shorted together, and so on by all kinds of events from a contractor cutting into walls to someone carelessly sticking a screwdriver where it doesn’t belong. Consequently, the Power over Ethernet power source (PSE) must be designed to handle these events. The most dramatic of these is shorting a powered port. What the PSE sees depends on how much CAT-5 cable is between it and the short. If the short occurs on the far end of a long cable, the cable inductance will prevent the 4258fb W UU 19 LTC4258 APPLICATIO S I FOR ATIO current in the cable from increasing too quickly and the LTC4258’s built-in short-circuit protection will take control of the situation and turn off the port. Some energy is stored in the cable, but the transient suppressor on the port clamps the port voltage when the cable inductance causes the voltage to fly back after the MOSFET is turned off. Because the cable only had 600mA or so going through it, an SMAJ58A or equivalent device can easily control the port voltage during flyback. With no cable connected at all, a powered port shorted at the PSE’s RJ-45 connector can reach high current levels before the port is shut down. There is no cable inductance to store energy so once the port is shut down the situation is under control. A short—hence low inductance—piece of CAT-5 will not limit the rapid increase of current when the port is shorted. Even though the LTC4258 short-circuit shutdown is fast, the cable may have many amps flowing through it before the MOSFET can be turned off. Due to the high current, this short piece of cable flies back with significant energy behind it and must be controlled by the transient suppressor. Choosing a surge suppressor that will not develop more than a few volts of forward voltage while passing more than 10A is important. A positive port voltage may forward bias the detect diode (D DETn), bringing the LTC4258’s DETECTn pin positive as well and engaging the DETECTn clamps. This will generally not damage the LTC4258 but extreme cases can cause the LTC4258 to reset. When it resets, the LTC4258 signals an interrupt, alerting the host controller which can then return the LTC4258 to normal operating mode. A substantial transient surge suppressor can typically protect the LTC4258 and the rest of the PSE from these faults. Placing a polyfuse between the RJ-45 connector and the LTC4258 and its associated circuitry can provide additional protection. To meet safety requirements, place the polyfuse in the ground leg of the PSE’s output. 20 U DC DISCONNECT DC disconnect monitors the sense resistor voltage whenever the power is on to make sure that the PD is drawing the minimum specified current. The disconnect timer counts up whenever port current is below 7.5mA (typ). If the tDIS timer runs out, the corresponding port will be turned off and the disconnect bit in the fault register will be set. If the undercurrent condition goes away before the tDIS timer runs out, the timer will reset. The timer will start counting from the beginning if the undercurrent condition occurs again. The undercurrent circuit includes a glitch filter to filter out noise. The DC disconnect feature can be disabled by clearing the corresponding DC Discon Enable bits in the Disconnect register (13h). The tDIS timer duration can be programmed by bits 1 and 0 of register 16h. The LTC4258 implements a variety of current sense and limit thresholds to control current flowing through the port. Figure 16 is a graphical representation of these thresholds and the action the LTC4258 takes when currrent crosses the thresholds. CURRENT LIMIT IN 1µs PORT OFF IN tICUT OR tSTART CURRENT LIMIT NORMAL OPERATION PORT OFF IN tDIS LIMIT (ILIM) SHORT CIRCUIT EFFECT 4258 F14 W UU 300mV 250mV 200mV 150mV 100mV 50mV 0mV SENSEn VOLTAGE 600mA 500mA 400mA 300mA 200mA 100mA 0mA CURRENT DC DISCUT RS = 0.5Ω CONNECT (ICUT) Figure 16. LTC4258 Current Sense and Limits 4258fb LTC4258 APPLICATIO S I FOR ATIO SERIAL DIGITAL INTERFACE The LTC4258 communicates with a host (master) using the standard 2-wire interface as described in the SMBus Specification Version 2.0 (available at http://smbus.org). The SMBus is an extension of the I2C bus, and the LTC4258 is also compatible with the I2C bus standard. The Timing Diagrams (Figures 5 through 9) show the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources, such as the LTC1694 SMBus accelerator, are required on these lines. If the SDA and SCL pull-ups are absent, not connected to the same positive supply as the LTC4258’s VDD pin, or are not activated when the power is applied to the LTC4258, it is possible for the LTC4258 to see a START condition on the I2C bus. The interrupt pin (INT) is only updated between I2C transactions. Therefore if the LTC4258 sees a START condition when it powers up because the SCL and SDA lines were left floating, it will not assert an interrupt (pull INT low) until it sees a STOP condition on the bus. In a typical application the I2C bus will immediately have traffic and the LTC4258 will see a STOP so soon after power up that this momentary condition will go unnoticed. Isolating the Serial Digital Interface IEEE 802.3af requires that network segments be electrically isolated from the chassis ground of each network interface device. However, the network segments are not required to be isolated from each other provided that the segments are connected to devices residing within a single building on a single power distribution system. For simple devices such as small powered Ethernet switches, the requirement can be met by using an isolated power supply to power the entire device. This implementation can only be used if the device has no electrically conducting ports other than twisted-pair Ethernet. In this case, the SDAIN and SDAOUT pins of the LTC4258 can be connected together to act as a standard I2C/SMBus SDA pin. If the device is part of a larger system, contains serial ports, or must be referenced to protective ground for some other reason, the Power over Ethernet subsystem U including the LTC4258s must be electrically isolated from the rest of the system. The LTC4258 includes separate pins (SDAIN and SDAOUT) for the input and output functions of the bidirectional data line. This eases the use of optocouplers to isolate the data path between the LTC4258s and the system controller. Figure 17 shows one possible implementation of an isolated interface. The SDAOUT pin of the LTC4258 is designed to drive the inputs of an optocoupler directly, but a standard I2C device typically cannot. U1 is used to buffer I2C signals into the optocouplers from the system controller side. Schmitt triggers must be used to prevent extra edges on transitions of SDA and SCL. Bus Addresses and Protocols The LTC4258 is a read-write slave device. The master can communicate with the LTC4258 using the Write Byte, Read Byte and Receive Byte protocols. The LTC4258’s primary serial bus address is (010A3A2A1A0)b, as designated by pins AD3-AD0. All LTC4258s also respond to the address (0110000)b, allowing the host to write the same command into all of the LTC4258s on a bus in a single transaction. If the LTC4258 is asserting (pulling low) the INT pin, it will also acknowledge the Alert Response Address (0001100)b using the receive byte protocol. The START and STOP Conditions When the bus is idle, both SCL and SDA must be high. A bus master (typically the host controller) signals the beginning of communication with a slave device (like the LTC4258) by transmitting a START condition. A START condition is generated by transitioning SDA from high to low while SCL is high. A REPEATED START condition is functionally the same as a START condition, but used to extend the protocol for a change in data transmission direction. A STOP condition is not used to set up a REPEATED START condition, for this would clear any data already latched in. When the master has finished communicating with the slave, it issues a STOP condition. A STOP condition is generated by transitioning SDA from low to high while SCL is high. The bus is then free for communication with another SMBus or I2C device. 4258fb W UU 21 LTC4258 APPLICATIO S I FOR ATIO 200Ω VDD CPU U1 SCL 200Ω SDA HCPL-063L TO CONTROLLER U3 SMBALERT 0.1µF GND CPU U1: FAIRCHILD NC7WZ17 U2, U3: AGILENT HCPL-063L HCPL-063L 0.1µF Figure 17. Optoisolating the I2C Bus 4258fb 22 U 0.1µF I2C ADDRESS VDD INT SCL SDAIN SDAOUT AD0 LTC4258 AD1 AD2 AD3 DGND AGND BYP 0.1µF 0.1µF 0100000 0.1µF U2 2k 2k VDD INT SCL SDAIN SDAOUT AD0 LTC4258 AD1 AD2 AD3 DGND AGND BYP 0.1µF 0.1µF VDD INT SCL SDAIN SDAOUT AD0 LTC4258 AD1 AD2 AD3 DGND AGND BYP 0.1µF • • • 0100001 200Ω 0100010 200Ω VDD INT SCL SDAIN SDAOUT AD0 LTC4258 AD1 AD2 AD3 DGND AGND BYP 0.1µF ISOLATED 3.3V 0.1µF 0101110 10µF W UU + ISOLATED GND VDD INT SCL SDAIN SDAOUT AD0 LTC4258 AD1 AD2 AD3 DGND AGND BYP 0.1µF 4258 F15 0101111 LTC4258 APPLICATIO S I FOR ATIO Acknowledge The Acknowledge signal is used for handshaking between the master and the slave. An Acknowledge (active LOW) generated by the slave lets the master know that the latest byte of information was received. The corresponding SCL clock pulse is always generated by the master. The master releases the SDA line (HIGH) during the Acknowledge clock pulse. The slave must pull down the SDA line during the Acknowledge clock pulse so that it remains a stable LOW during the HIGH period of this clock pulse. When the master is reading from a slave device, it is the master’s responsibility to acknowledge receipt of the data byte in the bit that follows unless the transaction is complete. In that case the master will decline to acknowledge and issue the STOP condition to terminate the communication. Write Byte Protocol The master initiates communication to the LTC4258 with a START condition and a 7-bit bus address followed by the Write Bit (Wr) = 0. If the LTC4258 recognizes its own address, it acknowledges and the master delivers the command byte, signifying to which internal LTC4258 register the master wishes to write. The LTC4258 acknowledges and latches the lower five bits of the command byte into its Register Address register. Only the lower five bits of the command byte are checked by the LTC4258; the upper three bits are ignored. The master then delivers the data byte. The LTC4258 acknowledges once more and latches the data into the appropriate control register. Finally, the master terminates the communication with a STOP condition. Upon reception of the STOP condition, the Register Address register is cleared (see Figure 6). Read Byte Protocol The master initiates communication from the LTC4258 with a START condition and the same 7-bit bus address followed by the Write Bit (Wr) = 0. If the LTC4258 recognizes its own address, it acknowledges and the master delivers the command byte, signifying which internal LTC4258 register it wishes to read from. The LTC4258 acknowledges and latches the lower five bits of the command byte into its Register Address register. At this time the master sends a REPEATED START condition and the same 7-bit bus address followed by the Read Bit U (Rd) = 1. The LTC4258 acknowledges and sends the contents of the requested register. Finally, the master declines to acknowledge and terminates communication with a STOP condition. Upon reception of the STOP condition, the Register Address register is cleared (see Figure 7). Receive Byte Protocol Since the LTC4258 clears the Register Address register on each STOP condition, the interrupt register (register 0) may be read with the Receive Byte Protocol as well as with the Read Byte Protocol. In this protocol, the master initiates communication with the LTC4258 with a START condition and a 7-bit bus address followed by the Read Bit (Rd) = 1. The LTC4258 acknowledges and sends the contents of the interrupt register. The master then declines to acknowledge and terminates communication with a STOP condition (see Figure 8). Alert Response Address and the INT Pin In a system where several LTC4258s share a common INT line, the master can use the Alert Response Address (ARA) to determine which LTC4258 initiated the interrupt. The master initiates the ARA procedure with a START condition and the 7-bit ARA bus address (0001100)b followed by the Read Bit (Rd) = 1. If an LTC4258 is asserting the INT pin, it acknowledges and sends its 7-bit bus address (010A3A2A1A0)b and a 1 (see Figure 9). While it is sending its address, it monitors the SDAIN pin to see if another device is sending an address at the same time using standard I2C bus arbitration. If the LTC4258 is sending a 1 and reads a 0 on the SDAIN pin on the rising edge of SCL, it assumes another device with a lower address is sending and the LTC4258 immediately aborts its transfer and waits for the next ARA cycle to try again. If transfer is successfully completed, the LTC4258 will stop pulling down the INT pin. When the INT pin is released in this way or if a 1 is written into the Clear Interrupt pin bit (bit 6 of register 1Ah), the condition causing the LTC4258 to pull the INT pin down must be removed before the LTC4258 will be able to pull INT down again. This can be done by reading and clearing the event registers or by writing a 1 into the Clear All Interrupts bit (bit 7 of register 4258fb W UU 23 LTC4258 APPLICATIO S I FOR ATIO 1Ah). The state of the INT pin can only change between I2C transactions, so an interrupt is cleared or new interrupts are generated after a transaction completes and before new I2C bus communication commences. Periodic polling of the alert response address can be used instead of the INT pin if desired. If any device acknowledges the alert response address, then the INT line, if connected, would have been low. System Software Strategy Control of the LTC4258 hinges on one decision, the LTC4258’s operating mode. The three choices are described under Operating Modes. In Auto mode the LTC4258 can operate autonomously without direction from a host controller. Because LTC4258s running in Auto mode will power every valid PD connected to them, the PSE must have 15.4W/port available. To reduce the power requirements of the –48V supply, PSE systems can track power usage, only turning on ports when sufficient power is available. The IEEE describes this as a power allocation algorithm and places two limitations: the PSE shall not power a PD unless it can supply the guaranteed power for that PD’s class (see Table 2) and power allocation may not be based solely on a history of each PD’s power consumption. In order for a PSE to implement power allocation, the PSE’s processor/controller must control whether ports are powered—the LTC4258 cannot be allowed to operate in Auto mode. Semiauto mode fits the bill as the LTC4258 automatically detects and classifies PDs, then makes this information available to the host controller, which decides to apply power or not. Operating the LTC4258 in Manual mode also lets the controller decide whether to power the ports but the controller must also control detection and classification. If the host controller operates near the limit of its computing resources, it may not be able to guide a Manual mode LTC4258 through detect, classification and port turn-on in less than the IEEE mandated maximum of 950ms. In a typical PSE, the LTC4258s will operate in Semiauto mode as this allows the controller to decide to power a port without unduly burdening the controller. With an interrupt mask of F4h, the LTC4258 will signal to the host after it has successfully detected and classified a PD, at 24 U which point the host can decide whether enough power is available and command the LTC4258 to turn that port on. Similarly, the LTC4258 will generate interrupts when a port’s power is turned off. By reading the LTC4258’s interrupt register, the host can determine if a port was turned off due to overcurrent (tSTART or tICUT faults) or because the PD was removed (Disconnect event). The host then updates the amount of available power to reflect the power no longer consumed by the disconnected PD. Setting the MSB of the interrupt mask causes the LTC4258 to communicate fault conditions caused by failures within the PSE, so the host does not need to poll to check that the LTC4258s are operating properly. This interrupt driven system architecture provides the controller with the final say on powering ports at the same time, minimizing the controller’s computation requirements because interrupts are only generated when a PD is detected or on a fault condition. The LTC4258 can also be used to power older powered Ethernet devices that are not 802.3af compliant and may be detected with other methods. Although the LTC4258 does not implement these older detection methods automatically, if software or external circuitry can detect the noncompliant devices, the host controller may command the LTC4258 to power the port, bypassing IEEE compliant detection and classification and sending power to the noncompliant device. LOGIC LEVEL SUPPLY In additon to the 48V used to source power to each port, a logic level supply is required to power the digital portion of the LTC4258. To simplify design and meet voltage isolation requirements, the logic level supply can be generated from the isolated – 48V supply. Figure 18 shows an example method using an LTC3803 to control a –48V to 3.3V current mode supply. This boost converter topology uses the LTC3803 current mode controller and a current mirror which reflects the 3.3V output voltage to the –48V rail, improving the regulation tolerance over the more traditional large resistor voltage divider. This approach achieves high accuracy with a transformerless design. 4258fb W UU LTC4258 APPLICATIO S I FOR ATIO IEEE 802.3af COMPLIANCE AND EXTERNAL COMPONENT SELECTION The LTC4258 is designed to control power delivery in IEEE 802.3af compliant Power Sourcing Equipment (PSE). Because proper operation of the LTC4258 may depend on external signals and power sources, like the –48V supply (VEE), external components such as the sense resistors (RS), and possibly software running on an external microprocessor, using the LTC4258 in a PSE does not guarantee 802.3af compliance. Using an LTC4258 does get you most of the way there. This section discusses the rest of the elements that go along with the LTC4258 to make an 802.3af complaint PSE. Each paragraph below addresses a component which is critical for PSE compliance as well as possible pitfalls that can cause a PSE to be noncompliant. For further assistance please contact Linear Technology’s Applications department. Sense Resistors The LTC4258 is designed to use a 0.5Ω sense resistor, RS, to monitor the current through each port. The value of the sense resistor has been minimized in order to reduce power loss and as a consequence, the voltage which the ISOLATED GND 10µF 63V + 0.22µF 100V 0.22µF 100V 1 56k VEE ISOLATED –48V 5 2200pF Figure 18. –48V to 3.3V Boost Converter U LTC4258 must measure is small. Each port may be drawing up to 450mA with this current flowing through the sense resistor and associated circuit board traces. To prevent parasitic resistance on the circuit board from obscuring the voltage drop across the sense resistor, the LTC4258 must Kelvin sense the resistor voltage. One way to achieve Kelvin sensing is “star grounding,” shown pictorially in Figure 1. Another option is to use a – 48V power plane to connect the sense resistor and the LTC4258 VEE pin. Either of these strategies will prevent voltages developed across parasitic circuit board resistances from affecting the LTC4258 current measurement accuracy. The precision of the sense resistor directly affects the measurement of the IEEE parameters IINRUSH, ILIM, ICUT and IMIN. Therefore, to maintain IEEE compliance, use a resistor with 0.5% or better accuracy. Power MOSFETs The LTC4258 controls power MOSFETs in order to regulate current flow through the Ethernet ports. Under certain conditions these MOSFETs have to dissipate significant power. See the Choosing External MOSFETs section for a detailed discussion of the requirements these devices must meet. 100µH 10µF 16V B1100 10µH VDD 3.3V 400mA 10µF 6.3V 10k 100µF 6.3V 3.32k 1% 5 VCC 6 ITH/RUN NGATE LTC3803 3 4 VFB SENSE GND 2 FMMT723 FDC2512 1k 0.100Ω 1% ISOLATED GND FMMT723 806 1% 47.5k 1% 4258 F16 W UU 4258fb 25 LTC4258 APPLICATIO S I FOR ATIO Common Mode Chokes Both nonpowered and powered Ethernet connections achieve best performance (for data transfer, power transfer and EMI) when a common mode choke is used on each port. In the name of cost reduction, some designs share a common mode choke between two adjacent ports. Even for nonpowered Ethernet, sharing a choke is not recommended. With two ports passing through the choke, it cannot limit the common mode current of either port. Instead, the choke only controls the sum of both ports’ common mode current. Because cabling from the ports generally connects to different devices up to 200m apart, a current loop can form. In such a loop, common mode current flows in one port and out the other, and the choke will not prevent this because the sum of the currents is zero. Another way to view this interaction between the paired ports is that the choke acts as a transformer coupling the ports’ common modes together. In nonpowered Ethernet, common mode current results from nonidealities like ground loops; it is not part of normal operation. However, Power over Ethernet sends power and hence significant current through the ports; common mode current is a byproduct of normal operation. As described in the Choosing External MOSFETs section and under the Power Supplies heading below, large transients can occur when a port’s power is turned on or off. When a powered port is shorted (see Surge Suppressors and Circuit Protection), a port’s common mode current may be excessive. Sharing a common mode choke between two ports couples start-up, disconnect and fault transients from one port to the other. The end result can range from momentary noncompliance with 802.3af to intermittent behavior and even to excessive voltages that may damage circuitry (in both the PSE and PD) connected to the ports. Detect Pin Diodes During detection and classification, the LTC4258 senses the port voltage through the detect diodes DDET. Excessive voltage drop across DDET will corrupt the LTC4258’s detect and classification results. Select a diode for DDET that will have less than 0.7V of forward drop at 0.4mA and less than 0.9V of forward drop at 50mA. 26 U Power Supplies The LTC4258 must be supplied with 3.3V (VDD) and –48V (VEE). Poor regulation on either of these supplies can lead to noncompliance. The IEEE requires a PSE output voltage between 44V and 57V. When the LTC4258 begins powering an Ethernet port, it controls the current through the port to minimize disturbances on VEE. However, if the VEE supply is underdamped or otherwise unstable, its voltage could go outside of the IEEE specified limits, causing all ports in the PSE to be noncompliant. This scenario can be even worse when a PD is unplugged because the current can drop immediately to zero. In both cases the port voltage must always stay between –44V and –57V. In addition, the 802.3af specification places specific ripple, noise and load regulation requirements on the PSE. Among other things, disturbances on either VDD or VEE can adversely affect detection and classification sensing. Proper bypassing and stability of the VDD and VEE supplies is important. Another problem that can affect the VEE supply is insufficient power, leading to the supply voltage drooping out of the specified range. The 802.3af specification states that if a PSE powers a PD it must be able to provide the maximum power level requested by the PD based on the PD’s classification. The specification does allow a PSE to choose not to power a port because the PD requires more power than the PSE has left to deliver. If a PSE is built with a VEE supply capable of less than 15.4W • (number of PSE’s Ethernet ports), it must implement a power allocation algorithm that prevents ports from being powered when there is insufficient power. Because the specification also requires the PSE to supply 400mA at up to a 5% duty cycle, the VEE supply capability should be at least a few percent more than the maximum total power the PSE will supply to PDs. Finally, the LTC4258s draw current from VEE. If the VDD supply is generated from VEE, that power divided by the switcher efficiency must also be added to the VEE supply’s capability. Fast VEE transients can damage the LTC4258. Limit the VEE slew rate to 50mV/µs. In most applications, existing VEE bypass capacitors will cause the VEE supply to slew much slower than 50mV/µs. 4258fb W UU LTC4258 PACKAGE DESCRIPTIO 1.143 ± 0.127 10.668 MIN 7.416 – 7.747 0.520 ±0.0635 RECOMMENDED SOLDER PAD LAYOUT 7.417 – 7.595** (.292 – .299) 0.254 – 0.406 × 45° (.010 – .016) 0° – 8° TYP 0.231 – 0.3175 (.0091 – .0125) 0.610 – 1.016 (.024 – .040) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U GW Package 36-Lead Plastic SSOP (Wide .300 Inch) (Reference LTC DWG # 05-08-1642) 15.290 – 15.544* (.602 – .612) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 10.160 – 10.414 (.400 – .410) 0.800 TYP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2.463 – 2.641 (.097 – .104) 2.286 – 2.387 (.090 – .094) 0.800 (.0315) BSC 0.304 – 0.431 (.012 – .017) 0.127 – 0.305 (.005 – .0115) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE GW36 SSOP 0502 4258fb 27 LTC4258 TYPICAL APPLICATIO 200Ω VDD CPU U1 SCL 200Ω TO CONTROLLER SDA HCPL-063L U3 –48V ISOLATED SMBALERT 0.1µF GND CPU HCPL-063L DDET: CENTRAL SEMI CMPD3003 DTSS: DIODES INC SMAJ58A L1: PULSE ENG PO473 Q1: FAIRCHILD IRFM120A RS: VISHAY WSL2010 0.5Ω 0.5% T1: PULSE ENG H2009 U1: FAIRCHILD NC7WZ17 U2, U3: AGILENT HCPL-063L RELATED PARTS PART NUMBER LT1619 LTC1694 LTC3803 LTC4255 LTC4257 LTC4257-1 LTC4259A-1 LTC4267 DESCRIPTION Low Voltage Current Mode PWM Controller SMBus/I2C Accelerator Current Mode Flyback DC/DC Controller in ThinSOT Quad Network Power Controller IEEE 802.3af PD Interface Controller IEEE 802.3af PD Interface Controller Quad IEEE 802.3af Power Over Ethernet Controller IEEE802.3af PD Interface with Integrated Switching Regulator COMMENTS –48V to 3.3V at 300mA, MSOP Package Improved I2C Rise Time, Ensures Data Integrity 200kHz Constant Frequency, Adjustable Slope Compensation, Optimized for High Input Voltage Applications Non-IEEE 802.3af Compliant Current Levels 100V 400mA Internal Switch, Programmable Classification 100V 400mA Internal Switch, Dual Current Limit With AC Disconnect 100V, 400mA UVLO Switch, Dual Inrush Current, Programmable Classification 4258fb 28 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● U ISOLATED 3.3V 0.1µF ISOLATED GND DGND AGND 0.1µF 2k U2 VDD SCL 1/4 SDAIN LTC4258 SDAOUT INT BYP DETECT 0.1µF 100V X7R L1 2k VEE SENSE GATE OUT 0.1µF DDET CMPD3003 RS 0.5Ω Q1 IRFM120A 10k DTSS 58V SMAJ58A 200Ω 1/2 PULSE H2009 RJ45 CONNECTOR 0.01µF 200V 75Ω 0.01µF 200V 75Ω 200Ω PHY (NETWORK PHYSICAL LAYER CHIP) T1A 1:1 1 2 3 4 5 6 7 8 0.01µF 200V 75Ω 75Ω 0.01µF 200V T1B 1:1 4258 F17 1000pF 2000V Figure 19. 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