LTC4268CDKD-1-TRPBF

FEATURES n n n n n n n n n n n LTC4268-1 High Power PD with Synchronous NoOpto Flyback Controller DESCRIPTION The LTC®4268-1 is an integrated Powered Device (PD) controller and switching regulator intended for IEEE 802.3af and high power PoE applications up to 35W. By including a precision dual current limit, the LTC4268-1 keeps inrush below IEEE 802.3af current limit levels to ensure interoperability success while enabling high power applications with a 750mA operational current limit. The LTC4268-1 synchronous, current-mode, flyback controller generates multiple supply rails in a single conversion providing for the highest system efficiency while maintaining tight regulation across all outputs. The LTC4268-1 includes Linear Technology’s patented NoOpto feedback topology to provide full IEEE 802.3af isolation without the need of optoisolator circuitry. The oversized power path and high performance flyback controller of the LTC4268-1 combine to make the ultimate solution for power hungry PoE applications such as WAPs, PTZ security cameras, RFID readers and ultra-efficient 802.3af applications running near the 12.95W limit. The LTC4268-1 is available in a space saving 32-pin DFN package. , LT LTC and LTM are registered trademarks of Linear Technology Corporation. , All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5841643. Robust 35W PD Front End IEEE 8X02.3af Compliant Rugged 750mA Power MOSFET with Precision Dual Level Current Limit High Performance Synchronous Flyback Controller IEEE Isolation Obtained without an Optoisolator Adjustable Frequency from 50kHz to 250kHz Tight Multi-Output Regulation with Load Compensation Onboard 25k Signature Resistor Programmable Classification Current to 75mA Complete Thermal and Over-Current Protection Available in Compact 32-Pin 7mm × 4mm DFN Package APPLICATIONS n n n n n n n VoIP Phones with Advanced Display Options Dual-Radio Wireless Access Points PTZ Security Cameras RFID Readers Industrial Controls Magnetic Card Readers High Power PoE Systems TYPICAL APPLICATION 35W High Efficiency PD Solution + 47k SMAJ58A DF1501S –54V FROM DATA PAIR 100k 47μF 0.1μF DF1501S –54V FROM SPARE PAIR BAS21 20Ω T1 28.7k 1% 3.01k 1% ≥5μF 100pF 56Ω • T1 + • 470μF ×4 47Ω FMMT618 3.3V • B0540W Si4490DY FB PG SENSE+ 0.02Ω SENSE– Si7336ADP ~+ ~– VPORTP PWRGD PWRGD UVLO ILIM_EN SHDN FMMT718 1μF 15Ω VCC ~+ ~– RCLASS LTC4268-1 SG VCMP OSC GND SFST CCMP 330Ω 0.1μF T2 10nF 2.2nF VPORTN T1: PA1477NL T2: PA0184 RCLASS VNEG PGDLY 12k tON SYNC RCMP ENDLY 169k 100k 47pF • • 10k BAT54 42681 TA01a 20k 0.033μF 42681fa 1 LTC4268-1 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION TOP VIEW SHDN NC RCLASS ILIM_EN VPORTN VPORTN VPORTN NC SG 1 2 3 4 5 6 7 8 9 33 32 VPORTP 31 NC 30 PWRGD 29 PWRGD 28 VNEG 27 VNEG 26 VNEG 25 NC 24 PG 23 PGDLY 22 RCMP 21 CCMP 20 SENSE+ 19 SENSE– 18 UVLO 17 VCMP VPORTN Voltage .......................................... 0.3V to –90V VNEG Voltage ...................VPORTN + 90V to VPORTN –0.3V VCC to GND Voltage (Note 3) Low Impedance Source ......................... –0.3V to 18V Current Fed ..........................................30mA into VCC RCLASS, ILIM_EN Voltage ...VPORTN + 7V to VPORTN – 0.3V SHDN Voltage ................VPORTN + 90V to VPORTN – 0.3V PWRGD Voltage (Note 3) Low Impedance Source ....VNEG + 11V to VNEG – 0.3V Current Fed ..........................................................5mA PWRGD Voltage .............VPORTN + 80V to VPORTN – 0.3V PWRGD Current .....................................................10mA RCLASS Current.....................................................100mA SENSE–, SENSE+ Voltage ........................ –0.5V to +0.5V UVLO, SYNC Voltage...................................–0.3V to VCC FB Current ..............................................................±2mA VCMP Current .........................................................±1mA Operating Ambient Temperature Range (Notes 4, 5) LTC4268-1C ............................................. 0°C to 70°C LTC4268-1I .......................................... –40°C to 85°C Junction Temperature (Note 5) ............................. 150°C Storage Temperature Range................... –65°C to 150°C VCC 10 tON 11 ENDLY 12 SYNC 13 SFST 14 OSC 15 FB 16 DKD32 PACKAGE 32-LEAD (7mm × 4mm) PLASTIC DFN TJMAX = 150°C,θJA = 49°C/W, θJC = 4.7°C/W EXPOSED PAD (PIN 33) MUST BE SOLDERED TO HEATSINKING PLANE THAT IS ELECTRICALLY CONNECTED TO GND ORDER INFORMATION LEAD FREE FINISH LTC4268CDKD-1#PBF LTC4268IDKD-1#PBF LEAD BASED FINISH LTC4268CDKD-1 LTC4268IDKD-1 TAPE AND REEL LTC4268CDKD-1#TRPBF LTC4268IDKD-1#TRPBF TAPE AND REEL LTC4268CDKD-1#TR LTC4268IDKD-1#TR PART MARKING* 42681 42681 PART MARKING* 42681 42681 PACKAGE DESCRIPTION 32-Lead (7mm × 4mm) Plastic DFN 32-Lead (7mm × 4mm) Plastic DFN PACKAGE DESCRIPTION 32-Lead (7mm × 4mm) Plastic DFN 32-Lead (7mm × 4mm) Plastic DFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 42681fa 2 LTC4268-1 ELECTRICAL CHARACTERISTICS SYMBOL VPORT PARAMETER Supply Voltage IEEE 802.3af System Signature Range Classification Range UVLO Turn-On Voltage UVLO Turn-Off Voltage VTURNON VTURNOFF VHYST VCLAMP IVCC IVCC_START VFB IFB_BIAS gm IFB VFBCLAMP %VREF AV ISFST ISFST VCMP_THLD VPG_HIGH, VSG_HIGH VPG_LOW, VSG_LOW VPG_SHDN, VSG_SHDN tPG_RISE, tSG_RISE tPG_FALL, tSG_FALL VSENSE_LIM ΔVSENSE/ΔVCMP VSENSE_OC VIH_SHDN VIL_SHDN PG, SG, Output Shutdown Strength PG, SG Rise Time PG, SG Fall Time Switch Current Threshold at Maximum VCMP Sense Threshold vs VCMP Sense Pin Overcurrent Fault Voltage Shutdown High Level Input Voltage Shutdown Low Level Input Voltage VSENSE+, VSFST < 1V With Respect to VPORTN High Level = Shutdown (Note 12) With Respect to VPORTN l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 14V, SG open, VCMP = 1.5V, VSENSE = 0V, RCMP = 1k, RtON = 90k, RPGDLY = 27.4k, RENDLY = 90k, unless otherwise specified. CONDITIONS Voltage with Respect to VPORTP Pin (Notes 6, 7, 8, 9, 10) MIN TYP MAX UNITS l l l l l l l l l l l l –1.5 –12.5 –37.7 –29.8 14 8 4 19.5 4 1.22 700 25 –38.9 –30.6 15.3 9.7 5.6 20.2 6.4 180 1.237 200 1000 55 2.56 0.84 –57 –10.1 –21 –40.2 –31.5 16.6 11 7.2 V V V V V V V V V VCC Turn-On Voltage VCC Turn-Off Voltage VCC Hysteresis VCC Shunt Regulator Voltage VCC Supply Current VCC Start-Up Current Feedback Regulation Voltage Feedback Pin Input Bias Current Feedback Amplifier Transconductance Feedback Amplifier Source or Sink Current Feedback Amplifier Clamp Voltage Reference Voltage Line Regulation Feedback Amplifier Voltage Gain Soft-Start Charging Current Soft-Start Discharge Current Control Pin Threshold (VCMP) PG, SG, Output High Level PG, SG, Output Low Level Voltage with Respect to GND Voltage with Respect to GND VTURNON – VTURNOFF IVCC = 15mA, VUVLO = 0V, Voltage with Respect to GND VCMP = Open (Note 11) VCC = 10V RCMP Open 10 400 1.251 1400 90 mA μA V nA A/V μA V V l l VFB = 0.9V VFB = 1.4V 12V ≤ VCC ≤ 18V VCMP = 1.2V to 1.7V VSFST = 1.5V VSFST = 1.5V, VUVLO = 0V Duty Cycle = Min l l l 0.005 1500 16 0.8 6.6 20 1.3 1 7.4 0.01 1.4 15 15 0.02 25 %/V V/V μA mA V 8 0.05 2.3 V V V ns ns VUVLO = 0V; IPG, ISG = 20mA CPG, CSG = 1nF CPG, CSG = 1nF Measured at VSENSE+ l l 88 100 0.07 205 110 mV V/V 230 57 0.45 mV V V 3 42681fa 3 LTC4268-1 ELECTRICAL CHARACTERISTICS SYMBOL RINPUT_SHDN VIH_ILIM VIL_ILIM IVPORTN IIN_CLASS ΔICLASS RSIGNATURE PARAMETER Shutdown Input Resistance ILIM_EN High Level Input Voltage ILIM_EN Low Level Input Voltage VPORTN Supply Current IC Supply Current During Classification Current Accuracy During Classification Signature Resistance The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 14V, SG open, VCMP = 1.5V, VSENSE = 0V, RCMP = 1k, RtON = 90k, RPGDLY = 27.4k, RENDLY = 90k, unless otherwise specified. CONDITIONS With Respect to VPORTN With Respect to VPORTN (Note 13) High Level Enables Current Limit With Respect to VPORTN (Note 13) VPORTN = –54V VPORTN = –17.5V, VNEG Tied to VPORTP (Note 14) 10mA < ICLASS < 75mA –12.5V ≤ VPORTN ≤ –21V (Notes 15, 16) –1.5V ≤ VPORTN ≤ –10.1V, SHDN Tied to VPORTN, IEEE 802.3af Two-Point Measurement (Notes 8, 9) –1.5V ≤ VPORTN ≤ –10.1V, SHDN Tied to VPORTP , IEEE 802.3af Two-Point Measurement (Notes 8, 9) I = 1mA, VPORTN = –54V, PWRGD Referenced to VPORTN I = 0.5mA, VPORTN = –52V, VNEG = –4V PWRGD Referenced to VNEG (Note 17) I = 2mA, VNEG = 0V, PWRGD Referenced to VNEG (Note 3) l l l l l l l l l l l l l l l l MIN 100 4 TYP MAX UNITS kΩ V 1 3 0.55 0.62 0.70 ±3.5 23.25 26 V mA mA % kΩ RINVALID Invalid Signature Resistance 10 11.8 kΩ VPWRGD_OUT IPWRGD_LEAK VPWRGD_OUT VPWRGD_VCLAMP IPWRGD_LEAK RON IOUT_LEAK ILIM_HI ILIM_LO ILIM_DISA Active Low Power Good Output Voltage 0.5 1 0.35 12 14 16.5 1 0.5 0.6 0.8 1 700 250 1.2 750 300 1.45 800 350 1.65 V μA V V μA Ω Ω μA mA mA A Active Low Power Good Output Leakage VPORT = 0V, VPWRGD = 57V Active High Power Good Output Voltage Active High Power Good Voltage Limiting Clamp Active High Power Good Output Leakage VPWRGD = 11V with Respect to VNEG, VNEG = VPORTN = –54V On-Resistance VOUT Leakage Input Current Limit, High Level Input Current Limit, Low Level Safeguard Current Limit When ILIM is Disabled Oscillator Frequency Oscillator Capacitor Value Minimum Switch on Time Flyback Enable Delay Time PG Turn-On Delay Time Maximum Switch Duty Cycle SYNC Pin Threshold SYNC Pin Input Resistance I = 700mA, VPORTN = –48V, Measured from VPORTN to VNEG (Note 16) VPORTN = –57V, VPORTP = SHDN = VNEG = 0V (Note 15) VPORTN = –54V, VNEG = –53V ILIM_EN Floating (Notes 18, 19) VPORTN = –54V, VNEG = –53V (Notes 18, 19) VPORTN = –54V, VNEG = –52.5V ILIM_EN Tied To VPORTN (Notes 18, 19, 20) COSC = 100pF (Note 21) fOSC COSC tON(MIN) tENDLY tPGDLY DCON(MAX) VSYNC RSYNC l 84 33 100 200 265 200 110 200 kHz pF ns ns ns % l l 85 88 1.53 40 2.1 V kΩ 42681fa 4 LTC4268-1 ELECTRICAL CHARACTERISTICS SYMBOL ILCOMP VLCOMP VUVLO IUVLOL IUVLOH PARAMETER Feedback Pin Load Compensation Current Load Comp to VSENSE Offset Voltage UVLO Pin Threshold UVLO Pin Bias Current VUVLO = 1.2V VUVLO = 1.3V The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 14V, SG open, VCMP = 1.5V, VSENSE = 0V, RCMP = 1k, RtON = 90k, RPGDLY = 27.4k, RENDLY = 90k, unless otherwise specified. CONDITIONS VRCMP with VSENSE+ = 0V VSENSE+ = 20mV, VFB = 1.23V l MIN TYP 20 1 MAX UNITS μA mV 1.215 –0.25 –4.50 1.237 0 –3.4 1.265 0.25 –2.5 V μA μA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages are with respect to VPORTP pin unless otherwise noted. Note 3: Active High PWRGD internal clamp circuit self-regulates to 14V with respect to VNEG. VCC has internal 20V clamp with respect to GND. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 5: TJ is calculated from the ambient temperature TA and power dissipation PDIS according to the formula: TJ = TA + (PDIS • 49°C/W) Note 6: The LTC4268-1 operates with a negative supply voltage in the range of –1.5V to –57V. To avoid confusion, voltages in this data sheet are referred to in terms of absolute magnitude. Terms such as “maximum negative voltage” refer to the largest negative voltage and a “rising negative voltage” refers to a voltage that is becoming more negative. Note 7: In IEEE 802.3af systems, the maximum voltage at the PD jack is defined to be –57V. Note 8: The LTC4268-1 is designed to work with two polarity protection diodes in series with the input. Parameter ranges specified in the Electrical Characteristics are with respect to LTC4268-1 pins and are designed to meet IEEE 802.3af specifications when the drop from the two diodes is included. See Applications Information. Note 9: Signature resistance is measured via the two-point ΔV/ΔI method as defined by IEEE 802.3af. The LTC4268-1 signature resistance is offset from 25k to account for diode resistance. With two series diodes, the total PD resistance will be between 23.75k and 26.25k and meet IEEE 802.3af specifications. The minimum probe voltages measured at the LTC4268-1 pins are –1.5V and –2.5V. The maximum probe voltages are –9.1V and –10.1V. Note 10: The LTC4268-1 includes hysteresis in the UVLO voltages to preclude any start-up oscillation. Per IEEE 802.3af requirements, the LTC4268-1 will power up from a voltage source with 20Ω series resistance on the first trial. Note 11: Supply current does not include gate charge current to the MOSFETs. See Application Information. Note 12: To disable the 25k signature, tie SHDN to VPORTP (±0.1V) or hold SHDN high with respect to VIN. See Applications Information. Note13: ILIM_EN pin is pulled high internally and for normal operation should be left floating. To disable current limit, tie ILIM_EN to VIN. See Applications Information. Note 14: IIN_CLASS does not include classification current programmed at Pin 3. Total supply current in classification mode will be IIN_CLASS + ICLASS (See Note 15). Note 15: ICLASS is the measured current flowing through RCLASS. ΔICLASS accuracy is with respect to the ideal current defined as ICLASS = 1.237/ RCLASS. TCLASSRDY is the time for ICLASS to settle to within ±3.5% of ideal. The current accuracy specification does not include variations in RCLASS resistance. The total classification current for a PD also includes the IC quiescent current (IIN_CLASS). See Applications Information. Note 16: This parameter is assured by design and wafer level testing. Note 17: Active high power good is referenced to VNEG and is valid for VPORTP – VNEG ≥ 4V. Note 18: The LTC4268-1 includes a dual current limit. At turn on, before C1 is charged, the LTC4268-1 current level is set to ILIMIT_LOW. After C1 is charged and with ILIM_EN floating, the LTC4268-1 switches to ILIMIT_HIGH. With ILIM_EN pin tied low, the LTC4268-1 switches to ILIMIT_DISA. The LTC4268-1 stays in ILIMIT_HIGH or ILIMIT_DISA until the input voltage drops below the UVLO turn-off threshold or a thermal overload occurs. Note 19: The LTC4268-1 features thermal overload protection. In the event of an over temperature condition, the LTC4268-1 will turn off the power MOSFET, disable the classification load current, and present an invalid power good signal. Once the LTC4268-1 cools below the over temperature limit, the LTC4268-1 current limit switches to ILIMIT_LOW and normal operation resumes. Note 20: ILIMIT_DISA is a safeguard current limit that is activated when the normal input current limit (ILIMIT_HIGH) is defeated using the ILIM_EN pin. Currents at or near ILIMIT_DISA will cause significant package heating and may require a reduced maximum ambient operating temperature in order to avoid tripping the thermal overload protection. Note 21: Component value range guaranteed by design. 42681fa 5 LTC4268-1 TYPICAL PERFORMANCE CHARACTERISTICS Input Current vs Input Voltage 25k Detection Range 0.5 TA = 25°C 100 Input Current vs Input Voltage TA = 25°C 12.0 11.5 80 INPUT CURRENT (mA) CLASS 5* 60 CLASS 4 40 CLASS 3 20 CLASS 2 CLASS 1 CLASS 0 INPUT CURRENT (mA) 11.0 10.5 10.0 9.5 Input Current vs Input Voltage CLASS 1 OPERATION 0.4 INPUT CURRENT (mA) 0.3 85°C –40°C 0.2 0.1 0 0 –2 –4 –6 INPUT VOLTAGE (V) –8 –10 42681 G01 0 0 –20 –30 –40 INPUT VOLTAGE (V) *OPTIONAL CLASS 5 CURRENT –10 –50 –60 9.0 –12 –14 –20 –18 –16 INPUT VOLTAGE (V) –22 42681 G03 42681 G02 Signature Resistance vs Input Voltage 28 RESISTANCE = V = V2 – V1 I I2 – I1 27 DIODES: DF1501S TA = 25°C IEEE UPPER LIMIT INPUT VOLTAGE 10V/DIV Class Operation vs Time 1.0 TA = 25°C 0.8 RESISTANCE (Ω) On Resistance vs Temperature SIGNATURE RESISTANCE (kΩ) 26 25 24 LTC4268-1 ONLY 23 IEEE LOWER LIMIT LTC4268-1 + 2 DIODES CLASS CURRENT 20mA/DIV 0.6 0.4 0.2 22 V1: –1 V2: –2 –3 –4 –7 –5 –8 –6 INPUT VOLTAGE (V) –9 –10 42681 G04 TIME (10μs/DIV) 0 –50 75 0 25 50 –25 JUNCTION TEMPERATURE (°C) 100 42681 G05 42681 G06 Active Low PWRGD: Output Low Voltage vs Current 4 1.0 TA = 25°C 0.8 Active High PWRGD: Output Low Voltage vs Current TA = 25°C GND – VNEG = 4V CURRENT LIMIT (mA) 800 Current Limit vs Input Voltage –40°C 85°C HIGH CURRENT MODE 600 VPWRGD_OUT – VPORTN (V) 3 PWRGD – VNEG (V) 0.6 2 0.4 400 –40°C 85°C LOW CURRENT MODE 1 0.2 0 0 0 2 6 8 4 INPUT CURRENT (mA) 10 42681 G07 0 1 0.5 1.5 INPUT CURRENT (mA) 2 42681 G08 200 –40 –55 –45 –50 INPUT VOLTAGE (V) –60 42681 G09 42681fa 6 LTC4268-1 TYPICAL PERFORMANCE CHARACTERISTICS VCC(ON) and VCC(OFF) vs Temperature 16 15 14 IVCC (mA) IVCC (μA) 13 VCC (V) 12 11 VCC(OFF) 10 9 8 –50 –25 0 50 75 25 TEMPERATURE (°C) 100 125 50 0 –50 –25 200 7 6 STATIC PART CURRENT 5 4 VCC = 14V 3 50 –50 –25 25 75 0 TEMPERATURE (°C) 150 100 VCC(ON) 300 250 VCC Start-Up Current vs Temperature 10 9 8 VCC Current vs Temperature DYNAMIC CURRENT CPG = 1nF , , CSG = 1nF fOSC = 100kHz 50 25 75 0 TEMPERATURE (°C) 100 125 100 125 42681 G10 42681 G11 42681 G12 SENSE Voltage vs Temperature 110 108 106 SENSE VOLTAGE (mV) 104 102 100 98 96 94 92 90 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 FB = 1.1V SENSE = VSENSE+ WITH VSENSE– = 0V SENSE VOLTAGE (mV) 220 SENSE Fault Voltage vs Temperature SENSE = VSENSE+ – 215 WITH VSENSE = 0V 210 fOSC (kHz) 205 200 195 190 185 180 –50 –25 0 50 75 25 TEMPERATURE (°C) 100 125 110 108 106 104 102 100 98 96 94 92 Oscillator Frequency vs Temperature COSC = 100pF 90 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 42681 G13 42681 G14 42681 G15 VFB vs Temperature 1.240 1.239 1.238 1.237 VFB (V) 1.236 1.235 1.234 1.233 1.232 1.231 1.230 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 FEEDBACK PIN INPUT BIAS (nA) 250 200 150 100 50 300 Feedback Pin Input Bias vs Temperature RCMP OPEN 1.04 1.03 1.02 VFB RESET (V) 50 25 75 0 TEMPERATURE (°C) 100 125 1.01 1.00 0.99 0.98 0.97 VFB Reset vs Temperature 0 –50 –25 0.96 –50 –25 0 75 50 25 TEMPERATURE (°C) 100 125 42681 G16 42681 G17 42681 G18 42681fa 7 LTC4268-1 TYPICAL PERFORMANCE CHARACTERISTICS Feedback Amplifier Output Current vs VFB 70 125°C 50 30 IVCMP (μA) 10 –10 –30 –50 –70 0.9 1 1.1 1.2 VFB (V) 1.3 1.4 1.5 42681 G19 Feedback Amplifier Source and Sink Current vs Temperature 70 25°C –40°C 60 IVCMP (μA) 55 50 950 45 40 –50 65 SOURCE CURRENT VFB = 1.1V SINK CURRENT VFB = 1.4V 1100 Feedback Amplifier gm vs Temperature 1050 gm (μmho) 1000 –25 50 25 75 0 TEMPERATURE (°C) 100 125 900 –50 –25 75 0 25 50 TEMPERATURE (°C) 100 125 42681 G20 42681 G21 Feedback Amplifier Voltage Gain vs Temperature 1700 1650 1600 1550 1500 UVLO (V) AV (V/V) 1450 1400 1350 1300 1250 1200 1150 1100 –50 –25 0 75 50 25 TEMPERATURE (°C) 100 125 1.225 1.240 1.245 1.250 UVLO vs Temperature 3.7 3.6 3.5 IUVLO (μA) 3.4 3.3 3.2 3.1 IUVLO Hysteresis vs Temperature 1.235 1.230 1.220 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 3.0 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 42681 G22 42681 G23 42681 G24 Soft-Start Charge Current vs Temperature 23 22 SFST CHARGE CURRENT (μA) 21 TIME (ns) 20 19 18 17 16 15 –50 –25 0 50 75 25 TEMPERATURE (°C) 100 125 80 70 PG, SG Rise and Fall Times vs Load Capacitance TA = 25°C 21.5 VCC Clamp Voltage vs Temperature ICC = 10mA 21.0 60 50 FALL TIME 40 30 RISE TIME 20 10 0 0 1 2 34567 CAPACITANCE (nF) 8 9 10 19.0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 19.5 20.5 42681 G25 VCC (V) 20.0 42681 G26 42681 G27 42681fa 8 LTC4268-1 TYPICAL PERFORMANCE CHARACTERISTICS Minimum PG On Time vs Temperature 340 330 320 tON(MIN) (ns) tPGDLY (ns) 310 300 290 280 270 260 –50 –25 0 50 75 25 TEMPERATURE (°C) 100 125 50 0 –50 225 205 –50 –25 200 tENDLY (ns) 150 100 RPGDLY = 16.9k RtON(MIN) = 158k 300 250 RPGDLY = 27.4k 285 265 245 PG Delay Time vs Temperature 325 305 Enable Delay Time vs Temperature RENDLY = 90k –25 25 0 75 50 TEMPERATURE (°C) 100 125 50 25 75 0 TEMPERATURE (°C) 100 125 42681 G28 42681 G29 42681 G30 PIN FUNCTIONS SHDN (Pin 1): Shutdown Input. Used to command the LTC4268-1 to present an invalid signature and remain inactive. Connecting SHDN to VPORTP lowers the signature resistance to an invalid value and disables other LTC4268-1 operations. If unused, tie SHDN to VPORTN. NC (Pin 2): No internal connection. RCLASS (Pin 3): Class Select Input. Used to set the current the LTC4268-1 maintains during classification. Connect a resistor between RCLASS and VPORTN. (See Table 2.) ILIM_EN (Pin 4): Input Current Limit Enable. Used for controlling the LTC4268-1 current limit behavior during powered operation. For normal operation, float ILIM_EN to enable ILIMIT_HIGH current. Tie ILIM_EN to VPORTN to disable input current limit. Note that the inrush current limit will always be active. See Applications Information. VPORTN (Pins 5, 6, 7): Power Input. Tie to the PD Input through the diode bridge. Pins 5, 6 and 7 must be electrically tied together. NC (Pin 8): No internal connection. SG (Pin 9): Secondary Gate Driver Output. This pin provides an output signal for a secondary-side synchronous switch. Large dynamic currents may flow during voltage transitions. See the Applications Information for details. VCC (Pin 10): Converter Voltage Supply. Bypass this pin to GND with 4.7μF or greater. This pin has a 20V clamp to ground. VCC has an undervoltage lockout function that turns on when VCC is approximately 15.3V and off at 9.7V. In a conventional “trickle-charge” bootstrapped configuration, the VCC supply current increases significantly during turn-on causing a benign relaxation oscillation action on the VCC pin if the part does not start normally. tON (Pin 11): Primary Switch Minimum On Time Control. A programming resistor (RTon) to GND sets the minimum time for each cycle. See Applications Information for details. ENDLY (Pin 12): Enable Delay Time Control. The enable delay time is set by a programming resistor (RENDLY) to GND and disables the feedback amplifier for a fixed time after the turn-off of the primary-side MOSFET. This allows the leakage inductance voltage spike to be ignored for flyback voltage sensing. See Applications Information for details. SYNC (Pin 13): External Sync Input. This pin is used to synchronize the internal oscillator with an external clock. The positive edge of the clock causes the oscillator to discharge causing PG to go low (off) and SG high (on). The sync threshold is typically 1.5V. Tie to ground if unused. See Applications Information for details. 42681fa 9 LTC4268-1 PIN FUNCTIONS SFST (Pin 14): Soft Start. This pin, in conjunction with a capacitor (CSFST) to GND, controls the ramp-up of peak primary current through the sense resistor. It is also used to control converter inrush at start-up. The SFST clamps the VCMP voltage and thus limits peak current until soft start is complete. The ramp time is approximately 70ms per μF of capacitance. Leave SFST open if not using the soft-start function. OSC (Pin 15): Oscillator. This pin in conjunction with an external capacitor (COSC) to GND defines the controller oscillator frequency. The frequency is approximately 100kHz • 100/COSC (pF). FB (Pin 16): Feedback Amplifier Input. Feedback is usually sensed via a third winding and enabled during the flyback period. This pin also sinks additional current to compensate for load current variation as set by the RCMP pin. Keep the Thevenin equivalent resistance of the feedback divider at roughly 3k. VCMP (Pin 17): Frequency Compensation Control. VCMP is used for frequency compensation of the switcher control loop. It is the output of the feedback amplifier and the input to the current comparator. Switcher frequency compensation components are normally placed on this pin to GND. The voltage on this pin is proportional to the peak primary switch current. The feedback amplifier output is enabled during the synchronous switch on time. UVLO (Pin 18): Undervoltage Lockout. A resistive divider from VIN to this pin sets an undervoltage lockout based upon VIN level (not VCC). When the UVLO pin is below its threshold, the gate drives are disabled, but the part draws its normal quiescent current from VCC. The VCC undervoltage lockout supersedes this function so VCC must be great enough to start the part. The bias current on this pin has hysteresis such that the bias current is sourced when UVLO threshold is exceeded. This introduces a hysteresis at the pin equivalent to the bias current change times the impedance of the upper divider resistor. The user can control the amount of hysteresis by adjusting the impedance of the divider. Tie the UVLO pin to VCC if you are not using this function. See the Applications Information for details. This pin is used for the UVLO function of the switching regulator. The PD interface section has an UVLO defined by the IEEE 802.3af specification. SENSE–, SENSE+ (Pins 19, 20): Current Sense Inputs. These pins are used to measure primary side switch current through an external sense resistor. Peak primary side current is used in the converter control loop. Make Kelvin connections to the sense resistor RSENSE to reduce noise problems. SENSE– connects to the GND side. At maximum current (VCMP at its maximum voltage) SENSE pins have 100mV threshold. The signal is blanked (ignored) during the minimum turn-on time. CCMP (Pin 21): Load Compensation Capacitive Control. Connect a capacitor from CCMP to GND in order to reduce the effects of parasitic resistances in the feedback sensing path. A 0.1μF ceramic capacitor suffices for most applications. Short this pin to GND in less demanding applications. RCMP (Pin 22): Load Compensation Resistive Control. Connect a resistor from RCMP to GND in order to compensate for parasitic resistances in the feedback sensing path. In less demanding applications, this resistor is not needed and this pin can be left open. See Applications Information for details. 42681fa 10 LTC4268-1 PIN FUNCTIONS PGDLY (Pin 23): Primary Gate Delay Control. Connect an external programming resistor (RPGDLY) to set delay from synchronous gate turn-off to primary gate turn-on. See Applications Information for details. PG (Pin 24): Primary Gate Drive. PG is the gate drive pin for the primary side MOSFET Switch. Large dynamic currents flow during voltage transitions. See the Applications Information for details. NC (Pin 25): No internal connection. VNEG (Pins 26, 27, 28): System Negative rail. Tie to the GND pin to supply power to the flyback controller through the internal power MOSFET. VNEG is high impedance until the input voltage rises above the UVLO turn-on threshold. The output is then connected to VPORTN through a current-limited internal MOSFET switch. Pins 26, 27 and 28 must be electrically tied together. PWRGD (Pin 29): Active High Power Good Output, Open-Collector. Signals to the flyback controller that the LTC4268-1 MOSFET is on and that the flyback controller can start operation. High impedance indicates power is good. PWRGD is referenced to VNEG and is low impedance during inrush and in the event of a thermal overload. PWRGD is clamped to 14V above VNEG. PWRGD (Pin 30): Active Low Power Good Output, OpenDrain. Signals to the DC/DC converter that the LTC4268-1 MOSFET is on and that the converter can start operation. Low impedance indicates power is good. PWRGD is referenced to VPORTN and is high impedance during detection, classification and in the event of a thermal overload. PWRGD h as no internal clamps. NC (Pin 31): No internal connection. VPORTP (Pin 32): Positive power input. Tie to the input port power return through the input diode bridge. GND (Pin 33): Ground. This is the negative rail connection for both signal ground and gate driver grounds. This pin should be connected to VNEG. Careful attention must be paid to layout. See the Applications Information for details. 42681fa 11 LTC4268-1 BLOCK DIAGRAM CLASSIFICATION CURRENT LOAD SHDN 1 2 NC RCLASS 1.237V + 16k 25k VPORTP 32 – NC 31 3 PWRGD 30 4 ILIM_EN CONTROL CIRCUITS 5 VPORTN 1400mA 750mA 300mA INPUT CURRENT LIMIT PWRGD 29 14V + – VNEG 6 VPORTN 28 VNEG 27 26 10 7 VPORTN BOLD LINE INDICATES HIGH CURRENT PATH CLAMPS VCC UVLO 20V 0.7 VNEG VCC + – 15.3V + – FB 1.3 16 – + S R Q Q ERROR AMP VCMP 17 1.237V REFERENCE (VFB) 3V INTERNAL REGULATOR COLLAPSE DETECT UVLO 18 IUVLO TSD CURRENT TRIP SENSE+ RCMPF 50k SET ENABLE CCMP SLOPE COMPENSATION 15 OSC OSCILLATOR 13 11 23 12 SYNC tON LOGIC BLOCK TO FB + – LOAD COMPENSATION PGDLY ENDLY VCC PGATE SGATE GATE DRIVE PG 24 + – 3V VCC GATE DRIVE SG GND 9 33 12 – + – CURRENT COMPARATOR + + – UVLO 1V OVERCURRENT FAULT SENSE– CURRENT SENSE AMP 19 + SFST 14 20 21 RCMP 22 42681 BD – – + 42681fa LTC4268-1 APPLICATIONS INFORMATION OVERVIEW Power over Ethernet (PoE) continues to gain popularity as an increasing number of products are taking advantage of having DC power and high speed data available from a single RJ45 connector. As PoE is becoming established in the marketplace, Powered Device (PD) equipment vendors are running into the 12.95W power limit established by the IEEE 802.3af standard. To solve this problem and expand the application of PoE, the LTC4268-1 breaks the power barrier by allowing custom PoE applications to deliver up to 35W for power hungry PoE applications such as dual band access points, RFID readers and PTZ security cameras. The LTC4268-1 is designed to be a complete solution for PD applications with power requirements up to 35W. The LTC4268-1 interfaces with custom Power Sourcing Equipment (PSE) using a high efficiency flyback topology for maximum power delivery without the need for optoisolator feedback. Off-the-shelf high power PSEs are available today from a variety of vendors for use with the LTC4268-1 to allow quick implementation of a custom system. Alternately, the system vendor can choose to build their own high power PSE. Linear Technology provides complete application information for high power PSE solutions delivering up to 35W for 2-pair systems and as much as 70W when used in 4-pair systems. PSE RJ45 4 5 GND 0.1μF 100V DGND BYP 3.3V VDD AGND DETECT 1/4 LTC4259A-1 CMPD3003 1k 0.47μF 100V Tx 2 3 Rx 6 SMAJ58A 58V 7 8 SPARE PAIR 42681 F01a One of the basic architectural decisions associated with a high power PoE system is whether to deliver power using four conductors (2-pair) or all eight conductors (4-pair). Each method provides advantages and the system vendor needs to decide which method best suits their application. 2-pair power is used today in 802.3af systems (see Figure 1A). One pair of conductors is used to deliver the current and a second pair is used for the return while two conductor pairs are not powered. This architecture offers the simplest implementation method but suffers from higher cable loss than an equivalent 4-pair system. 4-pair power delivers current to the PD via two conductor pairs in parallel (Figure 1B). This lowers the cable resistance but raises the issue of current balance between each conductor pair. Differences in resistance of the transformer, cable and connectors along with differences in diode bridge forward voltage in the PD can cause an imbalance in the currents flowing through each pair. The 4-pair system in Figure 1B solves this problem by using two independent DC/DC converters in the PD. Using this architecture solves the balancing issue and allows the PD to be driven by two independent PSEs, for example an Endpoint PSE and a Midspan PSE. Contact Linear Technology applications support for detailed information on implementing 2-pair and 4-pair PoE systems. RJ45 4 5 PD CAT 5 SPARE PAIR 0.1μF 1 1 Rx DATA PAIR 2 3 Tx DATA PAIR 6 DF1501S SMAJ58A 58V 0.1μF VEE SENSE GATE OUT 10k IRLR3410 + 7 8 DF1501S LTC4268-1 TYP APP VOUT 0.25Ω –54V S1B – Figure 1A. 2-Pair High Power PoE System Diagram 42681fa 13 LTC4268-1 APPLICATIONS INFORMATION The LTC4268-1 is specifically designed to implement the high power PD front end and switching regulator for power-hungry PoE applications that must operate beyond the power limits of IEEE 802.3af. The LTC4268-1 uses a precision, dual current limit that keeps inrush below IEEE 803.2af levels to ensure interoperability with any PSE. After inrush is complete, the LTC4268-1 input current limit switches to the ILIMIT_HIGH level, using an onboard, 750mA power MOSFET. This allows a PD (supplied by a custom PSE) to deliver power above the IEEE 802.3af 12.95W maximum, sending up to 35W to the PD load. The LTC4268-1 uses established IEEE 802.3af detection and PSE RJ45 GND 0.1μF DGND BYP 3.3V VDD AUTO AGND DETECT 1/4 LTC4259A CMPD3003 1k 0.47μF Rx1 VEE SENSE GATE OUT 10k S1B IRLR3410 0.1μF 0.1μF AGND DETECT 1/4 LTC4259A CMPD3003 1k 0.47μF Rx2 VEE SENSE GATE OUT 10k S1B IRLR3410 SMAJ58A 42681 F01b classification methods to maintain compliance and includes an extended programmable Class 5 range for use in custom PoE applications. The LTC4268-1 features both activehigh and active-low power good signaling for simplified interface to the converter. The SHDN pin on the LTC4268-1 can be used to provide a seamless interface for external wall adapters or other auxiliary power options. The ILIM_EN pin provides the option to remove the high current limit, ILIMIT_HIGH. The LTC4268-1 includes an onboard signature resistor, precision UVLO, thermal overload protection and is available in a thermally-enhanced 32-lead 7mm × 4mm DFN package for superior high current performance. PD RJ45 0.1μF Tx1 1 CAT5 1 Rx1 0.1μF DF1501S LTC4268-1 TYP APP SMAJ58A 2 3 2 3 Tx1 6 SMAJ58A 6 0.25Ω –54V – + SMAJ58A ++ –– VOUT GND 4 Tx2 5 7 5 7 Tx2 8 8 4 Rx2 LTC4268-1 TYP APP DF1501S 0.25Ω –54V Figure 1B. 4-Pair High Power PoE Gigabit Ethernet 42681fa 14 LTC4268-1 APPLICATIONS INFORMATION OPERATION Note: Please refer to the simplified application circuit (Figure 2) for voltage naming conventions used in this datasheet. The LTC4268-1 high power PD interface controller and switching regulator has several modes of operation depending on the applied VPORT voltage as shown in Figure 3 and summarized in Table 1. These various modes satisfy the requirements defined in the IEEE 802.3af specification. The input voltage is applied to the VPORTN pin with reference to the VPORTP pin and is always negative. SERIES DIODES The IEEE 802.3af-defined operating modes for a PD reference the input voltage at the RJ45 connector on the PD. In this datasheet port voltage is normally referenced to the pins of the LTC4268-1. Note that the voltage ranges specified in the LTC4268-1 Electrical Specifications are referenced with respect to the IC pins. The PD must be able to handle power received in either polarity. For this reason, it is common to install diode bridges between the RJ45 connector and the LTC4268-1 (Figure 4). The diode bridges introduce an offset that affects the threshold points for each range of operation. The LTC4268-1 meets the IEEE 802.3af-defined operating modes by compensating for the diode drops in the threshold points. For the signature, classification, and the UVLO RJ45 1 TX+ TX– RX+ RX– 16 T1 1 15 2 3 14 11 10 6 9 2 3 6 7 8 VPORTP SPARE+ VCC TO PHY thresholds, the LTC4268-1 extends two diode drops below the IEEE 802.3af specifications. The LTC4268-1 threshold points support the use of either traditional or Schottky diode bridges. DETECTION During detection, the PSE will apply a voltage in the range of –2.8V to –10V on the cable and look for a 25k signature resistor. This identifies the device at the end of the cable as a PD. With the PSE voltage in the detection range, the LTC4268-1 presents an internal 25k resistor between the VPORTP and VPORTN pins. This precision, temperaturecompensated resistor provides the proper characteristics to alert the PSE that a PD is present and requests power to be applied. Table 1. LTC4268-1 Operational Mode as a Function of VPORT Voltage VPORT 0V to –1.4V –1.5V to –10.1V –10.3V to –12.4V –12.5V to UVLO* UVLO* to –57V Inactive 25k Signature Resistor Detection Classification Load Current Ramps Up from 0% to 100% Classification Load Current Active Power Applied to PD Load MODE OF OPERATION *UVLO includes hysteresis. Rising input threshold ≅ –38.9V Falling input threshold ≅ –30.6V • ~ ~ + VPORT VIN + • + VOUT – 4 5 7 8 ~ ~ PD FRONT END + – PG LTC4268-1 GND VPORTN VNEG SWITCHING REGULATOR ISOLATED OUTPUT 42681 F02 SPARE– Figure 2. Simplified Application Circuit with Voltage Naming Conventions 42681fa 15 LTC4268-1 APPLICATIONS INFORMATION The IEEE 802.3af specification requires the PSE to use a ΔV/ΔI measurement technique to keep the DC offset voltage of the diode bridge from affecting the signature resistance measurement. However, the diode resistance appears in series with the signature resistor and must be included in the overall signature resistance of the PD. –10 VPORTN (V) –20 –30 –40 –50 TIME –10 VIN (V) –20 –30 –40 –50 dV =ILIMIT_LOW dt C1 TIME –10 PWRGD (V) –20 –30 –40 –50 PWRGD TRACKS VIN POWER BAD POWER GOOD POWER BAD UVLO OFF UVLO ON = RLOAD C1 UVLO OFF UVLO TURN-ON The LTC4268-1 compensates for the two series diodes in the signature path by offsetting the internal resistance so that a PD built with the LTC4268-1 meets the IEEE 802.3af specification. DETECTION V1 DETECTION V2 CLASSIFICATION TIME UVLO TURN-OFF 20 PWRGD – VIN (V) 10 POWER BAD POWER GOOD POWER BAD TIME ILIMIT_HIGH ILIMIT_LOW PD CURRENT ICLASS CLASSIFICATION DETECTION I2 DETECTION I1 I1 = V1 – 2 DIODE DROPS V2 – 2 DIODE DROPS I2 = 25kΩ 25kΩ TIME LOAD, ILOAD (UP TO ILIMIT_HIGH) ICLASS DEPENDENT ON RCLASS SELECTION ILIMIT_LOW = 300mA, ILIMIT_HIGH = 750mA ILOAD = VIN RLOAD LTC4268-1 IIN PSE VPORT R CLASS VPORTN RCLASS VPORTP PWRGD PWRGD VNEG RLOAD + C1 VIN 42681 F03 Figure 3. VIN Voltage, PWRGD, PWRGD and PD Current as a Function of Port Voltage 42681fa 16 LTC4268-1 APPLICATIONS INFORMATION In some designs that include an auxiliary power option, such as an external wall adapter, it is necessary to control whether or not the PD is detected by a PSE. With the LTC4268-1, the 25k signature resistor can be enabled or disabled with the SHDN pin (Figure 5). Taking the SHDN pin high will reduce the signature resistor to 10k which is an invalid signature per the IEEE 802.3af specifications. This will prevent a PSE from detecting and powering the PD. This invalid signature is present in the PSE probing range of –2.8V to –10V. When the input rises above –10V, the signature resistor reverts to 25k to minimize power dissipation in the LTC4268-1. To disable the signature, tie SHDN to VPORTP. Alternately, the SHDN pin can be driven high with respect to VPORTN. When SHDN is high, all functions are disabled. For normal operation tie SHDN to VPORTN. RJ45 1 TX+ TX– RX+ RX– VPORTP 4 5 SPARE+ BR2 0.1μF 100V LTC4268-1 D3 VPORTN SPARE– 42681 F04 CLASSIFICATION Once the PSE has detected a PD, the PSE may optionally classify the PD. Classification provides a method for more efficient allocation of power by allowing the PSE to identify lower-power PDs and assign the appropriate power level to these devices. For each class, there is an associated load current that the PD asserts onto the line during classification probing. The PSE measures the PD load current in order to assign the proper PD classification. Class 0 is included in the IEEE 802.3af specification to cover PDs that do not support classification. Class 1-3 partition PDs into three distinct power ranges as shown in Table 2. Class 4 was reserved by the IEEE 802.3af committee for future use and has been reassigned as a high power indicator by IEEE 802.3at. The new Class 5 T1 BR1 TO PHY 2 3 POWERED DEVICE (PD) INTERFACE AS DEFINED BY IEEE 802.3af 6 7 8 Figure 4. PD Front End Using Diode Bridges on Main and Spare Inputs LTC4268-1 TO PSE 16k SHDN VPORTP 25k SIGNATURE RESISTOR VPORTN 42681 F05 SIGNATURE DISABLE Figure 5. 25k Signature Resistor with Disable 42681fa 17 LTC4268-1 APPLICATIONS INFORMATION defined here is available for system vendors to implement a unique classification for use in closed systems and is not defined or supported by the IEEE 802.3af. With the extended classification range available in the LTC4268-1, it is possible for system designers to define multiple classes using load currents between 40mA and 75mA. During classification, the PSE presents a fixed voltage between –15.5V and –20.5V to the PD (Figure 6a). With the input voltage in this range, the LTC4268-1 asserts a load current from the VPORTP pin through the RCLASS resistor. The magnitude of the load current is set with the selection of the RCLASS resistor. The resistor value associated with each class is shown in Table 2. Table 2. Summary of IEEE 802.3af Power Classifications and LTC4268-1 RCLASS Resistor Selection MAXIMUM POWER LEVELS AT INPUT OF PD (W) 0.44 to 12.95 0.44 to 3.84 3.84 to 6.49 6.49 to 12.95 NOMINAL CLASSIFICATION LOAD CURRENT (mA) UVLO* ON *UVLO INCLUDES HYSTERESIS RISING INPUT THRESHOLD –38.9V FALLING INPUT THRESHOLD –30.6V CURRENT-LIMITED TURN ON Figure 7. LTC4268-1 Undervoltage Lockout 42681fa 19 LTC4268-1 APPLICATIONS INFORMATION During the inrush event as C1 is being charged, a large amount of power is dissipated in the MOSFET. The LTC4268-1 is designed to accept this load and is thermally protected to avoid damage to the onboard power MOSFET. If a thermal overload does occur, the power MOSFET turns off, allowing the die to cool. Once the die has returned to a safe temperature, the LTC4268-1 automatically switches to ILIMIT_LOW, and load capacitor C1 charging resumes. The LTC4268-1 has the option of disabling the normal operating input current limit, ILIMIT_HIGH, for custom high power PoE applications. To disable the current limit, connect ILIM_EN to VPORTN. To protect the LTC4268-1 from damage when the normal current limit is disabled, a safeguard current limit, ILIMIT_DISA keeps the current below destructive levels, typically 1.4A. Note that continuous operation at or near the safeguard current limit will rapidly overheat the LTC4268-1, engaging the thermal protection circuit. For normal operations, float the ILIM_EN pin. The LTC4268-1 maintains the ILIMIT_LOW inrush current limit for charging the load capacitor regardless of the state of ILIM_EN. The operation of the ILIM_EN pin is summarized in Table 3. Table 3. Current Limit as a Function of ILIM_EN STATE OF ILIM_EN Floating Tied to VPORTN INRUSH CURRENT LIMIT ILIMIT_LOW ILIMIT_LOW OPERATING INPUT CURRENT LIMIT ILIMT_HIGH ILIMIT_DISA POWER GOOD The LTC4268-1 includes complementary power good outputs (Figure 8) to simplify connection to any DC/DC converter. Power Good is asserted at the end of the inrush event when load capacitor C1 is fully charged and the DC/DC converter can safely begin operation. The power good signal stays active during normal operation and is de-asserted at power off when the port drops below the UVLO threshold or in the case of a thermal overload event. For PD designs that use a large load capacitor and also consume a lot of power, it is important to delay activation of the DC/DC converter with the power good signal. If the converter is not disabled during the current-limited turn-on sequence, the DC/DC converter will rob current intended for charging up the load capacitor and create a slow rising input, possibly causing the LTC4268-1 to go into thermal shutdown. LTC4268-1 UVLO THERMAL SD CONTROL CIRCUIT 30 PWRGD INRUSH COMPLETE AND NOT IN THERMAL SHUTDOWN REF VPORTN 5 29 PWRGD 28 VNEG POWER NOT GOOD POWER GOOD VPORTN 6 27 VNEG VPORT < UVLO OFF OR THERMAL SHUTDOWN VPORTN 7 BOLD LINE INDICATES HIGH CURRENT PATH 26 VNEG 42681 F08 Figure 8. LTC4268-1 Power Good Functional and State Diagram 42681fa 20 LTC4268-1 APPLICATIONS INFORMATION The active high PWRGD pin features an internal, open-collector output referenced to VNEG. During inrush, the active high PWRGD pin becomes valid when C1 reaches –4V and pulls low until the load capacitor is fully charged. At that point, PWRGD becomes high impedance, indicating the switching regulator may begin running. The active high PWRGD pin interfaces directly to the UVLO pin of the LTC4268-1 with the aid of an external pull-up resistor to Vcc. The PWRGD pin includes an internal 14V clamp to VNEG. During a power supply ramp down event, PWRGD becomes low impedance when VPORT drops below the 30V PD UVLO turn-off threshold, then goes high impedance when the VPORT voltages fall to within the detection voltage range. Figure 11 shows a typical connection scheme for the active high PWRGD pin. The LTC4268-1 also includes an active low PWRGD pin for system level use. PWRGD is referenced to the VPORTN pin and when active will be near the VPORTN potential. The negative rail (GND) of the internal switching regulator will typically be referenced to VNEG and care must be taken to ensure that the difference in potential of the PWRGD pin does not cause a problem for the switcher. THERMAL PROTECTION The LTC4268-1 includes thermal overload protection in order to provide full device functionality in a miniature package while maintaining safe operating temperatures. At turn-on, before load capacitor C1 has charged up, the instantaneous power dissipated by the LTC4268-1 can be as high as 20W. As the load capacitor charges, the power dissipation in the LTC4268-1 will decrease until it reaches a steady-state value dependent on the DC load current. The LTC4268-1 can also experience device heating after turn-on if the PD experiences a fast input voltage rise. For example, if the PD input voltage steps from –37V to –57V, the instantaneous power dissipated by the LTC4268-1 can be as high as 16W. The LTC4268-1 protects itself from damage by monitoring die temperature. If the die exceeds the overtemperature trip point, the power MOSFET and classification transistors are disabled until the part cools down. Once the die cools below the overtemperature trip point, all functions are enabled automatically. During classification, excessive heating of the LTC4268-1 can occur if the PSE violates the 75ms probing time limit. In addition, the IEEE 802.3af specification requires a PD to withstand application of any voltage from 0V to 57V indefinitely. To protect the LTC4268-1 in these situations, the thermal protection circuitry disables the classification circuit and the input current if the die temperature exceeds the overtemperature trip point. When the die cools down, classification and input current are enabled. Once the LTC4268-1 has charged up the load capacitor and the PD is powered and running, there will be some residual heating due to the DC load current of the PD flowing through the internal MOSFET. In some high current applications, the LTC4268-1 power dissipation may be significant. The LTC4268-1 uses a thermally enhanced DFN package that includes an exposed pad which should be soldered to the GND plane for heatsinking on the printed circuit board. MAXIMUM AMBIENT TEMPERATURE The LTC4268-1 ILIM_EN pin allows the PD designer to disable the normal operating current limit. With the normal current limit disabled, it is possible to pass currents as high as 1.4A through the LTC4268-1. In this mode, significant package heating may occur. Depending on the current, voltage, ambient temperature, and waveform characteristics, the LTC4268-1 may shut down. To avoid 42681fa 21 LTC4268-1 APPLICATIONS INFORMATION nuisance trips of the thermal shutdown, it may be necessary to limit the maximum ambient temperature. Limiting the die temperature to 125°C will keep the LTC4268-1 from hitting thermal shutdown. For DC loads the maximum ambient temperature can be calculated as: TMAX = 125 – θJA • PWR (°C) where TMAX is the maximum ambient operating temperature, θJA is the junction-to-ambient thermal resistance (49°C/W), and PWR is the power dissipation for the LTC4268-1 in Watts (IPD2 • RON). EXTERNAL INTERFACE AND COMPONENT SELECTION Transformer Nodes on an Ethernet network commonly interface to the outside world via an isolation transformer (Figure 9). For powered devices, the isolation transformer must include a center tap on the media (cable) side. Proper termination is required around the transformer to provide correct impedance matching and to avoid radiated and conducted emissions. For high power applications beyond IEEE 802.3af limits, the increased current levels increase the current imbalance in the magnetics. This imbalance RJ45 1 TX+ TX– RX+ RX– 16 T1 1 15 2 3 14 11 10 6 9 2 3 6 7 8 VPORTP BR2 HD01 VIN TO PHY BR1 HD01 reduces the perceived inductance and can interfere with data transmission. Transformers specifically designed for high current applications are required. Transformer vendors such as Bel Fuse, Coilcraft, Halo, Pulse, and Tyco (Table 4) can provide assistance with selection of an appropriate Table 4. Power over Ethernet Transformer Vendors VENDOR Bel Fuse Inc. CONTACT INFORMATION 206 Van Vorst Street Jersey City, NJ 07302 Tel: 201-432-0463 www.belfuse.com 1102 Silver Lake Road Gary, IL 60013 Tel: 847-639-6400 www.coilcraft.com 1861 Landings Drive Mountain View, CA 94043 Tel: 650-903-3800 www.haloelectronics.com 12220 World Trade Drive San Diego, CA 92128 Tel: 858-674-8100 www.pulseeng.com 308 Constitution Drive Menlo Park, CA 94025-1164 Tel: 800-227-7040 www.circuitprotection.com Coilcraft Inc. Halo Electronics Pulse Engineering Tyco Electronics PULSE H2019 SPARE+ 4 5 7 8 + C14 0.1μF 100V D3 SMAJ58A TVS LTC4268-1 C1 SPARE– VPORTN VNEG 42681 F09 Figure 9. PD Front-End Isolation Transformer, Diode Bridges, Capacitors and TVS 42681fa 22 LTC4268-1 APPLICATIONS INFORMATION isolation transformer and proper termination methods. These vendors have transformers specifically designed for use in high power PD applications. IEEE 802.3af allows power wiring in either of two configurations on the TX/RX wires, and power can be applied to the PD via the spare wire pair in the RJ45 connector. The PD is required to accept power in either polarity on both the data and spare inputs; therefore it is common to install diode bridges on both inputs in order to accommodate the different wiring configurations. Figure 9 demonstrates an implementation of the diode bridges to minimize heating. The IEEE 802.3af specification also mandates that the leakage back through the unused bridge be less than 28μA when the PD is powered with 57V. The PD may be configured to handle 2-pair or 4-pair power delivery over the Ethernet cable. In a 2-pair power delivery system, one of the two pairs is delivering power to the PD – either the main pair or the spare pair, but not both. In a 4-pair system, both the main and spare pairs deliver power to the PD simultaneously (see Figure 1). In either case, a diode bridge is needed on the front end to accept power in either polarity. Contact LTC applications for more information about implementing a 4-pair PoE system. The IEEE standard includes an AC impedance requirement in order to implement the AC disconnect function. Capacitor C14 in Figure 9 is used to meet this AC impedance requirement. A 0.1μF capacitor is recommended for this application. The LTC4268-1 has several different modes of operation based on the voltage present between the VPORTN and VPORTP pins. The forward voltage drop of the input diodes in a PD design subtracts from the input voltage and will affect the transition point between modes. The input diode bridge of a PD can consume over 4% of the available power in some applications. Schottky diodes can be used in order to reduce power loss. The LTC4268-1 is designed to work with both standard and Schottky diode bridges while maintaining proper threshold points for IEEE 802.3af compliance. Auxiliary Power Source In some applications, it may be necessary to power the PD from an auxiliary power source such as a wall adapter. The auxiliary power can be injected into the PD at several locations and various trade-offs exist. Figure 10 demonstrates four methods of connecting external power to a PD. Option 1 in Figure 10 inserts power before the LTC4268-1 interface controller. In this configuration, it is necessary for the wall adapter to exceed the LTC4268-1 UVLO turnon requirement. This option provides input current limit for the adapter, provides a valid power good signal and simplifies power priority issues. As long as the adapter applies power to the PD before the PSE, it will take priority and the PSE will not power up the PD because the external power source will corrupt the 25k signature. If the PSE is already powering the PD, the adapter power will be in parallel with the PSE. In this case, priority will be given to the higher supply voltage. If the adapter voltage is higher, the PSE may remove the port voltage since no current will be drawn from the PSE. On the other hand, if the adapter voltage is lower, the PSE will continue to supply power to the PD and the adapter will not be used. Proper operation will occur in either scenario. Option 2 applies power directly to the DC/DC converter. In this configuration the adapter voltage does not need to exceed the LTC4268-1 turn-on UVLO requirement and can be selected based solely on the PD load requirements. It 42681fa 23 LTC4268-1 APPLICATIONS INFORMATION OPTION 1: AUXILIARY POWER INSERTED BEFORE LTC4268-1 RJ45 1 TX+ TX– RX+ RX– TO PHY T1 ~ BR1 + D3 SMAJ58A TVS 2 3 C14 0.1μF 100V + C1 ~ – VIN VPORTP • 42V ≤ VWW ≤ 57V • NO POWER PRIORITY ISSUES • LTC4268-1 CURRENT LIMITS FOR BOTH PoE AND VWW 6 4 5 7 8 SPARE+ ~ BR2 + LTC4268-1 SPARE– ISOLATED WALL VWW TRANSFORMER ~ + – – D8 S1B VPORTN VNEG OPTION 2: AUXILIARY POWER INSERTED AFTER LTC4268-1 WITH SIGNATURE DISABLED RJ45 1 TX + T1 2 3 TX– RX+ RX– TO PHY ~ BR1 + D3 SMAJ58A TVS C14 0.1μF 100V + C1 ~ – VIN 4.7k VPORTP BSS63 100k LTC4268-1 SHDN VPORTN VNEG D10 S1B • VWW ANY VOLTAGE BASED ON PD LOAD • REQUIRES EXTRA DIODE • SEE APPS REGARDING POWER PRIORITY D9 S1B 6 4 5 7 8 SPARE+ ~ BR2 + SPARE– ISOLATED VWW WALL TRANSFORMER ~ + – – OPTION 3: AUXILIARY POWER APPLIED TO LTC4268-1 AND PD LOAD RJ45 1 TX+ TX– RX+ RX– TO PHY T1 ~ BR1 + D3 SMAJ58A TVS 2 3 C14 0.1μF 100V + C1 ~ – VIN VPORTP • 42V ≤ VWW ≤ 57V • NO POWER PRIORITY ISSUES • NO LTC4268-1 CURRENT LIMITS FOR VWW 6 4 5 7 8 SPARE+ ~ BR2 + LTC4268-1 SPARE– ISOLATED WALL VWW TRANSFORMER ~ + – – VPORTN VNEG D10 S1B OPTION 4: AUXILIARY POWER APPLIED TO ISOLATED LOAD RJ45 1 TX+ TX– RX+ RX– TO PHY T1 D3 SMAJ58A TVS C14 0.1μF 100V + ~ BR1 + C1 ISOLATED DC/DC CONVERTER 2 3 ~ – VPORTP PG LTC4268-1 SHDN GND DRIVE LOAD 6 4 5 7 8 SPARE+ ~ BR2 + SPARE– ISOLATED VWW WALL TRANSFORMER • VWW ANY VOLTAGE BASED ON PD LOAD • SEE APPS REGARDING POWER PRIORITY • BEST ISOLATION ~ + – – VPORTN VNEG Figure 10. Interfacing Auxiliary Power Source to the PD 42681fa 24 LTC4268-1 APPLICATIONS INFORMATION is necessary to include diode D9 to prevent the adapter from applying power to the LTC4268-1. Power priority issues require more intervention. If the adapter voltage is below the PSE voltage, then the priority will be given to the PSE power. The PD will draw power from the PSE while the adapter will remain unused. This configuration is acceptable in a typical PoE system. However, if the adapter voltage is higher than the PSE voltage, the PD will draw power from the adapter. In this situation, it is necessary to address the issue of power cycling that may occur if a PSE is present. The PSE will detect the PD and apply power. If the PD is being powered by the adapter, then the PD will not meet the minimum load requirement and the PSE may subsequently remove power. The PSE will again detect the PD and power cycling will start. With an adapter voltage above the PSE voltage, it is necessary to either disable the signature as shown in option 2, or install a minimum load on the output of the LTC4268-1 to prevent power cycling. A 3k, 1W resistor connected between VPORTP and VNEG will present the required minimum load. Option 3 applies power directly to the DC/DC converter bypassing the LTC4268-1 and omitting diode D9. With the diode omitted, the adapter voltage is applied to the LTC4268-1 in addition to the DC/DC converter. For this reason, it is necessary to ensure that the adapter maintain the voltage between 42V and 57V to keep the LTC4268-1 in its normal operating range. The third option has the advantage of corrupting the 25k signature resistance when the external voltage exceeds the PSE voltage and thereby solving the power priority issue. Option 4 bypasses the entire PD interface and injects power at the output of the low voltage power supply. If the adapter output is below the low voltage output there are no power priority issues. However, if the adapter is above the internal supply, then option 4 suffers from the same power priority issues as option 2 and the signature should be disabled or a minimum load should be installed. Shown in option 4 is one method to disable to the signature while maintaining isolation. If employing options 1 through 3, it is necessary to ensure that the end-user cannot access the terminals of the auxiliary power jack on the PD since this would compromise IEEE 802.3af isolation requirements and may violate local safety codes. Using option 4 along with an isolated power supply addresses the isolation issue and it is no longer necessary to protect the end-user from the power jack. The above power cycling scenarios have assumed the PSE is using DC disconnect methods. For a PSE using AC disconnect, a PD with less than minimum load will continue to be powered. Wall adapters have been known to generate voltage spikes outside their expected operating range. Care should be taken to ensure no damage occurs to the LTC4268-1 or any support circuitry from extraneous spikes at the auxiliary power interface. Classification Resistor Selection (RCLASS) The IEEE 802.3af specification allows classifying PDs into four distinct classes with class 4 being reserved for future use (Table 2). The LTC4268-1 supports all IEEE classes and implements an additional Class 5 for use in custom PoE applications. An external resistor connected from RCLASS to VPORTN (Figure 6) sets the value of the load current. The designer should determine which class the PD is to advertise and then select the appropriate value of RCLASS from Table 2. If a unique load current is required, the value of RCLASS can be calculated as: RCLASS = 1.237V/(ILOAD – IIN_CLASS) 42681fa 25 LTC4268-1 APPLICATIONS INFORMATION IIN_CLASS is the LTC4268-1 IC supply current during classification given in the electrical specifications. The RCLASS resistor must be 1% or better to avoid degrading the overall accuracy of the classification circuit. Resistor power dissipation will be 100mW maximum and is transient so heating is typically not a concern. In order to maintain loop stability, the layout should minimize capacitance at the RCLASS node. The classification circuit can be disabled by floating the RCLASS pin. The RCLASS pin should not be shorted to VPORTN as this would force the LTC4268-1 classification circuit to attempt to source very large currents. In this case, the LTC4268-1 will quickly go into thermal shutdown. Power Good Interface The LTC4268-1 provides complimentary power good signals to simplify the DC/DC converter interface. Using the power good signal to delay converter operation until the load capacitor is fully charged is recommended as this will help ensure trouble free start up. The active high PWRGD pin is controlled by an open collector transistor referenced to VNEG while the active low PWRGD pin is controlled by a high voltage, opendrain MOSFET referenced to VPORTN. The PWRGD pin is designed to interface directly to the UVLO pin with the aid of a pull-up resistor to Vcc. An example interface circuit is shown in Figure 11. Port Voltage Lockout PoE applications require the PD interface to turn on below 42V and turn off above 30V. The LTC4268-1 includes an internal port voltage lockout circuit to implement this basic chip on/off control. Additionally, the LTC4268-1 includes an enable/lockout function for the DC/DC converter that is controlled by the UVLO pin and is intended to be driven by PWRGD to ensure proper startup. (Refer to Power Good Interface.) Users have the ability to implement higher turn on voltages if necessary by connecting the UVLO pin to an external resistive divider between VPORTP and VPORTN. The UVLO pin also includes a bias current allowing implementation of hysteresis. When UVLO is below 1.24V, gate drivers are disabled and the converter sits idle. When the pin rises above the lockout threshold a small current is sourced out of the UVLO pin, increasing the pin voltage and thus creating hysteresis. As the pin voltage drops below this threshold, the current is disabled, further dropping the UVLO pin voltage. If not used, the UVLO pin can be disabled by tying to VCC. Shutdown Interface To disable the 25k signature resistor, connect SHDN to the VPORTP pin. Alternately, the SHDN pin can be driven high with respect to VPORTN. Examples of interface circuits that disable the signature and all LTC4268-1 functions are shown in Figure 10, options 2 and 4. Note that the SHDN input resistance is relatively large and the threshold voltage is fairly low. Because of high voltages present on the printed circuit board, leakage currents from the VPORTP pin could inadvertently pull SHDN high. To ensure trouble-free operation, use high voltage layout techniques in the vicinity of SHDN. If unused, connect SHDN directly to VPORTN. Load Capacitor The IEEE 802.3af specification requires that the PD maintain a minimum load capacitance of 5μF It is permissible to . have a much larger load capacitor and the LTC4268-1 can charge very large load capacitors before thermal issues become a problem. However, the load capacitor must not be too large or the PD design may violate IEEE 802.3af requirements. If the load capacitor is too large, there can be a problem with inadvertent power shutdown by the PSE. For example, if the PSE is running at –57V (IEEE 802.3af maximum allowed) and the PD is detected and powered up, the load capacitor will be charged to nearly –57V. If for some reason the PSE voltage is suddenly reduced to 42681fa 26 LTC4268-1 APPLICATIONS INFORMATION –44V (IEEE 802.3af minimum allowed), the input bridge will reverse bias and the PD power will be supplied by the load capacitor. Depending on the size of the load capacitor and the DC load of the PD, the PD will not draw any power from the PSE for a period of time. If this period of time exceeds the IEEE 802.3af 300ms disconnect delay, the PSE will remove power from the PD. For this reason, it is necessary to evaluate the load current and capacitance to ensure that inadvertent shutdown cannot occur. Refer also to Thermal Protection in this data sheet for further discussion on load capacitor selection. MAINTAIN POWER SIGNATURE In an IEEE 802.3af system, the PSE uses the maintain power signature (MPS) to determine if a PD continues to require power. The MPS requires the PD to periodically draw at least 10mA and also have an AC impedance less than 26.25k in parallel with 0.05μF If either the DC current . is less than 10mA or the AC impedance is above 26.25k, the PSE may disconnect power. The DC current must be less than 5mA and the AC impedance must be above 2M to guarantee power will be removed. The PD application circuits shown in this data sheet present the required AC impedance necessary to maintain power. IEEE 802.3at Interoperability In anticipation of the IEEE 802.3at standard release, the LTC4268-1 can be combined with a simple external circuit to be fully interoperable with an IEEE 802.3at-compliant PSE. For more information, please contact Linear Technology’s Application Engineering. ACTIVE-HIGH ENABLE SWITCHING REGULATOR OVERVIEW The LTC4268-1 includes a current mode converter designed specifically for use in an isolated flyback topology employing synchronous rectification. The LTC4268-1 operation is similar to traditional current mode switchers. The major difference is that output voltage feedback is derived via sensing the output voltage through the transformer. This precludes the need of an optoisolator in isolated designs greatly improving dynamic response and reliability. The LTC4268-1 has a unique feedback amplifier that samples a transformer winding voltage during the flyback period and uses that voltage to control output voltage. The internal blocks are similar to many current mode controllers. The differences lie in the feedback amplifier and load compensation circuitry. The logic block also contains circuitry to control the special dynamic requirements of flyback control. For more information on the basics of current mode switcher/controllers and isolated flyback converters see Application Note 19. Feedback Amplifier—Pseudo DC Theory For the following discussion refer to the simplified Flyback Amplifier diagram(Figure 12A). When the primary side MOSFET switch MP turns off, its drain voltage rises above the VPORTP rail. Flyback occurs when the primary MOSFET is off and the synchronous secondary MOSFET is on. During flyback the voltage on nondriven transformer pins is determined by the secondary voltage. The amplitude of this flyback pulse as seen on the third winding is given as: VFLBK = VOUT + ISEC • ESR + RDS(ON) NSF ( ) VPORTP TO PSE VCC LTC4268-1 PWRGD –54V VPORTN UVLO 42681 F11 4k RDS(ON) = on resistance of the synchronous MOSFET MS ISEC = transformer secondary current ESR = impedance of secondary circuit capacitor, winding and traces NSF = transformer effective secondary-to-flyback winding turns ratio (i.e., NS/NFLBK) 100k Figure 11. Power Good Interface Example 42681fa 27 LTC4268-1 APPLICATIONS INFORMATION The flyback voltage is scaled by an external resistive divider R1/R2 and presented at the FB pin. The feedback amplifier compares the voltage to the internal bandgap reference. The feedback amp is actually a transconductance amplifier whose output is connected to VCMP only during a period in the flyback time. An external capacitor on the VCMP pin integrates the net feedback amp current to provide the control voltage to set the current mode trip point. The regulation voltage at the FB pin is nearly equal to the bandgap reference VFB because of the high gain in the overall loop. The relationship between VFLBK and VFB is expressed as: VFLBK = R1+ R2 • VFB R2 VFLBK FLYBACK R1 16 R2 FB 1V VFB 1.237V LTC4268-1 FEEDBACK AMP T1 • VCMP 17 CVC VIN PRIMARY – + + – • SECONDARY + COUT • COLLAPSE DETECT MP MS ISOLATED OUTPUT R ENABLE S Q 42681 F12a Figure 12a. LTC4268-1 Switching Regulator Feedback Amplifier PRIMARY SIDE MOSFET DRAIN VOLTAGE VFLBK 0.8 • VFLBK VIN PG VOLTAGE SG VOLTAGE 42681 F12b tON(MIN) ENABLE DELAY MIN ENABLE FEEDBACK AMPLIFIER ENABLED PG DELAY Figure 12b. LTC4268-1 Switching Regulator Timing Diagram 42681fa 28 LTC4268-1 APPLICATIONS INFORMATION Combining this with the previous VFLBK expression yields an expression for VOUT in terms of the internal reference, programming resistors and secondary resistances: ⎞ ⎛ R1+ R2 VOUT = ⎜ • VFB • NSF ⎟ − ISEC • ESR + RDS(ON) ⎝ R2 ⎠ output voltage. Some time is also required for internal settling of the feedback amplifier circuitry. In order to maintain immunity to these phenomena, a fixed delay is introduced between the switch turn-off command and the enabling of the feedback amplifier. This is termed “enable delay.” In certain cases where the leakage spike is not sufficiently settled by the end of the enable delay period, regulation error may result. See Applications Information for further details. Collapse Detect Once the feedback amplifier is enabled, some mechanism is then required to disable it. This is accomplished by a collapse detect comparator, which compares the flyback voltage (FB) to a fixed reference, nominally 80% of VFB. When the flyback waveform drops below this level, the feedback amplifier is disabled. Minimum Enable Time The feedback amplifier, once enabled, stays on for a fixed minimum time period termed “minimum enable time.” This prevents lockup, especially when the output voltage is abnormally low; e.g., during start-up. The minimum enable time period ensures that the VCMP node is able to “pump up” and increase the current mode trip point to the level where the collapse detect system exhibits proper operation. This time is set internally. Effects of Variable Enable Period The feedback amplifier is enabled during only a portion of the cycle time. This can vary from the fixed minimum enable time described to a maximum of roughly the “off” switch time minus the enable delay time. Certain parameters of feedback amp behavior are directly affected by the variable enable period. These include effective transconductance and VCMP node slew rate. Load Compensation Theory The LTC4268-1 uses the flyback pulse to obtain information about the isolated output voltage. An error ( ) The effect of nonzero secondary output impedance is discussed in further detail; see Load Compensation Theory. The practical aspects of applying this equation for VOUT are found in the Applications Information. Feedback Amplifier Dynamic Theory So far, this has been a pseudo-DC treatment of flyback feedback amplifier operation. But the flyback signal is a pulse, not a DC level. Provision is made to turn on the flyback amplifier only when the flyback pulse is present using the enable signal as shown in the timing diagram (Figure 12b). Minimum Output Switch On Time (tON(MIN)) The LTC4268-1 affects output voltage regulation via flyback pulse action. If the output switch is not turned on, there is no flyback pulse and output voltage information is not available. This causes irregular loop response and startup/latch-up problems. The solution is to require the primary switch to be on for an absolute minimum time per each oscillator cycle. To accomplish this the current limit feedback is blanked each cycle for tON(MIN). If the output load is less than that developed under these conditions, forced continuous operation normally occurs. See Applications Information for further details. Enable Delay Time (ENDLY) The flyback pulse appears when the primary side switch shuts off. However, it takes a finite time until the transformer primary side voltage waveform represents the output voltage. This is partly due to rise time on the primary side MOSFET drain node but, more importantly, is due to transformer leakage inductance. The latter causes a voltage spike on the primary side, not directly related to 42681fa 29 LTC4268-1 APPLICATIONS INFORMATION source is caused by transformer secondary current flow through the synchronous MOSFET RDS(ON) and real life nonzero impedances of the transformer secondary and output capacitor. This was represented previously by the expression “ISEC • (ESR + RDS(ON)).” However, it is generally more useful to convert this expression to effective output impedance. Because the secondary current only flows during the off portion of the duty cycle (DC), the effective output impedance equals the lumped secondary impedance divided by off time DC. Since the off time duty cycle is equal to 1 – DC then: RS(OUT) = where: RS(OUT) = effective supply output impedance DC = duty cycle RDS(ON) and ESR are as defined previously ESR + RDS(ON) 1− DC This impedance error may be judged acceptable in less critical applications, or if the output load current remains relatively constant. In these cases the external FB resistive divider is adjusted to compensate for nominal expected error. In more demanding applications, output impedance error is minimized by the use of the load compensation function. Figure 13 shows the block diagram of the load compensation function. Switch current is converted to a voltage by the external sense resistor, averaged and lowpass filtered by the internal 50k resistor RCMPF and the external capacitor on CCMP. This voltage is impressed across the external RCMP resistor by op amp A1 and transistor Q3 producing a current at the collector of Q3 that is subtracted from the FB node. This effectively increases the voltage required at the top of the R1/R2 feedback divider to achieve equilibrium. The average primary side switch current increases to maintain output voltage regulation as output loading increases. The increase in average current increases RCMP resistor current which affects a corresponding increase in sensed output voltage, compensating for the IR drops. Assuming relatively fixed power supply efficiency, Eff, power balance gives: T1 VFLBK POUT = Eff • PIN VOUT • IOUT = Eff • VIN • IIN Average primary side current is expressed in terms of output current as follow: • R1 FB 16 Q1 Q2 VFB VPORTP • • R2 LOAD COMP I IIN = K1• IOUT where: K1= VOUT VIN • Eff MP + Q3 A1 – RCMPF + 50k SENSE 20 So the effective change in VOUT target is: 22 RCMP 21 CCMP RSENSE ΔVOUT = K1• RSENSE • R1• NSF RCMP 42681 F13 Figure 13. Load Compensation Diagram thus : R ΔVOUT = K1• SENSE • R1• NSF RCMP ΔIOUT 42681fa 30 LTC4268-1 APPLICATIONS INFORMATION where: K1 = dimensionless variable related to VIN, VOUT and efficiency as explained above RSENSE = external sense resistor Nominal output impedance cancellation is obtained by equating this expression with RS(OUT): K1• ESR + RDS(ON) RSENSE • R1• NSF = RCMP 1− DC RSENSE • (1− DC) • R1• NSF ESR + RDS(ON) For instance, if we wanted a 48V to 5V converter at 50% DC then: NDEAL = 5 1− 0.5 1 • = 48 0.5 9.6 Solving for RCMP gives: RCMP = K1• The practical aspects of applying this equation to determine an appropriate value for the RCMP resistor are found in the Applications Information. Transformer Design Transformer design/specification is the most critical part of a successful application of the LTC4268-1. The following sections provide basic information about designing the transformer and potential tradeoffs. If you need help, the LTC Applications group is available to assist in the choice and/or design of the transformer. Turns Ratios The design of the transformer starts with determining duty cycle (DC). DC impacts the current and voltage stress on the power switches, input and output capacitor RMS currents and transformer utilization (size vs power). The ideal turns ratio is: V 1− DC NDEAL = OUT • VIN DC Avoid extreme duty cycles as they, in general, increase current stresses. A reasonable target for duty cycle is 50% at nominal input voltage. In general, better performance is obtained with a lower turns ratio. A DC of 45.5% yields a 1:8 ratio. Note the use of the external feedback resistive divider ratio to set output voltage provides the user additional freedom in selecting a suitable transformer turns ratio. Turns ratios that are the simple ratios of small integers; e.g., 1:1, 2:1, 3:2 help facilitate transformer construction and improve performance. When building a supply with multiple outputs derived through a multiple winding transformer, lower duty cycle can improve cross regulation by keeping the synchronous rectifier on longer, and thus, keep secondary windings coupled longer. For a multiple output transformer, the turns ratio between output windings is critical and affects the accuracy of the voltages. The ratio between two output voltages is set with the formula VOUT2 = VOUT1 • N21 where N21 is the turns ratio between the two windings. Also keep the secondary MOSFET RDS(ON) small to improve cross regulation. The feedback winding usually provides both the feedback voltage and power for the LTC4268-1. Set the turns ratio between the output and feedback winding to provide a rectified voltage that under worst-case conditions is greater than the 11V maximum VCC turn-off voltage. NSF > VOUT 11+ VF where : VF = Diode Forward Voltage For our example: NSF > We will choose 1 3 5 1 = 11+ 0.7 2.34 42681fa 31 LTC4268-1 APPLICATIONS INFORMATION Leakage Inductance Transformer leakage inductance (on either the primary or secondary) causes a spike after the primary side switch turn-off. This is increasingly prominent at higher load currents, where more stored energy is dissipated. Higher flyback voltage may break down the MOSFET switch if it has too low a BVDSS rating. One solution to reducing this spike is to use a snubber circuit to suppress the voltage excursion. However, suppressing the voltage extends the flyback pulse width. If the flyback pulse extends beyond the enable delay time, output voltage regulation is affected. The feedback system has a deliberately limited input range, roughly ±50mV referred to the FB node. This rejects higher voltage leakage spikes because once a leakage spike is several volts in amplitude; a further increase in amplitude has little effect on the feedback system. Therefore, it is advisable to arrange the snubber circuit to clamp at as high a voltage as possible, observing MOSFET breakdown, such that leakage spike duration is as short as possible. Application Note 19 provides a good reference on snubber design. As a rough guide, leakage inductance of several percent (of mutual inductance) or less may require a snubber, but exhibit little to no regulation error due to leakage spike behavior. Inductances from several percent up to perhaps ten percent cause increasing regulation error. Avoid double digit percentage leakage inductances. There is a potential for abrupt loss of control at high load current. This curious condition potentially occurs when the leakage spike becomes such a large portion of the flyback waveform that the processing circuitry is fooled into thinking that the leakage spike itself is the real flyback signal! It then reverts to a potentially stable state whereby the top of the leakage spike is the control point, and the trailing edge of the leakage spike triggers the collapse detect circuitry. This typically reduces the output voltage abruptly to a fraction, roughly one-third to two-thirds of its correct value. Once load current is reduced sufficiently, the system snaps back to normal operation. When using transformers with considerable leakage inductance, exercise this worst-case check for potential bistability: 1. Operate the prototype supply at maximum expected load current. 2. Temporarily short circuit the output. 3. Observe that normal operation is restored. If the output voltage is found to hang up at an abnormally low value, the system has a problem. This is usually evident by simultaneously viewing the primary side MOSFET drain voltage to observe firsthand the leakage spike behavior. A final note—the susceptibility of the system to bistable behavior is somewhat a function of the load current/ voltage characteristics. A load with resistive—i.e., I = V/R behavior—is the most apt to be bistable. Capacitive loads that exhibit I = V2/R behavior are less susceptible. Secondary Leakage Inductance Leakage inductance on the secondary forms an inductive divider on the transformer secondary, reducing the size of the flyback pulse. This increases the output voltage target by a similar percentage. Note that unlike leakage spike behavior; this phenomenon is independent of load. Since the secondary leakage inductance is a constant percentage of mutual inductance (within manufacturing variations), the solution is to adjust the feedback resistive divider ratio to compensate. 42681fa 32 LTC4268-1 APPLICATIONS INFORMATION Winding Resistance Effects Primary or secondary winding resistance acts to reduce overall efficiency (POUT/PIN). Secondary winding resistance increases effective output impedance, degrading load regulation. Load compensation can mitigate this to some extent but a good design keeps parasitic resistances low. Bifilar Winding A bifilar or similar winding is a good way to minimize troublesome leakage inductances. Bifilar windings also improve coupling coefficients and thus improve cross regulation in multiple winding transformers. However, tight coupling usually increases primary-to-secondary capacitance and limits the primary-to-secondary breakdown voltage, so it isn’t always practical. Primary Inductance The transformer primary inductance, LP, is selected based on the peak-to-peak ripple current ratio (X) in the transformer relative to its maximum value. As a general rule, keep X in the range of 20% to 40% (i.e., X = 0.2 to 0.4). Higher values of ripple will increase conduction losses, while lower values will require larger cores. Ripple current and percentage ripple is largest at minimum duty cycle; in other words, at the highest input voltage. LP is calculated from: LP where: fOSC is the oscillator frequency DCMIN is the DC at maximum input voltage XMAX is ripple current ratio at maximum input voltage Using common high power PoE values a 48V (41V < VIN < 57V) to 5V/5.3A Converter with 90% efficiency, POUT= 26.5W and PIN = 29.5W Using X = 0.4 N = 1/8 and fOSC = 200kHz: DCMIN = 1+ LP = 1 = N • VIN(MAX ) VOUT 1 = 41.2% 1 57 1+ • 85 = 260μH (57V • 0.412)2 200kHz • 0.4 • 26.5W Optimization might show that a more efficient solution is obtained at higher peak current but lower inductance and the associated winding series resistance. A simple spreadsheet program is useful for looking at tradeoffs. Transformer Core Selection Once LP is known, the type of transformer is selected. High efficiency converters use ferrite cores to minimize core loss. Actual core loss is independent of core size for a fixed inductance, but decreases as inductance increases. Since increased inductance is accomplished through more turns of wire, copper losses increase. Thus transformer design balances core and copper losses. Remember that increased winding resistance will degrade cross regulation and increase the amount of load compensation required. ( VIN(MAX) • DCMIN )2 = ( VIN(MAX) • DCMIN )2 • Eff = fOSC • XMAX • PIN fOSC • XMAX • POUT 42681fa 33 LTC4268-1 APPLICATIONS INFORMATION The main design goals for core selection are reducing copper losses and preventing saturation. Ferrite core material saturates hard, rapidly reducing inductance when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and, consequently, output voltage ripple. Do not allow the core to saturate! The maximum peak primary current occurs at minimum VIN: IPK = now : DCMAX = 1+ 1 = N • VIN(MIN) VOUT 1 = 49.4% 1 41 1+ • 85 PIN ⎛X⎞ • ⎜ 1+ MIN ⎟ VIN(MIN) • DCMAX ⎝ 2⎠ feedback resistors: ⎛ ⎡ V + I • ESR + R ⎤⎞ DS(ON) ⎦ ⎣ OUT SEC − 1⎟ R1= R2 ⎜ VFB • NSF ⎜ ⎟ ⎝ ⎠ Continuing the example, if ESR + RDS(ON) = 8mΩ, R2 = 3.32k, then: ⎛ 5 + 5.3 • 0.008 ⎞ R1= 3.32k ⎜ − 1⎟ = 37.28k ⎝ 1.237 • 1/ 3 ⎠ choose 37.4k. It is recommended that the Thevenin impedance of the resistive divider (R1||R2) is roughly 3k for bias current cancellation and other reasons. Current Sense Resistor Considerations The external current sense resistor is used to control peak primary switch current, which controls a number of key converter characteristics including maximum power and external component ratings. Use a noninductive current sense resistor (no wire-wound resistors). Mounting the resistor directly above an unbroken ground plane connected with wide and short traces keeps stray resistance and inductance low. The dual sense pins allow for a full Kelvin connection. Make sure that SENSE+ and SENSE– are isolated and connect close to the sense resistor. Peak current occurs at 100mV of sense voltage VSENSE. So the nominal sense resistor is VSENSE/IPK. For example, a peak switch current of 10A requires a nominal sense resistor of 0.010Ω Note that the instantaneous peak power in the sense resistor is 1W, and that it is rated accordingly. The use of parallel resistors can help achieve low resistance, low parasitic inductance and increased power capability. Size RSENSE using worst-case conditions, minimum LP, VSENSE and maximum VIN. Continuing the example, let us ( ) XMIN ( VIN(MIN) • DCMAX )2 = = fOSC • LP • PIN = 0.267 200kHz • 260μH • 29.5W ( 41• 49.4%)2 Using the example numbers leads to: IPK = 29.5W ⎛ 0.267 ⎞ • 1+ = 1.65A ⎝ ⎠ 41• 0.494 ⎜ 2⎟ Multiple Outputs One advantage that the flyback topology offers is that additional output voltages can be obtained simply by adding windings. Designing a transformer for such a situation is beyond the scope of this document. For multiple windings, realize that the flyback winding signal is a combination of activity on all the secondary windings. Thus load regulation is affected by each winding’s load. Take care to minimize cross regulation effects. Setting Feedback Resistive Divider The expression for VOUT developed in the Operation section is rearranged to yield the following expression for the 42681fa 34 LTC4268-1 APPLICATIONS INFORMATION assume that our worst-case conditions yield an IPK of 40% above nominal so IPK = 2.3A. If there is a 10% tolerance on RSENSE and minimum VSENSE = 88mV, then RSENSE • 110% = 88mV/2.3A and nominal RSENSE = 35mΩ. Round to the nearest available lower value, 33mΩ. Selecting the Load Compensation Resistor The expression for RCMP was derived in the Operation section as: R • (1− DC) RCMP = K1• SENSE • R1• NSF ESR + RDS(ON) Continuing the example: ⎛V ⎞ 5 K1= ⎜ OUT ⎟ = = 0.116 ⎝ V • Eff ⎠ 48 • 90% IN 300 200 fOSC (kHz) 100 50 30 100 COSC (pF) 200 42681 F02 Figure 14. fOSC vs OSC Capacitor Values DC= 1+ 1 = N•VIN(NOM) VOUT 1 = 45.5% 1 48 1+ • 85 2. Temporarily ground the CCMP pin to disable the load compensation function. Measure output voltage while sweeping output current over the expected range. Approximate the voltage variation as a straight line. ΔVOUT/ΔIOUT = RS(OUT) . 3. Calculate a value for the K1 constant based on VIN, VOUT and the measured efficiency. 4. Compute: RCMP = K1• RSENSE • R1• NSF RS(OUT) If ESR + RDS(ON) = 8mΩ RCMP = 0.116 • = 3.25k 33mΩ • (1− 0.455) 1 • 37.4kΩ • 8mΩ 3 This value for RCMP is a good starting point, but empirical methods are required for producing the best results. This is because several of the required input variables are difficult to estimate precisely. For instance, the ESR term above includes that of the transformer secondary, but its effective ESR value depends on high frequency behavior, not simply DC winding resistance. Similarly, K1 appears as a simple ratio of VIN to VOUT times efficiency, but theoretically estimating efficiency is not a simple calculation. The suggested empirical method is as follows: 1. Build a prototype of the desired supply including the actual secondary components. 5. Verify this result by connecting a resistor of this value from the RCMP pin to ground. 6. Disconnect the ground short to CCMP and connect a 0.1μF filter capacitor to ground. Measure the output impedance RS(OUT) = ΔVOUT/ΔIOUT with the new compensation in place. RS(OUT) should have decreased significantly. Fine tuning is accomplished experimentally by slightly altering RCMP. A revised estimate for RCMP is: ⎛ RS(OUT)CMP ⎞ R′ = RCMP • ⎜ 1+ ⎟ CMP RS(OUT) ⎠ ⎝ 42681fa 35 LTC4268-1 APPLICATIONS INFORMATION where RCMP is the new value for the load compensation ′ resistor. RS(OUT)CMP is the output impedance with RCMP in place and RS(OUT) is the output impedance with no load compensation (from step 2). Setting Frequency The switching frequency of the LTC4268-1 is set by an external capacitor connected between the OSC pin and ground. Recommended values are between 200pF and 33pF yielding switching frequencies between 50kHz and , 250kHz. Figure 14 shows the nominal relationship between external capacitance and switching frequency. Place the capacitor as close as possible to the IC and minimize OSC trace length and area to minimize stray capacitance and potential noise pickup. You can synchronize the oscillator frequency to an external frequency. This is done with a signal on the SYNC pin. Set the LTC4268-1 frequency 10% slower than the desired external frequency using the OSC pin capacitor, then use a pulse on the SYNC pin of amplitude greater than 2V and with the desired frequency. The rising edge of the SYNC signal initiates an OSC capacitor discharge forcing primary MOSFET off (PG voltage goes low). If the oscillator frequency is much different from the sync frequency, problems may occur with slope compensation and system stability. Keep the sync pulse width greater than 500ns. Selecting Timing Resistors There are three internal “one-shot” times that are programmed by external application resistors: minimum on time, enable delay time and primary MOSFET turn-on delay. These are all part of the isolated flyback control technique, and their functions are previously outlined in the Theory of Operation section. The following information should help in selecting and/or optimizing these timing values. Minimum Output Switch On Time (tON(MIN)) Minimum on time is the programmable period during which current limit is blanked (ignored) after the turn on of the primary side switch. This improves regulator performance by eliminating false tripping on the leading edge spike in the switch, especially at light loads. This spike is due to both the gate/source charging current and the discharge of drain capacitance. The isolated flyback sensing requires a pulse to sense the output. Minimum on time ensures that the output switch is always on a minimum time and that there is always a signal to close the loop. The LTC4268-1 does not employ cycle skipping at light loads. Therefore, minimum on time along with synchronous rectification sets the switch over to forced continuous mode operation. The tON(MIN) resistor is set with the following equation R tON(MIN) (kΩ ) = tON(MIN) (ns) − 104 1.063 Keep RtON(MIN) greater than 70k. A good starting value is 160k. Enable Delay Time (ENDLY) Enable delay time provides a programmable delay between turn-off of the primary gate drive node and the subsequent enabling of the feedback amplifier. As discussed earlier, this delay allows the feedback amplifier to ignore the leakage inductance voltage spike on the primary side. The worst-case leakage spike pulse width is at maximum load conditions. So set the enable delay time at these conditions. While the typical applications for this part use forced continuous operation, it is conceivable that a secondary side controller might cause discontinuous operation at light loads. Under such conditions the amount of energy stored in the transformer is small. The flyback waveform becomes “lazy” and some time elapses before it indicates 42681fa 36 LTC4268-1 APPLICATIONS INFORMATION the actual secondary output voltage. The enable delay time should be made long enough to ignore the “irrelevant” portion of the flyback waveform at light loads. Even though the LTC4268-1 has a robust gate drive, the gate transition time slows with very large MOSFETs. Increase delay time as required when using such MOSFETs. The enable delay resistor is set with the following equation: RENDLY (kΩ ) = tENDLY (ns) − 30 2.616 spike in the transformer. This spike will cause additional component stress and a loss in regulator efficiency. The primary gate delay resistor is set with the following equation: RPGDLY (kΩ ) = tPGDLY (ns ) + 47 9.01 A good starting point is 27k. Soft Start Function The LTC4268-1 contains an optional soft-start function that is enabled by connecting an external capacitor between the SFST pin and ground. Internal circuitry prevents the control voltage at the VCMP pin from exceeding that on the SFST pin. There is an initial pull-up circuit to quickly bring the SFST voltage to approximately 0.8V. From there it charges to approximately 2.8V with a 20μA current source. The SFST node is discharged to 0.8V when a fault occurs. A fault occurs when VCC is too low (undervoltage lockout), current sense voltage is greater than 200mV or the IC’s thermal (over temperature) shutdown is tripped. When SFST discharges, the VCMP node voltage is also pulled low to below the minimum current voltage. Once discharged and the fault removed, the SFST charges up again. In this manner, switch currents are reduced and the stresses in the converter are reduced during fault conditions. The time it takes to fully charge soft-start is: t ss = CSFST • 1.4V = 70kΩ • CSFST ( μF ) 20μA Keep RENDLY greater than 40k. A good starting point is 56k. Primary Gate Delay Time (PGDLY) Primary gate delay is the programmable time from the turn-off of the synchronous MOSFET to the turn-on of the primary side MOSFET. Correct setting eliminates overlap between the primary side switch and secondary side synchronous switch(es) and the subsequent current VIN RTR VIN CTR VCC LTC4268-1 GND PG • • IVCC + • VON THRESHOLD VVCC IVCC 0 VPG 42681 F15 Converter Start-Up The standard topology for the LTC4268-1 utilizes a third transformer winding on the primary side that provides both feedback information and local VCC power for the LTC4268-1 (see Figure 15). This power “bootstrapping” improves converter efficiency but is not inherently selfstarting. Start-up is affected with an external “trickle charge” resistor and the LTC4268-1’s internal VCC undervoltage lockout circuit. The VCC undervoltage lockout has wide hysteresis to facilitate start-up. 42681fa Figure 15. Typical Power Bootstrapping 37 LTC4268-1 APPLICATIONS INFORMATION VCMP 17 CVCMP2 RVCMP CVCMP 42681 F16 Figure 16. VCMP Compensation Network Make CTR large enough to avoid the relaxation oscillatory behavior described above. This is complicated to determine theoretically as it depends on the particulars of the secondary circuit and load behavior. Empirical testing is recommended. Note that the use of the optional soft-start function lengthens the power-up timing and requires a correspondingly larger value for CTR. The LTC4268-1 has an internal clamp on VCC of approximately 20V. This provides some protection for the part in the event that the switcher is off (UVLO low) and the VCC node is pulled high. If RTR is sized correctly the part should never attain this clamp voltage. Control Loop Compensation Loop frequency compensation is performed by connecting a capacitor network from the output of the feedback amplifier (VCMP pin) to ground as shown in Figure 16. Because of the sampling behavior of the feedback amplifier, compensation is different from traditional current mode controllers. Normally only CVCMP is required. RVCMP can be used to add a “zero” but the phase margin improvement traditionally offered by this extra resistor is usually already accomplished by the nonzero secondary circuit impedance. CVCMP2 can be used to add an additional high frequency pole and is usually sized at 0.1 times CVCMP. In further contrast to traditional current mode switchers, VCMP pin ripple is generally not an issue with the LTC4268-1. The dynamic nature of the clamped feedback amplifier forms an effective track/hold type response, whereby the VCMP voltage changes during the flyback pulse, but is then “held” during the subsequent “switch on” portion of the next cycle. This action naturally holds the VCMP voltage stable during the current comparator sense action (current mode switching). Application Note 19 provides a method for empirically tweaking frequency compensation. Basically it involves introducing a load current step and monitoring the response. In operation, the “trickle charge” resistor RTR is connected to VIN and supplies a small current, typically on the order of 1mA to charge CTR. Initially the LTC4268-1 is off and draws only its start-up current. When CTR reaches the VCC turn-on threshold voltage the LTC4268-1 turns on abruptly and draws its normal supply current. Switching action commences and the converter begins to deliver power to the output. Initially the output voltage is low and the flyback voltage is also low, so CTR supplies most of the LTC4268-1 current (only a fraction comes from RTR.) VCC voltage continues to drop until after some time, typically tens of milliseconds, the output voltage approaches its desired value. The flyback winding then provides the LTC4268-1 supply current and the VCC voltage stabilizes. If CTR is undersized, VCC reaches the VCC turn-off threshold before stabilization and the LTC4268-1 turns off. The VCC node then begins to charge back up via RTR to the turn-on threshold, where the part again turns on. Depending upon the circuit, this may result in either several on-off cycles before proper operation is reached, or permanent relaxation oscillation at the VCC node. RTR is selected to yield a worst-case minimum charging current greater than the maximum rated LTC4268-1 start-up current, and a worst-case maximum charging current less than the minimum rated LTC4268-1 supply current. R TR(MAX ) < and R TR(MIN) > VIN(MAX ) − VCC(ON _ MIN) ICC(MIN) VIN(MIN) − VCC(ON _ MAX ) ICC(ST _ MAX ) 42681fa 38 LTC4268-1 APPLICATIONS INFORMATION Slope Compensation The LTC4268-1 incorporates current slope compensation. Slope compensation is required to ensure current loop stability when the DC is greater than 50%. In some switching regulators, slope compensation reduces the maximum peak current at higher duty cycles. The LTC4268-1 eliminates this problem by having circuitry that compensates for the slope compensation so that maximum current sense voltage is constant across all duty cycles. Minimum Load Considerations At light loads, the LTC4268-1 derived regulator goes into forced continuous conduction mode. The primary side switch always turns on for a short time as set by the tON(MIN) resistor. If this produces more power than the load requires, power will flow back into the primary during the “off” period when the synchronization switch is on. This does not produce any inherently adverse problems, although light load efficiency is reduced. Maximum Load Considerations The current mode control uses the VCMP node voltage and amplified sense resistor voltage as inputs to the current comparator. When the amplified sense voltage exceeds the VCMP node voltage, the primary side switch is turned off. In normal use, the peak switch current increases while FB is below the internal reference. This continues until VCMP reaches its 2.56V clamp. At clamp, the primary side MOSFET will turn off at the rated 100mV VSENSE level. This repeats on the next cycle. It is possible for the peak primary switch currents as referred across RSENSE to exceed the max 100mV rating because of the minimum switch on time blanking. If the voltage on VSENSE exceeds 205mV after the minimum turn-on time, the SFST capacitor is discharged, causing the discharge of the VCMP capacitor. This then reduces the peak current on the next cycle and will reduce overall stress in the primary switch. Short-Circuit Conditions Loss of current limit is possible under certain conditions such as an output short circuit. If the duty cycle exhibited by the minimum on time is greater than the ratio of secondary winding voltage (referred-to-primary) divided by input voltage, then peak current is not controlled at the nominal value. It ratchets up cycle-by-cycle to some higher level. Expressed mathematically, the requirement to maintain short-circuit control is DCMIN = tON(MIN) • fOSC < where: tON(MIN) is the primary side switch minimum on time ISC is the short-circuit output current NSP is the secondary-to-primary turns ratio (NSEC/ NPRI) (Other variables as previously defined) Trouble is typically encountered only in applications with a relatively high product of input voltage times secondary to primary turns ratio and/or a relatively long minimum switch on time. Additionally, several real world effects such as transformer leakage inductance, AC winding losses, and output switch voltage drop combine to make this simple theoretical calculation a conservative estimate. Prudent design evaluates the switcher for short-circuit protection and adds any additional circuitry to prevent destruction for these losses. Output Voltage Error Sources The LTC4268-1’s feedback sensing introduces additional minor sources of errors. The following is a summary list. • The internal bandgap voltage reference sets the reference voltage for the feedback amplifier. The specifications detail its variation. ISC • RSEC + RDS(ON) VIN • NSP ( ) 42681fa 39 LTC4268-1 APPLICATIONS INFORMATION VGS a MILLER EFFECT b 42681 F17 For the primary-side power MOSFET, the peak current is: IPK(PRI) = PIN VIN(MIN) • DCMAX ⎛X⎞ • ⎜ 1+ MIN ⎟ ⎝ 2⎠ QA QB GATE CHARGE (QG) Figure 17. Gate Charge Curve • The external feedback resistive divider ratio directly affects regulated voltage. Use 1% components. • Leakage inductance on the transformer secondary reduces the effective secondary-to-feedback winding turns ratio (NS/NF) from its ideal value. This increases the output voltage target by a similar percentage. Since secondary leakage inductance is constant from part to part (within a tolerance) adjust the feedback resistor ratio to compensate. • The transformer secondary current flows through the impedances of the winding resistance, synchronous MOSFET RDS(ON) and output capacitor ESR. The DC equivalent current for these errors is higher than the load current because conduction occurs only during the converter’s “off” time. So divide the load current by (1 – DC). If the output load current is relatively constant, the feedback resistive divider is used to compensate for these losses. Otherwise, use the LTC4268-1 load compensation circuitry. (See Load Compensation.) If multiple output windings are used, the flyback winding will have a signal that represents an amalgamation of all these windings impedances. Take care that you examine worst-case loading conditions when tweaking the voltages. Power MOSFET Selection The power MOSFETs are selected primarily on the criteria of “on” resistance RDS(ON), input capacitance, drain-to-source breakdown voltage (BVDSS), maximum gate voltage (VGS) and maximum drain current (ID(MAX)). where XMIN is peak-to-peak current ratio as defined earlier. For each secondary-side power MOSFET, the peak current is: IPK(SEC) = IOUT 1− DCMAX ⎛X⎞ • ⎜ 1+ MIN ⎟ ⎝ 2⎠ Select a primary-side power MOSFET with a BVDSS greater than: BVDSS ≥ IPK VOUT(MAX ) LLKG + VIN(MAX ) + CP NSP where NSP reflects the turns ratio of that secondary-to primary winding. LLKG is the primary-side leakage inductance and CP is the primary-side capacitance (mostly from the drain capacitance (COSS) of the primary-side power MOSFET). A snubber may be added to reduce the leakage inductance as discussed. For each secondary-side power MOSFET, the BVDSS should be greater than: BVDSS ≥ VOUT + VIN(MAX) • NSP Choose the primary side MOSFET RDS(ON) at the nominal gate drive voltage (7.5V). The secondary side MOSFET gate drive voltage depends on the gate drive method. Primary side power MOSFET RMS current is given by: IRMS(PRI) = PIN VIN(MIN) DCMAX 42681fa 40 LTC4268-1 APPLICATIONS INFORMATION For each secondary-side power MOSFET RMS current is given by: IRMS(SEC) = IOUT 1− DCMAX (1 + δ) is generally given for a MOSFET in the form of a normalized RDS(ON)vs temperature curve. If you don’t have a curve, use δ = 0.005/°C • ΔT for low voltage MOSFETs. The secondary-side power MOSFETs typically operate at substantially lower VDS, so you can neglect transition losses. The dissipation is calculated using: PDIS(SEC) = IRMS(SEC)2 • RDS(ON)(1 + δ) With power dissipation known, the MOSFETs’ junction temperatures are obtained from the equation: TJ = TA + PDIS • θJA where TA is the ambient temperature and θJA is the MOSFET junction to ambient thermal resistance. Once you have TJ iterate your calculations recomputing δ and power dissipations until convergence. Gate Drive Node Consideration The PG and SG gate drivers are strong drives to minimize gate drive rise and fall times. This improves efficiency but the high frequency components of these signals can cause problems. Keep the traces short and wide to reduce parasitic inductance. The parasitic inductance creates an LC tank with the MOSFET gate capacitance. In less than ideal layouts, a series resistance of 5Ω or more may help to dampen the ringing at the expense of slightly slower rise and fall times and poorer efficiency. The LTC4268-1 gate drives will clamp the max gate voltage to roughly 7.5V, so you can safely use MOSFETs with maximum VGS of 10V and larger. Synchronous Gate Drive There are several different ways to drive the synchronous gate MOSFET. Full converter isolation requires the synchronous gate drive to be isolated. This is usually accomplished by way of a pulse transformer. Usually the pulse driver is used to drive a buffer on the secondary as shown in the application on the front page of this data sheet. Calculate MOSFET power dissipation next. Because the primary-side power MOSFET operates at high VDS, a transition power loss term is included for accuracy. CMILLER is the most critical parameter in determining the transition loss, but is not directly specified on the data sheets. CMILLER is calculated from the gate charge curve included on most MOSFET data sheets (Figure 17). The flat portion of the curve is the result of the Miller (gate to-drain) capacitance as the drain voltage drops. The Miller capacitance is computed as: CMILLER = QB − Q A VDS The curve is done for a given VDS. The Miller capacitance for different VDS voltages are estimated by multiplying the computed CMILLER by the ratio of the application VDS to the curve specified VDS. With CMILLER determined, calculate the primary-side power MOSFET power dissipation: PD(PRI) = IRMS(PRI)2 • RDS(ON) (1+ δ ) + VIN(MAX ) • where: RDR is the gate driver resistance (≈10Ω) VTH is the MOSFET gate threshold voltage fOSC is the operating frequency VGATE(MAX) = 7.5V for this part PIN(MAX ) DCMIN • RDR • CMILLER •f VGATE(MAX ) − VTH OSC 42681fa 41 LTC4268-1 APPLICATIONS INFORMATION L1 0.1μH PRIMARY CURRENT IPRI FROM SECONDARY WINDING VOUT + C1 47μF 3 + COUT 470μF COUT2 1μF 42681 F19 RLOAD Figure 19. SECONDARY CURRENT IPRI N ΔVCOUT OUTPUT VOLTAGE RIPPLE WAVEFORM RINGING DUE TO ESL ΔVESR 42681 F18 Figure 18. Typical Flyback Converter Waveforms However, other schemes are possible. There are gate drivers and secondary side synchronous controllers available that provide the buffer function as well as additional features. Capacitor Selection In a flyback converter, the input and output current flows in pulses, placing severe demands on the input and output filter capacitors. The input and output filter capacitors are selected based on RMS current ratings and ripple voltage. Select an input capacitor with a ripple current rating greater than: IRMS(PRI) = PIN VIN(MIN) 1− DCMAX DCMAX Keep input capacitor series resistance (ESR) and inductance (ESL) small, as they affect electromagnetic interference suppression. In some instances, high ESR can also produce stability problems because flyback converters exhibit a negative input resistance characteristic. Refer to Application Note 19 for more information. The output capacitor is sized to handle the ripple current and to ensure acceptable output voltage ripple. The output capacitor should have an RMS current rating greater than: IRMS(SEC) = IOUT DCMAX 1− DCMAX 49.4% = 5.24A 1− 49.4% Continuing the example: IRMS(SEC) = 5.3A This is calculated for each output in a multiple winding application. ESR and ESL along with bulk capacitance directly affect the output voltage ripple. The waveforms for a typical flyback converter are illustrated in Figure 18. The maximum acceptable ripple voltage (expressed as a percentage of the output voltage) is used to establish a starting point for the capacitor values. For the purpose of simplicity we will choose 2% for the maximum output Continuing the example: IRMS(PRI) = 29.5W 41V 1− 49.4% = 0.728 A 49.4% 42681fa 42 LTC4268-1 APPLICATIONS INFORMATION ripple, divided equally between the ESR step and the charging/discharging ΔV. This percentage ripple changes, depending on the requirements of the application. You can modify the equations below. For a 1% contribution to the total ripple voltage, the ESR of the output capacitor is determined by: ESRCOUT ≤ 1% • VOUT • (1− DCMAX ) IOUT The design of the filter is beyond the scope of this data sheet. However, as a starting point, use these general guidelines. Start with a COUT 1/4 the size of the nonfilter solution. Make C1 1/4 of COUT to make the second filter pole independent of COUT. C1 may be best implemented with multiple ceramic capacitors. Make L1 smaller than the output inductance of the transformer. In general, a 0.1μH filter inductor is sufficient. Add a small ceramic capacitor (COUT2) for high frequency noise on VOUT. For those interested in more details refer to “Second-Stage LC Filter Design,” Ridley, Switching Power Magazine, July 2000 p8-10. Circuit simulation is a way to optimize output capacitance and filters, just make sure to include the component parasitic. LTC SwitcherCADTM is a terrific free circuit simulation tool that is available at www.linear.com. Final optimization of output ripple must be done on a dedicated PC board. Parasitic inductance due to poor layout can significantly impact ripple. Refer to the PC Board Layout section for more details. ELECTRO STATIC DISCHARGE AND SURGE PROTECTION The LTC4268-1 is specified to operate with an absolute maximum voltage of –90V and is designed to tolerate brief over-voltage events. However, the pins that interface to the outside world (primarily VPORTN and VPORTP) can routinely see peak voltages in excess of 10kV. To protect the LTC4268-1, it is highly recommended that the SMAJ58A unidirectional 58V transient voltage suppressor be installed between the diode bridge and the LTC4268-1 (D3 in Figure 4). The other 1% is due to the bulk C component, so use: COUT ≥ IOUT 1% • VOUT • fOSC In many applications the output capacitor is created from multiple capacitors to achieve desired voltage ripple, reliability and cost goals. For example, a low ESR ceramic capacitor can minimize the ESR step, while an electrolytic capacitor satisfies the required bulk C. Continuing our example, the output capacitor needs: ESRCOUT ≤ 1% • 5V • (1− 49.4%) = 4mΩ 5.3A 5.3A = 600μF COUT ≥ 1% • 5 • 200kHz These electrical characteristics require paralleling several low ESR capacitors possibly of mixed type. Most capacitor ripple current ratings are based on 2000 hour life. This makes it advisable to derate the capacitor or to choose a capacitor rated at a higher temperature than required. One way to reduce cost and improve output ripple is to use a simple LC filter. Figure 19 shows an example of the filter. 42681fa 43 LTC4268-1 APPLICATIONS INFORMATION ISOLATION The 802.3 standard requires Ethernet ports to be electrically isolated from all other conductors that are user accessible. This includes the metal chassis, other connectors and any auxiliary power connection. For PDs, there are two common methods to meet the isolation requirement. If there will be any user accessible connection to the PD, then an isolated DC/DC converter is necessary to meet the isolation requirements. If user connections can be avoided, then it is possible to meet the safety requirement by completely enclosing the PD in an insulated housing. In all PD applications, there should be no user accessible electrical connections to the LTC4268-1 or support circuitry other than the RJ-45 port. LAYOUT CONSIDERATIONS FOR THE LTC4268-1 The LTC4268-1’s PD front end is relatively immune to layout problems. Excessive parasitic capacitance on the RCLASS pin should be avoided. Include a PCB heat sink to which the exposed pad on the bottom of the package can be soldered. This heatsink should be electrically connected to GND. For optimum thermal performance, make the heat sink as large as possible. Voltages in a PD can be as large as –57V for PoE applications, so high voltage layout techniques should be employed. The SHDN pin should be separated from other high voltage pins, like VPORTP, VOUT, to avoid the possibility of leakage shutting down the LTC4268-1. If not used, tie SHDN to VPORTN. The load capacitor connected between VPORTP and VOUT of the LTC4268-1 can store significant energy when fully charged. The design of a PD must ensure that this energy is not inadvertently dissipated in the LTC4268-1. The polarity-protection diodes prevent an accidental short on the cable from causing damage. However if, VPORTN is shorted to VPORTP inside the PD while capacitor C1 is charged, current will flow through the parasitic body diode of the internal MOSFET and may cause permanent damage to the LTC4268-1. In order to minimize switching noise and improve output load regulation, connect the GND pin of the LTC4268-1 directly to the ground terminal of the VCC decoupling capacitor, the bottom terminal of the current sense resistor and the ground terminal of the input capacitor, using a ground plane with multiple vias. Place the VCC capacitor immediately adjacent to the VCC and GND pins on the IC package. This capacitor carries high di/dt MOSFET gate drive currents. Use a low ESR ceramic capacitor. Take care in PCB layout to keep the traces that conduct high switching currents short, wide and with minimal overall loop area. These are typically the traces associated with the switches. This reduces the parasitic inductance and also minimizes magnetic field radiation. Figure 20 outlines the critical paths. Keep electric field radiation low by minimizing the length and area of traces (keep stray capacitances low). The drain of the primary side MOSFET is the worst offender in this category. Always use a ground plane under the switcher circuitry to prevent coupling between PCB planes. Check that the maximum BVDSS ratings of the MOSFETs are not exceeded due to inductive ringing. This is done by viewing the MOSFET node voltages with an oscilloscope. If it is breaking down either choose a higher voltage device, add a snubber or specify an avalanche-rated MOSFET. Place the small-signal components away from high frequency switching nodes. This allows the use of a pseudo-Kelvin connection for the signal ground, where high di/dt gate driver currents flow out of the IC ground pin in one direction (to the bottom plate of the VCC decoupling capacitor) and small-signal currents flow in the other direction. Keep the trace from the feedback divider tap to the FB pin short to preclude inadvertent pickup. For applications with multiple switching power converters connected to the same input supply, make sure that the input filter capacitor for the LTC4268-1 is not shared with other converters. AC input current from another converter could cause substantial input voltage ripple and this could interfere with the LTC4268-1 operation. A few inches of PC trace or wire (L ≅100nH) between the CIN of the LTC4268-1 and the actual source VIN is sufficient to prevent current sharing problems. 42681fa 44 LTC4268-1 APPLICATIONS INFORMATION T1 VCC CVCC VCC PG MP GATE TURN-OFF RSENSE OUT GATE TURN-ON VIN • • + CVIN • + VCC COUT + VCC SG T2 CR Q4 GATE TURN-ON MS • • Q3 GATE TURN-OFF 42681 F20 Figure 20. Layout Critical High Current Paths 42681fa 45 LTC4268-1 TYPICAL APPLICATION 46 30W High Efficiency Triple Output PD Supply (Order Demo Circuit DC1080A) T1 PA1558NL L1 0.33μH C4 1500pF • L2 4.7μH C8 0.1μF 100V D1 SMAJ58A R2 10Ω D11 BAS21 R10 91Ω + • C5 47μF Q1 Si4470EY R3 10Ω 1/4W + C6 100μF 5V 2.4A VPORTP + C1A 12μF 100V R9 20k 1/4W C1B 2.2μF 100V • –54V IN FROM HIGH POWER PSE J1 D3 100k D5 Q5 FMMT723 B2100X8 R14 4.7k VPORTP PWRGD PWRGD UVLO ILIM_EN VCC FB PG SENSE+ D4 + C18 22μF 16V C19 0.1μF C11 220pF + • Q2 Si4488DY R8 10Ω 1/4W 1 TX+ T3 ETH1–230LD 16 1 C10 22μF ×2 11.8V 0.27A 15 2 2 TX– 3 RX+ 14 11 3 6 R6 75Ω C15 0.01μF 200V TO PHY R13 29.4k 1% C7 R20 3.01k 1000pF 100V 1% Q3 Si4488DY L3 0.33μH 10 7 6 D7 D8 RX– C44 0.001μF D2 2kV + • Q4 Si4362DY RSENSE 0.015Ω 1/8W 1% SENSE– SG Q7 Q6 FMMT718 FMMT618 R13 B0540W R15 47Ω C24 1μF C28 2200pF R17 330Ω C27 0.1μF R22 15Ω 9 8 XFMR C16 0.01μF 200V R7 75Ω C21 47μF ×2 + C22 100μF 3.3V 4A 4 D6 D9 LTC4268-1 SHDN RCLASS VPORTN VPORTN VPORTN VNEG VNEG VNEG PGDLY tON R21 20k RCLASS RPGDLY 15k S2B RtON 100k SYNC RCMP SPARE+ 5 R5 75Ω R18 100k R4 75Ω 7 8 SPARE– C14 0.01μF 200V C13 0.01μF 200V RJ45 J3 VPORTN ENDLY RCMP 2.1k OSC SFST VCMP CCMP GND RENDLY COSC CSFST CCMP 150k 33pF 0.033μF 0.1μF R27 10k C33 3300pF C26 680pF T2 PA0184 • • D14 BAT54 R28 10k 24V 30W AUX POWER IN 0.1μF 100V 42681 TA02 C23 4700pF 250VAC 42681fa LTC4268-1 PACKAGE DESCRIPTION DKD Package 32-Lead Plastic DFN (7mm × 4mm) (Reference LTC DWG # 05-08-1734 Rev Ø) 0.70 ± 0.05 4.50 ± 0.05 3.10 ± 0.05 2.65 ±0.05 6.43 ±0.05 PACKAGE OUTLINE 0.40 BSC 6.00 REF RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.23 ± 0.05 7.00 ±0.10 R = 0.05 TYP 17 R = 0.115 TYP 32 6.43 ±0.10 4.00 ±0.10 2.65 ±0.10 PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 16 0.75 ±0.05 0.40 BSC 0.20 ± 0.05 1 6.00 REF BOTTOM VIEW—EXPOSED PAD (DKD32) QFN 1106 REV Ø 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 42681fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 47 LTC4268-1 RELATED PARTS PART NUMBER LT 1952 LTC3803-3 LTC3805 LTC3825 LTC4257-1 LTC4258 LTC4259A-1 LTC4263 LTC4263-1 LTC4264 LTC4267 ® DESCRIPTION Single Switch Synchronous Forward Counter Current Mode Flyback DC/DC Controller in ThinSOT TM COMMENTS Synchronous Controller, Programmable Volt-Sec Clamp, Low Start Current 300kHz Constant Frequency, Adjustable Slope Compensation, Optimized for High Input Voltage Applications Slope Comp Overcurrent Protect, Internal/External Clock Adjustable Switching Frequency, Programmable Undervoltage Lockout, Accurate Regulation without Trim, Synchronous for High Efficiency 100V 400mA Internal Switch, Programmable Classification Dual Current Limit DC Disconnect Only, IEEE-Compliant PD Detection and Classification, Autonomous Operation or I2C Control AC or DC Disconnect IEEE-Compliant PD Detection and Classification, Autonomous Operation or I2C Control AC or DC Disconnect IEEE-Compliant PD Detection and Classification, Autonomous Operation or I2C Control Internal Switch, Autonomous Operation, 30W 750mA Internal Switch, Programmable Classification Current to 75mA. Precision Dual Current Limit with Disable. Adjustable Frequency Current Mode Flyback Controller Isolate No-Opto Synchronous Flyback Controller with Wide Input Supply Range IEEE 802.3af PD Interface Controller Quad IEEE 802.3af Power over Ethernet Controller Quad IEEE 802.3af Power over Ethernet Controller Single IEEE 802.3af Power over Ethernet Controller High Power Single PSE Controller High Power PD Interface Controller with 750mA Current Limit IEEE 802.3af PD Interface with an Integrated Switching 100V 400mA Internal Switch, Programmable Classification, 200kHz Regulator Constant Frequency PWM, Interface and Switcher Optimized for IEEECompliant PD System IEEE 802.3af PD Interface with an Integrated Switching 100V 400mA Internal Switch, Programmable Classification, 300kHz Regulator Constant Frequency PWM, Interface and Switcher Optimized for IEEECompliant PD System LTC4267-3 ThinSOT are trademarks of Linear Technology Corporation. 42681fa 48 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0108 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007