LTM4618

FEATURES n n n n n n n n n n n n n n LTM4618 6A DC/DC µModule Regulator with Tracking and Frequency Synchronization DESCRIPTION The LTM®4618 is a complete 6A output switching mode DC/DC power supply in a 9mm × 15mm × 4.32mm LGA package. Included in the package are the switching controller, power FETs, inductor and all support components. Operating over an input voltage range of 4.5V to 26.5V, the LTM4618 supports an output voltage range of 0.8V to 5V set by a single external resistor. Its high efficiency design delivers 6A continuous current (8A peak). Only a few input and output capacitors are needed. High switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. The device supports frequency synchronization and output voltage tracking for supply rail sequencing. Burst Mode operation or pulseskipping mode can be selected for light load operations. Fault protection features include overvoltage protection, overcurrent protection and foldback current limit for short-circuit protection. The LTM4618 is Pb-free and RoHS compliant. L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode and μModule are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Complete Standalone Power Supply Wide Input Voltage Range: 4.5V to 26.5V 6A DC Typical, 8A Peak Output Current 0.8V to 5V Output Output Voltage Tracking ±1.75% Maximum Total DC Error Current Mode Control/Fast Transient Response Phase-Lockable Fixed Frequency 250kHz to 780kHz On-Board Frequency Synchronization Selectable Burst Mode® Operation Power Good Voltage Indicator Output Overvoltage Protection Output Current Foldback Limiting 9mm × 15mm × 4.32mm LGA Package APPLICATIONS n n n n n n n Telecom and Networking Equipment Servers Storage Cards ATCA Cards Industrial Equipment Point of Load Regulation Medical Systems TYPICAL APPLICATION 2.5V/6A DC/DC Power μModule® with 6V to 26.5V Input Efficiency and Power Loss vs Load Current 95 EFFICIENCY 90 EFFICIENCY (%) VIN 6V to 26.5V MODE/PLLIN INTVCC EXTVCC FREQ VIN CIN COMP LTM4618 TK/SS 0.1μF RUN SGND PGND 4618 TA01 3.0 2.5 POWER LOSS (W) 2.0 VOUT VFB PGOOD 28.7k COUT VOUT 2.5V/6A 85 1.5 80 1.0 POWER LOSS 75 12VIN TO 2.5VOUT 24VIN TO 2.5VOUT 0 1 3 2 4 LOAD CURRENT (A) 5 6 4618 TA01b 0.5 0 70 4618f 1 LTM4618 ABSOLUTE MAXIMUM RATINGS (Note 1) PIN CONFIGURATION TOP VIEW 7 VIN, SW ...................................................... –0.3V to 28V INTVCC, RUN, EXTVCC, PGOOD .................... –0.3V to 6V COMP VFB ................................................. –0.3V to 2.7V , MODE/PLLIN, TK/SS, FREQ ..................................................... –0.3V to INTVCC VOUT ............................................................... 0.8V to 5V Operating Junction Temperature Range (Note 2)..................................................–40°C to 125°C Storage Temperature Range................... –55°C to 125°C Peak Package Body Temperature .......................... 250°C SW VIN 6 5 PGND EXTVCC SGND/PGND MODE/ PLLIN FREQ RUN 4 3 2 1 A B C D E F G H J K L M VOUT TK/SS COMP VFB PGOOD INTVCC LGA PACKAGE 84-LEAD (15mm 9mm 4.32mm) ΘJA = 16°C/W, ΘJCtop = 15°C/W, ΘJCbottom = 4°C/W, WEIGHT = 2.3g, θJB + θBA = 16°C/W, θBA = BOARD-TO-AMBIENT RESISTANCE, θ VALUES DEFINED PER JESD51-12 ORDER INFORMATION LEAD FREE FINISH LTM4618EV#PBF LTM4618IV#PBF PART MARKING* LTM4618V LTM4618V PACKAGE DESCRIPTION 84-Lead (15mm × 9mm × 4.32mm) LGA 84-Lead (15mm × 9mm × 4.32mm) LGA TEMPERATURE RANGE –40°C to 125°C –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ ELECTRICAL CHARACTERISTICS SYMBOL VIN(DC) VOUT(DC) PARAMETER Input DC Voltage Output Voltage Total Variation with Line and Load The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, per typical application in Figure 21. CONDITIONS (Note 5) CIN = 10μF ×2, RFB = 28.0kΩ COUT = 100μF ×3 X7R Ceramic MODE/PLLIN = 0V, VFREQ = 2.4V VIN = 6V to 26.5V, IOUT = 0A to 6A (Note 4) VINTVCC Rising VINTVCC Falling IOUT = 0A, CIN = 10μF ×2, COUT = 100μF ×3 VOUT = 2.5V VIN = 12V VIN = 26.5V l MIN 4.5 TYP MAX 26.5 UNITS V l 2.476 2.52 2.557 V Input Specifications VIN(UVLO) IINRUSH(VIN) Undervoltage Lockout Thresholds Input Inrush Current at Start-Up 2.00 1.85 2.20 2.00 2.35 2.15 V V 0.3 0.2 A A 4618f 2 LTM4618 ELECTRICAL CHARACTERISTICS SYMBOL IQ(VIN) PARAMETER Input Supply Bias Current The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, per typical application in Figure 21. CONDITIONS VIN = 12V, VOUT = 2.5V, IOUT = 0A VIN = 26.5V, VOUT = 2.5V, IOUT = 0A Shutdown, RUN = 0, VIN = 26.5V VIN = 12V, VOUT = 2.5V, IOUT = 6A VIN = 26.5V, VOUT = 2.5V, IOUT = 6A VIN = 12V, VRUN > 2V, No Load EXTVCC Ramping Positive INTVCC = 20mA, VEXTVCC = 5V l MIN TYP 26 20 80 1.430 0.675 MAX UNITS mA mA μA A A IS(VIN) INTVCC VEXTVCC VLDO External VEXTVCC Hysteresis IOUT(DC) ΔVOUT(LINE) VOUT ΔVOUT(LOAD) VOUT VOUT(AC) Input Supply Current Internal VCC Voltage EXTVCC Switchover Voltage EXTVCC Voltage Drop EXTVCC Hysteresis Output Continuous Current Range Line Regulation Accuracy Load Regulation Accuracy Output Ripple Voltage 4.8 4.5 5 4.7 50 200 5.2 100 V V mV mV Output Specifications VIN = 12V, VOUT = 2.5V (Note 4) VOUT = 2.5V, VIN from 6V to 26.5V IOUT = 0A VIN = 12V, VOUT = 2.5V, 0 to 6A (Note 4) IOUT = 0A, COUT = 100μF ×3 X5R Ceramic VIN = 12V, VOUT = 2.5V VIN = 26.5V, VOUT = 2.5V IOUT = 2A, VIN = 12V, VOUT = 2.5V, VFREQ = INTVCC COUT = 100μF ×3 X5R Ceramic VOUT = 2.5V, IOUT = 0A VIN = 12V VIN = 26.5V COUT = 100μF ×3 X5R Ceramic, VOUT = 2.5V, IOUT = 0A, TK/SS Capacitor = 0.01μF VIN = 12V VIN = 26.5V Load: 0% to 50% of Full Load COUT = 100μF ×3 X5R Ceramic, VOUT = 2.5V VIN = 12V Load: 0% to 50% of Full Load COUT = 100μF ×3 X5R Ceramic, VOUT = 2.5V VIN = 12V COUT = 100μF ×3 X5R Ceramic VIN = 6V, VOUT = 2.5V VIN = 26.5V, VOUT = 2.5V IOUT = 0A, VOUT = 2.5V (Note 3) Measured at VFB VTK/SS = 0V In Dropout (Note 3) (Note 3) VFREQ = 1.2V VFREQ = 0V 450 210 0.84 0.9 0.792 0.788 l l 0 0.02 0.3 6 0.04 0.6 A %/V % 10 12 780 mV mV kHz fS ΔVOUT(START) Output Ripple Voltage Frequency Turn-On Overshoot 20 20 mV mV tSTART Turn-On Time 0.75 0.70 ms ms ΔVOUTLS Peak Deviation for Dynamic Load 15 mV tSETTLE Settling Time for Dynamic Load Step 10 11 11 0.8 0.8 –10 0.86 1.3 97 90 500 250 550 290 0.808 0.808 –50 0.88 1.7 μs A A V V nA V μA % ns kHz kHz 4618f IOUT(PK) Output Current Limit Control Section VFB IFB VOVL ITK/SS DFMAX tON(MIN) fNOM fLOW Error Amplifier Feedback Voltage Error Amplifier Feedback Current Feedback Voltage Lockout Soft-Start Charge Current Maximum Duty Factor Minimum On-Time Nominal Frequency Lowest Frequency l 3 LTM4618 ELECTRICAL CHARACTERISTICS SYMBOL fHIGH VIH(MODE/PLLIN) VIL(MODE/PLLIN) RMODE/PLLIN IFREQ PARAMETER Highest Frequency Synchronous Clock High Level Synchronous Clock Low Level MODE/PLLIN Input Resistance FREQ Pin Sinking Current Sourcing Current RUN Pin On Threshold RUN Pin Hysteresis Resistor Between VOUT and VFB Pins PGOOD Voltage Low PGOOD Leakage Current PGOOD Trip Level IPGOOD = 2mA VPGOOD = 5V VFB with Respect to Set Regulated Voltage VFB Ramping Negative VFB Ramping Positive –5 5 –7.5 7.5 60.1 fMODE/PLLIN > fOSC fMODE/PLLIN < fOSC RUN Rising 1.1 250 –13 13 1.22 120 60.4 0.1 60.7 0.3 ±2 –10 10 1.35 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, per typical application in Figure 21. CONDITIONS VFREQ ≥ 2.4V, INTVCC MIN 700 2.0 0.8 TYP 780 MAX 860 UNITS kHz V V kΩ μA μA V mV kΩ V μA % % VRUN VRUN Hysteresis RFBHI PGOOD Output VPGL IPGOOD VPG Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4618 is tested under pulsed load conditions such that TJ ≈ TA. The LTM4618E is guaranteed to meet performance specifications over the 0°C to 125°C operating junction temperature range. Specifications over the full –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4618I is guaranteed to meet specifications over the full operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: 100% tested at wafer level only. Note 4: See Output Current Derating curves for different VIN, VOUT and TA. Note 5: For input voltages less than 6V, tie the VIN, INTVCC and EXTVCC together. The LTM4618 will operate from 5V inputs, but VIN, INTVCC and EXTVCC need to be tied together. 4618f 4 LTM4618 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Load Current with 5VIN (CCM) 100 95 EFFICIENCY (%) EFFICIENCY (%) 90 85 80 75 70 100 95 EFFICIENCY (%) 12V TO 1.2VOUT 12V TO 1.5VOUT 12V TO 2.5VOUT 12V TO 3.3VOUT 12V TO 5VOUT 0 1 3 2 4 LOAD CURRENT (A) 5 6 4618 G02 Efficiency vs Load Current with 12VIN (CCM) 95 Efficiency vs Load Current with 24VIN (CCM) 90 90 85 80 75 70 85 80 5V TO 0.8VOUT 5V TO 1.2VOUT 5V TO 1.5VOUT 5V TO 2.5VOUT 5V TO 3.3VOUT 0 1 3 2 4 LOAD CURRENT (A) 5 6 4618 G01 75 70 24V TO 2.5VOUT 24V TO 3.3VOUT 24V TO 5VOUT 0 1 2 4 3 LOAD CURRENT (A) 5 6 4618 G03 Efficiency vs Load Current with Different Mode Settings (12V to 3.3V) 100 VIN = 12V 90 VOUT = 3.3V 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.01 0.1 LOAD CURRENT (A) BURST PULSE SKIP CCM 1 4618 G04 1.2V Transient Response 1.5V Transient Response IOUT 1A/DIV VOUT 50mV/DIV 50μs/DIV VIN = 12V AND VOUT = 1.2V AT 3A/μs LOAD STEP COUT = 2 22μF 6.3V CERAMIC CAPACITOR 1 100μF 6.3V CERAMIC CAPACITOR 1 220μF SANYO POSCAP 4618 G05 IOUT 1A/DIV VOUT 50mV/DIV 50μs/DIV VIN = 12V AND VOUT = 1.5V AT 3A/μs LOAD STEP COUT = 2 22μF 6.3V CERAMIC CAPACITOR 1 100μF 6.3V CERAMIC CAPACITOR 1 220μF SANYO POSCAP 4618 G06 2.5V Transient Response 3.3V Transient Response 5V Transient Response IOUT 1A/DIV VOUT 50mV/DIV 50μs/DIV VIN = 12V AND VOUT = 2.5V AT 3A/μs LOAD STEP COUT = 2 22μF 6.3V CERAMIC CAPACITOR 1 100μF 6.3V CERAMIC CAPACITOR 1 220μF SANYO POSCAP 4618 G07 IOUT 1A/DIV VOUT 50mV/DIV 50μs/DIV VIN = 12V AND VOUT = 3.3V AT 3A/μs LOAD STEP COUT = 2 22μF 6.3V CERAMIC CAPACITOR 1 100μF 6.3V CERAMIC CAPACITOR 1 220μF SANYO POSCAP 4618 G08 IOUT 1A/DIV VOUT 100mV/DIV 50μs/DIV VIN = 12V AND VOUT = 5V AT 3A/μs LOAD STEP COUT = 2 22μF 6.3V CERAMIC CAPACITOR 1 100μF 6.3V CERAMIC CAPACITOR 1 220μF SANYO POSCAP 4618 G09 4618f 5 LTM4618 TYPICAL PERFORMANCE CHARACTERISTICS Start-Up, IOUT = 0A Start-Up, IOUT = 6A VOUT 1V/DIV IIN 0.2A/DIV 20ms/DIV VIN = 12V AND VOUT = 2.5V COUT = 2 22μF 6.3V CERAMIC, 1 100μF 6.3V CERAMIC AND 1 220μF SANYO POSCAP CSOFT-START = 0.1μF 4618 G10 VOUT 1V/DIV IIN 0.5A/DIV 20ms/DIV VIN = 12V AND VOUT = 2.5V COUT = 2 22μF 6.3V CERAMIC, 1 100μF 6.3V CERAMIC AND 1 220μF SANYO POSCAP CSOFT-START = 0.1μF 4618 G11 Short-Circuit Protection, IOUT = 0A VOUT 1V/DIV VOUT 1V/DIV Short-Circuit Protection, IOUT = 6A IIN 1A/DIV 100μs/DIV VIN = 12V AND VOUT = 2.5V COUT = 2 22μF 6.3V CERAMIC, 1 100μF 6.3V CERAMIC AND 1 220μF SANYO POSCAP 4618 G12 IIN 1A/DIV 100μs/DIV VIN = 12V AND VOUT = 2.5V COUT = 2 22μF 6.3V CERAMIC, 1 100μF 6.3V CERAMIC AND 1 220μF SANYO POSCAP 4618 G13 4618f 6 LTM4618 PIN FUNCTIONS NC (A1): No Connect. Leave floating. FREQ (A2): Frequency Selection Pin. An internal low pass filter is tied to this pin. The frequency can be selected from 250kHz to 780kHz by setting a voltage from this pin to SGND. A programming resistor divider can be used to set the operating frequency. See the Applications Information section. MODE/PLLIN (A3): Mode Selection or External Synchronization Pin. Tying this pin to INTVCC enables pulse-skipping operation. Tying this pin low enables forced continuous mode operation. Burst Mode operation is enabled by floating the pin. A clock on the pin will force the controller into forced continuous mode of operation and synchronize to the internal oscillator. The programming DC voltage has to be removed for clock synchronization. PGND (BANK 2: A4, B4, D4-D7, E1-E7, F1-F7, G1-G7, H1-H7, J5-J7, K5, K7, L5-L7, M5-M7): Power ground pins for both input and output returns. VIN (BANK 1: A5-A7, B5-B7, C5-C7): Power Input Pins. Apply input voltage between these pins and PGND pins. Recommend placing input decoupling capacitance directly between VIN pins and PGND pins. TK/SS (B1): Output Voltage Tracking and Soft-Start Pin. An internal soft-start current of 1.3μA charges the soft-start capacitor. See the Applications Information section. RUN (B2): Run Control Pin. A voltage above 1.35V on this pin turns on the module. Forcing this pin below 1.1V will shut down the output. The RUN pin has a 1μA pullup current source that increases to 10μA as the RUN pin voltage reaches 1.5V and up to compliance. Therefore the pin can be left floating for normal operation. A maximum of 6V can be applied to the pin. A voltage divider can be used for a UVLO function. See the Applications Information section. 7 SGND (B3, C2 and C3): Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection to PGND. See applications for details. COMP (C1): Current control threshold and error amplifier compensation point. The module has been internally compensated for most I/O ranges. EXTVCC (C4): External Voltage Input. Bypasses the internal INTVCC LDO and powers the internal circuitry and MOSFET drivers. If a 5V source is available, the internal LDO is disabled, and the power dissipation is lower, especially at higher input voltages. See the Applications Information section. VFB (D1): The negative input of the error amplifier. Internally, this pin is connected to VOUT with a 60.4kΩ precision resistor. Different output voltages can be programmed with an additional resistor between VFB and SGND pins. See applications for details. PGOOD (D2): Output Voltage Power Good Indicator. Opendrain logic output that is pulled to ground when the output voltage is not within ±7.5% of the regulation point. INTVCC (D3): Internal 5V Regulator Output. This pin is for additional decoupling of the 5V internal regulator. VOUT (BANK 3: J1-J4, K1-K4, L1-L4, M1-M4): Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing output decoupling capacitance directly between these pins and PGND pins. SW (K6): Switching Node of the Circuit. This pin is used to check the switching frequency. Leave pin floating. A resistor-capacitor snubber can be placed from SW to PGND to eliminate high frequency switch node ringing. See the Applications Information section. BANK 1 VIN 6 5 BANK 2 PGND SW SGND/PGND 4 3 2 BANK 3 VOUT CNTRL 1 A B C D E F G H J K L M 4618f 7 LTM4618 SIMPLIFIED BLOCK DIAGRAM ≤6V VIN TIE VIN, INTVCC AND EXTVCC TOGETHER INTERNAL FILTER EXTVCC INTVCC MODE/PLLIN TK/SS CSS RUN PGOOD COMP INTERNAL COMP POWER CONTROL M2 10μF 1.5μF M1 1.5μH VIN 4.5V TO 26.5V CIN SW VOUT 2.5V/6A COUT PGND 60.4k + + INTVCC FREQ VFB INTERNAL FILTER RFB 28k SGND 4618 F01 Figure 1. Simplified LTM4618 Block Diagram DECOUPLING REQUIREMENTS SYMBOL CIN COUT PARAMETER External Input Capacitor Requirement (VIN = 4.5V to 26.5V, VOUT = 2.5V) External Output Capacitor Requirement (VIN = 4.5V to 26.5V, VOUT = 2.5V) TA = 25°C. Use Figure 1 configuration. MIN 10 200 TYP MAX UNITS μF μF CONDITIONS IOUT = 6A IOUT = 6A 4618f 8 LTM4618 OPERATION Power Module Description The LTM4618 is a standalone non-isolated switching mode DC/DC power supply. It can deliver up to 6A (DC current) output with few external input and output capacitors. This module provides precisely regulated output voltages programmable via external resistors from 0.8VDC to 5.0VDC over 4.5V to 26.5V input voltages. The typical application schematic is shown in Figure 21. For ≤6V inputs, connect VIN, INTVCC and EXTVCC together. The LTM4618 has an integrated constant frequency current mode regulator and built-in power MOSFET devices with fast switching speed. The typical switching frequency is 750kHz. With current mode control and internal feedback loop compensation, the LTM4618 module has sufficient stability margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit and current foldback in a short-circuit condition. Pulling the RUN pin below 1.1V forces the controller into its shutdown state, by turning off both MOSFETs. The TK/SS pin can be used for programming the output voltage ramp and voltage tracking during start-up. See the Applications Information section. The LTM4618 is internally compensated to be stable over all operating conditions. The Linear Technology μModule Power Design Tool will be provided for transient and stability analysis. The VFB pin is used to program the output voltage with a single external resistor to ground. Multiphase operation can be easily employed with the synchronization control. High efficiency at light loads can be accomplished with selectable Burst Mode or pulse-skipping mode operations using the MODE/PLLIN pin. Efficiency graphs are provided for light load operation in the Typical Performance Characteristics section. 4618f 9 LTM4618 APPLICATIONS INFORMATION The typical LTM4618 application circuit is shown in Figure 21. External component selection is primarily determined by the maximum load current and output voltage. VIN to VOUT Step-Down Ratios There are restrictions in the maximum VIN to VOUT stepdown ratio that can be achieved for a given input voltage. One of the restrictions is the minimum on-time tON(MIN), which is the smallest time duration that the LTM4618 can operate. Make sure that the operating on-time is larger than the minimum on-time as shown in the equation below. See the Thermal Considerations and Output Current Derating sections in this data sheet for the current restrictions. tON(MIN) is approximately 90ns, guardband to 110ns. tON(MIN) < VOUT VIN • ƒ Input Capacitors The LTM4618 module should be connected to a low ACimpedance DC source. One 1.5μF input ceramic capacitor is included inside the module. Additional input capacitors are only needed if a large load step is required up to the 6A level. A 47μF to 100μF surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. This bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. If low impedance power planes are used, then this 47μF capacitor is not needed. For a buck converter, the switching duty-cycle can be estimated as: D= VOUT VIN Output Voltage Programming The PWM controller has an internal 0.8V reference voltage. As shown in the Block Diagram, a 60.4k internal feedback resistor connects VOUT to the VFB pin. Adding a resistor RFB from the VFB pin to SGND programs the output voltage: VOUT = 0.8V • 60.4k + RFB RFB 1 243 1.2 121 1.5 69.8 1.8 48.7 2.5 28.7 3.3 19.1 5 11.5 Without considering the inductor current ripple, the RMS current of the input capacitor can be estimated as: ICIN(RMS) = IOUT(MAX) η • D • (1– D) Table 1. VFB Resistor Table vs Various Output Voltages VOUT (V) RFB (kΩ) 0.8 Open In the above equation, η is the estimated efficiency of the power module. One 10μF ceramic input capacitor is typically rated for 2A of RMS ripple current, so the RMS input current at the worst case 6A maximum current is about 3A. If a low inductance plane is used to power the device, then two 10μF ceramic capacitors are enough for the output at 6A load and no external input bulk capacitor is required. The input RMS ripple current can be cancelled by paralleling multiple LTM4618 power modules out of phase, allowing the use of fewer input capacitors. Application Note 77 explains the details. 4618f 10 LTM4618 APPLICATIONS INFORMATION Output Capacitors The LTM4618 is designed for low output voltage ripple noise. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be a low ESR tantalum capacitor, a low ESR polymer capacitor or ceramic capacitor. The typical output capacitance range is from 100μF to 300μF Additional output . filtering may be required by the system designer if further reduction of output ripple or dynamic transient spikes is required. Table 4 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 3A/μs transient. The table optimizes the total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 4 matrix, and the Linear Technology μModule Power Design Tool is available for stability analysis. Multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. The Linear Technology μModule Power Design Tool can calculate the output ripple reduction as the number of implemented phases increases by N times. Mode Selections and Phase-Locked Loop The LTM4618 can be enabled to enter high efficiency Burst Mode operation, constant-frequency, pulse-skipping mode, or forced continuous conduction mode. To select the forced continuous operation, tie the MODE/PLLIN pin to ground. To select pulse-skipping mode of operation, tie the MODE/PLLIN pin to INTVCC . To select Burst Mode operation, float the pin. A phase-locked loop (PLL) is available on the LTM4618 to synchronize the internal oscillator to an external clock source that is connected to the MODE/PLLIN pin. The incoming clock should be applied before the regulator’s RUN pin is enabled. Frequency Synchronization The MODE/PLLIN pin allows the LTM4618 to be synchronized to an external clock (between 400kHz to 780kHz) and the internal phase-locked loop allows the LTM4618 to lock onto input clock phase as well. The FREQ pin has the onboard loop filter for the PLL. The incoming clock must be applied before the RUN pin is enabled. For applications powering the clock source from the LTM4618’s INTVCC , the RUN pin has to be enabled in order to activate INTVCC for the clock source. In this situation (see Figure 22) the TK/SS pin can be used to soft-start the regulator for 100ms using a ≈ 0.22μF capacitor. This will allow the regulator to synchronize to the right frequency before the regulator’s inductor ripple current peaks. Frequency Selection The switching frequency of the LTM4618’s controller can be selected using a DC voltage. If the MODE/PLLIN pin is not being driven by an external clock source, the FREQ pin can program the controller’s operating frequency from 250kHz to 780kHz by connecting a resistor divider as shown in Figure 21. The typical frequency is 750kHz. But if the minimum on-time is reached, a lower frequency needs to be set to increase the turn-on time. Otherwise, a significant amount of cycle skipping can occur with correspondingly larger ripple current and voltage ripple. 900 800 SWITCHING FREQUENCY (kHz) 700 600 500 400 300 200 100 0 0 0.5 1 1.5 FREQ PIN VOLTAGE (V) 2 2.5 4618 F03 Figure 3. Relationship Between Switching Frequency and Voltage at the FREQ Pin 4618f 11 LTM4618 APPLICATIONS INFORMATION The LTM4618 can be synchronized from 400kHz to 780kHz with an input clock that has a high level above 2.0V and a low level below 0.8V. The 400kHz low end operation limit is put in place to limit inductor ripple current. See the Typical Applications section for synchronization examples. The LTM4618 minimum on-time is limited to about 90ns. Guardband the on-time to 110ns. The on-time can be calculated as: tON(MIN) = 1 ⎛ VOUT ⎞ • FREQ ⎜ VIN ⎟ ⎝ ⎠ VTRACK is the track ramp applied to the slave’s TK/SS pin. VTRACK has a control range of 0V to 0.8V. When the master’s output is divided down with the same resistor values used to set the slave’s output, then the slave will coincident track with the master until it reaches its final value. The master will continue to its final value from the slave’s regulation point. Ratiometric modes of tracking can be achieved by selecting different divider resistor values to change the output tracking ratio. The master output must be greater than the slave output for the tracking to work. Master and slave data inputs can be used to implement the correct resistor values for coincident or ratio tracking. Soft-Start and Tracking LTM4618 has the ability to either soft-start by itself with a capacitor or track the output of an external supply. When the module is configured to soft-start by itself, a capacitor should be connected to its TK/SS pin. When the module is in the shutdown state, the TK/SS pin is actively pulled to ground. Once the RUN pin voltage is above 1.22V, the module powers up. Then a soft-start current of 1.3μA starts to charge its soft-start capacitor. Note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the TK/SS pin. Current foldback is disabled during this phase to ensure smooth soft-start or tracking. The soft-start or tracking range is defined as the voltage range from 0V to 0.8V on the TK/SS pin. The total soft-start time can be calculated as: 0.8V • CSS t SOFT-START = 1.3µA Output voltage tracking can be programmed externally using the TK/SS pin. The master voltage is divided down with an external resistor divider that is the same as the slave’s feedback divider to implement coincident tracking. The LTM4618 uses an accurate 60.4k resistor internally for the top feedback resistor. Figure 4 shows an example of coincident tracking. ⎛ R1⎞ VOUT(SLAVE) = ⎜ 1+ ⎟ • VTRACK ⎝ R2 ⎠ VIN 5V MASTER R1 OUTPUT 60.4k CIN MODE/PLLIN INTVCC EXTVCC VIN FREQ COMP LTM4618 TK/SS VFB PGOOD SGND PGND 4618 F04 VOUT 22pF VOUT(SLAVE) 2.5V/6A COUT R2 28.7k RUN 28.7k Figure 4. Output Voltage Coincident Tracking MASTER OUTPUT OUTPUT VOLTAGE SLAVE OUTPUT TIME 4618 F05 Figure 5. Coincident Tracking Characteristics 4618f 12 LTM4618 APPLICATIONS INFORMATION Slope Compensation The module has already been internally compensated for all output voltages. The Linear Technology μModule Power Design Tool will be provided for other control loop optimization. RUN Pin The RUN pin has a 1μA pull-up current source that will enable the device in a float condition. A voltage divider can be used to enable a UVLO function using the RUN pin. See Figure 21. Fault Conditions: Current Limit and Overcurrent Foldback The LTM4618 has a current mode controller, which inherently limits the cycle-by-cycle inductor current not only in steady-state operation, but also in transient. To further limit current in the event of an overload condition, the LTM4618 provides foldback current limiting. If the output voltage falls by more than 40%, then the maximum output current is progressively lowered to about 25% of its full current limit value. Thermal Considerations and Output Current Derating The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those parameters defined by JESD51-9 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a μModule package mounted to a hardware test board—also defined by JESD51-9 (“Test Boards for Area Array Surface Mount Package Thermal Measurements”). The motivation for providing these thermal coefficients in found in JESD 51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the μModule regulator’s thermal performance in their application at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application. The Pin Configuration section shows four thermal coefficients explicitly defined in JESD 51-12; these coefficients are quoted or paraphrased below: • θJA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defined test board, which does not reflect an actual application or viable operating condition. • θJCbottom, the thermal resistance from junction to the bottom of the product case, is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the package. In the typical μModule, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. • θJCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical μModule are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θJCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application. • θJB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the μModule and into the board, and 4618f 13 LTM4618 APPLICATIONS INFORMATION is really the sum of the θJCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured at specified distance from the package, using a two sided, two layer board. This board is described in JESD 51-9. A graphical representation of the forementioned thermal resistances is given in Figure 6; blue resistances are contained within the μModule, whereas green resistances are external to the μModule. As a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD 51-12 or provided in the Pin Configuration section replicates or conveys normal operating conditions of a μModule. For example, in actual board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the μModule—as the standard defines for θJCtop and θJCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. Within a SIP (System-In-Package) module, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity—but also, not ignoring practical realities—an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the μModule and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined JEDEC environment consistent with JSED51-9 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the μModule with heat sinks and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operating the device at the same power loss as that which was simulated. An outcome of this process and due-diligence yields a set of derating curves provided in other sections of this data sheet. After these laboratory tests have been performed and correlated to the μModule model, then the θJB and θBA are summed together to correlate quite well with the μModule model with no air flow or heat sinking in a properly define chamber. This θJB+ θBA value is shown in the Pin Configuration section and should accurately equal the θJA value because approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top mounted heat sink. JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD) JUNCTION-TO-CASE (TOP) RESISTANCE CASE (TOP)-TO-AMBIENT RESISTANCE JUNCTION JUNCTION-TO-BOARD RESISTANCE JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD (BOTTOM) RESISTANCE RESISTANCE BOARD-TO-AMBIENT RESISTANCE At 4618 F06 μMODULE DEVICE Figure 6. Graphical Representation of JESD51-12 Thermal Coefficients 4618f 14 LTM4618 APPLICATIONS INFORMATION The 1.5V and 3.3V power loss curves in Figures 7 and 8 can be used in coordination with the load current derating curves in Figures 9 to 16 for calculating an approximate θJA thermal resistance for the LTM4618 with various heat sinking and air flow conditions. The power loss curves are taken at room temperature, and are increased with multiplicative factors according to the ambient temperature. These approximate factors are: 1 for 40°C; 1.05 for 50°C; 1.1 for 60°C; 1.15 for 70°C; 1.2 for 80°C; 1.25 for 90°C; 1.3 for 100°C; 1.35 for 110°C and 1.4 for 125°C. The derating curves are plotted with the output current starting at 6A and the ambient temperature at 40°C. The output voltages are 1.5V, and 3.3V. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without air flow. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at 120°C maximum while lowering output current or power with increasing ambient temperature. The decreased output current will decrease the internal module loss as ambient temperature is increased. The monitored junction temperature of 120°C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example, in Figure 11 the load current is derated to ~5A at ~85°C with 2.0 no air flow or heat sink and the power loss for the 12V to 1.5V at 5A output is about 1.7W. The 1.7W loss is calculated with the ~1.4W room temperature loss from the 12V to 1.5V power loss curve at 5A, and the 1.2 multiplying factor at 85°C ambient. If the 85°C ambient temperature is subtracted from the 115°C junction temperature, then the difference of 30°C divided 1.7W equals a 17°C/W θJA thermal resistance. Table 2 specifies a 16°C/W value which is very close. Table 2 and Table 3 provide equivalent thermal resistances for 1.5V and 3.3V outputs with and without air flow and heat sinking. The derived thermal resistances in Tables 2 and 3 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived from the efficiency curves in the Typical Performance Characteristics section and adjusted with the above ambient temperature multiplicative factors. The printed circuit board is a 1.6mm thick four layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers. The PCB dimensions are 95mm × 76mm. The BGA heat sink is listed in Table 3. Safety Considerations The LTM4618 modules do not provide isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. 3.0 2.5 12VIN 24VIN 5VIN 12VIN 1.5 POWER LOSS (W) POWER LOSS (W) 0 1 3 2 4 LOAD CURRENT (A) 5 6 4618 F07 2.0 1.5 1.0 0.5 1.0 0.5 0 0 0 1 3 2 4 LOAD CURRENT (A) 5 6 4618 F08 Figure 7. Power Loss at 1.5VOUT Figure 8. Power Loss at 3.3VOUT 4618f 15 LTM4618 APPLICATIONS INFORMATION 6 5 LOAD CURRENT (A) LOAD CURRENT (A) 4 3 2 1 0 0LFM 200LFM 400LFM 70 75 80 85 90 95 100 105 110 115 AMBIENT TEMPERATURE (°C) 4618 F09 6 5 LOAD CURRENT (A) 4 3 2 1 0 0LFM 200LFM 400LFM 70 75 80 85 90 95 100 105 110 115 AMBIENT TEMPERATURE (°C) 4618 F10 6 5 4 3 2 1 0 0LFM 200LFM 400LFM 70 75 80 85 90 95 100 105 110 115 AMBIENT TEMPERATURE (°C) 4618 F11 Figure 9. 5VIN to 1.5VOUT without Heat Sink 6 5 LOAD CURRENT (A) LOAD CURRENT (A) 4 3 2 1 0 0LFM 200LFM 400LFM 70 75 80 85 90 95 100 105 110 115 AMBIENT TEMPERATURE (°C) 4618 F12 Figure 10. 5VIN to 1.5VOUT with Heat Sink 6 5 4 3 2 1 0 0LFM 200LFM 400LFM 60 65 70 75 80 85 90 95 100 105 110 AMBIENT TEMPERATURE (°C) 4618 F13 Figure 11. 12VIN to 1.5VOUT without Heat Sink 6 5 LOAD CURRENT (A) 4 3 2 1 0 0LFM 200LFM 400LFM 60 65 70 75 80 85 90 95 100 105 110 AMBIENT TEMPERATURE (°C) 4618 F14 Figure 12. 12VIN to 1.5VOUT with Heat Sink 6 5 LOAD CURRENT (A) Figure 13. 12VIN to 3.3VOUT without Heat Sink 6 5 LOAD CURRENT (A) 4 3 2 1 0 0LFM 200LFM 400LFM 60 65 Figure 14. 12VIN to 3.3VOUT with Heat Sink 4 3 2 1 0 0LFM 200LFM 400LFM 60 65 70 75 80 85 90 95 100 105 AMBIENT TEMPERATURE (°C) 4618 F15 70 75 80 85 90 95 100 105 AMBIENT TEMPERATURE (°C) 4618 F16 Figure 15. 24VIN to 3.3VOUT without Heat Sink Figure 16. 24VIN to 3.3VOUT with Heat Sink 4618f 16 LTM4618 APPLICATIONS INFORMATION Table 2. 1.5V Output DERATING CURVE Figures 9, 11 Figures 9, 11 Figures 9, 11 Figures 10, 12 Figures 10, 12 Figures 10, 12 VIN (V) 5, 12 5, 12 5, 12 5, 12 5, 12 5, 12 POWER LOSS CURVE Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 AIRFLOW (LFM) 0 200 400 0 200 400 HEAT SINK None None None BGA Heat Sink BGA Heat Sink BGA Heat Sink ΘJA (°C/W) 16 12.2 11.2 15.2 11.6 10.7 Table 3. 3.3V Output DERATING CURVE Figures 13, 15 Figures 13, 15 Figures 13, 15 Figures 14, 16 Figures 14, 16 Figures 14, 16 VIN (V) 12, 24 12, 24 12, 24 12, 24 12, 24 12, 24 POWER LOSS CURVE Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 AIRFLOW (LFM) 0 200 400 0 200 400 HEAT SINK None None None BGA Heat Sink BGA Heat Sink BGA Heat Sink ΘJA (°C/W) 15 11.2 10.2 14.2 10.6 9.7 Heat Sink Used: 15 × 9 Version of Aavid #375424B000346 Table 4. Output Voltage Response vs Component Matrix (Refer to Figure 21) 0A to 3A Load Step VOUT (V) 1 1 1 1.2 1.2 1.2 1.5 1.5 1.5 1.8 1.8 1.8 2.5 2.5 2.5 3.3 3.3 5 CIN (CERAMIC) 22μF × 2 22μF × 2 22μF × 2 22μF × 2 22μF × 2 22μF × 2 22μF × 2 22μF × 2 22μF × 2 22μF × 2 22μF × 2 22μF × 2 22μF × 2 22μF × 2 22μF × 2 22μF × 2 22μF × 2 22μF × 2 CIN (BULK) 68μF 68μF 68μF 68μF 68μF 68μF 68μF 68μF 68μF 68μF 68μF 68μF 68μF 68μF 68μF 68μF 68μF 68μF COUT1 (CERAMIC) 100μF × 4 100μF × 2 100μF 100μF × 4 100μF × 2 100μF 100μF × 3 100μF 100μF 100μF × 3 100μF 100μF × 4 100μF × 3 100μF × 4 100μF 100μF × 2 100μF × 2 100μF COUT2 (BULK) None 220μF 470μF None 220μF 470μF None 220μF 470μF None 220μF None None None 220μF None None None COMP None None None None None None None None None None None None None None None None None None C2 (pF) 100 None None 47 None None 47 None None 47 None 47 47 None None 22 47 47 FREQ (kHz) 400 400 400 400 400 400 500 500 500 500 500 500 500 600 600 600 600 600 DROOP P-P DEVIATION (mV) (mV) 38 35 30 40 37 27 48 40 30 52 45 50 65 75 60 90 80 150 76 70 60 80 74 54 96 80 60 104 90 100 130 150 120 180 160 300 RECOVERY TIME (μs) 35 35 35 30 35 35 36 36 40 36 35 35 38 35 45 36 40 40 LOAD STEP (A/μs) 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 RFB (kΩ) 242 242 242 121 121 121 68.1 68.1 68.1 48.7 48.7 48.7 28 28 28 19.1 19.1 11.5 4618f 17 LTM4618 APPLICATIONS INFORMATION VISHAY INLP1616BZERR22M01 0.22μH π FILTER VIN 6V TO 26.5V 10μF 2 VIN R1 CIN 10μF 2 C1 0.1μF INTVCC VIN COMP MODE/PLLIN EXTVCC FREQ VOUT VOUT COUT 3.3V/6A 100μF 3 LTM4618 TK/SS RUN SGND PGND VFB PGOOD SW 4618 F17 C2 47pF 19.1k VIN • R2 R1 R2 1.22V R2 RSNUB 1.2Ω 0805 CSNUB 470pF 0805, 50V Figure 17. 6V to 26.5V Input, 3.3V at 6A Design, Meeting CISPR25 Conducted and CISPR22 Radiated EMI Solution 10dB/μV PER DIV 150kHz VIDEO BANDWIDTH 100MHz 4618 F18 Figure 18. VIN 26.5V, VOUT 3.3V, IOUT 5A, π Filter 20μF to 0.22μH Vishay (1616BZ) to 20μF CISPR25 Conducted Emissions 55 AMPLITUDE (dBμV/m) 45 35 25 15 5 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) 4618 F19a 55 CISPR22 CLASS A 45 35 25 15 5 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) 4618 F19b AMPLITUDE (dBμV/m) CISPR22 CLASS B Figure 19. VIN 26.5V, VOUT 3.3V, IOUT 5A, π Filter 20μF to 0.22μH Vishay (1616BZ) to 20μF CISPR22 Radiated EMI Plots 4618f 18 LTM4618 APPLICATIONS INFORMATION EMI Section The LTM4618 has been evaluated for CISPR22 A and B Radiated EMI and CISPR25 Conducted EMI. The CISPR25 Conducted EMI test was performed with an input π filter as shown in Figure 17. An RC snubber circuit is optionally used from the SW pin to the PGND pin to improve the higher frequency attenuation and EMI limit guard band. Figure 18 shows the CISPR25 conducted emissions plot for 26.5V input to 3.3V output at 5A load. Several conditions were evaluated, and Figure 18 results are from the worst-case condition. The input π filter is used to attenuate the reflected noise from the regulator input, and is primarily utilized when the power regulators are closed to the input power feed to a board, like the input power connectors. If the regulator design is placed out on the center of the system board, then the input π filter may not be needed because all of the extra board capacitance and the inductive planes will provide filtering for reflected emissions. If the system board has noise sensitive circuitry that is powered from the same voltage rail as the regulators are, then an input π filter is a good idea to keep regulator noise from corrupting the noise sensitive circuitry on the system board. Figure 19 shows the CISPR22 B Radiated EMI plots. The input π filter is used to attenuate the reflected noise from propagating out onto the input power cables, thus possibly causing radiated EMI issues. An RC snubber circuit is optionally used from the SW pin to the PGND pin to improve the higher frequency attenuation and EMI limit guard band. A placeholder can accommodate the RSNUB . and CSNUB components with 1.2Ω and 470pF These components are probably not necessary, but can be used or adjusted to improve the radiated limit guard bands at the higher frequencies by attenuating any switch node ringing due to parasitic values in the high speed switching paths. It is important to follow the recommended layout guidelines and use good X5R or X7R ceramic capacitors to get good results. Layout Checklist/Example The high integration of LTM4618 makes the PC board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. PGND • Use large PCB copper areas for high current path, including VIN, PGND and VOUT. It helps to minimize the PCB conduction loss and thermal stress. • Test points can be placed on signal pin for monitoring during testing. • Place high frequency ceramic input and output capacitors next to the VIN, PGND and VOUT pins to minimize high frequency noise. • Place a dedicated power ground layer underneath the unit. • To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. • Do not put vias directly on the pad, unless they are capped. • Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND to PGND underneath the unit. Figure 20 gives a good example of the recommended layout. VIN PGND 7 6 5 4 3 CNTRL 2 1 A B C CNTRL D E F G H J K L COUT COUT VOUT 4618 F20 M Figure 20. Recommended PCB Layout Example 4618f 19 LTM4618 TYPICAL APPLICATIONS 31.6k VIN 6V TO 26.5V INTVCC VIN COMP LTM4618 TK/SS RUN SGND PGND 4618 F21 MODE/PLLIN CIN 10μF 2 C1 0.1μF EXTVCC FREQ VOUT VFB PGOOD 10k VOUT COUT 2.5V/6A 100μF 3 C2 47pF 28.7k VIN R1 VIN • R2 1.22V R1 R2 UVLO FUNCTION R2 Figure 21. Typical 6V to 26.5V Input, 2.5V at 6A Design, 500kHz Operation CLOCK SYNC 0° PHASE VIN 6V TO 26.5V PGOOD VIN CIN1 10μF COMP LTM4618 TK/SS C3 ON/OFF 0.47μF C5 0.1μF V+ OUT1 LTC6908-1 OUT2 GND SET MOD CIN2 10μF PGOOD VIN COMP LTM4618 WITH CLOCK SYNC, SOFT-START THE REGULATOR FOR APPROXIMATELY 100ms TK/SS RUN SGND VFB INTVCC PGND EXTVCC 4618 F22 MODE/PLLIN FREQ VOUT VFB INTVCC PGND EXTVCC C4 47pF R4 14.3k VOUT 2.5V/12A COUT 100μF 4 RUN SGND R5 165k CLOCK SYNC 180° PHASE MODE/PLLIN FREQ VOUT 2-PHASE OSCILLATOR 100ms • 2 • 1.3μA C3 0.8V Figure 22. Two LTM4618 Parallel, 2.5V at 12A Design 4618f 20 R6 68.1k 48V INPUT ISOLATED INTERMEDIATE BUS C7 100μF 35V OPT CLOCK SYNC 1 4-PHASE OSCILLATOR CLOCK SYNC 3 MODE/PLLIN FREQ VOUT LTM4618 TK/SS R1 11.5k ON/OFF RUN SGND INTVCC PGND EXTVCC R9 28.7k VFB TK/SS COUT1 100μF C1 47pF LTM4618 VFB R8 60.4k COMP VOUT1 5V/6A CIN3 10μF VOUT VOUT1 FREQ C3 47pF R3 28.7k PGOOD VIN PGOOD VIN COMP MODE/PLLIN + SET V+ U5 MOD DIV LTC6902 GND PH OUT4 OUT1 OUT3 OUT2 C8 0.1μF TYPICAL APPLICATIONS VIN 6V to 26.5V CIN1 10μF C6 ON/OFF 0.22μF RUN SGND INTVCC PGND EXTVCC VOUT3 2.5V/6A COUT3 100μF 3 CLOCK SYNC 2 MODE/PLLIN FREQ VOUT LTM4618 TK/SS RUN SGND R2 19.1k R11 48.7k VFB COUT2 100μF 2 C2 22pF R10 60.4k VOUT2 3.3V/6A VOUT1 CIN4 10μF PGOOD VIN COMP PGOOD VIN COMP CLOCK SYNC 4 MODE/PLLIN FREQ VOUT LTM4618 TK/SS RUN SGND VFB INTVCC PGND EXTVCC C4 47pF R4 48.7k VOUT4 1.8V/6A COUT4 100μF 3 VOUT1 R5 60.4k CIN2 10μF R1 19.1k INTVCC PGND EXTVCC 4618 F23 Figure 23. 4-Phase, Four Outputs (5V, 3.3V, 2.5V and 1.8V) with Tracking LTM4618 21 4618f LTM4618 PACKAGE PHOTOGRAPH PACKAGE DESCRIPTION Pin Assignment Tables (Arranged by Pin Function) PIN NAME A1 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 C1 C2 C3 C4 C5 C6 C7 N/C FREQ MODE/PLLIN PGND VIN VIN VIN TK/SS RUN SGND PGND VIN VIN VIN COMP SGND SGND EXTVCC VIN VIN VIN D1 D2 D3 D4 D5 D6 D7 E1 E2 E3 E4 E5 E6 E7 F1 F2 F3 F4 F5 F6 F7 PIN NAME VFB PGOOD INTVCC PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND G1 G2 G3 G4 G5 G6 G7 H1 H2 H3 H4 H5 H6 H7 J1 J2 J3 J4 J5 J6 J7 PIN NAME PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND VOUT VOUT VOUT VOUT PGND PGND PGND K1 K2 K3 K4 K5 K6 K7 L1 L2 L3 L4 L5 L6 L7 M1 M2 M3 M4 M5 M6 M7 PIN NAME VOUT VOUT VOUT VOUT PGND SW PGND VOUT VOUT VOUT VOUT PGND PGND PGND VOUT VOUT VOUT VOUT PGND PGND PGND 4618f 22 LGA Package 84-Lead (15mm × 9mm × 4.32mm) (Reference LTC DWG # 05-08-1842 Rev Ø) DETAIL A 4.22 – 4.42 aaa Z 7 6 5 4 3 2 1 DIA (0.630) PAD 1 A B C D E 12.70 BSC PAD “A1” CORNER 4 F G H PACKAGE DESCRIPTION 15.00 BSC MOLD CAP SUBSTRATE 0.27 – 0.37 3.95 – 4.05 DETAIL B Z bbb Z J K L M X Y DETAIL B eee S X Y 0.630 ±0.025 SQ. 83x 3 CHAMFER 0.22 45° 7.620 BSC 9.00 BSC 1.27 BSC PADS SEE NOTES 3 aaa Z PACKAGE TOP VIEW PACKAGE BOTTOM VIEW 0.315 0.315 3.810 2.540 1.270 0.000 1.270 2.540 3.810 DETAIL A 6.985 5.715 4.445 3.175 1.905 0.635 0.000 0.635 1.905 3.175 4.445 5.715 6.985 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3 4 LAND DESIGNATION PER JESD MO-222 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE COMPONENT PIN “A1” Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 84 LTMXXXXXX μModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION LGA 84 0409 REV Ø SYMBOL TOLERANCE 0.15 aaa bbb 0.10 eee 0.05 LTM4618 23 SUGGESTED PCB LAYOUT TOP VIEW 4618f LTM4618 TYPICAL APPLICATION 5V Input, 2.5V at 6A Design, 500kHz Operation 31.6k VIN 5V 4.5V ≤ VIN ≤ 6V INTVCC VIN COMP LTM4618 TK/SS RUN SGND PGND 4618 TA02 MODE/PLLIN CIN 10μF 2 C1 0.1μF EXTVCC FREQ VOUT VFB PGOOD 10k VOUT COUT 2.5V/6A 100μF 3 C2 47pF 28.7k VIN R1 VIN • R2 R1 R2 1.22V R2 UVLO FUNCTION RELATED PARTS PART NUMBER LTM4603 LTM4604A LTM4608A LTM4612 LTM4619 LTM8025 DESCRIPTION 6A DC/DC μModule Regulator with PLL and Output Tracking/Margining 4A DC/DC μModule Regulator 8A DC/DC μModule Regulator 36VIN DC/DC μModule Regulator Dual 4A DC/DC μModule Regulator 36VIN, 3A DC/DC μModule Regulator COMMENTS 4.5V to 20V Input, 0.6V to 5V Output, 15mm × 15mm × 2.8mm LGA Package 2.375V to 5.5V Input, 0.8V to 5V Output, Tracking 2.7V to 5.5V Input, 0.6V to 5V Output, PLL, Tracking 4.5V to 36V Input, 3.3V to 15V Output, PLL, Tracking, Margining 4.5V to 26.5V Input, Dual 0.8V to 5V Output, PLL, Tracking 3.6V ≤ VIN ≤ 36V; 0.8V ≤ VOUT ≤ 24V; 9mm × 15mm × 4.32mm LGA Package 4618f 24 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0710 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2010