L2340

L2340 DEVICES INCORPORATED Digital Synthesizer L2340 DEVICES INCORPORATED Digital Synthesizer DESCRIPTION The L2340 is a digital synthesizer that performs waveform synthesis, modulation, and demodulation. The L2340 automatically generates quadrature matched pairs of 16-bit sine and cosine waves in DACcompatible 16-bit offset binary format with15-bit amplitude and 32-bit phase inputs. Output waveforms can be phase or frequency modulated. Digital output frequencies are restricted to the Nyquist limit. Functional Description The L2340 converts Polar (Phase and Magnitude) data into Rectangular (Cartesian) coordinates. The user selects the numeric format. A valid transformed result is seen at the output after 22 clock cycles and will continue upon every clock cycle thereafter. 15-bit amplitude and 32-bit phase data are input into the L2340 to produce an output of 16-bit rectangular data. The user may select the data format to either 16-bit offset binary or 15-bit unsigned magnitude format. High accuracy phase increment values with minimal accumulation error is accomplished by use of a 32-bit phase accumulator. The phase accumulator structure supports frequency or phase modulation and is selected by ENP1-0 and accumulator controls FM and PM. FEATURES u Digital Waveform Synthesis at 50 MHz u 24-Bit Polar Phase Angle Accuracy u User-selectable Waveform Synthesis, Frequency Modulation, or Phase Modulation. u Amplitude Input for Amplitude Modulation and Gain Adjustment. u Replaces TRW/Raytheon/Fairchild TMC2340A u 120-pin PQFP L2340 BLOCK DIAGRAM ENA AM 14-0 ENP 1-0 PH 31-0 15 2 32 16 OEI Digital Synthesizer 16 I 15-0 FM PM OBIQ OEQ Q 15-0 CLK Special Arithmetic Functions 1 08/16/2000–LDS.2340-E L2340 DEVICES INCORPORATED Digital Synthesizer Outputs I15-0 — x-coordinate Data Output ENP1-0 32 M AM C 2 FM PM L2340 FUNCTIONAL BLOCK DIAGRAM AM14-0 15 ENA 32 PH31-0 I15-0 is the 16-bit Cartesian x-coordinate Data output port. When OEI is HIGH, I15-0 is forced into the highimpedance state. I15 is forced HIGH if OBIQ is LOW. Q15-0 — y-coordinate Data Output 32 PM 32 Q15-0 is the 16-bit Cartesian y-coordinate Data output port. When OEQ is HIGH, Q15-0 is forced into the highimpedance state. Q15 is forced HIGH if OBIQ is LOW. Controls ENA — Amplitude Modulation Data Input Enable FM 24 15 32 15 OBIQ 16 * TRANSFORM PROCESSOR 24 16 When ENA is HIGH, AM is latched into the input register on the rising edge of clock. When ENA is LOW, the value stored in the register is unchanged. OEQ 16 OEI 16 ENP1-0 — Phase Modulation Data Input Control ENP1-0 is the 2-bit Phase Modulation Data Input Control that determines one of the four modes shown in Table 1. ‘M’ is the Modulation Register and ‘C’ is the Carrier Register as shown in the Functional Block Diagram. I15-0 Q15-0 * REQUIRES 18 CYCLES TO COMPLETE AND IS FULLY PIPELINED SIGNAL DEFINITIONS Power Vcc and GND +5V power supply. All pins must be connected. Clock CLK — Master Clock The rising edge of CLK strobes all enabled registers. Inputs AM14-0 — Amplitude Modulation Data Input AM14-0 is the 15-bit Amplitude Modulation Data input port. AM14-0 is latched on the rising edge of CLK. PH31-0 — Phase Angle Data Input PH31-0 is the 32-bit Phase Angle Data input port. Input phase accumulators are loaded through this port into registers enabled by ENP1-0. PH31-0 is latched on the rising edge of CLK. TABLE 1. REGISTER OPERATION ENP1-0 Configuration 00 01 10 11 No registers enabled, current data held M register input enabled, C data held C register input enabled, M data held M register = 0, C register input enabled TABLE 2. ACCUMULATOR CONTROL FM PM Configuration 0 0 1 1 0 No accumulation (normal operation) 1 PM accumulator path enabled 0 FM accumulator path enabled 1 Logical OR of PM and FM (Nonsensical) Special Arithmetic Functions 2 08/16/2000–LDS.2340-E L2340 DEVICES INCORPORATED Digital Synthesizer OBIQ — Data Input/Output Format Select When OBIQ is HIGH, offset binary format is selected. When OBIQ is LOW, unsigned format is selected. OEI — x-coordinate Data Output Enable When OEI is LOW, I15-0 is enabled for data output. When OEI is HIGH, I15-0 is placed in a high-impedance state. OEQ — y-coordinate Data Output Enable When OEQ is LOW, Q15-0 is enabled for data output. When OEQ is HIGH, Q15-0 is placed in a high-impedance state. FM, PM — Frequency Modulation, Phase Modulation Control FM and PM is the 2-bit Frequency Modulation/Phase Modulation Control that determines one of the four modes shown in Table 2. When full-scale is exceeded, the accumulator will roll over correctly allowing continuous phase accumulation through 2π radians. FIGURE 1A. INPUT FORMATS AM PH (RTP = 0) Fract. Unsigned Mag./Two's Comp. 31 30 29 *±20 2–1 2–2 210 2–29 2–30 2–31 Integer Unsigned Magnitude 14 13 12 214 213 212 210 22 21 20 *±20 denotes two's complement sign or highest magnitude bit. Since phase angles are modulo 2π 32 and phase accumulator is modulo 2 , this bit may be regarded as ±π. FIGURE 1B. OUTPUT FORMATS I Integer Unsigned Magnitude (OBIQ = 0) 14 13 12 214 213 212 210 22 21 20 14 13 12 214 213 212 210 22 21 20 Q Offset Binary (OBIQ = 1) 15 14 13 NS 214 213 210 22 21 20 15 14 13 NS 214 213 210 22 21 20 NS denotes negative sign. (i.e. '1' negates the number) Special Arithmetic Functions 3 08/16/2000–LDS.2340-E L2340 DEVICES INCORPORATED Digital Synthesizer error will introduce noise when performing waveform sythesis, modulation, and demodulation. Data values for Figure 2 and Figure 3 are shown in Table 3. By looking at these values, we observe the step resolution on a 16-bit internal processor is not 1 unit in the x and y. In most cases, the minimum step resolution is 2 units in the x and y. On the other hand, step resolution on a 24-bit internal processor is 1 unit in the x and y thus resulting in greater accuracy. The minimum theoretical angle resolution that could be produced is 0.00175° when x = 7FFFH and y = 1H. A 16-bit internal processor can produce a minimum angle resolution of only 0.00549° and will not be able to properly calculate the theoretical minimum angle resolution. On the other hand, a 24-bit internal processor can produce a minimum angle resolution of 0.00002° and could therefore properly calculate the theoretical minimum angle resolution. Circle Test When performing a coordinate transformation, inaccuracies are introduced by a combination of quantization and approximation errors. The accuracy of a coordinate transformer is dependent on the word length used for the input variables, the word length used for internal calculations, as well as the number of iterations or steps performed. Truncation errors are due to the finite word length and approximation errors are due to the finite number of iterations. For example, in the case of performing a polar-to-rectangular transformation, the accuracy of the rotation will be determined by how closely the input rotation angle was approximated by the summation of sub-rotation angles. In this study, we compare how accurately a coordinate transformer with a 16-bit internal processor versus a 24-bit internal processor can calculate all the coordinates of a circle. By setting the radius to 7FFFH, θ is incremented using the accumulator of the L2340 in steps of 0000 4000H until all the points of a full circle are calculated into rectangular coordinates. The resulting rectangular coordinates were plotted and graphed. A graphical representation of the resulting vectors for both 16-bit and 24-bit internal processors are compared at 45°. Theoretically, a perfect circle is the desired output but when the resulting vectors from a coordinate transformer with 16-bit internal processor are graphed and displayed as shown in Figure 2, we see significant errors due to the inherent properties of a digital synthesizer. In comparison, the 24bit internal processor proves to be significantly more accurate than a 16-bit internal processor due to minimization of truncation errors. In many applications, this margin of FIGURE 2. SOR) CIRCLE TEST RESULT NEAR 45° (16-BIT INTERNAL PROCES23200 23190 23180 Y 23170 23160 23150 23140 23140 23150 23160 23170 23180 23190 23200 X FIGURE 3. SOR) CIRCLE TEST RESULT NEAR 45° (24-BIT INTERNAL PROCES23200 23190 23180 Y 23170 23160 23150 23140 23140 23150 23160 23170 23180 23190 23200 X Special Arithmetic Functions 4 08/16/2000–LDS.2340-E L2340 DEVICES INCORPORATED Digital Synthesizer TABLE 3. RESULTANT DATA VALUES OF CIRCLE TEST NEAR 45° 16-bit Internal Processor x 23201 23199 23199 23199 23199 23197 23197 23197 23197 23195 23195 23195 23195 23192 23192 23192 23192 23190 23190 23190 23190 23187 23187 23187 23187 23185 23185 23185 23185 23183 x (HEX) 5AA1 5A9F 5A9F 5A9F 5A9F 5A9D 5A9D 5A9D 5A9D 5A9B 5A9B 5A9B 5A9B 5A98 5A98 5A98 5A98 5A96 5A96 5A96 5A96 5A93 5A93 5A93 5A93 5A91 5A91 5A91 5A91 5A8F y 23139 23141 23141 23141 23141 23143 23143 23143 23143 23145 23145 23145 23145 23148 03148 23148 23148 23150 23150 23150 23150 23152 23152 23152 23152 23154 23154 23154 23154 23156 y (HEX) 5A63 5A65 5A65 5A65 5A65 5A67 5A67 5A67 5A67 5A69 5A69 5A69 5A69 5A6C 5A6C 5A6C 5A6C 5A6E 5A6E 5A6E 5A6E 5A70 5A70 5A70 5A70 5A72 5A72 5A72 5A72 5A74 24-bit Internal Processor x 23199 23198 23198 23197 23197 23196 23196 23195 23194 23194 23194 23193 23192 23191 23191 23191 23190 23189 23189 23189 23188 23187 23186 23186 23186 23185 23184 23184 23184 23183 x (HEX) 5A9F 5A9E 5A9E 5A9D 5A9D 5A9C 5A9C 5A9B 5A9A 5A9A 5A9A 5A99 5A98 5A97 5A97 5A97 5A96 5A95 5A95 5A95 5A94 5A93 5A92 5A92 5A92 5A91 5A90 5A90 5A90 5A8F y 23140 23141 23141 23142 23142 23143 23143 23144 23145 23145 23145 23146 23147 23148 23148 23148 23149 23150 23150 23150 23151 23152 23153 23153 23153 23154 23155 23155 23155 23156 y (HEX) 5A64 5A65 5A65 5A66 5A66 5A67 5A67 5A68 5A69 5A69 5A69 5A6A 5A6B 5A6C 5A6C 5A6C 5A6D 5A6E 5A6E 5A6E 5A6F 5A70 5A71 5A71 5A71 5A72 5A73 5A73 5A73 5A74 Special Arithmetic Functions 5 08/16/2000–LDS.2340-E L2340 DEVICES INCORPORATED Digital Synthesizer MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ............................................................................... –0.5 V to V CC + 0.5 V Signal applied to high impedance output ...................................................................... –0.5 V to VCC + 0.5 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Active Operation, Commercial Active Operation, Military Temperature Range (Ambient) 0°C to +70°C –55°C to +125°C Supply Voltage 4.75 V ≤ VCC ≤ 5.25 V 4.50 V ≤ VCC ≤ 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol VOH VOL VIH VIL IIX IOZ ICC1 ICC2 CIN COUT Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Current Output Leakage Current VCC Current, Dynamic VCC Current, Quiescent Input Capacitance Output Capacitance (Note 3) Test Condition VCC = Min., IOH = –2.0 mA VCC = Min., IOL = 4.0 mA Min 2.4 Typ Max Unit V 0.4 2.0 0.0 VCC 0.8 ±10 ±10 95 5 10 10 V V V µA µA mA mA pF pF Ground ≤ VIN ≤ VCC (Note 12) Ground ≤ VOUT ≤ VCC (Note 12) (Notes 5, 6) (Note 7) TA = 25°C, f = 1 MHz TA = 25°C, f = 1 MHz Special Arithmetic Functions 6 08/16/2000–LDS.2340-E 32109876543210987654321 32109876543210987654321 32109876543210987654321 32109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 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Max 15 15 25 13 13 22 Special Arithmetic Functions Min Min 25 25 7 7 2 0 9 8 7 7 L2340– 25* L2340– 25* Digital Synthesizer Max Max 14 14 20 13 13 18 Min Min 08/16/2000–LDS.2340-E 20 20 6 6 1 7 1 7 6 6 20* 20 L2340 Max Max 18 16 13 13 13 13 L2340 DEVICES INCORPORATED Digital Synthesizer NO ACCUMULATION 1 tH tPWH tCYC 00 00 00 SWITCHING WAVEFORMS: 0 CLK 2 3 22 23 24 tPWL tS OBIQ FM, PM ENA ENP1-0 AM14-0 PH31-0 I15-0 Q15-0 EN EN EN A B C tD f(A) f(B) SWITCHING WAVEFORMS: 0 CLK 1 PHASE MODULATION 2 3 4 22 23 24 25 OBIQ FM, PM 00 01 01 01 01 ENA AM14-0 R ENP1-0 10 01 01 01 01 PH31-0 I15-0 Q15-0 C I J K L C+I 2C + J 3C + K 4C + L Special Arithmetic Functions 8 08/16/2000–LDS.2340-E L2340 DEVICES INCORPORATED Digital Synthesizer NOTES 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of I OH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Never- used. Parasitic capacitance is 30 pF theless, conventional precautions minimum, and may be distributed. should be observed during storage, handling, and use of these circuits in This device has high-speed outputs caorder to avoid exposure to excessive pable of large instantaneous current electrical stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping testing of this device. The following of transient undershoot and overshoot. measures are recommended: Input levels below ground or above VCC will be clamped beginning at – a. A 0.1 µF ceramic capacitor should be 0.6 V and VCC + 0.6 V. The device can installed between VCC and Ground withstand indefinite operation with in- leads as close to the Device Under Test puts in the range of –0.5 V to +7.0 V. (DUT) as possible. Similar capacitors Device operation will not be adversely should be installed between device VCC affected, however, input current levels and the tester common, and device ground and tester common. will be well in excess of 100 mA. 4. Actual test conditions may vary b. Ground and VCC supply planes from those designated but operation is must be brought directly to the DUT guaranteed as specified. socket or contactor fingers. 5. Supply current for a given application c. Input voltages should be adjusted to can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter6. Tested with all outputs changing ev- nal system must supply at least that ery cycle and no load, at a 20 MHz clock much time to meet the worst-case requirements of all parts. Responses from rate. the internal circuitry are specified from 7. Tested with all inputs within 0.1 V of the point of view of the device. Output VCC or Ground, no load. delay, for example, is specified as a 8. These parameters are guaranteed maximum since worst-case operation of any device always provides data within but not 100% tested. that time. N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT DUT S1 IOL CL IOH VTH FIGURE B. THRESHOLD LEVELS tENA OE Z 0 1.5 V 1.5 V 1.5 V tDIS 3.5V Vth VOL* 0.2 V 0 1 Z Z 1.5 V VOH* 0.2 V Z 1 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA Special Arithmetic Functions 9 08/16/2000–LDS.2340-E L2340 DEVICES INCORPORATED Digital Synthesizer ORDERING INFORMATION Q5 Q6 GND Q7 Q8 Q9 GND Q10 Q11 Q12 VCC Q13 Q14 Q15 GND GND I0 I1 VCC I2 I3 I4 GND I5 I6 I7 GND I8 I9 VCC 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 VCC Q4 Q3 GND Q2 Q1 Q0 VCC OEQ GND GND CLK GND OBIQ ENP0 GND ENP1 PM FM VCC PH0 PH1 PH2 PH3 PH4 PH5 PH6 GND PH7 PH8 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 120-pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Top View I10 I11 GND I12 I13 I14 VCC I15 GND OEI VCC GND AM14 AM13 GND AM12 AM11 AM10 AM9 AM8 AM7 AM6 GND AM5 AM4 AM3 GND AM2 AM1 VCC Speed 0°C to +70°C — COMMERCIAL SCREENING 20 ns L2340QC20 GND PH9 PH10 VCC PH11 PH12 PH13 PH14 PH15 PH16 PH17 VCC PH18 PH19 PH20 GND PH21 PH22 PH23 VCC PH24 PH25 PH26 PH27 PH28 PH29 PH30 PH31 ENR AM0 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Plastic Quad Flatpack (Q1) Special Arithmetic Functions 10 08/16/2000–LDS.2340-E 121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 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PH30 GND PH9 PH7 PH4 PH1 FM Q0 Q2 Q4 Q7 2 PH11 PH13 PH16 PH18 PH20 PH23 PH25 PH28 GND GND GND VCC VCC VCC CLK PH3 Q6 Q8 3 GND VCC Q10 Q9 4 Ceramic Pin Grid Array (G4) Discontinued Package Top View Through Package (i.e., Component Side Pinout) YPI14 GND Q11 Q12 5 KEY 11 VCC VCC Q13 Q14 6 GND GND GND Q15 7 VCC VCC I1 I0 8 PH27 PH31 GND I3 I2 9 GND Special Arithmetic Functions 10 I5 I4 GND GND GND AM12 AM13 GND ENA AM9 VCC VCC VCC VCC 11 I7 I6 AM10 AM11 GND AM14 GND AM1 AM3 AM5 AM7 12 I14 I11 I9 I8 Digital Synthesizer AM0 AM2 AM4 AM6 AM8 OEI 13 I15 I13 I12 I10 08/16/2000–LDS.2340-E L2340