L9D112G80BG4E8

P reLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) FEATURES DDR SDRAM Data Rate = 200, 250, 266, and 333 Mbps Package: • 25mm x 25mm, Encapsulated Plastic Ball Grid array (PBGA), 219 balls, 1.27mm pitch. 2.5V ±0.2V Core Power supply 2.5V ±0.2V I/O Power supply (SSTL_2 compatible) Differential Clock inputs (CLKx, CLKx\) Commands entered on each positive CLKx edge Internal pipelined double-datarate (DDR) Architecture; two data accesses per clock cycle Programmable Burst Length: 2, 4, or 8 Bidirectional data strobe (DQSLx, DQsHx) per byte transmitted/ received with data i.e. source-synchronous data capture DQS edge-aligned with data for READ; center-aligned with data for WRITE DLL to align DQx and DQSLx, DQSHx transitions with CLKx Four internal banks for concurrent operation One data mask per byte, IMOD contains (10) bytes Programmable IOL/IOH Option Auto PRECHARGE option Auto REFRESH and SELF REFRESH Modes Available in INDUSTRIAL, EXTENDED and Mil-Temp ranges Organized as 16M x 72/80 Weight: LOGIC Devices, Inc. L9D112G80BG4 = 2.75 grams typical Benefits 53% SPACE savings vs. Monolithic, TSOPII-66 solution Reduced I/O routing (34%) Reduced trace length providing improved/reduced parasitic capacitance Impedance matched (60ohm) packaging High TCE organic laminate interposer Suitable for High Reliability applications Upgradable to 32M x 72/80: L9D125G80BG4 *Note: This integrated product and/or its specifications are subject to change without notice. Latest document should be retrieved from LDI prior to your design consideration. MONOLITHIC SOLUTION O P T I O N S AREA I/O 11.9 11.9 11.9 11.9 11.9 IMOD SOLUTION S A V I N G S 25mm 25mm 22.3 5 X 265mm = 1328mm PLUS 5 X 66 pins = 320 pins total 625mm 219 Balls/Locations 53% 34% LOGIC Devices Incorporated www.logicdevices.com 1 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) L9D112G80BG4, DDR1 SIGNAL LOCATION DIAGRAM 1 A B C D E F G H J K L M N P R T DQ1 DQ3 DQ6 DQ7 CAS0\ CS0\ VSS VSS CLK3\ NC DQ56 DQ57 DQ60 DQ62 VSS 2 DQ0 DQ2 DQ4 DQ5 DQML0 WE0\ RAS0\ VSS VSS CKE3 CLK3 DQMH3 DQ58 DQ59 DQ61 DQ63 3 DQ14 DQ12 DQ10 DQ8 VCC VCC VCC VCC VCC VCC VCC VCC DQ55 DQ53 DQ51 DQ49 4 DQ15 DQ13 DQ11 DQ9 5 VSS VSS VCC VCCQ 6 VSS VSS VCC VCCQ 7 A9 A0 A2 A12 8 A10 A7 A5 RFU BA0 9 A11 A6 A4 RFU BA1 10 A8 A1 A3 RFU 11 VCCQ VCC VSS VSS 12 VCCQ VCC VSS VSS Vref RAS1\ CAS1\ VCC VCC CLK2\ DQSL2 13 DQ16 DQ18 DQ20 DQ22 DQML1 WE1\ CS1\ VSS VSS CKE2 CLK2 DQMH2 DQ41 DQ43 DQ45 DQ47 14 DQ17 DQ19 DQ21 DQ23 VSS VSS VSS VSS VSS VSS VSS VSS DQ40 DQ42 DQ44 DQ46 15 DQ31 DQ29 DQ27 DQ26 NC DQMH1 CLK1\ VCCQ VCCQ RAS2\ WE2\ DQML2 DQ37 DQ36 DQ34 DQ32 16 VSS DQ30 DQ28 DQ25 DQ24 CLK1 CKE1 VCC VCC CS2\ CAS2\ DQ39 DQ38 DQ35 DQ33 VCC A B C D E F G H J K L M N P R T DQMH0 DQSH3 DQSL0 DQSH0 CLK0 CKE0 VCCQ VCCQ CS3\ CAS3\ WE3\ DQ54 DQ52 DQ50 DQ48 DQSL3 CLK0\ VSS VSS DQSL4 RAS3\ DQML3 DQSH4 VSS VCC VCCQ CKE4 CLK4\ VSS VCC VCCQ DQMH4 DQ73 DQ75 DQ77 DQ79 DQSL1 DQSH1 CLK4 DQ72 DQ74 DQ76 DQ78 CAS4\ DQ71 DQ69 DQ67 DQ65 WE4\ DQ70 DQ68 DQ66 DQ64 RAS4\ CS4\ DQML4 DQSH2 VCC VSS VSS VCC VSS VSS 1 2 3 VSS Data IO 4 5 6 7 8 9 10 11 12 13 14 15 Address 16 V + (Core Power) CNTRL V + (I/O Power) NC UNPOPULATED Level REF LOGIC Devices Incorporated www.logicdevices.com 2 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C P reLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) Functional Block Diagram VCCQ VCC VRef VSS A0-A12, BA0-1 A, BA VSS VRef VCC VCCQ DQ 0 • • • DQ 7 DQ 8 • • • DQ 15 DQ 0 • • • DQ 7 DQ 8 • • • DQ 15 CS0\ RAS0\ CAS0\ CKE0 CLK0 CLK0\ WE0\ DQML0 DQMH0 DQSL0 DQSH0 D0 A, BA VSS VRef VCC VCCQ DQ 0 • • • DQ 7 DQ 8 • • • DQ 15 DQ 16 • • • DQ 23 DQ 24 • • • DQ 31 CS1\ RAS1\ CAS1\ CKE1 CLK1 CLK1\ WE1\ DQML1 DQMH1 DQSL1 DQSH1 D1 A, BA VSS VRef VCC VCCQ DQ 0 • • • DQ 7 DQ 8 • • • DQ 15 DQ 32 • • • DQ 39 DQ 40 • • • DQ 47 CS2\ RAS2\ CAS2\ CKE2 CLK2 CLK2\ WE2\ DQML2 DQMH2 DQSL2 DQSH2 D2 A, BA VSS VRef VCC VCCQ DQ 0 • • • DQ 7 DQ 8 • • • DQ 15 DQ 48 • • • DQ 55 DQ 56 • • • DQ 63 CS3\ RAS3\ CAS3\ CKE3 CLK3 CLK3\ WE3\ DQML3 DQMH3 DQSL3 DQSH3 D3 A, BA VSS VRef VCC VCCQ DQ 0 • • • DQ 7 DQ 8 • • • DQ 15 DQ 64 • • • DQ 71 DQ 72 • • • DQ 79 CS4\ RAS4\ CAS4\ CKE4 CLK4 CLK4\ WE4\ DQML4 DQMH4 DQSL4 DQSH4 D4 LOGIC Devices Incorporated www.logicdevices.com 3 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) Pin/Ball locations/DeFinitions anD Functional DescriPtion BGA Locations F4, F16, G5, G15, K1, K12, L2, L13, N6, M8 Symbol Type Description CKX,CKX\ CNTL. Input Clock: CKx and CKx\ are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CKx and negative edge of CKx\. Output data (DQ’s and DQS) is referenced to the crossings of the differential clock inputs. G4, G16, K2, K13, M6 CKEx CNTL. Input Clock Enable: CKE controls the clock inputs. CKE High enables, CKE Low disables the clock input pins. Driving CKE Low provides PRECHARGE POWER-DOWN. CKE is synchronous for POWER-DOWN entry and exit, and for SELF-REFRESH entry CKE is asynchronous for SELF-REFRESH exit and disabling the outputs. CKE must be maintained High throughout READ and WRITE accesses. Input buffers are disabled during POWER-DOWN, input buffers are disabled during SELF-REFRESH. CKE is an SSTL-2 input but will detect an LVCMOS LOW level after VCC is applied. G1, G13, K4, K16, M12 CSX\ CNTL. Input Chip Select: CSx\ enables the COMMAND register(s) of each of the five (5) integrated words. All commands are masked (registered) HIGH with CSx\ driven true. CSx\ provides for external word/bank selection on systems with multiple banks. CSx\ is considered part of the COMMAND CODE. F12, G2, K15, L5, M11 F1, G12, L4, L16, M9 F2, F13, L15, M4, M10 E2, E4, E13, F15, M2, RASX\ CASX\ WEX\ DQMLX, CNTL. Input Row Address Strobe: Command input along with CASx\ and WEx\ CNTL. Input Column Address Strobe: Command input along with RASx\ and WEx\ CNTL. Input WRITE (word): Command input along with CASx\ and RASx\ CNTL. Input Input Data Mask: DQM is an input mask signal for WRITE operations. Input Data is masked when DQML/Hx is sampled HIGH at time of a WRITE access DQML/Hx is sampled on both edges of DQSL/Hx. M5, M7, M13, M15, N11 DQMHX E5, E6, E7, E10, E11, F5, K5, L12, N5, N12 E12 DQSLX, DQSHX Vref Level REF Input Data Strobe: Output flag on READ data and Input flag on WRITE data. DQS is edge-aligned with READ data, centered in WRITE data operations. Reference Voltage Address input: Provide the ROW address for ACTIVE commands and the COLUMN address and AUTO PRE-CHARGE bit (A10) for READ/WRITE commands to select one location out of the total array within a selected bank A10 sampled during a PRE-CHARGE command determines whether the PRE-CHARGE applies to one bank or all banks. The address inputs also provide the OP-CODE during a MODE REGISTER SET command. A7, A8, A9, A10, B7, B8, A0-A12 B9, B10, C7, C8, C9, C10, D7 E8, E9 BA0, BA1 Input Bank Address input: define which BANK is active during a READ, WRITE, or PRE-CHARGE command. LOGIC Devices Incorporated www.logicdevices.com 4 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C P reLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) Pin/Ball locations/DeFinitions anD Functional DescriPtion continueD BGA Locations D8, D9, D10 A2, A3, A4, A13, A14, A15, B1, B2, B3, B4, B13, B14, B15, B16, C1, C2, C3, C4, C13, C14, C15, C16, D1, D2, D3, D4, D13, D14, D15, D16, E1, E16, M1, M16, N1, N2, N3, N4, N7, N8, N9, N10, N13, N14, N15, N16, P1, P2, P3, P4, P7, P8, P9, P10, P13, P14, P15, P16, R1, R2, R3, R4, R7, R8, R9, R10, R13, R14, R15, R16, T2, T3, T4, T7, T8, T9, T10, T13, T14, T15 B11, B12, C5, C6, E3, F3, G3, H3, H12, H16, J3, J12, J16, K3, L3, M3, P11, P12, R5, R6, T16 A11, A12, D5, D6, H4, H15, J4, J15, T5, T6 A5, A6, A16, B5, B6, C11, C12, D11, D12, E14, F14, G14, H1, H2, H5, H13, H14, J1, J2, J5, J13, J14, K14, L14, M14, P5, P6, R11, R12, T1, T11, T12 VSS Supply Ground (Digital) VCCQ Supply I/O Power VCC Supply Core Power Symbol RFU Type Input Description Reserved Future Use: Pins reserved for future Address and Bank Select inputs DQ0-DQ79 Input/Output Data I/O LOGIC Devices Incorporated www.logicdevices.com 5 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C P reLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) GENERAL DESCRIPTION The LOGIC Devices, 1.2Gb, DDR SDRAM IMOD, is one member of its Integrated Module family. This family of Integrated memory modules contains DDR3/DDR2 and DDR device definitions in three package footprints including this 25mm2, a 16mm x 22mm package and a 25mm x 32mm footprint. This device, a high speed CMOS random-access, integrated memory device based on use of (5) silicon devices each containing 268,435,456 bits. Each chip is internally configured as a quad-bank SDRAM. Each of the chips 67,108,864 bit banks is organized as 8,192 rows by 512 columns by 16bits. Each of the Silicon devices equates to a WORD or DUAL-BYTES, each BYTE containing Data Mask and Data Strobes. The 1.2Gb DDR IMOD uses the double-data-rate (DDR) architecture to achieve high-speed operation. The double-data-rate architecture is a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle via the I/O pins. A single READ or WRITE access for the 1.2Gb DDR IMOD effectively consists of a single 2n-bit wide, one clock cycle transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock cycle data transfers at the DQ (I/O) pins. A bidirectional data strobe (DQSLx, DQSHx) is transmitted externally, along with data, for use in data capture at the end-point receiver. DQSLx, DQSHx are strobes transmitted by the DDR SDRAM during READ operations and by the memory controller during WRITE operations. Each strobe, DQSLx, DQSHx control each of two bytes contained within each of the (5) silicon chips contained in LDI’s IMOD. The 1.2Gb DDR SDRAM operated from a differential clock (CLKx, CLKx\); the crossing of CLKx going HIGH and CLKx\ going LOW will be referred to as the positive edge of CLK. Commands (address and control signals) are registered at every positive edge of CLK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CLK. READ and WRITE accesses to the DDR memory are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR IMOD provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An AUTO-PRECHARGE function may be enabled to provide a self-timed row PRECHARGE that is initiated at the end of the burst access. The pipelined, multi-banked architecture of the DDR SDRAM architecture allows for concurrent operations, therefore providing high effective bandwidth, by hiding row PRECHARGE and activation time. An AUTO REFRESH mode is provided, along with a power-saving powerdown mode. FUNCTIONAL DESCRIPTION READ and WRITE accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the IMOD must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. INITIALIZATION DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VCC and VCCQ simultaneously, and then to VREF (and to the System VTT). VTT must be applied after VCCQ to avoid device latch-up, which may cause permanent damage to the device. VREF can be applied after VCCQ but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after FREF is applied. CKE during power-up is required to ensure that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a READ access). After all power supply and reference voltages are stable, and the clock is stable, the IMOD requires a 200us delay prior to applying an executable command. Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a LOAD MODE REGISTER command should be issued for the extended mode register (BA1 LOW and BA0 HIGH) to enable the DLL, followed by another LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL and to program the operating parameters. Two-hundred clock cycles are required between the DLL reset and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO PRECHARGE cycles must be performed (tRFC must be satisfied). Additionally, a LOAD MODE REGISTER command for the mode register with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) is required. Following these requirements, the DDR IMOD is ready for normal operation. LOGIC Devices Incorporated www.logicdevices.com 6 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C P reLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) REGISTER DEFINITION moDe register The MODE REGISTER is used to define the specific mode of operation of the DDR IMOD. This definition includes the selection of a burst length, a burst type, a CAS latency as shown in Figure 2 and the operating mode, as shown in Figure 3. The MODE REGISTER is programmed via the MODE REGISTER SET command (with BA0=0 and BA1=0) and will retain the stored information until it is programmed again or the device realizes a loss of power (except for bit A8 which is self clearing). Reprogramming the MODE REGISTER will not alter the contents of the memory, provided it is performed correctly. The MODE REGISTER must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. MODE REGISTER bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A12 specify the operating mode. Burst length READ and WRITE accesses to the DDR IMOD are burst oriented, with the burst length being programmable, as shown in Figure 3. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility issues with future version may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two; by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight. The remaining (least significant) address bits are used to select the starting location within the block. The programmed burst length applies to both the READ and WRITE bursts. Burst tyPe Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1. taBle 1: Burst DeFinition Order of Accesses within a Burst Burst Length 2 Starting Column Address Type = Sequential A0 0 1 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Type = Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Notes 1. For a burst length of two, A1-Ai selects a two-data-element block; A0 selects the starting column within the block. 2. For a burst length of four, A2-Ai selects a four-data-element block; A0-1 selects the starting column within the block. 3. For a burst length of eight, A3-Ai selects an eight-data-element block; A0-2 selects the starting column within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 4 A1 0 0 1 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 8 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 LOGIC Devices Incorporated www.logicdevices.com 7 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C P reLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) READ LATENCY The READ latency is the delay in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks. If a READ command is registered at clock edge [n], and the latency is [m] clocks, the data will be available by clock edge [n+m]. Table 2 indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Table 2 - Cas latency Allowable Operating Frequency (MHz) Speed -10 -8 -75 -6 CAS Latency = 2 ≤83 ≤100 ≤125 NA CAS Latency = 2.5 ≤100 ≤125 ≤133 ≤166 OPERATING MODE The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A12, each set to zero, and bits A0-A6, set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A12, each set to zero, bit A8 set to one, and bits A0-A6, set to the desired values. Although not required, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility from future versions may result. EXTENDED MODE REGISTER The EXTENDED MODE REGISTER controls functions beyond those controlled by the MODE REGISTER; these additional functions are DLL enable/disable, output drive strength, and QFC#. These functions are controlled via the bits shown in Figure 4. The EXTENDED MODE REGISTER command to the MODE REGISTER (with BA0=1, BA1=0) and the register will retain the stored information until it is programmed again or the device realizes loss of power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the MODE REGISTER (BA0=BA1=LOW) to reset the DLL. The EXTENDED MODE REGISTER must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. LOGIC Devices Incorporated www.logicdevices.com 8 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) REGISTER DEFINITION Figure 1 - moDe register DeFinition BA1 BA0 An . . . A9 A 8 A7 A6 A5 A4 A3 A 2 A 1 A 0 Address bus n+2 0 n+1 0 n1 . . . 9 8 7 6 5 4 3 2 1 0 Operating mode CAS Latency BT Burst length Mode register (Mx) Mn + 2 Mn + 1 0 0 1 1 0 1 0 1 Mode Register Definition Base mode register Extended mode register Reserved Reserved M3 0 1 Burst Type Sequential Interleaved M2 M1 M0 Burst Length 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Reserved 2 4 8 Reserved Reserved Reserved Reserved Mn 0 0 – . . . M9 0 0 – 0 0 – M8 0 1 – M7 0 0 – M6–M0 Valid Valid – Operating Mode Normal operation Normal operation/reset DLL All other states reserved M6 0 0 0 0 1 1 1 1 1 1 M5 0 0 1 1 0 0 1 1 M4 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 3 (-5B only) Reserved Reserved 2.5 Reserved Note: 1. n is the most significant row address bit LOGIC Devices Incorporated www.logicdevices.com 9 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) REGISTER DEFINITION Figure 2 - case latency T0 CK# CK Comman d READ NOP CL = 2 DQS DQ NOP NOP T1 T2 T2n T3 T3n CK# CK Comman d T0 T1 T2 T2n T3 T3n READ NOP CL = 2.5 NOP NOP DQS DQ CK# CK Comman d T0 T1 T2 T3 T3n READ NOP CL = 3 NOP NOP DQS DQ Transitioning Data Don ’t Care Note: BL = 4 in the cases shown; shown with nominal t AC, t DQSCK, and t DQSQ. LOGIC Devices Incorporated www.logicdevices.com 10 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) REGISTER DEFINITION Figure 3 - extenDeD moDe register BA1 BA0 An . . . A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus n + 2 n + 1 n1 . . . 9 8 7 6 Operating Mode 0 1 5 4 3 2 10 DS DLL Extended mode register (Ex) E0 Mn + 2 Mn + 1 0 0 1 1 0 1 0 1 Mode Register Definition Base mode register Extended mode register Reserved Reserved 2 E1 0 1 DLL Enable Disable 0 1 Drive Strength Normal Reduced 3 En . . . E9 E8 E7 E6 E5 E4 E3 E2 E1, E0 0 – 0 – 0 – 0 – 0 – 0 – 0 – 0 – 0 – 0 – Valid – Operating Mode Reserved Reserved Notes: 1. n is the most significant row address bit. . 2. The reduced drive strength option is available only on Design Revision F and K. 3. The QFC# option is not supported. outPut Drive strength The normal full drive strength for all outputs are specified to be SSTL2, Class II. The DDR IMOD supports an option for reduced drive. This option is intended for the support of the lighter load and/or point-to-point environments. The selection of the reduced drive strength will alter the DQs and DQSs from SSTL2, Class II drive strength to a reduced drive strength, which is approximately 54% of the SSTL, Class II drive strength. Dll enaBle/DisaBle The DLL must be enabled for normal operation. The DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. When the device exits SELF REFRESH mode, the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. LOGIC Devices Incorporated www.logicdevices.com 11 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) REGISTER DEFINITION commanDs The TRUTH TABLE (below) provides a quick reference of available commands, followed by a written description of each command. truth taBle Name (Function) Deselect (NOP) No Operation (NOP) ACTIVE (select bank and activate row) READ (select bank and column, and start READ burst) WRITE (select bank and column and start WRITE burst) BURST TERMINATE PRECHARGE (deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (enter soft refresh mode) LOAD MODE REGISTER CSx\ H L L L L L L L L RASx\ X H L H H H L L L CASx\ X H H L L H H L L WEx\ X H H H L L L H L ADDR X X Bank/Row Bank/Column Bank/Column X Code X OP Code Notes 1,9 1,9 1,3 1,4 1,4 1,8 1,5 6,7 1,2 truth taBle - Dm oPeration Name (Function) WRITE ENABLE WRITE INHIBIT NOTES: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. A0-A12 define the op-code to be written to the selected MODE REGISTER BA0, BA1 select either the MODE REGISTER or the EXTENDED MODE REGISTER. 3. A0-A12 provide row addresses, and BA0, BA1 provide bank addresses. 4. A0-A8 provide column address; A10 HIGH enables the AUTO PRECHARGE feature (non-persistent), while A10 LOW disables the AUTO PRECHARGE feature; BA0, BA1 provide bank address. 5. A10 LOW; BA0, BA1 determine the bank being PRECHARGED. A10 HIGH all banks PRECHARGED and BA0, BA1 or “Don’t Care”. 6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW. 7. Internal REFRESH counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CLE. 8. Applies only to READ bursts with AUTO PRECHARGE disabled. This command is undefined (and should not be used) for READ burst with AUTO PRECHARGE enabled. 9. DESELECT and NOP are functionally interchangeable. 10. Used to mask WRITE data; provided coincident with the corresponding data. DQMLx, DQMHx L H DQSLx, DQSHx Valid X Notes 1,10 1,10 Deselect The DESELECT function (CSx\=HIGH) prevents new commands from being executed by the DDR IMOD. The IMOD is effectively deselected. Operations already in progress are not affected. LOGIC Devices Incorporated www.logicdevices.com 12 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) REGISTER DEFINITION no oPeration (noP) The NO OPERATION command is used to perform a NOP to the selected DDR Silicon within the IMOD (CSx\=LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Active The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank and the address provided on inputs A0-A12, selects the row. This row remains active (or opens) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. LoaD moDe register The MODE REGISTER is loaded via inputs A0-A12. The LOAD MODE REGISTER command can only be issued when all banks idle and a subsequent executable command cannot be issued until tMRD is met. activating a sPeciFic row in a sPeciFic Bank CK# CK CKE CS # HIGH RAS# CAS# WE# Add ress Row BA0, BA1 Bank Don ’t Care LOGIC Devices Incorporated www.logicdevices.com 13 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) reaD The READ command is used to initiate a burst READ access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A8 selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be PRECHARGED at the end of the READ burst; If AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. reaD commanD CK# CK CKE CS# HIGH RAS# CAS# WE# Address Col EN AP A10 DIS AP BA0, BA1 Bank Don ’t Care Note: EN AP = enable auto precharge DIS AP = disable auto precharge. LOGIC Devices Incorporated www.logicdevices.com 14 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) write The WRITE command is used to initiate a burst WRITE access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A8 selects the starting column location. The value on the input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be AUTO PRECHARGED at the end of the WRITE burst; If AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQ lines is written to the memory array subject to DQMLx, DQMHx for each WORD. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte column location. write commanD CK# CK CKE HIGH CS# RAS# CAS# WE# Address Col EN AP A10 DIS AP BA0, BA1 Bank Don ’t Care Note: EN AP = enable auto precharge DIS AP = disable auto precharge.. LOGIC Devices Incorporated www.logicdevices.com 15 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) Precharge The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank or banks will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Except in the case of concurrent auto PRECHARGE, where a READ or WRITE command to a different bank is allowed as long as it does not violate any other timing parameters. Input A10 determines whether one or all banks are to be PRECHARGED and in the case where only one bank is to be PRECHARGED, inputs BA0, BA1 select the bank. In all other cases BA0, BA1 are treated as “Don’t Care”. Once a bank has been PRECHARGED, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of PRECHARGING. Precharge commanD CK# CK CKE CS# HIGH RAS# CAS# WE# Address All banks A10 One bank BA0, BA1 Bank1 Don ’t Care Note: 1. If A10 is HIGH, bank address becomes “Don’t Care.” auto Precharge AUTO PRECHARGE is a feature which performs the same individual bank PRECHARGE function described prior, but without requiring an explicit command. This is accomplished by using A10 to enable the command/function in conjunction with a specific READ or WRITE command. A PRECHARGE of the bank/ row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. AUTO PRECHARGE is non-persistent in that it is either enabled or disabled for each individual READ or WRITE command. The device supports concurrent AUTO PRECHARGE if the command to the other bank does not interrupt the data transfer to the current bank. AUTO PRECHARGE ensures that the PRECHARGE is initiated at the earliest valid stage within a burst. This earliest valid stage is determined as if an explicit PRECHARGE command was issued at the earliest possible time without violating tRAS (MIN). LOGIC Devices Incorporated www.logicdevices.com 16 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) Burst terminate The BURST TERMINATE command is used to truncate READ bursts. The most recently registered READ command prior to the BURST TERMINATE command will be truncated. The open page which the READ burst was terminated from, remains open. ABsolute maximum ratings Parameter VCC Supply Voltage relative to VSS VCCQ I/O Supply Voltage relative to VSS VREF and inputs Voltage relative to VSS I/O pins Voltage relative to VSS Storage Temperature Short circuit current MIN -1.0V -1.0V -1.0V -0.5V -55 −− MAX +3.6V +3.6V +3.6V VCCQ + 0.5V +150 50 UNITS V V V V C mA Auto reFresh AUTO REFRESH is used during normal operations of the IMOD and is analogous to CASx\-BEFORE-RASx\ (CBR) REFRESH in conventional DRAMs. This command is non-persistent so it must be issued each time a REFRESH is required. The addressing is generated by the internal REFRESH controller. This makes the address bits “Don’t Care” during an AUTO REFRESH command. Each DDR die within the IMOD, requires AUTO REFRESH cycles at an average of 7.8125 us (maximum). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute REFRESH interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR die, meaning that the maximum absolute interval between any AUTO REFRESH command is 9 x 7.8125uS (70.3uS). This maximum absolute interval is to allow future support for DLL updates internal to the DDR SDRAM die. Although not a JEDEC requirement, to provide for future functionality enhancements, CKEx must be active (HIGH) during the AUTO REFRESH period. The AUTO REFRESH period begins when the AUTO REFRESH command is registered and ends tRFC later. CaPacitance Parameter Input Capacitance [CKx\CKx\] Addresses, BA0-1 Input Capacitance [All other Input Pins] DQ line SYMBOL Cl1 CA C12 C10 MAX 5 30 7 8 UNITS pF pF pF pF SelF reFresh The SELF REFRESH command can be used to retain data in the DDR IMOD even if the rest of the system is powered down. When in the SELF REFRESH mode, the DDR IMOD retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKEx is disabled (LOW). The DLL is automatically enabled upon entering SELF REFRESH (200 clock cycles must then occur before a READ command can be issued). Input signals except CLEx are “Don’t Care” during SELF REFRESH. The procedure for exiting SELF REFRESH requires a sequence of commands. First, CLKx must be stable prior to CKEx going back to HIGH. Once CLEx is HIGH, the DDR die must have a NOP command issued for tXSNR, because time is required for the completion of any internal REFRESH in progress. A simple algorithm for meeting both REFRESH and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command. LOGIC Devices Incorporated www.logicdevices.com 17 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) Dc electrical characteristics anD oPerating conDitionsackage outline Dimensions P (notes 1, 6) VCC, VCCQ=+2.5V±0.2V;-55°C≤TA≤+125°C Parameter Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage Input High Voltage Input Low Voltage Input Leakage Current: Any input 0V≤VIN≤VCC, VREF pin 0V≤VIN≤1.35V All other pins not under test = 0V Output Leakage Current: DQ lines disabled; 0V≤VOUT≤VCCQ Full Drive Output Option Reduced Drive Output Option Ambient Operating Temperature Industrial = “I” Extended = “E” Mil-Temp = “M” Symbol VCC VCCQ VREF VTT VIH VIL II MIN 2.3 2.3 0.49 x VCCQ VREF - 0.04 TYP 2.5 2.5 0.50 x VCCQ VREF MAX 2.7 2.7 0.51 x VCCQ VREF + 0.04 UNITS V V V V -2 +2 uA IOZ -5 +5 uA IOH IOL IOH IOL -16.8 +16.8 -9 +9 −− −− −− −− 25 25 25 mA mA mA mA TA TA TA -40 -40 -55 85 105 125 °C °C °C LOGIC Devices Incorporated www.logicdevices.com 18 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) icc oPerating sPeciFication limits anD conDitions (notes 1-5, 10, outline Dimensions Package 12, 14) VCC, VCCQ=+2.5V±0.2V;-55°C≤TA≤+125°C 333 Mbps 266/250 Mbps @CL=2 575 200 Mbps @CL=2 520 Parameter OPERATING current: One bank active - precharge tCL=tCK(MIN), tRC=tRC(MIN), tRAS=tRAS MIN(ICC); DQ, DQM, DQS inputs changing once per clock cycle; Address and Control inputs changing once every two clock cycles OPERATING current: One bank active - READ - precharge current Active-Read-Precharge; Burst=2; tRC=tRC(MIN); tCK=tCK(MIN); IOUT=0mA; Address and control inputs changing once per clock cycle (notes: 22, 48) Precharge POWER-DOWN current All banks idle; POWER-DOWN mode; tCK=tCK(MIN), CKE=LOW (notes: 23, 32, 50) IDLE STANDBY current CS\=HIGH; All banks idle; POWER-DOWN mode; tCK=tCK(MIN); CKE=HIGH; Address and other Control inputs changing once per clock cycle; VSS=VREF for DQ, DQS and DM (note: 51) ACTIVE POWER-DOWN, STANDBY current One bank active; POWER-DOWN mode; tCK=tCK(MIN), CKE=LOW (notes: 23, 32, 50) ACTIVE STANDBY current CS\=HIGH; CKE=HIGH; One bank Active Precharge; tRC=tRAS(MAX); tCK=tCK(MIN); DQ, DQM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per cycle (note: 22) OPERATING current Burst=2 READS Continuous Burst; One bank active; Address and Control inputs changing once per clock cycle; tCK=tCK(MIN); IOUT=0mA cycle (notes: 22, 48) OPERATING current Burst=2 WRITES Continuous Burst; One bank active; Address and Control inputs changing once per clock cycle; tCK=tCK(MIN); DQ, DQM and DQS inputs changing twice per clock cycle (note: 22) AUTO REFRESH current tREF=tRC (MIN) (notes: 27, 50) tREF=7.8125us (notes: 27, 50) =tRC (MIN) SELF REFRESH current; CKE=≤0.2V OPERATING current Four bank interleaving READS (BL=4) with AUTO PRECHARGE; tRC=tRC (MIN); tCK=tCK (MIN); Address and Control inputs change only during ACTIVE READ or WRITE commands (notes: 22, 49) Symbol ICC0 @CL=2.5 625 Units mA ICC1 775 700 650 mA ICC2P 25 25 25 mA ICC2F 225 225 195 mA ICC3P 175 175 150 mA ICC3N 225 225 200 mA ICC4R 350 300 245 mA ICC4W 1250 1025 775 mA ICC5 ICC5A ICC6 ICC7 1450 50 25 2000 1450 50 25 1925 1400 50 25 1700 mA mA mA mA LOGIC Devices Incorporated www.logicdevices.com 19 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) ac electrical sPeciFications anD recommenD oPeratingPackage outline (notes 1-5, 14-17, 33) characteristics Dimensions -6, 333 Mbps 167 MHz, CLKx CL = 2.5 -75, 266 [250]Mbps 133 MHz CLKx CL = 2.5 [2] -8, 250 [200]Mbps 125 MHz CLKx CL = 2.5 [2] -10, 200 [167] Mbps 100 MHz CLKx CL = 2.5 [2] Parameter Access window of DQs from CLKx / CLKx\ CLKx High level Width CLKx Low level Width Clock Cycle Time CL=2.5 CL=2 DQ and DM Input Hold Time relative to DQS DQ and DM Input Setup Time relative to DQS DQ and DM Input Pulse Width Access window of DQs from CLKx / CLKx\ DQS Input HIGH Pulse Width DQS Input LOW Pulse Width DQS-DQ Skew, DQS to last DQ valid, per grp. WRITE command to first DQS latching transition DQS falling edge to CLKx rising - setup time DQS falling edge to CLKx rising - hold time Half Clock period Data-Out HIGH impedance window from CLKx / CLKx\ Data-Out LOW impedance window from CLKx / CLKx\ Address and Control Input hold time Address and Control Input setup time Address and Control Input hold time Address and Control Input setup time Load Mode Register DQ-DQS hold. DQS to first DQ to go non-valid Data Hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with AUTO PRECHARGE command ACTIVE to ACTIVE/AUTO REFRESH command per. AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS READ Preamble DQS READ Postamble ACTIVE bank to ACTIVE bank b command DQS WRITE Preamble DQS READ Preamble Setup Time Symbol tAC tCH tCL tCK tCK tDH tDS tDIPW tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS tDSH tHP tHZ tLZ tIHF tISF tHIS tISS tMRD tQH tQHS tRAS tRAP tRC tRFC tRCD tRP tRPRC tRPST tRRD tWPRC tWPRCS MIN -0.7 0.45 0.45 6 7.5 0.45 0.45 1.75 -0.6 0.35 0.35 MAX 0.7 0.55 0.55 13 13 MIN -0.75 0.45 0.45 7.5 10 0.5 0.5 1.75 MAX 0.75 0.55 0.55 13 13 MIN -0.8 0.45 0.45 8 10 0.6 0.6 2 MAX 0.8 0.55 0.55 13 13 MIN -0.8 0.45 0.45 10 13 MAX 0.8 0.55 0.55 13 15 0.6 0.6 UNITS ns tCLK tCLK ns ns ns ns ns 2 0.8 -0.8 0.35 0.35 0.6 0.6 0.75 0.2 0.2 tCH,tCL 0.8 0.8 -0.8 1.1 1.1 1.1 1.1 16 tHP-tQHS 1 40 20 70 80 20 20 1.1 0.6 0.9 0.4 15 0.25 0 1.1 0.6 120000 1.25 0.8 0.6 -0.75 0.35 0.35 0.75 -0.8 0.35 0.35 ns tCLK tCLK ns tCLK tCLK tCLK ns ns ns ns ns 0.45 0.75 0.2 0.2 tCH,tCL 0.7 -0.70 0.75 0.75 0.8 0.8 12 tHP-tQHS 0.55 42 15 60 72 15 15 0.9 0.4 12 0.25 0 1.1 0.6 70000 40 20 65 75 20 20 0.9 0.4 15 0.25 0 -0.75 0.9 0.9 1 1 1.25 0.75 0.2 0.2 tCH,tCL 0.5 1.25 0.75 0.2 0.2 tCH,tCL 0.75 -0.8 1.1 1.1 1.1 1.1 16 1.25 15 tHP-tQHS 0.75 120000 ns ns ms ms ms ns ns ns ns tCLK tCLK ns tCLK ns tHP-tQHS 1 40 20 70 80 20 20 120000 1.1 0.6 0.9 0.4 15 0.25 0 LOGIC Devices Incorporated www.logicdevices.com 20 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) ac electrical sPeciFications anD recommenD oPeratingPackage outline (notes 1-5, 14-17, 33) characteristics Dimensions -6, 333 Mbps 167 MHz, CLKx CL = 2.5 -75, 266 [250]Mbps 133 MHz CLKx CL = 2.5 [2] -8, 250 [200]Mbps 125 MHz CLKx CL = 2.5 [2] -10, 200 [167] Mbps 100 MHz CLKx CL = 2.5 [2] Parameter DQS WRITE Postamble WRITE Recovery Time Internal WRITE to READ command delay Data Valid Output Window REFRESH to REFRESH command Interval (Industrial) REFRESH to REFRESH command Interval (Extended) REFRESH to REFRESH command Interval (Mil-Temp) Average Periodic REFRESH Interval (Industrial) Average Periodic REFRESH Interval (Extended) Average Periodic REFRESH Interval (Mil-Temp) Terminating delay reference to VDD Exit Self REFRESH to non-READ Command Exit Self REFRESH to READ Command Symbol tWPST tWR tWTR na tREFC tREFC tREFC tREFI tREFI tREFI tVTD tXSNR tXSRD MIN 0.4 12 1 MAX MIN 0.4 15 1 MAX MIN 0.4 15 1 MAX 0.6 MIN 0.4 15 1 MAX 0.6 UNITS tCLK ns tCLK us us us us us us us ns ns tCLK tQH-tDQSQ 70.3 35 7.8 3.9 5.9 3.9 0 75 200 tQH-tDQSQ 70.3 53 35 7.8 5.9 3.9 0 75 200 tQH-tDQSQ 70.3 53 35 7.8 5.9 3.9 0 80 200 tQH-tDQSQ 70.3 53 35 7.8 5.9 3.9 0 80 200 LOGIC Devices Incorporated www.logicdevices.com 21 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) ac sPeciFication notes 1.All voltages referenced to VSS 2.Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and the device operation are guaranteed for the full voltage range specified. 3. Outputs (except for IDD measurements) measured with equivalent load: VTT 50Ω Reference point 30pF V/ns, functionality is uncertain. 16. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. 17. Inputs are not recognized as valid until VREF stabilizes. Once initialized, including self refresh mode, VREF must be powered within specified range. Exception: during the period before VREF stabilizes, CKE < 0.3 × VDD is recognized as LOW. 18. The output timing reference level, as measured at the timing reference point (indicated in Note 3), is VTT. 19. tHZ and tLZ transitions occur in the same access time windows as data valid transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (High-Z) or begins driving (Low-Z). 20. The intent of the “Don’t Care” state after completion of the postamble is the DQS-driven signal should either be HIGH, LOW, or High-Z, and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions HIGH (above VIH[DC] MIN) then it must not transition LOW (below VIH[DC] prior to tDQSH [MIN]). 21. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 22. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 23. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 24. The refresh period is 64ms. This equates to an average refresh rate of 7.8125μs (15.625μs for 128Mb DDR). However, an AUTO REFRESH command must be asserted at least once every 70.3μs (140.6μs for 128Mb DDR); burst refreshing or posting by the DRAM controller greater than 8 REFRESH cycles is not allowed. 25. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device. 26. The data valid window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55, because functionality is uncertain when operating beyond a 45/55 ratio. 27. Referenced to each output group: x4 = DQS with DQ0–DQ3; x8 = DQS with DQ0–DQ7; x16 = LDQS with DQ0–DQ7 and UDQS with DQ8–DQ15. 28. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during the REFRESH command period (tRFC [MIN]), else CKE is LOW (that is, during standby). Output (VOUT) 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1 V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 standard (that is, the receiver will effectively switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. All speeds may not be offered on all device grades. Refer to “Ordering Information” for availability. 7. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may not exceed ±2% of the DC value. Thus, from VDDQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest VREF bypass capacitor. 8. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, it is expected to be set equal to VREF, and it must track variations in the DC level of VREF. 9. VID is the magnitude of the difference between the input level on CK and the input level on CK#. 10. The value of VIX and VMP is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same. 11. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle times. 12. Enables on-chip refresh and address counters. 13. IDD specifications are tested after the device is properly initialized and is averaged at the defined cycle rate. 14. This parameter is sampled. VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100MHz, TA= 25°C, VOUT(DC) = VDDQ/2, VOUT (peak-topeak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 15. For slew rates less than 1 V/ns and greater than or equal to 0.5 V/ns. If the slew rate is less than 0.5 V/ns, timing must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew rate from the 500 mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5 LOGIC Devices Incorporated www.logicdevices.com 22 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) ac sPeciFication notes 29. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). 30. The input capacitance per pin group will not differ by more than this maximum amount for any given device. 31. CK and CK# input slew rate must be ≥1 V/ns (≥2 V/ns if measured differentially). 32. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100 mV/ns reduction in slew rate. 33. VDD must not vary more than 4% if CKE is not active while any bank is active. 34. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount. 35. tHP (MIN) is the lesser of tCL (MIN) and tCH (MIN) actually applied to the device CK and CK# inputs, collectively, during bank active. 36. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN) can be satisfied prior to the internal PRECHARGE command being issued. 37. Any positive glitch must be less than 1/3 of the clock cycle and not more than +400mV or 2.9V, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either –300mV or 2.2V, whichever is more positive. The average cannot be below the +2.5V minimum. 38. Normal output drive curves: a. The full driver pull-down current variation from MIN to MAX process; temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 4. b. The driver pull-down current variation, within nominal voltage and temperature limits, is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 4. c. The full driver pull-up current variation from MIN to MAX process; temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 5. d. The driver pull-up current variation within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 5. e. The full ratio variation of MAX to MIN pull-up and pull-down current should be between 0.71 and 1.4 for drain-to-source voltages from 0.1V to 1.0V at the same voltage and temperature. f. The full ratio variation of the nominal pull-up to pull-down current should be unity ±10% for device drain-to-source 39. Reduced output drive curves: a. The full driver pull-down current variation from MIN to MAX process; temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 6. b. The driver pull-down current variation, within nominal voltage and temperature limits, is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 6. c. The full driver pull-up current variation from MIN to MAX process; temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 7. d. The driver pull-up current variation, within nominal voltage and temperature limits, is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 7. e. The full ratio variation of the MAX-to-MIN pull-up and pulldown current should be between 0.71 and 1.4 for device drain-to-source voltages from 0.1V to 1.0V at the same voltage and temperature. IOUT (mA) Figurevoltages from 0.1V to 1.0V. own characteristics 4 - Full Drive Pull-D 160 140 120 100 80 60 40 20 0 0.0 0.5 1.0 1.5 2.0 2.5 VOUT (V) Figure 5 - Full Drive Pull-uP characteristics 0 -20 -40 -60 IOUT (mA) -80 -100 -120 -140 -160 -180 -200 0.0 0. 5 1.0 1. 5 2.0 2. 5 VDDQ - VOUT (V) LOGIC Devices Incorporated www.logicdevices.com 23 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) ac sPeciFication notes f. The full ratio variation of the nominal pull-up to pull-down current should be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0V. Figure 6 - reDuceD Drive Pull-Down characteristics 80 70 60 50 45. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power-up, even if VDD/VDDQ are 0V, provided a minimum of 42Ω of series resistance is used between the VTT supply and the input pin. 46. The current LDI part operates below 83 MHz (slowest specified JEDEC operating frequency). As such, future die may not reflect this option. 47. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or LOW. 48. Random address is changing; 50% of data is changing at every transfer. 49. Random address is changing; 100% of data is changing at every transfer. 50. CKE must be active (HIGH) during the entire time a REFRESH command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tRFC has been satisfied. 51. IDD2N specifies the DQ, DQS, and DM to be driven to a valid HIGH or LOW logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.” 52. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset followed by 200 clock cycles before any READ command. 53. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20 MHz. Any noise above 20 MHz at the DRAM generated from any source other than that of the DRAM itself may not exceed the DC voltage range of 2.6V ±100mV. 54. The -6 speed grades will operate with tRAS (MIN) = 40ns and tRAS (MAX) = 120,000ns at any slower frequency. IOUT (mA) 40 30 20 10 0 0 .0 0 .5 1. 0 1. 5 2.0 2.5 VOUT (V) Figure 7 - reDuceD Drive Pull-uP characteristics 0 -10 -20 -30 IOUT (mA) -40 -50 -60 -70 -80 0.0 0.5 1.0 1.5 2.0 2.5 VDDQ - VOUT (V) 40. The voltage levels used are derived from a minimum VDD level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 41. VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a pulse width ≤ 3ns, and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = –1.5V for a pulse width ≤ 3ns, and the pulse width can not be greater than 1/3 of the cycle rate. 42. VDD and VDDQ must track each other. 43. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPRE (MAX) condition. 44. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST) or begins driving (tRPRE). LOGIC Devices Incorporated www.logicdevices.com 24 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) AC SWITCHING DIAGRAMS AC Switching diagrams reference 16 bits, LDI’s IMOD contains (5) 16 bit devices totaling 80 bits Figure 8 - reaD Burst CK# CK Command Address T0 T1 T2 T2n T3 T3n T4 T5 READ Bank a , Col n NOP NOP NOP NOP NOP CL = 2 DQS DQ DO n CK# CK Command Address T0 T1 T2 T2n T3 T3n T4 T5 READ Bank a , Col n NOP NOP NOP NOP NOP CL = 2.5 DQS DQ DO n T0 CK# CK Command Address READ Bank a , Col n T1 T2 T3 T3n T4 T4n T5 NOP NOP NOP NOP NOP CL = 3 DQS DQ DO n Transitioning Data Don’t Care Notes: 1. 2. 3. 4. DO n = data-out from column n. BL = 4. Three subsequent elements of data-out appear in the programmed order following DO n. Shown with nominal t AC, t DQSCK, and t DQSQ. LOGIC Devices Incorporated www.logicdevices.com 25 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) AC SWITCHING DIAGRAMS Figure 9 - consecutive reaD Burst CK# CK Command Address T0 T1 T2 T2n T3 T3n T4 T4n T5 T5n READ Bank, Col n NOP READ Bank, Col b NOP NOP NOP CL = 2 DQS DQ DO n DO b CK# CK Command Address T0 T1 T2 T2n T3 T3n T4 T4n T5 T5n READ Bank, Col n NOP READ Bank, Col b NOP NOP NOP CL = 2.5 DQS DQ DO n DO b CK# CK Command Address T0 T1 T2 T3 T3n T4 T4n T5 T5n READ Bank, Col n NOP READ Bank, Col b NOP NOP NOP CL = 3 DQS DQ DO n Transitioning Data DO b Don’t Care Notes: 1. DO n (or b) = data-out from column n (or column b). 2. BL = 4 or BL = 8 (if BL = 4, the bursts are concatenated; if BL = 8, the second burst interrupts the first). 3. Three subsequent elements of data-out appear in the programmed order following DO n. 4. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b. 5. Shown with nominal t AC, t DQSCK, and t DQSQ. 6. Example applies only when READ commands are issued to same device. LOGIC Devices Incorporated www.logicdevices.com 26 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) AC SWITCHING DIAGRAMS Figure 10 - nonconsecutive reaD Burst CK# CK Comman d Add ress T0 T1 T2 T2n T3 T3n T4 T5 T5n T6 READ Bank, Col n NOP NOP READ Bank, Col b NOP NOP NOP CL = 2 DQS DQ DO n DO b CK# CK Comman d Add ress T0 T1 T2 T2n T3 T3n T4 T5 T5n T6 READ Bank, Col n NOP NOP READ Bank, Col b NOP NOP NOP CL = 2.5 DQS DO n DO b DQ CK# CK Comman d Add ress T0 T1 T2 T3 T3n T4 T4n T5 T 6 READ Bank, Col n NOP NOP READ Bank, Col b NOP NOP NOP CL = 3 DQS DQ DO n Transitioning Data DO b Don ’t Care Notes: 1. DO n (or b) = data-out from column n (or column b). 2. BL = 4 or BL = 8 (if BL = 4, the bursts are concatenated; if BL = 8, the second burst interrupts the first). 3. Three subsequent elements of data-out appear in the programmed order following DO n. 4. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b. 5. Shown with nominal t AC, t DQSCK, and t DQSQ. LOGIC Devices Incorporated www.logicdevices.com 27 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) AC SWITCHING DIAGRAMS Figure 11 - ranDom reaD accesses CK# CK Comman d Add ress T0 T1 T2 T2n T3 T3n T4 T4n T5 T5n READ Bank, Col n READ Bank, Col x READ Bank, Col b READ Bank, Col g NOP NOP CL = 2 DQS DQ DO n DO n' DO x DO x' DO b DO b' DO g CK# CK Command Address T0 T1 T2 T2n T3 T3n T4 T4n T5 T5n READ Bank, Col n READ Bank, Col x READ Bank, Col b READ Bank, Col g NOP NOP CL = 2.5 DQS DO n DO n' DO x DO x' DO b DO b' DQ CK# CK Command Address T0 T1 T2 T3 T3n T4 T4n T5 T5n READ Bank, Col n READ Bank, Col x READ Bank, Col b READ Bank, Col g NOP NOP CL = 3 DQS DQ DO n DO n' DO x DO x' DO b DO b' Transitioning Data Don’t Care Notes: 1. 2. 3. 4. 5. DO n (or x or b or g) = data-out from column n (or column x (or column b or column g). BL = 2, BL = 4, or BL = 8 (if BL = 4 or BL = 8, the following burst interrupts the previous). n', x', b', or g' indicate the next data-out following DO n, DO x, DO b, or DO g, respectively. READs are to an active row in any bank . Shown with nominal t AC, t DQSCK, and t DQSQ. LOGIC Devices Incorporated www.logicdevices.com 28 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) AC SWITCHING DIAGRAMS Figure 12 - terminating a reaD Burst T0 CK# CK Command Address READ T1 T2 T2n T3 T4 T5 BST1 NOP NOP NOP NOP Bank a , Col n CL = 2 DQS DQ DO n CK# CK Command Address T0 T1 T2 T2n T3 T4 T5 READ Bank a, Col n BST1 NOP NOP NOP NOP CL = 2.5 DQS DO n DQ T0 CK# CK Command Address READ Bank a, Col n T1 T2 T3 T3n T4 T5 BST1 NOP NOP NOP NOP CL = 3 DQS DQ DO n Transitioning Data Don’t Care Notes: 1. 2. 3. 4. 5. Page remains open. DO n = data-out from column n. BL = 4. Subseqent element of data-out appears in the programmed order following DO n. Shown with nominal t AC, t DQSCK, and t DQSQ. LOGIC Devices Incorporated www.logicdevices.com 29 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) AC SWITCHING DIAGRAMS Figure 13 - reaD to write T0 T1 T2 T2n T3 T4 T4n T5 T5n CK# CK Command Address READ Bank, Col n 1 BST NOP WRITE Bank, Col b NOP NOP CL = 2 DQS DQ DM DO n t DQSS (NOM) DI b CK# CK Command Address T0 T1 T2 T2n T3 T3n T4 T5 T5n READ Bank, Col n 1 BST NOP NOP WRITE Bank, Col b NOP CL = 2.5 DQS DQ DM DO n t DQSS (NOM) DI b CK# CK Command Address T0 T1 T2 T3 T3n T4 T5 T5n READ Bank a, Col n BST1 NOP NOP WRITE NOP CL = 3 DQS DQ DM DO n t DQSS (NOM) DI b Transitioning Data Don’t Care Notes: 1. 2. 3. 4. 5. 6. Page remains open. DO n = data-out from column n; DI b = data-in from column b . BL = 4 (applies for bursts of 8 as well; if BL = 2, the BURST command shown can be NOP). One subsequent element of data-out appears in the programmed order following DO n. Data-in elements are applied following DI b in the programmed order. Shown with nominal t AC, t DQSCK, and t DQSQ. LOGIC Devices Incorporated www.logicdevices.com 30 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) AC SWITCHING DIAGRAMS Figure 14 - reaD to Precharge T0 T1 T2 T2n T3 T3n T4 T5 CK# CK Command Address READ Bank a, Col n NOP PRE Bank a, (a or all ) NOP NOP ACT Bank a, Row CL = 2 DQS DQ DO n t RP CK# CK Command Address T0 T1 T2 T2n T3 T3n T4 T5 READ Bank a, Col n NOP PRE Bank a, (a or all ) NOP NOP ACT Bank a, Row CL = 2.5 DQS DQ DO n t RP CK# CK Command Address T0 T1 T2 T3 T3n T4 T4n T5 READ Bank a, Col n NOP PRE Bank a, (a or all ) NOP NOP ACT Bank a, Row CL = 3 DQS DQ t RP DO n Transitioning Data Don’t Care Notes: 1. Provided (MIN) is met, a READ command with auto precharge enabled would cause a precharge to be performed at x number of clock cycles after the READ command, where x = BL/2. 2. DO n = data-out from column n. 3. BL = 4 or an interrupted burst of 8. 4. Three subsequent elements of data-out appear in the programmed order following DO n. 5. Shown with nominal t AC, t DQSCK, and t DQSQ. 6. READ-to-PRECHARGE equals two clocks, which allows two data pairs of data-out; it is also assumed that t RAS (MIN) is met. 7. An ACTIVE command to the same bank is only allowed if t RC (MIN) is met. t RAS LOGIC Devices Incorporated www.logicdevices.com 31 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) AC SWITCHING DIAGRAMS Figure 15 - Bank reaD without Precharge T0 T1 T2 T3 T4 T5 T5n T6 T6n T7 T8 CK# CK t IS t IH t CK t CH t CL CKE t IS Command t IH ACT t IS Address Row t IH Col n Row 1 NOP 2 READ 1 NOP 3 PRE 1 NOP 1 NOP ACT 1 NOP t IS t IH All banks Row One bank A10 Row t IS t IH 4 BA0, BA1 Bank x t RCD Bank x Bank x 5 Bank x CL = 2 t RP 3 t RAS t RC DM Case 1: t AC (MIN) and t DQSCK(MIN) DQS t LZ (MIN) t RPRE t DQSCK(MIN) t RPST DQ t LZ (MIN) DO n t AC (MIN) Case 2: t AC (MAX) and t DQSCK(MAX) DQS t RPRE t DQSCK (MAX) t RPST DQ DO n t AC (MAX) t HZ (MAX) Transitioning Data Don’t Care Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. BL = 4. 3. The PRECHARGE command can only be applied at T5 if t RAS (MIN) is met. 4. Disable auto precharge. 5. “Don’t Care” if A10 is HIGH at T5. 6. DO n (or b) = data-out from column n (or column b); subsequent elements are provided in the programmed order. LOGIC Devices Incorporated www.logicdevices.com 32 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) AC SWITCHING DIAGRAMS Figure 16 - Data outPut timing – tDQsQ, tQh, anD Data valiD winDow CK# CK t HP1 t HP1 t DQSQ 2 LDQS3 4 t HP1 t DQSQ 2 t HP1 t HP1 t DQSQ 2 t HP1 t DQSQ 2 T1 T2 T2n T3 T3n T4 DQ (last data valid) 4 DQ 4 DQ 4 DQ DQ DQ DQ 4 4 4 4 Lower byte DQ (first data no longer valid) t QH5 DQ (last data valid) DQ (first data no longer vali d) DQ0–DQ7 and LDQS Collectively 4 T2 T2 t QH5 T2n T2n t QH5 T3 T3 t QH5 T3n T3n 4 6 T2 T2n T3 T3n Data valid window t DQSQ 2 3 Data valid window t DQSQ 2 Data valid window t DQSQ 2 t DQSQ 2 Data valid window UDQS 7 DQ 7 DQ 7 DQ 7 DQ 7 DQ 7 DQ 7 DQ (first data no longer vali d) DQ (last data valid) 7 Upper byte t QH5 DQ (last data valid) DQ (first data no longer vali d) 7 7 T2 T2 t QH5 T2n T2n t QH5 T3 T3 t QH5 T3n T3n 6 DQ8–DQ15 and UDQS Collectively T2 T2n T3 T3n Data valid window Data valid window Data valid window Data valid window Notes: 1. t HP is the lesser of t CL or t CH clock transition collectively when a bank is active. 2. t DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS transition, and ends with the last valid DQ transition. 3. DQ transitioning after DQS transition define the t DQSQ window. LDQS defines the lower byte, and UDQS defines the upper byte. 4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7. 5. t QH is derived from t HP: t QH = t HP - t QHS. 6. The data valid window is derived for each DQS transition and is t QH - t DQSQ. 7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15. LOGIC Devices Incorporated www.logicdevices.com 33 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) AC SWITCHING DIAGRAMS Figure 17 - Data outPut timing - tac anD tDQsck CK# CK T01 T1 T2 T2n T3 T3n T4 T4n T5 T5n T6 t LZ (MIN) t RPRE t DQSCK2 (MAX) t DQSCK2 (MIN) t t DQSCK 2 (MAX) HZ (MAX) t DQSCK 2 (MIN) t RPST DQS or LDQS/UDQS 3 DQ (last data valid) DQ (first data valid) All DQ values collectively 4 T2 T2 T2 t LZ (MIN) T2n T2n T2n T3 T3 T3 T3n T3n T3n T4 T4 T4 T4n T4n T4n T5 T5 T5 T5n T5n T5n t AC5 (MIN) t AC5 (MAX) t HZ (MAX) Notes: 1. READ command with CL = 2 issued at T0. 2. t DQSCK is the DQS output window relative to CK and is the “long term” component of the DQS skew. 3. DQ transitioning after DQ S transition define the t DQSQ window. 4. All DQ must transition by t DQSQ after DQS transitions, regardless of t AC. 5. t AC is the DQ output window relative to CK and is the “long term” component of DQ skew. 6. t LZ (MIN) and t AC (MIN) are the first valid signal transitions. 7. t HZ (MAX) and t AC (MAX) are the latest valid signal transitions. LOGIC Devices Incorporated www.logicdevices.com 34 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) AC SWITCHING DIAGRAMS Figure 18 - write Burst CK# CK Command Address t DQSS (NOM) DQS DQ DM t DQSS (MIN) DQS DQ DM t DQSS (MAX) DQS DQ DM T0 T1 T2 T2n T3 WRITE Bank a, Col b NOP NOP NOP t DQSS DI b t DQSS DI b t DQSS DI b Transitioning Data Don’t Care Notes: 1. 2. 3. 4. DI b = data-in for column b. Three subsequent elements of data-in are applied in the programmed order following DI b. An uninterrupted burst of 4 is shown. A10 is LOW with the WRITE command (auto precharge is disabled). LOGIC Devices Incorporated www.logicdevices.com 35 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) AC SWITCHING DIAGRAMS Figure 19 - consecutive write to write CK# CK T0 T1 T1n T2 T2n T3 T3n T4 T4n T5 Command W RITE NOP W RITE NOP NOP NOP Address t DQSS (NOM) DQS Bank, Col b t DQSS Bank, Col n DQ DI b DI n DM Transitioning Data Don’t Care Notes: 1. 2. 3. 4. 5. DI b (or n) = data-in from column b (or column n). Three subsequent elements of data-in are applied in the programmed order following DI b. Three subsequent elements of data-in are applied in the programmed order following DI n. An uninterrupted burst of 4 is shown. Each WRITE command may be to any bank. LOGIC Devices Incorporated www.logicdevices.com 36 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) AC SWITCHING DIAGRAMS Figure 20 - nonconsecutive write to write CK# CK T0 T1 T1n T2 T2n T3 T4 T4n T5 T5n Command W R IT E NOP NOP WRITE NOP NOP Address t DQSS (NOM) DQS Bank, Col b t DQSS Bank, Col n DQ DI b DI n DM Transitioning Data Don’t Care Notes: 1. 2. 3. 4. 5. DI b (or n) = data-in from column b (or column n). Three subsequent elements of data-in are applied in the programmed order following DI b. Three subsequent elements of data-in are applied in the programmed order following DI n. An uninterrupted burst of 4 is shown. Each WRITE command may be to any bank. Figure 21 - ranDom write cycles CK# CK T0 T1 T1n T2 T2n T3 T3n T4 T4n T5 T5n Command WRITE WRITE WRITE WRITE WRITE NOP Address Bank, Col b Bank, Col x Bank, Col n Bank, Col a Bank, Col g t DQSS (NOM) DQS DI b DI b' DI x DI x' DI n DI n' DI a DI a' DI g DI g' DQ DM Transitioning Data Don’t Care Notes: 1. DI b (or x or n or a or g) = data-in from column b (or column x, or column n, or column a, or column g). 2. b', x', n', a' or g' indicate the next data-in following DO b, DO x, DO n, DO a, or DO g, respectively. 3. Programmed BL = 2, BL = 4, or BL = 8 in cases shown. 4. Each WRITE command may be to any bank. LOGIC Devices Incorporated www.logicdevices.com 37 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) AC SWITCHING DIAGRAMS Figure 22 - write to reaD uninterruPteD CK# CK Command T0 T1 T1n T2 T2n T3 T4 T5 T6 T6n W RITE NOP NOP NOP t WTR REA D NOP NOP Address Bank a, Col b t DQSS Bank a, Col n t DQSS (NOM) CL = 2 DQS DQ DM t DQSS (MIN) t DQSS DI b DO n CL = 2 DQS DQ DM t DQSS (MAX) t DQSS DI b DO n CL = 2 DQS DQ DM DI b DO n Transitioning Data Don’t Care Notes: 1. 2. 3. 4. 5. DI b = data-in for column b; DO n = data-out for column n. Three subsequent elements of data-in are applied in the programmed order following DI b. An uninterrupted burst of 4 is shown. t WTR is referenced from the first positive CK edge after the last data-in pair. The READ and WRITE commands are to the same device. However, the READ and WRITE commands may be to different devices, in which case t WTR is not required, and the READ command could be applied earlier. 6. A10 is LOW with the WRITE command (auto precharge is disabled). LOGIC Devices Incorporated www.logicdevices.com 38 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) AC SWITCHING DIAGRAMS Figure 23 - write to reaD interruPting CK# CK Command T0 T1 T1n T2 T2n T3 T3n T4 T5 T5n T6 T6n WRITE NOP NOP t WTR READ NOP NOP NOP Address Bank a, Col b t DQSS Bank a, Col n t DQSS (NOM) CL = 2 DQS DQ DM t DQSS (MIN) t DQSS DI b DO n CL = 2 DQS DQ DM t DQSS (MAX) t DQSS DI b DO n CL = 2 DQS DQ DM Transitioning Data Don’t Care DI b DO n Notes: 1. 2. 3. 4. 5. 6. 7. DI b = data-in for column b; DO n = data-out for column n. An interrupted burst of 4 is shown; two data elements are written. One subsequent element of data-in is applied in the programmed order following DI b. t WTR is referenced from the first positive CK edge after the last data-in pair. A10 is LOW with the WRITE command (auto precharge is disabled). DQS is required at T2 and T2n (nominal case) to register DM. If the burst of 8 is used, DM and DQS are required at T3 and T3n because the READ command will not mask these two data elements. LOGIC Devices Incorporated www.logicdevices.com 39 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) AC SWITCHING DIAGRAMS Figure 24 - write to reaD, oDD numBer oF Data, interruPting CK# CK Command T0 T1 T1n T2 T2n T3 T3n T4 T5 T5n T6 T6n W RITE NOP NOP t WTR READ NOP NOP NOP Address t DQSS (NOM) DQS DQ DM t DQSS (MIN) DQS DQ DM t DQSS (MAX) DQS DQ DM Bank a, Col b t DQSS Bank a, Col n CL = 2 DI b DO n t DQSS CL = 2 DI b DO n t DQSS CL = 2 DI b DO n Transitioning Data Don’t Care Notes: 1. DI b = data-in for column b; DO n = data-out for column n. 2. An interrupted burst of 4 is shown; one data element is written. 3. t WTR is referenced from the first positive CK edge after the last desired data-in pair (not the last two data elements). 4. A10 is LOW with the WRITE command (auto precharge is disabled). 5. DQS is required at T1n, T2, and T2n (nominal case) to register DM. 6. If the burst of 8 is used, DM and DQS are required at T3–T3n because the READ command will not mask these data elements. LOGIC Devices Incorporated www.logicdevices.com 40 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) AC SWITCHING DIAGRAMS Figure 25 - write to Precharge - uninterruPteD CK# CK Command T0 T1 T1n T2 T2n T3 T4 T5 T6 WRITE NOP NOP NOP t WR NOP PRE t RP Bank, (a or all ) NOP Address t DQSS (NOM) DQS Bank a, Col b t DQSS DQ DM t DQSS (MIN) DQS DQ DM t DQSS (MAX) DQS t DQSS DI b t DQSS DI b DQ DM DI b Transitioning Data Don’t Care Notes: 1. 2. 3. 4. 5. DI b = data-in for column b. Three subsequent elements of data-in are applied in the programmed order following DI b. An uninterrupted burst of 4 is shown. t WR is referenced from the first positive CK edge after the last data-in pair. The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE and WRITE commands may be to different devices, in which case t WR is not required and the PRECHARGE command could be applied earlier. 6. A10 is LOW with the WRITE command (auto precharge is disabled). LOGIC Devices Incorporated www.logicdevices.com 41 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) AC SWITCHING DIAGRAMS Figure 26 - write to Precharge - interruPting T0 CK# CK Command WRITE T1 T1n T2 T2n T3 T3n T4 T4n T5 T6 NOP NOP t WR NOP PRE NOP t RP NOP Address t DQSS (NOM) DQS Bank a, Col b t DQSS Bank, (a or all ) DQ DM t DQSS (MIN) DQS DI b t DQSS DI b DQ DM t DQSS (MAX) DQS t DQSS DQ DI b DM Transitioning Data Don’t Care Notes: 1. 2. 3. 4. 5. 6. 7. DI b = data-in for column b. Subsequent element of data-in is applied in the programmed order following DI b. An interrupted burst of 8 is shown; two data elements are written. t WR is referenced from the first positive CK edge after the last data-in pair. A10 is LOW with the WRITE command (auto precharge is disabled). DQS is required at T4 and T4n (nominal case) to register DM. If the burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n. LOGIC Devices Incorporated www.logicdevices.com 42 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) AC SWITCHING DIAGRAMS Figure 27 - Data inPut timing 1 T0 CK# CK t DQSS DQS T1 T1n T2 T2n T3 t DSH2 t DSS3 t DSH2 t DSS3 t WPRES t WPRE DQ DM t DS t DH DI b t DQSL t DQSH t WPST Transitioning Data Don’t Care Notes: 1. 2. 3. 4. 5. WRITE command issued at T0. t DSH (MIN) generally occurs during t DQSS (MIN). t DSS (MIN) generally occurs during t DQSS (MAX). For x16, LDQS controls the lower byte and UDQS controls the upper byte. DI b = data-in from column b. LOGIC Devices Incorporated www.logicdevices.com 43 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) mechanical Drawing 25 ± 0.15 2.35 ± 0.15 0.60 ± 0.04 19.05 ± 0.10 SQ 25 ± 0.15 1.27 ± 0.10 1.75 ± 0.11 219 X 0.76 ± 0.05 1.27 ± 0.10 8.89 ± 0.10 SQ LOGIC Devices Incorporated www.logicdevices.com 44 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C PreLIMINArY INforMAtIoN L 9D112G80BG4 1.2 Gb, DDR - SDRAM Integrated Module (IMOD) orDering inFormation Part Number L9D112G80BG4I6 L9D112G80BG4E6 L9D112G80BG4M6 Package outline Dimensions Core FREQ. 166 MHz 166 MHz 166 MHz Data Transfer Rate 333 Mbps 333 Mbps 333 Mbps Package 25mm2-219 PBGA 25mm2-219 PBGA 25mm2-219 PBGA Grade INDUSTRIAL EXTENDED MIL-TEMP L9D112G80BG4I75 L9D112G80BG4E75 L9D112G80BG4M75 133 MHz 133 MHz 133 MHz 266 Mbps 266 Mbps 266 Mbps 25mm2-219 PBGA 25mm2-219 PBGA 25mm2-219 PBGA INDUSTRIAL EXTENDED MIL-TEMP L9D112G80BG4I8 L9D112G80BG4E8 L9D112G80BG4M8 125 MHz 125 MHz 125 MHz 250 Mbps 250 Mbps 250 Mbps 25mm2-219 PBGA 25mm2-219 PBGA 25mm2-219 PBGA INDUSTRIAL EXTENDED MIL-TEMP L9D112G80BG4I10 L9D112G80BG4E10 L9D112G80BG4M10 100 MHz 100 MHz 100 MHz 200 MHz 200 MHz 200 MHz 25mm2-219 PBGA 25mm2-219 PBGA 25mm2-219 PBGA INDUSTRIAL EXTENDED MIL-TEMP revision history Revision A B Engineer DH/JM DH/JM Issue Date 11/7/2008 01/21/2009 Description Of Change INITIATE Pgs 1, 45: Change all incidences of “LBGA” to “PBGA”, revise wording to Plastic Ball Grid Array Pgs 4,5: Revision to include ball E12, Vref in Pin/Ball Locations/Definitions Section Pg 8 : Changes to allowable frequency parameters (CAS =2) in CAS latency table (speed -10 changes from ≤75 to ≤83, -75 changes from ≤100 to ≤125, -6 changes from ≤133 to NA) Pg 19: Revise CL parameter (333 Mbps: change CL from 2 to 2.5) Pg 20, 21: AC chart specs changes for 167 MHz, correct tLZ min. from -0.07 to -0.70 C CM/JM 02/02/2009 Pg 44: Correction to mechanical drawing LOGIC Devices Incorporated reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. LOGIC Devices does not assume any liability arising out of the application or use of any product or circuit described herein. In no event shall any liability exceed the product purchase price. Products of LOGIC Devices are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with LOGIC Devices. Furthermore, LOGIC Devices does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. LOGIC Devices Incorporated www.logicdevices.com 45 High Performance, Integrated Memory Module Product Feb 2, 2009 LDS-L9D112G80BG4-C