LF2249QC25

LF2249 DEVICES INCORPORATED 12 x 12-bit Digital Mixer LF2249 DEVICES INCORPORATED 12 x 12-bit Digital Mixer DESCRIPTION The LF2249 is a high-speed digital mixer comprised of two 12-bit multipliers and a 24-bit accumulator. All multiplier inputs are user accessible, and each can be updated on every clock cycle. The LF2249 utilizes a pipelined architecture with fully registered inputs and outputs and an asynchronous three-state output enable control for optimum flexibility. Independent input register clock enables allow the user to hold the data inputs over multiple clock cycles. Each multiplier input also includes a user-selectable 1-16 clock pipeline delay. The output of each multiplier can be independently negated under user control for subtraction of products. The sum of the products can also be internally rounded to 16 bits during the accumulation process. A separate 16-bit input port connected to the accumulator is included to allow cascading of multiple LF2249s. Access to all 24 bits of the accumulator is gained by switching between upper or lower 16-bit words. The accumulated output data is updated on every clock cycle. All inputs and outputs of the LF2249 are registered on the rising edge of clock, except for OE. Internal pipeline registers for all data and control inputs are provided to maintain FEATURES u 40 MHz Data and Computation Rate u Two 12 x 12-bit Multipliers with Individual Data Inputs u Separate 16-bit Input Port for Cascading Devices u Independent, User-Selectable 1–16 Clock Pipeline Delay for Each Data Input u User-Selectable Rounding of Products u Fully Registered, Pipelined Architecture u Three-State Outputs u Fully TTL Compatible u Replaces TRW/Raytheon/Fairchild TMC2249 u 120-pin PQFP 1 2 3 4 5 6 7 LF2249 BLOCK DIAGRAM ADEL3-0 A11-0 ENA BDEL3-0 B11-0 ENB CDEL3-0 C11-0 ENC DDEL3-0 D11-0 END 8 1–16 1–16 1–16 1–16 9 4 NEG2 CLK NEG1 4 10 11 RND 4 2's COMP 2's COMP 4 ACC FT 16 3 CASEN 2:1 16 24 CAS15-0 MS 1 16 0 0 16 1 LS SWAP 2:1 2:1 OE 16 NOTE: NUMBERS IN REGISTERS INDICATED NUMBER OF PIPELINE DELAYS. S15-0 Video Imaging Products 1 08/16/2000–LDS.2249-J LF2249 DEVICES INCORPORATED 12 x 12-bit Digital Mixer DETAILED VIEW OF BLOCK DIAGRAM OUTLINED AREA ADEL3-0 4 A11-0 12 ENA synchronous operation between the incoming data and all available control functions. The LF2249 operates at a clock rate of 40 MHz over the full commercial temperature and supply voltage ranges. Because of its flexibility, the LF2249 is ideally suited for applications such as image switching and mixing, digital quadrature mixing and modulating, FIR filtering, and arithmetic function and waveform synthesis. R1 R2 SIGNAL DEFINITIONS Power VCC and GND +5 V power supply. All pins must be connected. Clock CLK — Master Clock The rising edge of CLK strobes all enabled registers. All timing specifications are referenced to the rising edge of CLK. Inputs A11-0–D11-0 — Data Inputs A11-0–D11-0 are 12-bit data input registers. Data is latched into the input registers on the rising edge of CLK. The contents of the input registers are clocked into the top of the corresponding 16-stage pipeline delay (pushing the contents of the register stack down one register position) on the next clock cycle if the pipeline register stack is enabled. The LSBs are A0-D0 (Figure 1a). CAS15-0 — Cascade Data Input CAS15-0 is the 16-bit cascade data input port. Data is latched into the register on the rising edge of CLK. The LSB is CAS0 (Figure 1a). 16 : 1 12 CLK R16 FIGURE 1A. INPUT FORMATS Data Input 11 10 9 8 7 6 5 4 3 2 1 0 –211 210 29 28 27 26 25 24 23 22 21 20 (Sign) Cascade Input 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 –223 222 221 220 219 218 217 216 215 214 213 212 211 210 29 28 (Sign) FIGURE 1B. OUTPUT FORMATS Sum Output (Upper 16 bits) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 –223 222 221 220 219 218 217 216 215 214 213 212 211 210 29 28 (Sign) Sum Output (Lower 16 bits) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 Video Imaging Products 2 08/16/2000–LDS.2249-J LF2249 DEVICES INCORPORATED 12 x 12-bit Digital Mixer NEG1–NEG2 — Negate Control ACC — Accumulator Control The ACC input determines whether internal accumulation is performed on the data input during the current clock cycle. If ACC is LOW, no accumulation is performed, the prior accumulated sum is cleared, and the current sum of products is output. When ACC is HIGH, the emerging products are added to the sum of the previous products. RND — Rounding Control When RND is HIGH, the sum of the products of the data being input on the current clock cycle will be rounded to 16 bits. To avoid the accumulation of roundoff errors, rounding is only performed during the first cycle of each accumulation process. SWAP — Output Select The SWAP control allows the user to access all 24 bits of the accumulator output by switching between upper and lower 16-bit words. When SWAP is HIGH, the upper 16 bits of the accumulator are always output. When SWAP is LOW, the lower 16 bits of the accumulator are output on every other clock cycle. As long as SWAP remains LOW, new output data will not be clocked into the output registers. OE — Output Enable When the OE signal is LOW, the current data in the output registers is available on the S 15-0 p ins. When OE is HIGH, the outputs are in a high-impedance state. Outputs S15-0 — Data Output The NEG1 and NEG2 controls determine whether a subtraction or accumuThe current 16-bit result is available lation of products is performed. When on the S 15-0 outputs. The output data NEG1 is HIGH, the product A x B is may be either the upper or lower 16 negated, causing the product to be subbits of the accumulator output, detracted from the accumulator contents. pending on the state of SWAP. The Likewise, when NEG2 is HIGH, the LSB is S0 (Figure 1b). product C x D is negated, causing the product to be subtracted as well. NEG1 and NEG2 determine the operation to Controls be performed on the data input during ENA–END — Pipeline Register Enable the current clock cycle when ADEL– Input data in the N (N = A, B, C, or D) DDEL = 0000. input register is latched into the corresponding pipeline register stack on CASEN — Cascade Enable each rising edge of CLK for which ENN is LOW. Data already in the N register When CASEN is LOW, data being instack is pushed down one register posi- put on the CAS15-0 inputs during that tion. When ENN is HIGH, the data in clock cycle will be registered and accuthe N pipeline register stack does not mulated internally. When CASEN is change, and the data in the N input HIGH, the CAS15-0 inputs are ignored. register will not be stored in the register stack. FT — Feedthrough Control When FT is LOW and ADEL–DDEL = ADEL3-0–DDEL3-0 — Pipeline Delay 0000, data being input on the CAS15-0 Select inputs is delayed three clock cycles to NDEL (N = A, B, C, or D) is the 4-bit align the data with the data being input registered pipeline delay select word. on the A11-0–D11-0 inputs. When FT is NDEL determines which stage of the N HIGH, the cascade data being input is pipeline register stack is routed to the routed around the three delay registers multiplier inputs. The minimum delay to simplify the cascading of multiple is one clock cycle (NDEL = 0000), and devices. the maximum delay is 16 clock cycle (NDEL = 1111). Upon power up, the values of ADEL–DDEL and the contents of the pipeline register stacks are unknown and must be initialized by the user. 1 2 3 4 5 6 7 8 9 10 11 Video Imaging Products 3 08/16/2000–LDS.2249-J LF2249 DEVICES INCORPORATED 12 x 12-bit Digital Mixer MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ............................................................................... –0.5 V to V CC + 0.5 V Signal applied to high impedance output ...................................................................... –0.5 V to VCC + 0.5 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Active Operation, Commercial Active Operation, Military Temperature Range (Ambient) 0°C to +70°C –55°C to +125°C Supply Voltage 4.75 V ≤ VCC ≤ 5.25 V 4.50 V ≤ VCC ≤ 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol VOH VOL VIH VIL IIX IOZ ICC1 ICC2 CIN COUT Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Current Output Leakage Current VCC Current, Dynamic VCC Current, Quiescent Input Capacitance Output Capacitance (Note 3) Test Condition Vcc = Min., IOH = –2.0 mA Vcc = Min., IOL = 4.0 mA Min 2.4 Typ Max Unit V 0.4 2.0 0.0 VCC 0.8 ±10 ±40 100 6 10 10 V V V µA µA mA mA pF pF Ground ≤ VIN ≤ VCC (Note 12) (Note 12) (Notes 5, 6) (Note 7) TA = 25°C, f = 1 MHz TA = 25°C, f = 1 MHz Video Imaging Products 4 08/16/2000–LDS.2249-J 432109876543210987654321 432109876543210987654321 432109876543210987654321 *DISCONTINUED SPEED GRADE Symbol Symbol *Assumes ADEL–DDEL = 0000 21098765432109876543210987654321 21098765432109876543210987654321 21098765432109876543210987654321 21098765432109876543210987654321 21098765432109876543210987654321 21098765432109876543210987654321 21098765432109876543210987654321 21098765432109876543210987654321 21098765432109876543210987654321 21098765432109876543210987654321 21098765432109876543210987654321 21098765432109876543210987654321 21098765432109876543210987654321 21098765432109876543210987654321 21098765432109876543210987654321 21098765432109876543210987654321 21098765432109876543210987654321 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76543210987654321 76543210987654321 1 76543210987654321 76543210987654321 7654321098765432 Min DEVICES INCORPORATED SWITCHING WAVEFORMS MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) SWITCHING CHARACTERISTICS tDIS tENA tD tH tS tPWH tPWL tCYC tDIS tENA tD tH tS tPWH tPWL tCYC CONTROLS (Except OE) A11-0 – D11-0 S15-0* OE CLK Parameter Three-State Output Disable Delay (Note 11) Three-State Output Enable Delay (Note 11) Output Delay Input Hold Time Input Setup Time Clock Pulse Width, HIGH Clock Pulse Width, LOW Cycle Time Three-State Output Disable Delay (Note 11) Three-State Output Enable Delay (Note 11) Output Delay Input Hold Time Input Setup Time Clock Pulse Width, HIGH Clock Pulse Width, LOW Cycle Time Parameter tS N 1 tH N+1 tPWH 2 tPWL N+2 tDIS 3 5 HIGH IMPEDANCE 10 40 15 tENA 0 8 40* Max 15 15 17 tD 6 Video Imaging Products 12 x 12-bit Digital Mixer Min 10 40 10 33 15 15 0 0 8 8 SN LF224933 40* 7 Max Max 15 15 17 15 15 15 LF2249- SN + 1 Min Min 10 33 10 25 15 10 08/16/2000–LDS.2249-J 0 0 8 7 33* LF2249 25 8 SN + 2 Max Max 15 15 15 15 15 14 11 10 9 8 7 6 5 4 3 2 1 LF2249 DEVICES INCORPORATED 12 x 12-bit Digital Mixer NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of IOH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a minN = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with all outputs changing every cycle and no load, at a 25 MHz clock rate. 7. Tested with all inputs within 0.1 V of VCC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. imum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT DUT S1 IOL CL IOH VTH FIGURE B. THRESHOLD LEVELS tENA OE Z 0 1.5 V 1.5 V 1.5 V tDIS 3.5V Vth VOL* 0.2 V 0 1 Z Z 1.5 V VOH* 0.2 V Z 1 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA Video Imaging Products 6 08/16/2000–LDS.2249-J LF2249 DEVICES INCORPORATED 12 x 12-bit Digital Mixer ORDERING INFORMATION D5 D6 D7 D8 GND D9 D10 D11 VCC C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 120-pin DDEL0 DDEL1 DDEL2 DDEL3 END D0 D1 D2 D3 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 D4 CLK ACC NEG1 NEG2 RND S15 S14 GND S13 S12 S11 VCC S10 S9 S8 GND S7 S6 S5 VCC S4 S3 S2 GND S1 S0 OE SWAP BDEL0 BDEL1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Top View 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 C0 ENC CDEL3 CDEL2 CDEL1 CDEL0 FT CASEN CAS0 CAS1 CAS2 CAS3 CAS4 CAS5 CAS6 CAS7 CAS8 CAS9 GND CAS10 CAS11 CAS12 CAS13 CAS14 CAS15 NC ADEL0 ADEL1 ADEL2 ADEL3 1 2 3 4 5 6 7 8 9 10 11 Speed 0°C to +70°C — COMMERCIAL SCREENING 33 ns 25 ns LF2249QC33 LF2249QC25 –40°C to +85°C — COMMERCIAL SCREENING BDEL2 BDEL3 ENB B0 B1 B2 B3 B4 B5 B6 B7 GND B8 B9 B10 VCC B11 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ENA 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Plastic Quad Flatpack (Q1) Video Imaging Products 7 08/16/2000–LDS.2249-J 121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 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9 10 C4 C7 C9 A6 A4 A1 CDEL3 CDEL0 CASEN ADEL3 NC CAS15 ADEL0 CAS14 CAS12 CAS13 CAS11 CAS10 GND CAS9 CAS8 CAS6 CAS7 CAS5 CAS2 CAS3 CAS4 FT 11 C1 C5 C6 A3 A0 Video Imaging Products 12 x 12-bit Digital Mixer ADEL2 ADEL1 ENC CDEL1 CAS0 CAS1 12 C2 C3 A2 CDEL2 ENA 13 C0 08/16/2000–LDS.2249-J LF2249