LF2301JC55

LF2301 DEVICES INCORPORATED Image Resampling Sequencer LF2301 DEVICES INCORPORATED Image Resampling Sequencer DESCRIPTION The LF2301 is a self-sequencing address generator designed to filter a two-dimensional image or remap and resample it from one set of Cartesian coordinates (x,y) into a new set (u,v). The LF2301 can resample digitized images or perform such manipulations as rotation, panning, zooming, and warping as well as compression in real-time. By using two LF2301s in a Image Transformation System (ITS), nearest-neighbor, bilinear interpolation, and cubic convolution algorithms, with kernel sizes up to 4 x 4 pixels, are all possible (see Figure 1). This system can also implement simple static filters with kernel sizes up to 16 x 16 pixels. DETAILS OF OPERATION Most video applications use a pair of LF2301s in tandem to construct an ITS. One LF2301 is the row coordinate generator (x to u) and the other is the column generator (y to v). External RAM is needed for storage of the interpolation coefficient lookup table, as well as for buffers of the source and destination images. An external MultiplierAccumulator is required when performing interpolation or implementing static filters. The ITS is capable of performing the general second-order coordinate transformation of the form: x(u,v) = Au 2+Bu+Cuv+Dv2+Ev+F y(u,v) = Gu2+Hu+Kuv+Lv2+Mv+N where parameters A through N of the transform are user-defined. The system steps sequentially through each pixel in the “target” image lying within a user-defined rectangle. For each “target” pixel at (u,v), the LF2301 points to a corresponding “source” pixel at (x,y). FEATURES u 40 MHz Clock Rate u High-Speed Image Manipulation u Maximum Image Size: 4096 x 4096 Pixels u Supports Following Interpolation Algorithms: • Nearest-Neighbor • Bilinear Interpolation • Cubic Convolution u Applications: • Video Special-Effects • Image Recognition • High-Speed Data Encoding/ Decoding u Replaces TRW/Raytheon/Fairchild TMC2301 u 68-pin PLCC, J-Lead LF2301 BLOCK DIAGRAM LDR WEN B3-0 P11-0 NOOP INTER INIT PARAMETER STORAGE CONTROL WALK COUNT ACC DONE END SOURCE ADDRESS GENERATOR FRACTION INTEGER INPUT IMAGE BOUNDARY COMPARATOR TARGET ADDRESS GENERATOR OETA CA7-0 X11-0 CZERO UWRI U11-0 Video Imaging Products 2-1 08/16/2000–LDS.2301-H LF2301 DEVICES INCORPORATED Image Resampling Sequencer FIGURE 1. IMAGE TRANSFORMATION SYSTEM (ITS) IMAGE DATA IN 12 SIGNAL DEFINITIONS Power Vcc and GND +5V power supply. All pins must be connected. Clock CLK — Master Clock The rising edge of CLK strobes all enabled registers. Inputs P11-0 — Parameter Register Data Input P11-0 is the 12-bit Parameter Register Data input port. P11-0 is latched on the rising edge of CLK. B3-0 — Parameter Register Address Input B3-0 is the 4-bit Parameter Register Address input port. B3-0 is latched on the rising edge of CLK. Outputs X11-0 — Source Address Output X11-0 is the 12-bit registered Source Address output port. CA7-0 — Coefficient Address Output CA7-0 is the 8-bit registered Coefficient Address output port. U11-0 — Target Address Output U11-0 is the 12-bit registered Target Address output port. Controls INIT — Initialize When INIT is HIGH for a minimum of two clock cycles, the control logic is cleared and initialized for the start of a new image transformation. When INIT goes LOW, normal operation begins after two clock cycles. INIT is latched on the rising edge of CLK. WEN — Write Enable When WEN is LOW, data latched into the device on P11-0 is loaded into the preload register addressed by the data P11-0 B3-0 INIT, LDR, WEN, NOOP, OETA 12 4 5 X11-0 LF2301 Row Address Generator (X) CA7-0 8 12 24 ACC UWRI U11-0 12 INTER END SOURCE IMAGE RAM 12 X ACC INTERPOLATION COEFFICIENT RAM LMA1009/2009 12 x 12 bit MultiplierAccumulator X,Y,P DOUT 12 8 12 Y CA7-0 LF2301 Column Address Generator (Y) 12 12 24 Y11-0 V11-0 INTER END DESTINATION IMAGE RAM 12 CLK IMAGE DATA OUT latched into the device on B3-0. When WEN is HIGH, data cannot be loaded into the preload registers and their contents will not be changed. WEN is latched on the rising edge of CLK. LDR — Load Data Register When LDR is HIGH, data in all preload registers is latched into the Transformation Parameter Registers. When LDR is LOW, data cannot be loaded into the Transformation Parameter Registers and their contents will not be changed. LDR is latched on the rising edge of CLK. ACC — Accumulate The registered ACC output initializes the accumulation register of the external multiplier-accumulator. At the start of each interpolation “walk,” ACC goes LOW for one cycle effectively clearing the storage register by loading in only the new first product. ACC from either the row or column LF2301 may be used. UWRI — Target Memory Write Enable The Target Memory Write Enable goes LOW for one clock cycle after the end of each interpolation “walk.” When OETA is HIGH, this registered output is forced to the high-impedance state. UWRI from either the row or column LF2301 may be used. INTER — Interconnect When two LF2301s are used to form an ITS, the END flag on each device is connected to INTER on the other device. The END flag from the row device indicates an “end of line” to the column device. The END flag from the column device indicates a “bottom of frame” to the row device, forcing a reset of the address counter. NOOP — No Operation When NOOP is LOW, the clock is overridden holding all address generators in their current state. X11-0 and CA 7-0 are forced to the high- Video Imaging Products 2-2 08/16/2000–LDS.2301-H LF2301 DEVICES INCORPORATED Image Resampling Sequencer When Mode is set to “01” or “11” END goes HIGH on the row device for K+1 clock cycles starting at (K+1) + 2 clock cycles before the last X address of a row. END goes HIGH on the column device for (K+1) x (K+1) clock cycles starting at [(K+1) x (K+1)] + 1 clock cycles before the last X address of a frame. DONE — End of Transform In a two LF2301 system, after the last walk of the last row of an image, the registered DONE flag goes HIGH indicating the end of the transform. DONE goes HIGH one clock cycle before the last X address of a frame. If AIN is HIGH, DONE will remain HIGH for one clock cycle. If AIN is LOW, DONE will remain HIGH until a new transform begins. Transformation Control Parameters XMIN, XMAX, YMIN, YMAX XMIN, XMAX, YMIN, YMAX define the valid area in the source image from which pixels may be read. The CZERO flags will denote a valid memory read whenever the LF2301s generate an (x,y) address within this boundary. UMIN, UMAX, VMIN, VMAX UMIN, UMAX, VMIN, VMAX define the area in the destination image into which pixels will be written. (UMIN, VMIN) is the top left corner and (UMAX + 1, VMAX) is the bottom right corner. The following conditions must be met: UMAX>UMIN and VMAX>VMIN. x0, y0 x0, y0 determine what the first pixel read out of the source image will be at the beginning of an image transformation. x0, y0 will be the upper left corner of the original image in non-inverting, nonreversing applications. dx/du dx/du is the displacement along the x axis corresponding to a one-pixel movement along the u axis. 2-3 impedance state. Users may then access external memory. Normal operation resumes on the next clock cycle after NOOP goes HIGH. NOOP is latched on the rising edge of CLK. OETA — Target Memory Output Enable When OETA is HIGH, UWRI and U11-0 are forced to the high-impedance state. When OETA is LOW, UWRI and U11-0 are enabled on the next clock cycle. OETA is latched on the rising edge of CLK. Flags CZERO — Coefficient Zero If in a row device x