LMU217

LMU217 DEVICES INCORPORATED 16 x 16-bit Parallel Multiplier LMU217 DEVICES INCORPORATED 16 x 16-bit Parallel multiplier DESCRIPTION The L MU217 i s a high-speed, low RND is loaded on the rising edge of power 16-bit parallel multiplier. CLK, provided either ENA or ENB are LOW. RND, when HIGH, adds ‘1’ to The LMU217 produces the 32-bit prodthe most significant bit position of the uct of two 16-bit numbers. Data present least significant half of the product. at the A inputs, along with the TCA Subsequent truncation of the 16 least control bit, is loaded into the A register significant bits produces a result on the rising edge of CLK. B data and correctly rounded to 16-bit precision. the TCB control bit are similarly loaded. Loading of the A and B At the output, the Right Shift control registers is controlled by the ENA and (RS) selects either of two output formats. ENB controls. When HIGH, these con- RS LOW produces a 31-bit product trols prevent application of the clock to with a copy of the sign bit inserted in the the respective register. The TCA and MSB postion of the least significant half. TCB controls specify the operands as RS HIGH gives a full 32-bit product. Two two’s complement when HIGH, or 16-bit output registers are provided to unsigned magnitude when LOW. hold the most and least significant halves of the result (MSP and LSP) as defined by RS. These registers are loaded on the rising edge of CLK, subject to the ENR control. When ENR is B 15-0/ HIGH, clocking of the result registers is R 15-0 prevented. A 15-0 TCB 16 A REGISTER 16 B REGISTER FEATURES u 25 ns Worst-Case Multiply Time u Low Power CMOS Technology u Replaces Cypress CY7C517, IDT 7217L, and AMD Am29517 u Single Clock Architecture with Register Enables u Two’s Complement, Unsigned, or Mixed Operands u Three-State Outputs u 68-pin PLCC, J-Lead LMU217 BLOCK DIAGRAM TCA CLK ENA ENB For asynchronous output, these registers may be made transparent by setting the feed through control (FT) HIGH and ENR LOW. The two halves of the product may be routed to a single 16-bit three-state output port (MSP) via a multiplexer. MSPSEL LOW causes the MSP outputs to be driven by the most significant half of the result. MSPSEL HIGH routes the least significant half of the result to the MSP pins. In addition, the LSP is available via the B port through a separate three-state buffer. RND REGISTER 32 RS FORMAT ADJUST 16 FT ENR RESULT 16 REGISTER MSPSEL OEM 16 R 31-16 16 OEL Multipliers 1 08/16/2000–LDS.217-H LMU217 DEVICES INCORPORATED 16 x 16-bit Parallel Multiplier FIGURE 1A. INPUT FORMATS AIN BIN Fractional Two’s Complement (TCA, TCB = 1) 15 14 13 –20 2–1 2–2 (Sign) 210 2–13 2–14 2–15 15 14 13 –20 2–1 2–2 (Sign) 210 2–13 2–14 2–15 Integer Two’s Complement (TCA, TCB = 1) 15 14 13 –215 214 213 (Sign) 210 22 21 20 15 14 13 –215 214 213 (Sign) 210 22 21 20 Unsigned Fractional (TCA, TCB = 0) 15 14 13 2–1 2–2 2–3 210 2–14 2–15 2–16 15 14 13 2–1 2–2 2–3 210 2–14 2–15 2–16 Unsigned Integer (TCA, TCB = 0) 15 14 13 215 214 213 210 22 21 20 15 14 13 215 214 213 210 22 21 20 FIGURE 1B. OUTPUT FORMATS MSP Fractional Two’s Complement (RS = 0) 31 30 29 –20 2–1 2–2 (Sign) LSP 18 17 16 2–13 2–14 2–15 15 14 13 –20 2–16 2–17 (Sign) 210 2–28 2–29 2–30 Fractional Two’s Complement (RS = 1) 31 30 29 –21 20 2–1 (Sign) 18 17 16 2–12 2–13 2–14 15 14 13 2–15 2–16 2–17 210 2–28 2–29 2–30 Integer Two’s Complement (RS = 1) 31 30 29 –231 230 229 (Sign) 18 17 16 218 217 216 15 14 13 215 214 213 210 22 21 20 Unsigned Fractional (RS = 1) 31 30 29 2–1 2–2 2–3 18 17 16 2–14 2–15 2–16 15 14 13 2–17 2–18 2–19 210 2–30 2–31 2–32 Unsigned Integer (RS = 1) 31 30 29 231 230 229 18 17 16 218 217 216 15 14 13 215 214 213 210 22 21 20 Multipliers 2 08/16/2000–LDS.217-H LMU217 DEVICES INCORPORATED 16 x 16-bit Parallel Multiplier MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Active Operation, Commercial Active Operation, Military Temperature Range (Ambient) 0°C to +70°C –55°C to +125°C Supply Voltage 4.75 V ≤ VCC ≤ 5.25 V 4.50 V ≤ VCC ≤ 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol VOH VOL VIH VIL IIX IOZ ICC1 ICC2 Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Current Output Leakage Current VCC Current, Dynamic VCC Current, Quiescent (Note 3) Test Condition VCC = Min., IOH = –2.0 mA VCC = Min., IOL = 8.0 mA Min 2.4 Typ Max Unit V 0.5 2.0 0.0 VCC 0.8 ±20 ±20 12 25 1.0 V V V µA µA mA mA Ground ≤ VIN ≤ VCC (Note 12) Ground ≤ VOUT ≤ VCC (Note 12) (Notes 5, 6) (Note 7) Multipliers 3 08/16/2000–LDS.217-H 432109876543210987654321 432109876543210987654321 432109876543210987654321 *DISCONTINUED SPEED GRADE Symbol Symbol OEM OEL R31-0 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 543210987654321098765432121098765432109876543210987654321 Min Max Min Max Min Max Min Max Min Max Min Max 15 20 3 DEVICES INCORPORATED COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) SWITCHING CHARACTERISTICS 16 x 16-bit Parallel Multiplier LMU217– 45* 35 1098765432 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 1 10987654321 11 9 1 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 1 98765432109876543210987654321 98765432109876543210987654321 9876543210987654321098765432 15 15 3 SWITCHING WAVEFORMS MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) tDIS tENA tSEL tD tH tS tPW tMUC tMC tDIS tENA tSEL tD tH tS tPW tMUC tMC Parameter Three-State Output Disable Delay (Note 11) Three-State Output Enable Delay (Note 11) Output Select Delay Output Delay Input Hold Time Input Setup Time Clock Pulse Width Unclocked Multiply Time Clocked Multiply Time Parameter Three-State Output Disable Delay (Note 11) Three-State Output Enable Delay (Note 11) Output Select Delay Output Delay Input Hold Time Input Setup Time Clock Pulse Width Unclocked Multiply Time Clocked Multiply Time ENA, ENB MSPSEL INPUT ENR CLK tS tH tDIS tPW Min Max Min Max Min Max Min Max Min Max Min Max tENA HIGH IMPEDANCE tMC 75* 65* 4 25 25 25 30 65 85 25 25 30 35 75 95 tPW tMUC 15 15 15 15 3 3 55* 65* tS 25 25 25 30 55 75 25 25 30 30 65 85 15 15 15 15 3 3 tH LMU217– 55* 40* tPW 25 25 25 30 45 65 tSEL 25 25 30 30 55 75 tD 12 10 15 15 1 2 25 25 25 25 35 55 25 25 25 25 40 60 12 10 12 10 1 2 30* 25 Multipliers 20 20 20 20 25 38 20 20 20 20 30 43 08/16/2000–LDS.217-H LMU217 12 10 2 25* 20* 18 18 18 18 20 30 20 20 20 20 25 38 LMU217 DEVICES INCORPORATED 16 x 16-bit Parallel Multiplier NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of I OH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter6. Tested with all outputs changing ev- nal system must supply at least that ery cycle and no load, at a 5 MHz clock much time to meet the worst-case requirements of all parts. Responses from rate. the internal circuitry are specified from 7. Tested with all inputs within 0.1 V of the point of view of the device. Output VCC or Ground, no load. delay, for example, is specified as a 8. These parameters are guaranteed maximum since worst-case operation of any device always provides data within but not 100% tested. that time. N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT DUT S1 IOL CL IOH VTH FIGURE B. THRESHOLD LEVELS tENA OE Z 0 1.5 V 1.5 V 1.5 V tDIS 3.5V Vth VOL* 0.2 V 0 1 Z Z 1.5 V VOH* 0.2 V Z 1 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA Multipliers 5 08/16/2000–LDS.217-H DEVICES INCORPORATED ORDERING INFORMATION 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 R31 R30 R29 R28 R27 R26 R25 R24 R23 R22 R21 R20 R19 R18 R17 R16 Speed 35 ns 25 ns –55°C to +125°C — MIL-STD-883 COMPLIANT –55°C to +125°C — COMMERCIAL SCREENING 0°C to +70°C — COMMERCIAL SCREENING 68-pin R31 R30 R29 R28 R27 R26 R25 R24 R23 R22 R21 R20 R19 R18 R17 R16 NC Plastic J-Lead Chip Carrier (J2) LMU217JC35 LMU217JC25 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 64-pin 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 10 Top View 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 NC A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 OEL CLK ENB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 6 Ceramic Flatpack (F4) 16 x 16-bit Parallel Multiplier Discontinued Package Top View Multipliers R15, B15 R14, B14 R13, B13 R12, B12 R11, B11 R10, B10 R9, B9 R8, B8 R7, B7 R6, B6 R5, B5 R4, B4 R3, B3 R2, B2 R1, B1 R0, B0 08/16/2000–LDS.217-H R15, B15 R14, B14 R13, B13 R12, B12 R11, B11 R10, B10 R9, B9 R8, B8 R7, B7 R6, B6 R5, B5 R4, B4 R3, B3 R2, B2 R1, B1 R0, B0 NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LMU217 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 OEL CLK ENB NC ENR OEM RS FT MSPSEL GND GND VCC VCC TCB TCA RND ENA A15 A14 A13 ENR OEM RS FT MSPSEL GND GND VCC VCC TCB TCA RND ENA A15 A14 A13