LSH32JC32

LSH32 DEVICES INCORPORATED 32-bit Cascadable Barrel Shifter LSH32 DEVICES INCORPORATED 32-bit Cascadable Barrel Shifter DESCRIPTION The LSH32 is a 32-bit high speed shifter designed for use in floating point normalization, word pack/ unpack, field extraction, and similar applications. It has 32 data inputs, and 16 output lines. Any shift configuration of the 32 inputs, including circular (barrel) shifting, left shifts with zero fill, and right shift with sign extend are possible. In addition, a built-in priority encoder is provided to aid floating point normalization. SHIFT ARRAY The 32 inputs to the LSH32 are applied to a 32-bit shift array. The 32 outputs of this array are multiplexed down to 16 lines for presentation at the device outputs. The array may be configured such that any contiguous 16-bit field (including wraparound of the 32 inputs) may be presented to the output pins under control of the shift code field (wrap mode). Alternatively, the wrap feature may be disabled, resulting in zero or sign bit fill, as appropriate (fill mode). The shift code control assignments and the resulting input to output mapping for the wrap mode are shown in Table 1. Essentially the LSH32 is configured as a left shift device. That is, a shift code of 000002 results in no shift of the input field. A code of 000012 provides an effective left shift of 1 position, etc. When viewed as a right shift, the shift code corresponds to the two’s complement of the shift distance, i.e., a shift code of 111112 (–110) results in a right shift of one position, etc. When not in the wrap mode, the LSH32 fills bit positions for which there is no corresponding input bit. The fill value and the positions filled depend on the RIGHT/LEFT (R/L) direction pin. This pin is a don’t care input when in wrap mode. For left shifts in fill mode, lower bits are filled with zero as shown in Table 2. For right shifts, however, the SIGN input is used as the fill value. Table 3 depicts the bits to be filled as a function of shift code for the right shift case. Note that the R/L input changes only the fill convention, and does not affect the definition of the shift code. In fill mode, as in wrap mode, the shift code input represents the number of shift positions directly for left shifts, but the two’s complement of the shift code results in the equivalent right shift. However, for fill mode the R/L input can be viewed as the most OE MS/LS FEATURES u 32-bit Input, 32-bit Output Multiplexed to 16 Lines u Full 0-31 Position Barrel Shift Capability u Integral Priority Encoder for 32-bit Floating Point Normalization u Sign-Magnitude or Two’s Complement Mantissa Representation u 32-bit Linear Shifts with Sign or Zero Fill u Independent Priority Encoder Outputs for Block Floating Point u 68-pin PLCC, J-Lead LSH32 BLOCK DIAGRAM SIGN I 31 -I 0 32 32:5 PRIORITY ENCODE 32 5 2:1 SI 4 -SI 0 RIGHT/LEFT FILL/WRAP 16 NORM 32-bit BARREL SHIFT ARRAY 16 2:1 5 16 SO 4 -SO 0 Y 15 -Y 0 Special Arithmetic Functions 1 08/16/2000–LDS.32-Q LSH32 DEVICES INCORPORATED 32-bit Cascadable Barrel Shifter significant bit of a 6-bit two’s complement shift code, comprised of R/L concatenated with the SI4–SI0 lines. Thus a positive shift code (R/L = 0) results in a left shift of 0–31 positions, and a negative code (R/L = 1) a right shift of up to 32 positions. The LSH32 can thus effectively select any contiguous 32-bit field out of a (sign extended and zero filled) 96-bit "input." OUTPUT MULTIPLEXER The shift array outputs are applied to a 2:1 multiplexer controlled by the MS/LS select line. This multiplexer makes available at the output pins either the most significant or least significant 16 outputs of the shift array. PRIORITY ENCODER The 32-bit input bus drives a priority encoder which is used to determine the first significant position for purposes of normalization. The priority encoder produces a five-bit code representing the location of the first non-zero bit in the input word. Code assignment is such that the priority encoder output represents the number of shift positions required to left align the first non-zero bit of the input word. Prior to the priority encoder, the input bits are individually exclusive OR’ed with the SIGN input. This allows normalization in floating point systems using two’s complement mantissa representation. A negative value in two’s complement representation will cause the exclusive OR gates to invert the input data to the encoder. As a result the leading significant digit will always be "1." This affects only the encoder inputs; the shift array always operates on the raw input data. The priority encoder function table is shown in Table 4. TABLE 1. WRAP MODE SHIFT CODE DEFINITIONS Shift Code 00000 00001 00010 00011 • • • Y 31 I 31 I 30 I 29 I 28 • • • Y 30 I 30 I 29 I 28 I 27 • • • Y 29 I 29 I 28 I 27 I 26 • • • ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• Y 16 I 16 I 15 I 14 I 13 • • • Y 15 I 15 I 14 I 13 I 12 • • • ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• Y2 I 2 I 1 I 0 I 31 • • • Y1 I 1 I 0 I 31 I 30 • • • Y0 I 0 I 31 I 30 I 29 • • • 01111 10000 10001 10010 • • • I 16 I 15 I 14 I 13 • • • I 15 I 14 I 13 I 12 • • • I 14 I 13 I 12 I 11 • • • I 1 I 0 I 31 I 30 • • • I 0 I 31 I 30 I 29 • • • I 19 I 18 I 17 I 16 • • • I 18 I 17 I 16 I 15 • • • I 17 I 16 I 15 I 14 • • • 11100 11101 11110 11111 I 3 I 2 I 1 I 0 I 2 I 1 I 0 I 31 I 1 I 0 I 31 I 30 I 20 I 19 I 18 I 17 I 19 I 18 I 17 I 16 I 6 I 5 I 4 I 3 I 5 I 4 I 3 I 2 I 4 I 3 I 2 I 1 TABLE 2. Shift Code 00000 00001 00010 00011 • • • FILL MODE SHIFT CODE DEFINITIONS — LEFT SHIFT Y 31 I 31 I 30 I 29 I 28 • • • Y 30 I 30 I 29 I 28 I 27 • • • Y 29 I 29 I 28 I 27 I 26 • • • ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• Y 16 I 16 I 15 I 14 I 13 • • • Y 15 I 15 I 14 I 13 I 12 • • • ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• Y2 I 2 I 1 I 0 0 • • • Y1 I 1 I 0 0 0 • • • Y0 I 0 0 0 0 • • • 01111 10000 10001 10010 • • • I 16 I 15 I 14 I 13 • • • I 15 I 14 I 13 I 12 • • • I 14 I 13 I 12 I 11 • • • I 1 I 0 0 0 • • • I 0 0 0 0 • • • 0 0 0 0 • • • 0 0 0 0 • • • 0 0 0 0 • • • 11100 11101 11110 11111 I 3 I 2 I 1 I 0 I 2 I 1 I 0 0 I 1 I 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Special Arithmetic Functions ffs2 08/16/2000–LDS.32-Q LSH32 DEVICES INCORPORATED 32-bit Cascadable Barrel Shifter NORMALIZE MULTIPLXER Y0 S I 31 I 30 I 29 • • • TABLE 3. Shift Code 00000 00001 00010 00011 • • • FILL MODE SHIFT CODE DEFINITIONS — RIGHT SHIFT Y 31 S S S S • • • Y 30 S S S S • • • Y 29 S S S S • • • ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• Y 16 S S S S • • • Y 15 S S S S • • • ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• Y2 S S S I 31 • • • Y1 S S I 31 I 30 • • • 01111 10000 10001 10010 • • • S S S S • • • S S S S • • • S S S S • • • S S I 31 I 30 • • • S I 31 I 30 I 29 • • • I 19 I 18 I 17 I 16 • • • I 18 I 17 I 16 I 15 • • • I 17 I 16 I 15 I 14 • • • The NORM input, when asserted results in the priority encoder output driving the internal shift code inputs directly. It is exactly equivalent to routing the SO4 –SO 0 outputs back to the SI4 –SI0 inputs. The NORM input provides faster normalization of 32-bit data by avoiding the delay associated with routing the shift code off chip. When using the NORM function, the LSH32 should be placed in fill mode, with the R/L input low. APPLICATIONS EXAMPLES Normalization of mantissas up to 32 bits can be accomplished directly by a single LSH32. The NORM input is asserted, and fill mode and left shift are selected. The normalized mantissa is then available at the device output in two 16-bit segments, under the control of the output data multiplexer select, the MS/LS. If it is desirable to avoid the necessity of multiplexing output data in 16-bit segments, two LSH32 devices can be used in parallel. Both devices receive the same input word, with the MS/LS select line of one wired high, and the other low. Each device will then independently determine the shift distance required for normalization, and the full 32 bits of output data will be available simultaneously. 11100 11101 11110 11111 S S S S S S S I 31 S S I 31 I 30 I 20 I 19 I 18 I 17 I 19 I 18 I 17 I 16 I 6 I 5 I 4 I 3 I 5 I 4 I 3 I 2 I 4 I 3 I 2 I 1 TABLE 4. 31 I 30 I PRIORITY ENCODER FUNCTION TABLE 29 I ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• 16 I 15 I ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• 2 I 1 I 0 I Shift Code 00000 00001 00010 • • 1 0 0 • • X 1 0 • • X X 1 • • X X X • • X X X • • X X X • • X X X • • X X X • • 0 0 0 • • 0 0 0 • • 0 0 0 • • 1 0 0 • • X 1 0 • • X X X • • X X X • • X X X • • 01111 10000 10001 • • 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 X 1 0 11110 11111 11111 Special Arithmetic Functions 3 08/16/2000–LDS.32-Q LSH32 DEVICES INCORPORATED 32-bit Cascadable Barrel Shifter slices, including the first. The exception is that all SI4 lines are grounded, limiting the shift distance to 16 positions. The shift distance required for normalization is produced by the priority encoder in the most significant slice. The priority encoder will produce the shift code necessary to normalize the input word if the leading non-zero digit is found in the upper 16 bits. If this is the case, the number of shift positions necessary to accomplish normalization is placed on the SO 4 –SO 0 outputs for use by all slices, and the appropriate 0–15 bit shift is accomplished. If the upper 16 bits are all zero, then the maximum shift of 15 places is executed. Single clock normalization requiring shifts longer than 16 bits can be accomplished by a bank-select technique described below. SINGLE CYCLE LONG-WORD NORMALIZATION An extension of the above concept is a single clock normalization of long words (potentially requiring shifts of more than 15 places). The arrangement of LSH32s required is shown in Figure 1. Cascading of LSH32 units is accomplished by connecting the SI3 – SI0 input lines of each unit to the SO 3 – SO 0 outputs of the most significant device in the row as before. Essen- LONG-WORD NORMALIZATION (MULTIPLE CYCLES) Normalization of floating point mantissas longer than 32 bits can be accomplished by cascading LSH32 units. When cascading for normalization, the device inputs are overlapped such that each device lower in priority than the first shares 16 inputs with its more significant neighbor. Fill mode and left shift are selected, however, internal normalization (NORM) is not used. The most significant result half of each device is enabled to the output. The shift out (SO 4 –SO 0) lines of the most significant slice are connected to the shift in lines of all FIGURE 1. SINGLE CYCLE LONG-WORD NORMALIZATION USING LSH32S I 63 -I 48 MSBs 4 LSH32 SI3-0 SO 4-0 OE I 47 -I 32 I 31 -I 16 5 4 LSH32 SI3-0 OE I 15 -I 0 4 LSH32 SI3-0 OE 0 4 LSH32 SI3-0 OE SI4 I 47 -I 32 I 31 -I 16 I 15 -I 0 0 PRIORITY ENCODE 2:4 DECODE 4 LSH32 SI3-0 SO 4-0 OE I 31 -I 16 I 15 -I 0 5 4 LSH32 SI3-0 OE 0 4 LSH32 SI3-0 OE SI4 4 LSH32 SI3-0 SO 4-0 OE I 16 -I 0 0 5 4 LSH32 SI3-0 OE SI4 4 LSH32 SO 4-0 SI3-0 OE SI4 5 Y 63 -Y 48 Y 47 -Y 32 Y 31 -Y 16 Y 15 -Y 0 Special Arithmetic Functions ffs4 08/16/2000–LDS.32-Q LSH32 DEVICES INCORPORATED 32-bit Cascadable Barrel Shifter The number of shift positions can be determined simply by concatenation of the SO 3 –SO 0 outputs of the most significant slice in the selected row with the encoded Output Enable-bits determining the row number. Note that lower rows need not be fully populated. This is because they represent left shifts in multiples of 16 positions, and the lower bits of the output word will be zero filled. In order to accomplish this zero fill, the least significant device in each row is always enabled, and the row select is instead connected to the SI4 input. This will force the shift length of the least significant device to a value greater than 15 whenever the row containing that device is not selected. This results in zero fill being accomplished by the equivalently positioned slice in a higher bank, as shown in the diagram. BLOCK FLOATING POINT With a small amount of external logic, block floating point operations are easily accomplished by the LSH32. Data resulting from a vector operation are applied to the LSH32 with the NORM-input deasserted. The SO 4 – SO 0 outputs fill then represent the normalization shift distance for each vector element in turn. By use of an external latch and comparator, the maximum shift distance encountered across all elements in the vector is saved for use in the next block operation (or block normalization). During this subsequent pass through the data, the shift code saved from the previous pass is applied uniformly across all elements of the vector. Since the LSH32 is not used in the internal normalize mode, this operation can be pipelined, thereby obtaining the desired shift distance for the next pass while simultaneously applying the normalization required from the previous pass. tially the LSH32s are arranged in multiple rows or banks such that the inputs to successive rows are leftshifted by 16 positions. The outputs of each row are multiplexed onto a three-state bus. The normalization problem then reduces to selecting from among the several banks that one which has the first non-zero bit of the input value among its 16 most significant positions. If the most significant one in the input file was within the upper 16 locations of a given bank, the SO 4 output of the most significant slice in that bank will be low. Single clock normalization can thus be accomplished simply by enabling onto the three-state output bus the highest priority bank in which this condition is met. In this way the input word will be normalized regardless of the number of shift positions required to accomplish this. Special Arithmetic Functions 5 08/16/2000–LDS.32-Q LSH32 DEVICES INCORPORATED 32-bit Cascadable Barrel Shifter MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Active Operation, Commercial Active Operation, Military Temperature Range (Ambient) 0°C to +70°C –55°C to +125°C Supply Voltage 4.75 V ≤ VCC ≤ 5.25 V 4.50 V ≤ VCC ≤ 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol VOH VOL VIH VIL IIX IOZ ICC1 ICC2 Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Current Output Leakage Current VCC Current, Dynamic VCC Current, Quiescent (Note 3) Test Condition VCC = Min., IOH = –2.0 mA VCC = Min., IOL = 8.0 mA Min 2.4 Typ Max Unit V 0.4 2.0 0.0 VCC 0.8 ±20 ±20 10 30 1.5 V V V µA µA mA mA Ground ≤ VIN ≤ VCC (Note 12) Ground ≤ VOUT ≤ VCC (Note 12) (Notes 5, 6) (Note 7) Special Arithmetic Functions ffs6 08/16/2000–LDS.32-Q 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 *DISCONTINUED SPEED GRADE Symbol Symbol 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 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6543210987654321 6543210987654321 6543210987654321 6543210987654321 543210987654321 6543210987654321 6543210987654321 6 Min DEVICES INCORPORATED SWITCHING WAVEFORMS MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) SWITCHING CHARACTERISTICS tENA tDIS tMSY tSIY tISO tIYN tIY tENA tDIS tMSY tSIY tISO tIYN tIY SI4-SI0 RIGHT/LEFT SO4-SO0 MS/LS Y31-Y0 Y31-Y0 I31-I0 SIGN Parameter Parameter Three-State Output Enable Delay (Note 11) Three-State Output Disable Delay (Note 11) MS/LS Select to Y Outputs SI, RIGHT/LEFT to Y Outputs I, SIGN Inputs to SO Outputs I, SIGN Inputs to Y Outputs, Normalize Mode I, SIGN Inputs to Y Outputs Three-State Output Enable Delay (Note 11) Three-State Output Disable Delay (Note 11) MS/LS Select to Y Outputs SI, RIGHT/LEFT to Y Outputs I, SIGN Inputs to SO Outputs I, SIGN Inputs to Y Outputs, Normalize Mode I, SIGN Inputs to Y Outputs OE tDIS tSIY tISO tIY, tIYN HIGH IMPEDANCE 7 32-bit Cascadable Barrel Shifter 50* 42* tENA Special Arithmetic Functions Max Max 85 75 62 52 22 20 32 28 22 20 65 55 50 42 tMSY Min Min LSH32– 40* LSH32– 32 Max Max 75 60 52 40 20 20 26 24 20 20 52 42 40 32 Min Min 08/16/2000–LDS.32-Q 30* 20 LSH32 Max Max 58 20 40 20 17 15 24 15 17 15 42 20 30 20 LSH32 DEVICES INCORPORATED 32-bit Cascadable Barrel Shifter NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of IOH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a minN = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with all outputs changing every cycle and no load, at a 5 MHz clock rate. 7. Tested with all inputs within 0.1 V of VCC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. imum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT DUT S1 IOL CL IOH VTH FIGURE B. THRESHOLD LEVELS tENA OE Z 0 1.5 V 1.5 V 1.5 V tDIS 3.5V Vth VOL* 0.2 V 0 1 Z Z 1.5 V VOH* 0.2 V Z 1 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA Special Arithmetic Functions ffs8 08/16/2000–LDS.32-Q DEVICES INCORPORATED ORDERING INFORMATION 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 7654321098765432121098765432109876543210987654321 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+125°C — COMMERCIAL SCREENING 0°C to +70°C — COMMERCIAL SCREENING I30 I31 SIGN SO4 SO3 SO2 SO1 SO0 NORM SI4 SI3 SI2 SI1 SI0 R/L F/W Y31/15 68-pin 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 Plastic J-Lead Chip Carrier (J2) 7 6 5 4 LSH32JC32 LSH32JC20 3 2 Top View 1 68 67 66 65 64 63 62 61 60 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 GND I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 VCC VCC 9 Y30/14 Y29/13 Y28/12 Y27/11 Y26/10 Y25/9 Y24/8 Y23/7 Y22/6 Y21/5 Y20/4 Y19/3 Y18/2 Y17/1 Y16/0 OE MS/LS I29 I28 I27 I26 I25 I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 GND 32-bit Cascadable Barrel Shifter 1 Y29/13 Y27/11 Y25/9 Y23/7 Y21/5 Y19/3 Y17/1 SO1 SO3 R/L SI1 SI3 I30 I29 2 Special Arithmetic Functions I27 I28 Ceramic Pin Grid Array (G1) 3 Discontinued Package (i.e., Component Side Pinout) I25 I26 4 Through Package I23 I24 5 Top View I21 I22 6 I19 I20 7 I17 I18 8 OE MS/LS I15 I16 9 08/16/2000–LDS.32-Q GND GND 10 I12 I14 I10 I0 I2 I4 I6 I8 LSH32 VCC 11 I13 I11 I1 I3 I5 I7 I9