LS7766

UL ® LSI/CSI LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 RS2 RS1 RS0 NC DB0 DB1 DB2 DB3 DB4 LS7766 (631) 271-0400 FAX (631) 271-0405 October 2007 A3800 32-BIT SINGLE- AXIS/DUAL-AXIS QUADRATURE COUNTER FEATURES: • Direct interface with Incremental Encoders • Read/write registers for count and I/O modes. Count modes include: non-quadrature (Up/Down), quadrature (x1, x2, x4.) free-run, non-recycle, modulo-n and range limit • Programmable IOs for Index and Marker Flags • Separate mode-control registers for each axis • 40MHz count frequency at 5V; 20MHz count frequency at 3V • Sets of 32-bit counters, input registers, output registers, comparators and octal Status registers for each axis • Digital filtering of the input quadrature clocks for noise immumity. • Pin selectable 3-state Hex / Octal bus • 3V to 5.5V operating voltage range • Available in four different configurations identified by the following suffixes: DH = Dual-axis with pin selectable Hex/Octal IO Bus DO = Dual-axis Octal IO Bus SH = Single-axis pin selectable Hex/Octal IO Bus SO = Single axis Octal IO Bus LS7766DH-TS; LS7766DO, LS7766DO-S, LS7766DO-TS; LS7766SO, LS7766SO-S, LS7766SO-TS; LS7766SH-TS P/N = DIP; P/N-S = SOIC; P/N-TS = TSSOP 1 2 3 4 5 6 7 8 9 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 V DD PCKO PCKI RD/ WR/ CS/ NC x1B x1A x1INDX/ x1FLGa x1FLGb x1CKO V SS IO16/ x0/_x1 x0CKO x0FLGb x0FLGa NC x0INDX/ x0A x0B NC LSI DB5 10 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 NC NC NC V SS 11 12 13 14 15 16 17 18 19 20 21 22 23 24 LS7766DH GENERAL DESCRIPTION: The LS7766 consists of two identical modules of 32-bit programmable up/down counters (CNTR) with direct interface to incremental encoders. The modules can be configured to operate as quadrature-clock counters or non-quadrature up/down counters. In both quadrature and non-quadrature modes, the modules can be further configured into free-running, non-recycle, modulo-n and range-limit count modes. The mode configuration is made via two octal read/write addressable mode control registers, MCR0 and MCR1. Data can be written into a 32-bit input data register (IDR), organized in addressable Word segments using the hex IO bus or in byte segments using the octal IO Bus. The IDR can be used to store target encoder positions and compared with the CNTR for generating marker flags when the CNTR reaches the target value. A 32-bit digital comparator is included for monitoring the equality of the CNTR to the IDR. Snapshots of the CNTR value can be stored in a read-addressable 32-bit output data register (ODR). The ODR can be read in Word segments or byte segments in accordance with the selected bus width. Data transfers among the registers and various register reset functions are performed by means of a write-addressable octal transfer control register (TCR). A read-addressable octal status register (STR), stores the count related status information such as CNTR overflow, underflow, count direction, etc. 7766-102307-1 Pin Assignment - Top View x1A x1B CS/ WR/ RD/ PCKI V DD RS2 RS1 RS0 DB0 DB1 DB2 DB3 1 2 3 4 5 28 27 26 25 24 23 22 21 20 19 18 17 16 15 x1INDX/ x1FLGa x1FLGb x0/_x1 x0FLGb x0FLGa x0INDX/ x0A x0B V SS DB7 DB6 DB5 DB4 RS2 RS1 RS0 DB0 DB1 DB2 DB3 DB4 DB5 DB6 1 2 3 4 5 6 7 8 9 10 38 37 36 35 34 33 32 LSI 6 7 8 9 10 11 12 13 14 V DD PCKO PCKI RD/ NC WR/ CS/ NC NC NC IO16/ NC CKO FLGb FLGa INDX/ A B V SS Pin Assignment - Top View LS7766DO LSI 31 30 29 28 27 26 25 24 23 22 21 20 LS7766SH DB7 11 DB8 DB10 RS2 RS1 RS0 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 1 2 3 4 5 6 7 8 9 10 11 24 23 22 21 20 19 18 17 16 15 14 13 12 DB9 13 14 15 16 17 18 19 V DD PCKO PCKI RD/ WR/ CS/ CKO FLGb FLGa INDX/ A B DB11 DB12 DB13 DB14 DB15 LSI LS7766SO Pin Assignment - Top View V SS 12 Pin Assignment - Top View 7766-110806-2 REGISTER DESCRIPTION: Following is a list of the hardware registers for the single-axis device. For the dual axis device, these registers are duplicated for the second axis. IDR The IDR is a 32-bit data register directly addressable for write. In the octal bus-configuration, the input STR: The STR is an 8-bit status register indicating count related status. STR: CY BW CMP IDX CEN 0 B7 B6 B5 B4 B3 U/D S B0 B2 B1 data is written in byte segments of byte0 (IDR0), byte1 (IDR1), byte2 (IDR2) and byte3 (IDR3). In the hex busconfiguration the data is written in word segments of word0 (IDR1:IDR0) and word1 (IDR3:IDR20). B31------------------------------------------------------------------- B0 IDR: IDR3 IDR2 IDR1 IDR0 B7------------B0 B7-----------B0 B7-----------B0 B7---------B0 -----byte3------ -----byte2----- -----byte1----- -----byte0------------------- word1---------------- --------------- word0 ------------ An individual STR bit is set to 1 when the bit related event has taken place. The STR is cleared to 0 at power-up. The STR can also be cleared through the control register TCR with the exception of bit_1(U/D) and bit3_(CEN). These two STR bits always indicate the instantaneous status of the count_direction and count_enable assertion/de-assertion. The STR bits are described below: B7 (CY): Carry; set by CNTR overflow B6 (BW): Borrow; set by CNTR underflow B5 (CMP): Set when CNTR = PR B4 (IDX): Set when INDX input is at active level B3 (CEN): Set when counting is enabled, reset when counting is disabled B2 (0): Always 0 B1 (U/D): Set when counting up, reset when counting down B0 (S): Sign of count value; set when negative, reset when positive TCR: The TCR is a write only register, which when written into, generates transient signals to perform load and reset operations as described below: TCR: B7 B6 B5 B4 B3 B2 B1 B0 The IDR serves as the input portal for the counter (CNTR) since the CNTR is not directly addressable for either read or write. In order to preset the CNTR to any desired value the data is first written into the IDR and then transferred to the CNTR. In mod-n and range-limit count modes the IDR serves as the repository for the division factor n and the count range-limit, respectively. The IDR can also be used to hold a target position data for comparing with the running CNTR. A compare equality flag is generated at IDR = CNTR to signal the event of arriving at the target. CNTR: The CNTR is a 32-bit up/down counter which counts the up/down pulses resulting from the quadrature clocks applied at A and B inputs or alternatively, in nonquadrature mode, pulses applied at the A input. The CNTR is not directly accessible for read or write; instead it can be preloaded with data from the IDR or it can port its own data out to the ODR which in turn can be accessed by read operation. In both quadrature and nonquadrature modes, the CNTR can be further configured into either free-running or single-cycle or mod-n or range-limit mode. In quadrature mode, the count resolution is programmable to be x1 or x2 or x4 of the A quad B cycles. ODR: The ODR is a 32-bit data register directly addressable for read. In the octal bus-configuration, the output data is read in byte segments of byte0 (ODR0), byte1 (ODR1), byte2 (ODR2), and byte3 (ODR3). In the hex busconfiguration the data is read in word segments of word0 (ODR1:ODR0) and word1 (ODR3:ODR2). B31------------------------------------------------------------------- B0 ODR: ODR3 ODR2 ODR1 ODR0 B7------------B0 B7-----------B0 B7-----------B0 B7---------B0 -----byte3------ -----byte2----- -----byte1----- -----byte0------------------- word1---------------- --------------- word0 -----------7766-042407-3 B0 = 0: Nop = 1: Reset CNTR to 0. (Should not be combined with load_CNTR operation). B1 = 0: Nop = 1: Load CNTR from IDR. Affects all 32 bits. (Should not be combined with reset_CNTR operation) B2 = 0: Nop = 1: Load ODR from CNTR. Affects all 32 bits. B3 = 0: Nop = 1: Reset STR. Affects status bits for carry, borrow, compare and index. Status bits corresponding to count_enable, count direction and sign are not affected B4 = 0: Nop. 1: Master reset. Resets MCR0, MCR1, IDR, ODR, STR B5 = 0: Nop 1: Set sign bit (STR bit0) B6 = 0: Nop 1: Reset sign bit (STR bit0) B7 = x: Not used. MCR0 : The MCR0 is an 8-bit read/write register which configures the counting modes and the index input functionality. Upon power-up, the MCR0 is cleared to zero. MCR0: B7 B6 B5 B4 B3 B2 B1 B0 B1B0 = 00: = 01: = 10: = 11: B3B2 = 00: = 01: = 10: Non-quadrature count mode (A = clock, B = direction). x1 quadrature count mode (one count per quadrature cycle). x2 quadrature count mode (two counts per quadrature cycle). x4 quadrature count mode (four counts per quadrature cycle). Free-running count mode. Single-cycle count mode (CNTR disabled with carry and borrow, re-enabled with reset or load) Range-limit count mode (up and down count ranges are limited between IDR and zero, respectively. Counting freezes at these limits but resumes when the direction is reversed) = 11: Modulo-n count mode (input count clock frequency is divided by a factor of [n+1], where n = IDR. In up direction, the CNTR is cleared to 0 at CNTR = IDR and up count continues. In down direction, the CNTR is preset to the value of IDR at CNTR = 0 and down count continues. A mod-n rollover marker pulse is generated at each limit at the FLGa output). B5B4 = 00: Disable INDX/ input. = 01: Configure INDX/ input as the load_CNTR input (transfers IDR to CNTR). = 10: Configure INDX/ as the reset _CNTR input (clears CNTR to 0). = 11: Configure INDX/ as the load_ODR input (transfers CNTR to ODR). B6 = 0: Asynchronous index. = 1: Synchronous index (overridden in non-quadrature mode). B7 = 0: Input filter clock (PCK) division factor = 1. Filter clock frequency = fPCK. = 1: Input filter clock division factor = 2. Filter clock frequency = fPCK/2. MCR1: The MCR1 is an 8-bit read/write register which configures the FLGa and FLGb output functionality. In addition, the MCR1 can be used to enable/disable counting.Upon power-up, the MCR1 is cleared to zero: MCR1: B7 B6 B5 B4 B3 B2 B1 B0 = 1: Enable Carry on FLGa (flags CNTR overflow; latched or unlatched logic low on carry). = 1: Enable Borrow on FLGa (flags CNTR underflow, latched or unlatched logic low on borrow). = 1: Enable Compare on FLGa (In free-running count mode a latched or unlatched logic low is generated in both up and down count directions at CNTR = IDR. In contrast, in range-limit and mod-n count modes a latched or unlatched low is generated at CNTR = IDR in the up-count direction only. B3 = 1: Enable index on FLGa (flags index, latched or unlatched logic low when INDX input is at active level) B5B4 = 00: FLGb disabled (fixed high) = 01: FLGb = Sign, high for negative signifying CNTR underflow, low for positive. = 10: FLGb = Up/Down count direction, high in count-up, low in count-down. B6 = 0: Enable counting. = 1: Disable counting. B7 = 0: FLGa is latched. = 1: FLGa is non-latched and instantaneous. NOTE: Carry, Borrow, Compare and Index can all be simultaneously enabled on FLGa. B0 B1 B2 7766-111406-4 I/O PINS: The following is a description of the input/out pins. RS0, RS1, RS2 Inputs. These three inputs select the hardware registers for read/write access according to Table 1 and Table 2. Table 1 applies to Octal bus configuration. Table 2 applies to Hex bus configuration. TABLE 1 DATABUS SELECTED REGISTER REGISTER MAP none none MCR0 DBL MCR1 DBL ODR0 DBL ODR1 DBL ODR2 DBL ODR3 DBL STR DBL MCR0 DBL MCR1 DBL IDR0 DBL IDR1 DBL IDR2 DBL IDR3 DBL TCR DBL CS/ 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RS2 x 0 0 0 0 1 1 1 0 0 0 0 1 1 1 RS1 x 0 0 1 1 0 0 1 0 0 1 1 0 0 1 RS0 x 0 1 0 1 0 1 0 0 1 0 1 0 1 0 RD/ x 0 0 0 0 0 0 0 1 1 1 1 1 1 1 WR/ x 1 1 1 1 1 1 1 0 0 0 0 0 0 0 OPERATION none READ READ READ READ READ READ READ WRITE WRITE WRITE WRITE WRITE WRITE WRITE TABLE 2 DATABUS SELECTED REGISTER REGISTER MAP OPERATION none none none [MCR1:MCR0] [DBH:DBL] READ [ODR1:ODR0] [DBH:DBL] READ [ODR3:ODR2] [DBH:DBL] READ [STR] [DBL] READ [MCR1:MCR0] [DBH:DBL] WRITE [IDR1:IDR0] [DBH:DBL] WRITE [IDR3:IDR2] [DBH:DBL] WRITE [TCR] [DBL] WRITE CS/ 1 0 0 0 0 0 0 0 0 RS2 x 0 0 1 1 0 0 1 1 RS1 x 0 1 0 1 0 1 0 1 RS0 x 0 0 0 0 0 0 0 0 RD/ x 0 0 0 0 1 1 1 1 WR/ x 1 1 1 1 0 0 0 0 Note 1. x indicates don’t care case. Note 2. DBL stands for DB ; DBH stands for DB . 7766-111406-5 x0/_x1 Input. The x0/_x1 input selects between axis-0 and axis-1 for Read and Write operations. A low at this input selects axis-0 while a high selects axis-1. RD/ Input. A low on RD/ input accesses an addressed register(s) for read and places the data on the databus, DB in accordance with Table 1 and Table 2. CS/ Input. A low on the CS/ input enables the chip for read or write operation. When the CS/ input is high, read and write operations are disabled and the databus, DB is placed in a high impedance state. WR/ Input. A low pulse on the WR/ input writes the data on the databus, DB into the addressed register according to Table 1 and Table 2. The write operation is completed at the trailing edge of the WR/ pulse. PCKI, PCKO. Input, Output. A clock applied at PCKI input is used for validating the logic states of the A and B quadrature clocks and the INDX/ input. Alternatively, a crystal oscillator connected between PCKI and PCKO can be used to generate the filter clock. The PCK input frequency, fPCK is divided down by a factor of 1 or 2 according to bit7 of MCR0. The resultant clock is used to sample the logic levels of the A, the B and the INDX inputs. If a logic level at any of these inputs remains stable for a minimum of two filter clock periods, it is validated as a correct logic state. The PCKI input is common to both axes, but the filter clock frequency for any axis is set by its associated MCR0 register. In non-quadrature mode, no filter clock is used and the PCKI input should be connected to either VDD or GND. x0A, x0B Inputs. These are the A and B count inputs in axis-0. These inputs can be configured to function either in quadrature mode or in non-quadrature mode. The configuration is made through MCR0. In quadrature mode, A and B clocks are 90 degrees out of phase such as the output from an Incremental Encoder. When A leads B in phase, the CNTR counts up and when B leads A in phase, the CNTR counts down. In non-quadrature mode, A serves as the count input while B controls the count direction. When B is high, positive transitions at the A input causes the CNTR to count up. Conversely, when B is low, the positive transition at the A input causes the CNTR to count down. In quadrature mode, A and B inputs are sampled by an internal filter clock generated from the PCKI input. In non-quadrature mode, A and B inputs are not sampled and the count clocks are applied to the CNTR, bypassing the filter circuit. x1A , x1B: These are the A and B inputs corresponding to axis-1, . Functionally, they are identical with the A and B inputs of axis-0. x0INDX/ Input. The INDX/ input in axis-0. The INDX/ input can be configured to function as load_CNTR or reset_CNTR or load_ODR input via MCR0. In quadrature mode the INDX/ input can be configured to operate in either synchronous or asynchronous mode. In the synchronous mode the INDX/ input is sampled with the same filter clock used for sampling the A and the B inputs and must satisfy the phase relationship with A and B in which INDX/ is at the active level during a minimum of a quarter cycle of both A and B high or both A and B low. The active level of the INDX/ input is logic low. In non-quadrature mode the INDX/ input is unconditionally set to the asynchronous mode. In the asynchronous mode the INDX/ input is not sampled and can be applied in any phase relationship with respect to the A and B inputs. The INDX/ input can be either enabled or disabled in both quadrature and non-quadrature modes. x1INDX/. The INDX/ input corresponding to axes-1. Functionally, it is identical with the INDX/ input of axis-0. IO16/ Input. When low, hex databus configuration is invoked in accordance with Table 2. When high, octal databus configuration is invoked in accordance with Table 1. This input has an internal pull-up. x0FLGa Output. The FLGa output in axis-0. The FLGa output is configured by MCR1 register to function as Carry and/or Borrow and/or Compare and/or Index flag. A Carry flag is generated when the CNTR overflows, a Borrow flag is generated when the CNTR underflows, a Compare flag is generated by the condition, CNTR = IDR and Index flag is generated when Index input is at active level. The FLGa output can be configured to produce outputs in either latched mode or instantaneous mode. In the latched mode when the selected event of Carry or Borrow or Compare or index has taken place, FLGa switches low and remains low until the status register, STR is cleared. In the instantaneous mode, a negative pulse is generated instantaneously when the event takes place. The FLGa output can be disabled to remain at a fixed logic high. x1FLGa Output. The FLGa output corresponding to axes-1. Functionally, it is identical with the FLGa output of axis-0. 7766-110806-6 x0FLGb Output. The FLGb output in axis-0. The FLGb output is configured by MCR1 to function as either Sign or Up/Down count direction indicator. When configured as Sign, the FLGb output remains high when CNTR is in an underflow state (caused by down counts at or below zero), indicating a negative number. When the CNTR counts up past zero, FLGb switches low, indicating a positive number. When configured as Up/Down indicatior, a high at the FLGb indicates that the current count direction is up (incremental) whereas a low indicates that the direction is down or decremental. The FLGb output can be disabled to remain at a fixed logic high. x1FLGb Output. The FLGb output of axis-1. Functionally, it is identical with the FLGb output of axis-0. x0CKO Output. Axis-0 count clock output. In nonquadrature mode, the CKO output is identical with the input-A clock. In quadrature mode, CKO is derived from the filtered and decoded quadrature clocks applied at the A and B inputs. In either mode CKO is a true representative of the internal count clock. x1CKO Output. Axis-1 count clock output. Functionally, it is identical with the CKO output of axis-0. VDD. Supply voltage. Positive terminal. GND. Supply voltage. Negative terminal. The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. 7766-062207-7 Absolute Maximum Ratings: Parameter Voltage at any input Supply Voltage Operating Temperature Storage Temperature Symbol VIN VDD TA TSTG Values VSS - 0.3 to VDD + 0.3 +7.0 -25 to +80 -65 to +150 Unit V V oC oC DC Electrical Characteristics. (TA = -25oC to +80oC, VDD = 3V to 5.5V) Parameter Supply Voltage Supply Current Input Logic Low Input Logic High Input Leakage Current Data Bus Leakage Current Data Bus Source Current Data Bus Sink Current FLGa, FLGb, INT/ Source FLGa, FLGb, INT/ Sink Symbol VDD IDD VIL VIH IILK IDLK IDBH IDBL IOSRC IOSNK Min. Value 3.0 0.5VDD 2.0 -6.0 1.0 -6.0 Max.Value 5.5 800 0.15VDD 30 60 Unit V µA V V nA nA mA mA mA mA Remarks All clocks off Data bus off VO = VDD - 0.5V, VDD = 5V VO = 0.5V, VDD = 5V VO = VDD - 0.5V, VDD = 5V VO = 0.5V, VDD = 5V Transient Characteristics. (TA = -25o to +80oC, VDD = 3V to 5.5V) Parameter Read Cycle (See Fig. 2) RD/ Pulse Width CS/ Set-up Time CS/ Hold Time RS Set-up Time RS Hold Time x0/_x1 Set-up Time x0/_x1 Hold Time DB AccessTime DB Release Time Back to Back Read delay Write Cycle (See Fig. 3) WR/ Pulse Width CS/ Set-up Time CS/ Hold Time RS Set-up Time RS Hold Time x0/_x1 Set-up Time x0/_x1 Hold Time DB Set-up Time DB Hold Time Back to Back Write Delay Symbol tr1 tr2 tr3 tr4 tr5 tr6 tr7 tr8 tr9 tr10 tW1 tW2 tW3 tW4 tW5 tW6 tW7 tW8 tW9 tW10 Min. Value 80 80 0 80 10 80 10 80 10 45 45 0 45 10 45 10 45 10 90 Max.Value 35 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks Access starts when both RD/ and CS/ are low. Release starts when either RD/ or CS/ is terminated. - 7766-110806-8 For VDD = 3.3V ±10% Parameter Symbol Quadrature Mode (See Fig. 4 - 6) PCKI High Pulse Width t1 PCKI Low Pulse Width t2 PCKI Frequency fpCK Filter Clock (ff) Period t3 t3 Filter Clock frequency Quadrature Separation Quadrature Clock Pulse Width Quadrature Clock frequency Quadrature Clock to Count Delay x1, x2, x4 Count Clock Pulse Width Quadrature Clock to FLGa delay Quadrature Clock to FLGb delay INDX/ Input Pulse Width INDX/ set-up time INDX/ hold time FLGa Output Width Non-Quadrature Mode (See Fig. 7 - 8) Clock A - High Pulse Width Clock A - Low Pulse Width Direction Input B Set-up Time Direction Input B Hold Time Clock Frequency Clock to FLGa Out Delay FLGa Out Pulse Width INDX/ Pulse Width For VDD = 5V ±10% Parameter Quadrature Mode (See Fig. 4 - 6) PCK High Pulse Width PCK Low Pulse Width PCK frequency Filter Clock (ff) period Filter Clock frequency Quadrature Separation Quadrature Clock Pulse Width Quadrature Clock frequency Quadrature Clock to Count Delay x1, x2, x4 Count Clock Pulse Width Quadrature Clock to FLGa delay Quadrature Clock to FLGb delay INDX/ Input Pulse Width INDX/ set-up time INDX/ hold time FLGa Output Width Non-Quadrature Mode (See Fig. 7 - 8) Clock A - High Pulse Width Clock A - Low Pulse Width Direction Input B Set-up Time Direction Input B Hold Time Clock frequency Clock to FLGa Out Delay FLGa Out Pulse Width INDX/ Pulse Width 7766-110806-9 Min. Value 24 24 50 100 52 105 4t3 25 4.5t3 3t3 60 10 10 50 24 24 24 20 24 30 Max.Value 20 20 4.5 5t3 5.5t3 4t3 20 40 - Unit ns ns MHz ns ns MHz ns ns MHz ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns Remarks t3 = t1+ t2, MDR0 = 0 t3 = t1+ t2, MDR0 = 1 ff = 1/t3 t4 > t3 t5 > 2t3 fQA = fQB < 1/4t3 tQ2 = t3/2 tid > t4 tfw ≈ t4 fA = (1/(t6 + t7)) t10 = t7 - ff t4 t5 fQA, fQB tQ1 tQ2 tfda tfdb tid tis tih tfw t6 t7 t8s t8 fA t9 t10 t11 Symbol t1 t2 fpCK t3 t3 ff t4 t5 fQA, fQB tQ1 tQ2 tfda tfdb tid tis tih tfw t6 t7 t8 t8 fA t9 t10 t11 Min. Value 12 12 25 50 26 52 4t3 12 4.5t3 3t3 32 5 5 24 12 12 12 10 12 15 Max.Value 40 40 9.6 5t3 5.5t3 4t3 40 20 - Unit ns ns MHz ns ns MHz ns ns MHz ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns Remarks t3 = t1+ t2, MDR0 = 0 t3 = t1+ t2, MDR0 = 1 t4 > t3 t5 > 2t3 fQA = fQB < 1/4t3 tQ2 = t3/2 tid > t4 tfw ≈ t4 fA = (1/(t6 + t7)) t10 = t7 - tr1 RD/ tr2 CS/ tr4 RS tr6 x0/_x1 tr8 DB tr9 VALID DATA tr10 tr3 tr5 tr7 VALID DATA FIGURE 2. READ CYCLE tw1 tw10 WR/ tw2 CS/ tw4 tw5 tw7 tw9 tw3 RS tw6 x0/_x1 tw8 DB INPUT DATA INPUT DATA FIGURE 3. WRITE CYCLE t1 PCKI t3 t2 f f (Note 3) (MCR0 = 0) t3 t5 t4 tis Note 1 tid t4 tih t4 tis Note 2 f f (Note 3) (MCR0 = 1) t5 t4 tih A B INDX/ Note 1. Synchronous mode index coincident with both A and B high. Note 2. Synchronous mode index coincident with both A and B low. Note 3. fF is the internal effective filter clock. FIGURE 4. PCKI, A, B AND INDX/ 7766-110806-10 UP tQ1 DOWN A B CKO (x4 Mode) CKO (x2 Mode) tQ2 CKO (x1 Mode) NOTE. CKO is identical with internal count clock. FIGURE 5. A/B QUADRATURE CLOCKS vs OUTPUT CLOCK, CKO UP DOWN A B CKO (x4 Mode) CNTR FFFFFC FFFFFD FFFFFE FFFFFF 000000 000001 000002 000001 000000 FFFFFF FFFFFE FFFFFD t fda FLGa FLGb (up/dn) FLGb (sign) positive CY (SHOWN WITH PR=000OO1) tfw CMP tfdb BW negative NOTE. FLGa is in non-latched mode. FIGURE 6. QUADRATURE CLOCKS vs FLGa, FLGb OUTPUTS 7766-042407-11 DOWN UP DOWN B t6 A t7 t8S t8H FIGURE 7. COUNT (A) AND DIRECTION (B) INPUTS IN NON-QUADRATURE MODE B A (Shown with PR= 2) CNTR FFFFFFC FFFFFFD FFFFFFE FFFFFFF t9 FLGa CY 0 2 1 0 FFFFFFF t10 CNTR DISABLED CNTR DISABLED t11 INDX (LOAD CNTR) CNTR ENABLED FIGURE 8. SINGLE-CYCLE, NON-QUADRATURE UP DOWN B A (Shown with PR = 3) CNTR FLGa 0 1 2 3 0 1 2 1 0 3 2 1 0 CMP BW FIGURE 9. MODULO-N, NON-QUADRATURE B UP DOWN A (Shown with PR = 3) CNTR 000000 000001 000002 FLGa 000003 000002 000001 000000 CMP CMP CMP CMP BW BW BW FIGURE 10. RANGE-LIMIT, NON-QUADRATURE 7766-110806-12 READ CY, BW, CMP, INDX, SIGN, UP/DOWN STR (8) OUT-BUS MUX FLAG-MASKS FLGa AND/OR/BUF IN-BUS WRITE READ MCR1(8) MCR0(8) IDR3(8) IDR2(8) IDR1(8) IDR0(8) TCR(8) LD/SET/RESET OUT-BUS CLOCK BUFFER CK0 FLGb MODES, FLAG-MASKS MODE LOGIC CLOCK A B INDX/ PCKI PCK0 COUNT CLOCK & INDEX GENERATOR INDX CNTR (32) C O M P CMP OSC READ MARKER LOGIC CY, BW, SIGN RD/ WR/ CS/ x0/_x1 RS READ/WRITE & AXIS SELECT LOGIC WRITE ODR3(8) ODR2(8) ODR1(8) ODR0(8) READ READ OUT-BUS REGISTER SELECT LOGIC OUTPUT 3-STATE BUFFER IO16/ WRITE INPUT BUFFER IN-BUS DB FIGURE 11. LS7766 BLOCK DIAGRAM FOR SINGLE-AXIS 7766-110806-13 ISA / EISA BUS IOW/ IOR/ WR/ RD/ D PC DB LS7766 IO16/ A A x0/_x1 RS2 RS1 RS0 CS/ A< 4:1 > A< 7:5> AEN A A ADDRESS DECODE FIGURE 12. LS7766 TO ISA / EISA INTERFACE with HEX BUS R/W LDS RD/ WR/ D D D 15pF PCKI 1MΩ 40MHz DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 PCKO 15pF DTACK/ MC68HC000 D D D D D D D LS7766 A2 A3 - A 0 A A1 A0 A3 RS2 RS1 RS0 x0/_x1 CS/ A ADDRESS DECODE FIGURE 13. LS7766 TO MC68HC000 INTERFACE with OCTAL BUS 7766-111406-14