LY62L256PV

® LY62L256 Rev. 1.2 32K X 8 BIT LOW POWER CMOS SRAM REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Description Initial Issue Revised STSOP Package Outline Dimension Deleted L Spec. Revised VTERM to VT1 and VT2 Revised Test Condition of ISB1/IDR Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Added packing type in ORDERING INFORMATION Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Issue Date Jul.25.2004 Mar.26.2008 Apr.13.2009 Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0 ® LY62L256 Rev. 1.2 32K X 8 BIT LOW POWER CMOS SRAM GENERAL DESCRIPTION The LY62L256 is a 262,144-bit low power CMOS static random access memory organized as 32,768 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The LY62L256 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The LY62L256 operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are fully TTL compatible FEATURES Fast access time : 35/55/70ns Low power consumption: Operating current : 20/15/10mA (TYP.) Standby current : 0.5μA (TYP.) LL-version Single 2.7V ~ 3.6V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data retention voltage : 1.5V (MIN.) Green package available Package : 28-pin 600 mil PDIP 28-pin 330 mil SOP 28-pin 8mm x 13.4mm STSOP PRODUCT FAMILY Product Family LY62L256 LY62L256(E) LY62L256(I) Operating Temperature 0 ~ 70℃ -20 ~ 80℃ -40 ~ 85℃ Vcc Range 2.7 ~ 3.6V 2.7 ~ 3.6V 2.7 ~ 3.6V Speed 35/55/70ns 35/55/70ns 35/55/70ns Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 0.5µA(LL) 20/15/10mA 0.5µA(LL) 20/15/10mA 0.5µA(LL) 20/15/10mA FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION SYMBOL DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input Power Supply Ground Vcc Vss A0 - A14 DQ0 – DQ7 DECODER 32Kx8 MEMORY ARRAY CE# WE# OE# VCC VSS A0-A14 DQ0-DQ7 I/O DATA CIRCUIT COLUMN I/O CE# WE# OE# CONTROL CIRCUIT Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 1 ® LY62L256 Rev. 1.2 32K X 8 BIT LOW POWER CMOS SRAM PIN CONFIGURATION A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PDIP/SOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc WE# A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 OE# A11 A9 A8 A13 WE# Vcc A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 TA TSTG PD IOUT RATING -0.5 to 4.6 -0.5 to VCC+0.5 0 to 70(C grade) -20 to 80(E grade) -40 to 85(I grade) -65 to 150 1 50 UNIT V V ℃ ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. LY62L256 LY62L256 STSOP TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# H L L L OE# X H L X WE# X H H L I/O OPERATION High-Z High-Z DOUT DIN SUPPLY CURRENT ISB,ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 H = VIH, L = VIL, X = Don't care. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 2 ® LY62L256 Rev. 1.2 32K X 8 BIT LOW POWER CMOS SRAM DC ELECTRICAL CHARACTERISTICS SYMBOL TEST CONDITION PARAMETER Supply Voltage VCC *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current ILI VCC ≧ VIN ≧ VSS Output Leakage VCC ≧ VOUT ≧ VSS, ILO Current Output Disabled Output High Voltage VOH IOH = -1mA Output Low Voltage VOL IOL = 2mA -35 Cycle time = Min. ICC CE# = VIL , II/O = 0mA -55 Other pins at VIL or VIH Average Operating -70 Power supply Current Cycle time = 1µs ICC1 CE#≦0.2V and II/O = 0mA other pins at 0.2V or VCC-0.2V ISB CE# = VIH, others at VIL or VIH Standby Power CE# ≧VCC - 0.2V Supply Current -LL ISB1 Others at 0.2V orVCC - 0.2V Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. 10µA for special request 5. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃ MIN. 2.7 2.0 - 0.5 -1 -1 2.4 - TYP. 3.3 3.0 20 15 10 3 1 0.5 *5 MAX. 3.6 VCC+0.5 0.6 1 1 0.4 40 30 20 6 3 20 *4 UNIT V V V µA µA V V mA mA mA mA mA µA CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 6 8 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 3 ® LY62L256 Rev. 1.2 32K X 8 BIT LOW POWER CMOS SRAM AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH LY62L256-35 MIN. MAX. 35 35 35 25 10 5 15 15 10 LY62L256-55 MIN. MAX. 55 55 55 30 10 5 20 20 10 LY62L256-70 MIN. MAX. 70 70 70 35 10 5 25 25 10 UNIT ns ns ns ns ns ns ns ns ns SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* LY62L256-35 MIN. MAX. 35 30 30 0 25 0 20 0 5 15 LY62L256-55 MIN. MAX. 55 50 50 0 45 0 25 0 5 20 LY62L256-70 MIN. MAX. 70 60 60 0 55 0 30 0 5 25 UNIT ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4 ® LY62L256 Rev. 1.2 32K X 8 BIT LOW POWER CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout Previous Data Valid tOH Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE OE# tOE tOLZ tCLZ Dout High-Z tOH tOHZ tCHZ Data Valid High-Z Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low. 3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5 ® LY62L256 Rev. 1.2 WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW tAS WE# tWHZ Dout (4) High-Z tDW Din tDH TOW (4) tWP tWR 32K X 8 BIT LOW POWER CMOS SRAM Data Valid WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) tWC Address tAW CE# tAS tCW tWP WE# tWHZ Dout (4) High-Z tDW Din tDH tWR Data Valid Notes : 1.WE#, CE# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 6 ® LY62L256 Rev. 1.2 32K X 8 BIT LOW POWER CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time SYMBOL TEST CONDITION VDR CE# ≧ VCC - 0.2V VCC = 1.5V IDR CE# ≧ VCC - 0.2V Others at 0.2V or VCC-0.2V See Data Retention tCDR Waveforms (below) tR MIN. 1.5 -LL 0 tRC* TYP. 0.5 MAX. 3.6 10 UNIT V µA ns ns DATA RETENTION WAVEFORM VDR ≧ 1.5V Vcc Vcc(min.) tCDR CE# VIH CE# ≧ Vcc-0.2V Vcc(min.) tR VIH Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 7 ® LY62L256 Rev. 1.2 32K X 8 BIT LOW POWER CMOS SRAM PACKAGE OUTLINE DIMENSION 28 pin 600 mil PDIP Package Outline Dimension UNIT SYM. INCH.(BASE) 0.010 (MIN) 0.150±0.005 0.020 (MAX) 0.055 (MAX) 0.012 (MAX) 1.430 (MAX) 0.6 (TYP) 0.52 (MAX) 0.100 (TYP) 0.625 (MAX) 0.180(MAX) 0.06 (MAX) 0.08(MAX) o 15 (MAX) MM(REF) 0.254 (MIN) 3.810±0.127 0.508(MAX) 1.397(MAX) 0.304 (MAX) 36.322 (MAX) 15.24 (TYP) 13.208 (MAX) 2.540(TYP) 15.87 (MAX) 4.572(MAX) 1.524 (MAX) 2.032(MAX) o 15 (MAX) A1 A2 B B1 c D E E1 e eB L S Q1 Θ Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8 ® LY62L256 Rev. 1.2 32K X 8 BIT LOW POWER CMOS SRAM 28 pin 330 mil SOP Package Outline Dimension UNIT SYM. INCH(BASE) 0.120 (MAX) 0.002(MIN) 0.098±0.005 0.016 (TYP) 0.010 (TYP) 0.728 (MAX) 0.340 (MAX) 0.465±0.012 0.050 (TYP) 0.05 (MAX) 0.067±0.008 0.047 (MAX) 0.003(MAX) o o 0 ～10 MM(REF) 3.048 (MAX) 0.05(MIN) 2.489±0.127 0.406(TYP) 0.254(TYP) 18.491 (MAX) 8.636 (MAX) 11.811±0.305 1.270(TYP) 1.270 (MAX) 1.702 ±0.203 1.194 (MAX) 0.076(MAX) o o 0 ～10 A A1 A2 b c D E E1 e L L1 S y Θ Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 9 ® LY62L256 Rev. 1.2 32K X 8 BIT LOW POWER CMOS SRAM 28 pin 8x13.4mm STSOP Package Outline Dimension HD c L 12° (2x) 1 28 12° (2x) e 14 15 "A" D Seating Plane b E y 12° (2X) 14 15 GAUGE PLANE A A2 c 0.254 0 A1 SEATING PLANE 12° (2X) L 1 28 "A" DATAIL VIEW L1 SYMBOLS A A1 A2 b c HD D E e L L1 Y Θ DIMENSIONS IN MILLIMETERS MIN NOM MAX 1.00 1.10 1.20 0.05 0.15 0.91 1.00 1.05 0.17 0.22 0.27 0.10 0.15 0.20 13.20 13.40 13.60 11.70 11.80 11.90 7.90 8.00 8.10 0.55 0.30 0.50 0.70 0.675 0.00 0.076 0° 3° 5° DIMENSIONS IN INCHES MIN NOM MAX 0.040 0.043 0.047 0.002 0.006 0.036 0.039 0.041 0.007 0.009 0.011 0.004 0.006 0.008 0.520 0.528 0.535 0.461 0.465 0.469 0.311 0.315 0.319 0.0216 0.012 0.020 0.028 0.027 0.000 0.003 0° 3° 5° Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10 ® LY62L256 Rev. 1.2 32K X 8 BIT LOW POWER CMOS SRAM ORDERING INFORMATION LY62L256 U V - WW XX Y Z Z : Packing Type Blank : Tube or Tray T : Tape Reel Y : Temperature Range Blank : (Commercial) 0°C ~ 70°C E : (Extended) -20°C ~ +80°C I : (Industrial) -40°C ~ +85°C XX : Power Type LL : Ultra Low Power WW : Access Time(Speed) V : Lead Information L : Green Package U : Package Type P : 28-pin 600 mil P-DIP S : 28-pin 330 mil SOP R : 28-pin 8 mm x 13.4 mm STSOP Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 11 ® LY62L256 Rev. 1.2 32K X 8 BIT LOW POWER CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 12