Cover
88F6190 and 88F6192
Integrated Controller
Hardware Specifications
Doc. No. MV-S104987-U0, Rev. F December 2, 2008, Preliminary L Marvell. Moving Forward Faster Document Classification: Proprietary Information
88F619x Hardware Specifications
Document Conventions
Note: Provides related information or information of special importance.
Caution: Indicates potential damage to hardware or software, or loss of data.
Warning: Indicates a risk of personal injury.
Document Status
Doc Status: Preliminary Technical Publication: 0.xx
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Doc. No. MV-S104987-U0 Rev. F Page 2 Document Classification: Proprietary Information
Copyright © 2008 Marvell December 2, 2008, Preliminary
88F6190 and 88F6192
Integrated Controller
Hardware Specifications
PRODUCT OVERVIEW
The Marvell® 88F6190 and 88F6192 are high-performance, highly integrated controllers. These controllers are based on the Marvell proprietary, ARMv5TE-compliant, high-speed Sheeva™ CPU core. The CPU core integrates a 256 KB L2 cache.
Processor
Sheeva™ CPU Core
JTAG interface
16 KB-I, 16 KB-D cache Up to 600 MHz
L2 cache 256 KB
High Speed I/0
PCI Express
PCI Express x1
Memory
External DDR 400 MHz DDR SDRAM controller
SATA USB 2.0
SATA port
USB 2.0 port
AES/DES/ 3DES
SHA-1/MD5
Internal bus
Security Engine
Gigabit Ethernet IEEE 1588AVB support
Gigabit Ethernet Fast Ethernet
XOR Engine
4 XOR/DMA channels
Misc
Slow bus
UART x2 GPIO, TWSI
SPI, NAND, SDIO
Flash, SDIO
88F6190 Functional Block Diagram
Copyright © 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S104987-U0 Rev. F Page 3
88F619x Hardware Specifications
P rocessor
Sheeva™ C PU Core
JTAG interface
High Speed I/0
L2 cache 256 KB PCI Express SATA
PCI Express x1
16 KB-I, 16 KB-D cache Up to 800 M Hz
Dual SATA ports
Mem ory
External DDR 400 MHz DDR SDRAM controller
USB 2.0
USB 2.0 port
M edia interfaces Security Engine
AES/DES/ 3DES SHA-1/MD5 Audio
I 2 S / S/PDIF
MPEG TS
M PEG2-TS
XO R Engine
4 XOR/DM A channels
Misc
FXS / FXO
G igabit Ethernet IEEE 1588AVB support
TDM UART x2 GPIO, TW SI Slow bus GbE GbE
SPI, NAND, SDIO
Flash, SDIO
88F6192 Functional Block Diagram
Doc. No. MV-S104987-U0 Rev. F Page 4 Document Classification: Proprietary Information
Copyright © 2008 Marvell December 2, 2008, Preliminary
Features
FEATURES
88F6190 – Incorporates a single GbE port and a single SATA port. CPU speed is up to 600 MHz. 88F6192 – Incorporates two GbE ports and two SATA ports. CPU speed is up to 800 MHz. It also supports a Sony/Philips Digital Interconnect Format / Integrated Interchip Sound (S/PDIF / I2S) Audio interface, a TDM SLIC/SLAC Codec interface, and an MPEG Transport Stream (TS) interface. The 88F6190 and 88F6192 controllers include: • High-performance CPU core, running at up to 600 MHz in the 88F6190 or 800 MHz in the 88F6192, with integrated, four-way, set-associative L1 16-KB I-cache/16-KB D-cache and unified, 256-KB, four-way, set-associative L2 cache • High-bandwidth dual-port DDR2 memory interface (16-bit DDR2 SDRAM @ up to 400 MHz data rate) • PCI Express (x1) port with integrated PHY • Gigabit Ethernet (10/100/1000 Mbps) MAC(s) • USB 2.0 port with integrated PHY • SATA 2.0 port(s) with integrated 3 Gbps SATA II PHY • Security Cryptographic engine S/PDIF / I2S Audio in/out interface (88F6192 only) SD/SDIO/MMC interface TDM SLIC/SLAC Codec interface (88F6192 only) Two XOR engines, each containing two XOR/DMA channels (a total of four XOR/DMA channels) • MPEG Transport Stream (TS) interface (88F6192 only) • SPI port with SPI flash boot support • 8-bit NAND flash interface with boot support • Two 16550 compatible UART interfaces • TWSI port • 36 multi-purpose pins • Internal Real Time Clock (RTC) • Interrupt controller • Timers • 128-bit eFuse (one-time programmable memory) Sheeva™ CPU core • 88F6190 – Up to 600 MHz • 88F6192 – Up to 800 MHz • 32-bit and 16-bit RISC architecture • Compliant with v5TE architecture, as published in the ARM Architect Reference Manual, Second Edition • Includes MMU to support virtual memory features • 256-KB, four-way, set-associative L2 unified cache • 16-KB, four-way, set-associative I-cache • 16-KB, four-way, set-associative D-cache • 64-bit internal data bus
• Branch Prediction unit • Supports JTAG/ARM ICE • Supports both Big and Little Endian modes
DDR2 SDRAM controller • 16-bit interface • Up to 200 MHz clock frequency (400 MHz data rate) • DDR SDRAM with a clock ratio of 1:N and 2:N between the DDR SDRAM and the CPU core, respectively • SSTL 1.8V I/Os • Auto calibration of I/Os output impedance • Supports two DRAM chip selects • Supports all DDR devices densities up to1 Gb • Supports up to16 open pages (page per bank) • Up to 512 MB total address space • Supports on-board DDR designs (no DIMM support) • Supports 2T mode, to enable high-frequency operation under heavy load configuration • Supports DRAM bank interleaving • Supports up to a 128-byte burst per single memory access PCI Express interface (x1) • PCI Express Base 1.1 compatible • Integrated low-power SERDES PHY, based on proven Marvell® SERDES technology • Serves as a Root Complex or an Endpoint port • x1 link width • 2.5 Gbps data rate • Lane polarity reversal support • Maximum payload size of 128 bytes • Single Virtual Channel (VC-0) • Replay buffer support • Extended PCI Express configuration space • Advanced Error Reporting (AER) support • Power management: L0s and software L1 support • Interrupt emulation message support • Error message support PCI Express master specific features • Single outstanding read transaction • Maximum read request of up to 128 bytes • Maximum write request of up to 128 bytes • Up to four outstanding read transactions in Endpoint mode PCI Express target specific features • Supports up to eight read request transactions • Maximum read request size of 4 KB • Maximum write request of 128 bytes
• • • •
Copyright © 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S104987-U0 Rev. F Page 5
88F619x Hardware Specifications
• Supports PCI Express access to all of the
controller’s internal registers Integrated GbE (10/100/1000) MAC port(s) • 88F6190 – One GbE port and one Fast Ethernet port • 88F6192 – Two GbE ports • Supports 10/100/1000 Mbps • Dedicated DMA for data movement between memory and port • Priority queuing on receive based on Destination Address (DA), VLAN Tag, and IP TOS • Layer 2/3/4 frame encapsulation detection • TCP/IP checksum on receive and transmit • Supports proprietary 200 Mbps Marvell MII (MMII) interface • 88F6190 supports the following modes: - Port 0 RGMII, Port 1 MII/MMII - Port 0 GMII, Port 1 N/A • 88F6192 supports the following modes: - Port 0 RGMII, Port 1 RGMII - Port 0 RGMII, Port 1 MII/MMII - Port 0 MII/MMII, Port 1 RGMII - Port 0 GMII, Port 1 N/A • DA filtering Precise Timing Protocol (PTP) • Supports precise time stamping for packets, as defined in IEEE 1588 PTP v1 and v2 and IEEE 802.1AS draft standards • Supports Flexible Time Application interface to distribute PTP clock and time to other devices in the system • Optionally accepts an external clock input for time stamping Audio Video Bridging networks • Supports IEEE 802.1Qav draft Audio Video Bridging networks • Supports time- and priority-aware egress pacing algorithm to prevent bunching and bursting effects—suitable for audio/video applications • Supports Egress Jitter Pacer for AVB-Class A and AVB-Class B traffic and strict priority for legacy traffic queues USB 2.0 port • Serves as a peripheral or host • USB 2.0 compliant • Integrated USB 2.0 PHY • Enhanced Host Controller Interface (EHCI) compatible as a host • As a host, supports direct connection to all peripheral types (LS, FS, HS) • As a peripheral, connects to all host types (HS, FS) and hubs
• Up to four independent endpoints, supporting
control, interrupt, bulk, and isochronous data transfers • Dedicated DMA for data movement between memory and port Integrated Marvell 3 Gbps (Gen2i) SATA PHYs • 88F6190 – Single SATA port • 88F6192 – Two SATA ports • Compliant with SATA II Phase 1 specifications - Supports SATA II Native Command Queuing (NCQ), up to 128 outstanding commands per port - Fully supports first party DMA (FPDMA) - Backwards compatible with SATA I devices • Supports SATA II Phase 2 advanced features - 3 Gbps (Gen2i) SATA II speed - Port Multiplier (PM)—performs FIS-based switching, as defined in SATA working group PM definition - Port Selector (PS)—issues the protocol-based Out-Of-Band (OOB) sequence, for selecting the active host port • Supports device 48-bit addressing • Supports ATA Tag Command Queuing SATA II Host controller • Enhanced-DMA (EDMA) for the SATA ports • Automatic command execution, without host intervention • Command queuing support, for up to 32 outstanding commands • Separate SATA request/response queues • 64-bit addressing support for descriptors and data buffers in system memory • Read ahead • Advanced interrupt coalescing • Target mode operation—supports attaching two 88F6190/88F6192 controllers through their Serial-ATA ports, enabling data communication between the 88F6190/88F6192 controllers • Advanced drive diagnostics via the ATA SMART command Cryptographic engine • Hardware implementation on encryption and authentication engines, to boost packet processing speed • Dedicated DMA to feed the hardware engines with data from the internal SRAM memory or from the DDR memory • Implements AES, DES, and 3DES encryption algorithms • Implements SHA1 and MD5 authentication algorithms
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Copyright © 2008 Marvell December 2, 2008, Preliminary
Features
S/PDIF / I2S Audio In/Out interface (88F6192 only) • Either S/PDIF or I2S inputs can be active at one time • Both S/PDIF and I2S outputs can be active simultaneously, transferring the same PCM data S/PDIF-specific features (88F6192 only) • Compliant with 60958-1, 60958-3, and IEC61937 specifications • Sample rates of 44.1/48/96 kHz • 16/20/24-bit depths I2S-specific features (88F6192 only) • Sample rates of 44.1/48/96 kHz
Serial Peripheral Interface (SPI) controller • Up to 41.6 MHz clock • Supports direct boot from external SPI serial flash memory MPEG Transport Stream (TS) interface (88F6192 only) • ISO/IEC 13818-1 standard compliant • Supports any one of the following modes: - Parallel (8 bit) input - Parallel output - Two independent serial interfaces • Data rate up to 80 Mbps Two UART interfaces • 16550 UART compatible • Two pins for transmit and receive operations • Two pins for modem control functions Two-Wire Serial Interface (TWSI) • General purpose TWSI master/slave port • Can also be used for serial ROM initialization 36 dedicated Multi-Purpose Pins (MPPS) for peripheral functions and general purpose I/O • Each pin can be configured independently. • GPIO inputs can be used to register interrupts from external devices, and to generate maskable interrupts. • In the 88F6192, one of the following multiplexed interfaces may be configured at a time: - Audio - TS - TDM - GbE Port 0 in GMII mode or GbE Port 1 Interrupt Controller Maskable interrupts to CPU core (and PCI Express for a PCI Express endpoint) Two general purpose 32-bit timers/counters Internal architecture • Mbus-L bus for high-performance, low-latency CPU core to DDR SDRAM connectivity • Advanced Mbus architecture • Dual port DDR SDRAM controller connectivity to both CPU and Mbus Bootable from • SPI flash • SATA device • NAND flash • PCI Express • UART (for debug purpose) 216-pin LQFP package, 24 x 24 mm, 0.4 mm pitch
• I2S input and I2S output operate at the same
sample rate
• 16/24-bit depths • I2S in and I2S out support independent bit depths
(16 bit/24 bit)
• Supports plain I2S, right-justified and left-justified
formats SD/SDIO/MMC host interface • 1-bit/4-bit SDmem, SDIO, and MMC cards • Up to 50 MHz • Hardware generate/check CRC, on all command and data transactions on the card bus TDM SLIC/SLAC Codec interface (88F6192 only) • Generic interface to standard SLIC/SLAC codec devices • Compatible with standard PCM highway formats • TDM protocol support for two channels, up to 128 time slots • Dedicated SPI interface for codec management • Integrated DMA to transfer voice data to/from memory buffer Two XOR engines and DMA • Two XOR/DMA channels per XOR engine (for a total of four XOR/DMA channels) • Chaining via linked-lists of descriptors • Moves data from source interface to destination interface • Supports increment or hold on both Source and Destination Addresses • Supports XOR operation, on up to eight source blocks—useful for RAID applications • Supports iSCSI CRC-32 calculation NAND flash controller • 8-bit NAND flash interface • Glueless interface to CE Care and CE Don’t Care NAND flash devices • Boot support
Copyright © 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S104987-U0 Rev. F Page 7
88F619x Hardware Specifications
Hard Disk Drive
PCI Express Mini Card Wi-Fi
x1
x16
On Board DDR2
88F6190
USB Host SPI Flash
Gigabit Ethernet PHY
88F6190 Usage Model Example: Common NAS Application
SATA Port Multiplier
Hard Disk Drive
PCI Express Mini Card Wi-Fi
x1
x16
On Board DDR2
88F6192
USB Host SPI Flash
Gigabit Ethernet PHY
88F6192 Usage Model Example: Common NAS Application
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Copyright © 2008 Marvell December 2, 2008, Preliminary
Table of Contents
Table of Contents
Product Overview ....................................................................................................................................... 3 Features....................................................................................................................................................... 5 Preface.......................................................................................................................................................16
About this Document .......................................................................................................................................16 Related Documentation...................................................................................................................................16 Document Conventions ...................................................................................................................................17
1 2
2.1 2.2 2.3
Overview....................................................................................................................................... 18 Pin and Signal Descriptions ....................................................................................................... 20
Pin Logic .........................................................................................................................................................21 Pin Descriptions ..............................................................................................................................................23 Internal Pull-up and Pull-down Pins ................................................................................................................55
3 4 5 6
6.1 6.2 6.3
Unused Interface Strapping........................................................................................................ 56 88F6190 Pinout ............................................................................................................................ 57 88F6192 Pinout ............................................................................................................................ 59 Pin Multiplexing ........................................................................................................................... 61
Multi-Purpose Pins Functional Summary ........................................................................................................61 Gigabit Ethernet (GbE) Pins Multiplexing on MPP ..........................................................................................68 TSMP (TS Multiplexing Pins) on MPP.............................................................................................................70
7
7.1
Clocking ....................................................................................................................................... 71
Spread Spectrum Clock Generator (SSCG)....................................................................................................72
8
8.1 8.2 8.3 8.4 8.5 8.6 8.7
System Power Up/Down and Reset Settings ............................................................................ 73
Power-Up/Down Sequence Requirements......................................................................................................73 Hardware Reset ..............................................................................................................................................74 PCI Express Reset ..........................................................................................................................................76 Sheeva™ CPU TAP Controller Reset..............................................................................................................76 Pins Sample Configuration..............................................................................................................................76 Serial ROM Initialization ..................................................................................................................................80 Boot Sequence................................................................................................................................................81
Copyright © 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S104987-U0 Rev. F Page 9
88F619x Hardware Specifications
9
9.1 9.2 9.3 9.4 9.5
JTAG Interface ............................................................................................................................. 83
TAP Controller.................................................................................................................................................83 Instruction Register .........................................................................................................................................83 Bypass Register ..............................................................................................................................................84 JTAG Scan Chain ...........................................................................................................................................84 ID Register ......................................................................................................................................................84
10
10.1 10.2 10.3 10.4 10.5 10.6 10.7
Electrical Specifications (Preliminary) ......................................................................................85
Absolute Maximum Ratings ............................................................................................................................85 Recommended Operating Conditions .............................................................................................................87 Thermal Power Dissipation .............................................................................................................................89 Current Consumption ......................................................................................................................................91 DC Electrical Specifications ............................................................................................................................92 AC Electrical Specifications ............................................................................................................................97 Differential Interface Electrical Characteristics..............................................................................................127
11 12 13
13.1 13.2
Thermal Data (Preliminary) .......................................................................................................138 Package ......................................................................................................................................139 Part Order Numbering/Package Marking ................................................................................141
Part Order Numbering ...................................................................................................................................141 Package Marking ..........................................................................................................................................142
A
Revision History ........................................................................................................................143
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Copyright © 2008 Marvell December 2, 2008, Preliminary
List of Tables
List of Tables
1 2 Overview............................................................................................................................................ 18
Table 1: 88F6190 and 88F6192 Device Differences ......................................................................................18
Pin and Signal Descriptions ............................................................................................................ 20
Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Pin Functions and Assignments Table Key ......................................................................................23 Interface Pin Prefix Codes ................................................................................................................23 Power Pin Assignments ....................................................................................................................25 Miscellaneous Pin Assignments .......................................................................................................27 DDR SDRAM Interface Pin Assignments .........................................................................................28 PCI Express Interface Pin Assignments ...........................................................................................30 SATA Port Interface Pin Assignment ................................................................................................31 88F6190 Gigabit Ethernet Interface Pin Assignments .....................................................................32 88F6192 Gigabit Ethernet Port0/1 Interface Pin Assignments ........................................................34 Serial Management Interface (SMI) Pin Assignments ......................................................................39 USB 2.0 Interface Pin Assignments..................................................................................................40 JTAG Pin Assignment.......................................................................................................................41 RTC Interface Pin Assignments........................................................................................................42 NAND Flash Interface Pin Assignment .............................................................................................43 MPP Interface Pin Assignment .........................................................................................................44 Two-Wire Serial Interface (TWSI) Interface Pin Assignment ............................................................45 UART Port 0/1 Interface Pin Assignment .........................................................................................46 Audio (S/PDIF / I2S) Interface Signal Assignment ............................................................................47 Serial Peripheral Interface (SPI) Interface Signal Assignment .........................................................48 Secure Digital Input/Output (SDIO) Interface Signal Assignment.....................................................49 Time Division Multiplexing (TDM) Interface Signal Assignment .......................................................50 Transport Stream (TS) Interface Signal Assignment ........................................................................52 Precise Timing Protocol (PTP) Interface Signal Assignment............................................................54 Internal Pull-up and Pull-down Pins ..................................................................................................55
3 4 5 6
Unused Interface Strapping............................................................................................................. 56
Table 26: Unused Interface Strapping ..............................................................................................................56
88F6190 Pinout ................................................................................................................................. 57
Table 27: 88F6190 Pinout Sorted by Pin Number ............................................................................................58
88F6192 Pinout ................................................................................................................................. 59
Table 28: 88F6192 Pinout Sorted by Pin Number ............................................................................................60
Pin Multiplexing ................................................................................................................................ 61
Table 29: Table 30: Table 31: MPP Functionality .............................................................................................................................62 88F6190 MPP Function Summary....................................................................................................63 88F6192 MPP Function Summary....................................................................................................65
Copyright © 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S104987-U0 Rev. F Page 11
88F619x Hardware Specifications
Table 32: Table 33: Table 34:
88F6190 Ethernet Ports Pins Multiplexing........................................................................................68 88F6192 Ethernet Ports Pins Multiplexing........................................................................................69 TS Port Pin Multiplexing .................................................................................................................70
7
Clocking............................................................................................................................................. 71
Table 35: Table 36: 88F619x Clocks ................................................................................................................................71 Supported Clock Combinations ........................................................................................................72
8
System Power Up/Down and Reset Settings ................................................................................. 73
Table 37: Table 38: I/O and Core Voltages ......................................................................................................................73 Reset Configuration ..........................................................................................................................77
9
JTAG Interface .................................................................................................................................. 83
Table 39: Table 40: Supported JTAG Instructions............................................................................................................83 IDCODE Register Map .....................................................................................................................84
10
Electrical Specifications (Preliminary) ........................................................................................... 85
Table 41: Table 42: Table 43: Table 44: Table 45: Table 46: Table 47: Table 48: Table 49: Table 50: Table 51: Table 52: Table 53: Table 54: Table 55: Table 56: Table 57: Table 58: Table 59: Table 60: Table 61: Table 62: Table 63: Table 64: Table 65: Table 66: Table 67: Table 68: Table 69: Absolute Maximum Ratings ..............................................................................................................85 Recommended Operating Conditions...............................................................................................87 Thermal Power Dissipation ...............................................................................................................89 Current Consumption........................................................................................................................91 General 3.3V Interface (CMOS) DC Electrical Specifications...........................................................92 RGMII 1.8V Interface (CMOS) DC Electrical Specifications .............................................................93 SDRAM DDR2 Interface DC Electrical Specifications ......................................................................94 TWSI Interface 3.3V DC Electrical Specifications.............................................................................95 SPI Interface 3.3V DC Electrical Specifications................................................................................95 TDM Interface 3.3V DC Electrical Specifications..............................................................................96 Reference Clock AC Timing Specifications ......................................................................................97 SDRAM DDR2 Interface AC Timing Table .......................................................................................99 RGMII 10/100/1000 AC Timing Table at 1.8V ................................................................................102 RGMII 10/100 AC Timing Table at 3.3V .........................................................................................102 GMII AC Timing Table ....................................................................................................................104 MII/MMII MAC Mode AC Timing Table ...........................................................................................106 SMI Master Mode AC Timing Table................................................................................................108 JTAG Interface AC Timing Table ....................................................................................................110 TWSI Master AC Timing Table .......................................................................................................112 TWSI Slave AC Timing Table .........................................................................................................112 S/PDIF AC Timing Table ................................................................................................................114 Inter-IC Sound (I2S) AC Timing Table ............................................................................................116 TDM Interface AC Timing Table .....................................................................................................118 SPI (Master Mode) AC Timing Table ..............................................................................................120 SDIO Host in High Speed Mode AC Timing Table .........................................................................122 Transport Stream Output Interface AC Timing Table ....................................................................124 Transport Stream Input Interface AC Timing Table ........................................................................124 PCI Express Interface Differential Reference Clock Characteristics ..............................................127 PCI Express Interface Spread Spectrum Requirements.................................................................128
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Copyright © 2008 Marvell December 2, 2008, Preliminary
List of Tables
Table 70: Table 71: Table 72: Table 73: Table 74: Table 75:
PCI Express Interface Driver and Receiver Characteristics ...........................................................129 SATA-I Interface Gen1i Mode Driver and Receiver Characteristics ...............................................132 SATA-II Interface Gen2i Mode Driver and Receiver Characteristics ..............................................133 USB Low Speed Driver and Receiver Characteristics ....................................................................134 USB Full Speed Driver and Receiver Characteristics.....................................................................135 USB High Speed Driver and Receiver Characteristics ...................................................................136
11 12
Thermal Data (Preliminary) ............................................................................................................138
Table 76: Thermal Data for the 88F619x in the QFP 216-pin Package (Preliminary) ....................................138
Package ...........................................................................................................................................139
Table 77: Table 78: LQFP 216-pin Package Dimensions...............................................................................................140 LQFP 216-pin Package Exposed Pad (ePAD) Size .......................................................................140
13 A
Part Order Numbering/Package Marking......................................................................................141
Table 79: Part Order Options..........................................................................................................................141
Revision History .............................................................................................................................143
Table 80: Revision History ..............................................................................................................................143
Copyright © 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S104987-U0 Rev. F Page 13
88F619x Hardware Specifications
List of Figures
1 2 Overview........................................................................................................................................... 18 Pin and Signal Descriptions ........................................................................................................... 20
Figure 1: Figure 2: 88F6190 Pin Logic Diagram .............................................................................................................21 88F6192 Pin Logic Diagram .............................................................................................................22
3 4
Unused Interface Strapping............................................................................................................ 56 88F6190 Pinout ................................................................................................................................ 57
Figure 3: 88F6190 Pin Map Top View .............................................................................................................57
5
88F6192 Pinout ................................................................................................................................ 59
Figure 4: 88F6192 Pin Map Top View .............................................................................................................59
6 7 8
Pin Multiplexing ............................................................................................................................... 61 Clocking............................................................................................................................................ 71 System Power Up/Down and Reset Settings ................................................................................ 73
Figure 5: Figure 6: Figure 7: Power-Up Sequence Example..........................................................................................................74 Serial ROM Data Structure ...............................................................................................................80 Serial ROM Read Example...............................................................................................................81
9 10
JTAG Interface ................................................................................................................................. 83 Electrical Specifications (Preliminary) .......................................................................................... 85
Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: SDRAM DDR2 Interface Test Circuit ..............................................................................................100 SDRAM DDR2 Interface Write AC Timing Diagram .......................................................................100 SDRAM DDR2 Interface Address and Control AC Timing Diagram ...............................................101 SDRAM DDR2 Interface Read AC Timing Diagram .......................................................................101 RGMII Test Circuit ..........................................................................................................................103 RGMII AC Timing Diagram .............................................................................................................103 GMII Test Circuit .............................................................................................................................104 GMII Output AC Timing Diagram ....................................................................................................105 GMII Input AC Timing Diagram.......................................................................................................105 MII/MMII MAC Mode Test Circuit....................................................................................................106 MII/MMII MAC Mode Output Delay AC Timing Diagram.................................................................106 MII/MMII MAC Mode Input AC Timing Diagram..............................................................................107 MDIO Master Mode Test Circuit .....................................................................................................108 MDC Master Mode Test Circuit ......................................................................................................109 SMI Master Mode Output AC Timing Diagram ...............................................................................109 SMI Master Mode Input AC Timing Diagram ..................................................................................109 JTAG Interface Test Circuit ............................................................................................................110
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Copyright © 2008 Marvell December 2, 2008, Preliminary
List of Figures
Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49:
JTAG Interface Output Delay AC Timing Diagram .........................................................................111 JTAG Interface Input AC Timing Diagram ......................................................................................111 TWSI Test Circuit............................................................................................................................113 TWSI Output Delay AC Timing Diagram.........................................................................................113 TWSI Input AC Timing Diagram .....................................................................................................113 S/PDIF Test Circuit .........................................................................................................................115 Inter-IC Sound (I2S) Test Circuit ....................................................................................................116 Inter-IC Sound (I2S) Output Delay AC Timing Diagram .................................................................117 Inter-IC Sound (I2S) Input AC Timing Diagram ..............................................................................117 TDM Interface Test Circuit ..............................................................................................................119 TDM Interface Output Delay AC Timing Diagram...........................................................................119 TDM Interface Input Delay AC Timing Diagram..............................................................................119 SPI (Master Mode) Test Circuit ......................................................................................................120 SPI (Master Mode) Output AC Timing Diagram .............................................................................121 SPI (Master Mode) Input AC Timing Diagram ................................................................................121 Secure Digital Input/Output (SDIO) Test Circuit .............................................................................122 SDIO Host in High Speed Mode Output AC Timing Diagram .........................................................123 SDIO Host in High Speed Mode Input AC Timing Diagram............................................................123 Transport Stream Interface Test Circuit..........................................................................................125 Transport Stream Output Interface AC Timing Diagram ................................................................125 Transport Stream Input Interface AC Timing Diagram ...................................................................126 PCI Express Interface Test Circuit..................................................................................................130 Low/Full Speed Data Signal Rise and Fall Time ............................................................................136 High Speed TX Eye Diagram Pattern Template .............................................................................137 High Speed RX Eye Diagram Pattern Template.............................................................................137
11 12
Thermal Data (Preliminary) ........................................................................................................... 138 Package .......................................................................................................................................... 139
Figure 50: LQFP 216-pin Package and Dimensions........................................................................................139
13
Part Order Numbering/Package Marking..................................................................................... 141
Figure 51: Figure 52: Sample Part Number ......................................................................................................................141 Package Marking and Pin 1 Location .............................................................................................142
Copyright © 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S104987-U0 Rev. F Page 15
88F619x Hardware Specifications
Preface
About this Document
This datasheet provides the hardware specifications for the 88F6190 and 88F6192 integrated controllers. The hardware specifications include detailed pin information, configuration settings, electrical characteristics and physical specifications. This datasheet is intended to be the basic source of information for designers of new systems. All feature descriptions and specifications described in this document refer to both controllers, unless otherwise specified. In this document, the 88F6190 and 88F6192 are often referred to as “88F619x“ or “the device(s)”.
Related Documentation
The following documents contain additional information related to the 88F619x: 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications, Doc No. MV-S104860-U0 Sheeva™ 88SV131 ARM v5TE Processor Core with MMU and L1/L2 Cache Datasheet, Doc No. MV-S104950-U0 Unified Layer 2 (L2) Cache for Sheeva™ CPU Cores Addendum, Doc No. MV-S104858-U0 88F6180, 88F6190, 88F6192, and 88F6281 Functional Errata, Interface Guidelines, and Restrictions, Doc No. MV-S501157-U0 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide, Doc No. MV-S301398-001 AN-63: Thermal Management for Marvell Technology Products Doc No. MV-S300281-001 AN-179: TWSI Software Guidelines for Discovery™, Horizon™, and Feroceon® Devices, Doc No. MV-S300754-001 AN-183: 88F5181 and 88F5281 Big Endian and Little Endian Support, Doc No. MV-S300767-001 AN-249: Configuring the Marvell® SATA PHY to Transmit Predefined Test Patterns, Doc No. MV-S301342-001 AN-260 System Power-Saving Methods for 88F6180, 88F6190, 88F6192, and 88F6281, Doc No. MV-S301454-001 TB-227: Differences Between the 88F6190, 88F6192, and 88F6281 Stepping Z0 and A0, Doc No. MV-S105223-001 White Paper, ThetaJC, ThetaJA, and Temperature Calculations, Doc No. MV-S700019-00 ARM Architecture Reference Manual, Second Edition PCI Express Base Specification, Revision 1.1 Universal Serial Bus Specification, Revision 2.0, April 2000, Compaq, Hewlett-Packard, Intel, Lucent, Microsoft, NEC, Philips Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 0.95, November 2000, Intel Corporation ARC USB-HS OTG High-Speed Controller Core reference V 4.0.1 Federal Information Processing Standards (FIPS) 46-2 (Data Encryption Standard)
1. This document is a Marvell proprietary, confidential document, requiring an NDA and can be downloaded from the Marvell Extranet.
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Copyright © 2008 Marvell December 2, 2008, Preliminary
Preface
Document Conventions
FIPS 81 (DES Modes of Operation) FIPS 180-1 (Secure Hash Standard) FIPS draft - Advanced Encryption Standard (Rijndeal) RFC 1321 (The MD5 Message-Digest Algorithm) RFC 1851 – The ESP Triple DES Transform RFC 2104 (HMAC: Keyed-Hashing for Message Authentication). RFC 2405 – The ESP DES-CBC Cipher Algorithm With Explicit IV IEEE standard, 802.3-2000 Clause 14 ANSI standard X3.263-1995 See the Marvell Extranet website for the latest product documentation.
Document Conventions
The following conventions are used in this document:
Signal Range
A signal name followed by a range enclosed in brackets represents a range of logically related signals. The first number in the range indicates the most significant bit (MSb) and the last number indicates the least significant bit (LSb). Example: DB_Addr[12:0]
Active Low Signals #
An n letter at the end of a signal name indicates that the signal’s active state occurs when voltage is low. Example: INTn
State Names
State names are indicated in italic font. Example: linkfail
Register Naming Conventions
Register field names are indicated by angle brackets. Example: Register field bits are enclosed in brackets. Example: Field [1:0] Register addresses are represented in hexadecimal format. Example: 0x0 Reserved: The contents of the register are reserved for internal use only or for future use. A lowercase in angle brackets in a register indicates that there are multiple registers with this name. Example: Multicast Configuration Register
Reset Values
Reset values have the following meanings: 0 = Bit clear 1 = Bit set Kb: kilobit KB: kilobyte Mb: megabit MB: megabyte Gb: gigabit GB: gigabyte Unless otherwise indicated, all numbers in this document are decimal (base 10). An 0x prefix indicates a hexadecimal number. An 0b prefix indicates a binary number.
Abbreviations
Numbering Conventions
Copyright © 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S104987-U0 Rev. F Page 17
88F619x Hardware Specifications
1
Overview
The Marvell® 88F6190 and 88F6192 devices are high-performance, highly integrated controllers. The devices are based on the ARMv5TE-compliant, high-speed Sheeva™ 88SV131 CPU core with 256 KB L2 cache. Table 1 provides a list of the differences between the 88F6190 and 88F6192 devices.
Table 1:
™
88F6190 and 88F6192 Device Differences
88 F 6 1 9 0 88F6192 Running at up to 800 MHz L2 cache at up to 400 MHz Yes1
Sheeva
CPU Core
Running at up to 600 MHz L2 cache at up to 300 MHz No
Time Division Multiplexing (SLIC/codec) Interface Serial ATA II (SATA II) Interface Gigabit Ethernet Interface
1 port 2 Ethernet ports • Port0 RGMII, Port1 MII/MMII • Port0 GMII, Port1 N/A
2 ports 2 Ethernet ports1 • Port0 RGMII, Port1 RGMII • Port0 RGMII, Port1 MII/MMII • Port0 MII/MMII, Port1 RGMII • Port0 GMII, Port1 N/A Yes1 Yes1 • • • • • Up to 200 MHz clock frequency with an 400 MHz data rate Supports two DRAM chip selects Supports all DDR devices densities up to 1Gb Supports up to 16 open pages (page per bank) Up to 512 MB total address space Yes Yes Yes
Audio S/PDIF / I2S Interface MPEG Video / Transport Stream Interface (TS) DDR SDRAM Interface
No No
PCI Express Interface USB 2.0 Interface Cryptographic Engine and Security Accelerator XOR engine and DMA Two-Wire Serial Interface (TWSI) UART Interface NAND Flash Interface SPI Serial Flash Interface SDIO Interface
Yes 1 port 2 ports Yes Yes Yes
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Overview
Table 1:
88F6190 and 88F6192 Device Differences (Continued)
88 F 6 1 9 0 88F6192 36-bits Yes
General-Purpose I/O Port Real-Time Clock (RTC)
1. The following interfaces are multiplexed and only one of them may be selected at a time: - Audio - TS - TDM - GbE Port 0 in GMII mode - GbE Port 1 For further details, see Section 6, Pin Multiplexing, on page 61.
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Doc. No. MV-S104987-U0 Rev. F Page 19
88F619x Hardware Specifications
2
Pin and Signal Descriptions
This section provides a detailed description of the 88F6190 and 88F6192 device pin assignments and their functionality.
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Pin and Signal Descriptions
Pin Logic
2.1
Pin Logic
Figure 1: 88F6190 Pin Logic Diagram
REF_CLK_XIN
VDD VDDO VDD_GE_A VDD_GE_B VDD_M VSS CPU_PLL_AVDD CORE_PLL_AVDD XTAL_AVDD XTAL_AVSS PEX_AVDD SATA_AVDD USB_AVDD RTC_AVDD SSCG_AVDD VHV MPP[35:0]
Misc.
XOUT SYSRSTn TP ISET NC
Power PCI Express
PEX_CLK_P PEX_CLK_N PEX_TX_P PEX_TX_N PEX_RX_P PEX_RX_N PEX_ISET
MPP
USB
USB_DP USB_DM
NF_CLE NF_ALE NF_CEn NF_REn NF_WEn
GE_TXCLKOUT GE_TXD[3:0]
NAND Flash
Gigabit Ethernet
GE_TXCTL GE_RXD[3:0] GE_RXCTL GE_RXCLK GE_MDC GE_MDIO
JT_CLK JT_TDI JT_TDO JT_TMS_CPU JT_TMS_CORE JT_RSTn
JTAG
M_CLKOUT M_CLKOUTn M_CKE M_RASn M_CASn M_WEn M_A[13:0] M_BA[2:0] M_CSn[1:0] M_DQ[15:0] M_DQS[1:0] M_DQSn[1:0] M_DM[1:0] M_ODT M_STARTBURST M_STARTBURST_IN M_PCAL M_NCAL
SATA_T_P SATA_T_N SATA_R_P SATA_R_N
SATA
SDRAM
RTC_XIN RTC_XOUT
RTC
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Doc. No. MV-S104987-U0 Rev. F Page 21
88F619x Hardware Specifications
Figure 2: 88F6192 Pin Logic Diagram
VDD VDDO VDD_GE_A VDD_GE_B VDD_M VSS CPU_PLL_AVDD CORE_PLL_AVDD XTAL_AVDD XTAL_AVSS PEX_AVDD SATA0_AVDD SATA1_AVDD USB_AVDD RTC_AVDD SSCG_AVDD VHV
REF_CLK_XIN
Misc.
XOUT SYSRSTn TP ISET
Power PCI Express
PEX_CLK_P PEX_CLK_N PEX_TX_P PEX_TX_N PEX_RX_P PEX_RX_N PEX_ISET
USB
MPP[35:0]
USB_DP USB_DM
MPP
GE_TXCLKOUT GE_TXD[3:0]
NF_CLE NF_ALE NF_CEn NF_REn NF_WEn
NAND Flash
Gigabit Ethernet
GE_TXCTL GE_RXD[3:0] GE_RXCTL GE_RXCLK GE_MDC GE_MDIO
JT_CLK JT_TDI JT_TDO JT_TMS_CPU JT_TMS_CORE JT_RSTn
JTAG
M_CLKOUT M_CLKOUTn M_CKE M_RASn M_CASn M_WEn M_A[13:0] M_BA[2:0] M_CSn[1:0] M_DQ[15:0] M_DQS[1:0] M_DQSn[1:0] M_DM[1:0] M_ODT M_STARTBURST M_STARTBURST_IN M_PCAL M_NCAL
SATA0_T_P SATA0_T_N SATA0_R_P SATA0_R_N SATA1_T_P SATA1_T_N SATA1_R_P SATA1_R_N RTC_XIN RTC_XOUT
SDRAM SATA0/1
RTC
NOTE: The GE_TXCLKOUT pin is an input only when used as the MII/MMII Transmit Clock (88F6192 only).
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Pin and Signal Descriptions
Pin Descriptions
For details about MPP configuration options see Section 6.1, Multi-Purpose Pins Functional Summary, on page 61.
2.2
Pin Descriptions
This section details all the pins for the different interfaces providing a functional description of each pin and pin attributes. Table 2 defines the abbreviations and acronyms used in the pin description tables.
Table 2:
Te r m [n] Analog Calib CML CMOS DDR GND HCSL I I/O O o/d
Pin Functions and Assignments Table Key
D e fi n it io n n - Represents the SERDES pair number Represents port number when there are more than one ports Analog Driver/Receiver or Power Supply Calibration pad type Common Mode Logic Complementary Metal-Oxide-Semiconductor Double Data Rate Ground Supply High-speed Current Steering Logic Input Input/Output Output Open Drain pin The pin allows multiple drivers simultaneously (wire-OR connection). A pullup is required to sustain the inactive value. VDD Power Supply Stub Series Terminated Logic for 1.8V Tri-State pin n - Suffix represents an Active Low Signal
Power SSTL t/s XXXn
Table 3:
In t e r f a c e Misc
Interface Pin Prefix Codes
P re fi x N/A M_ PEX_ 88F6190– SATA_ 88F6192 – SATA0_, SATA1_
DDR SDRAM PCI Express SATA
Gigabit Ethernet
GE_
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88F619x Hardware Specifications
Table 3:
In t e r f a c e USB 2.0 JTAG RTC
Interface Pin Prefix Codes (Continued)
P re fi x USB_ JT_ RTC_ NF_ N/A TW_ UA0_ UA1_ AU_ SPI_ SD_ TDM_ PTP_
NAND Flash MPP TWSI UART
Audio SPI SDIO TDM PTP
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Pin and Signal Descriptions
Pin Descriptions
2.2.1
Power Supply Pins
Table 4 provides the voltage levels for the various interface pins. These do not include the analog power supplies for the PLLs or PHYs which are explicitly mentioned in the other pin description tables.
Table 4:
Power Pin Assignments
I /O Pi n Ty p e Power Power Power D es c r ip t i o n
Pin Name
VDD VDDO For the 88F6190 – VDD_GE_A
I I I
1.0V Digital core and CPU voltage 3.3V I/O power for MPP[19:0] and JTAG pins 1.8 or 3.3V I/O supply voltage for RGMII and SMI interfaces 3.3V I/O supply voltage for GMII and SMI interfaces 3.3V I/O supply voltage for SMI interface when operating in MII/MMII mode. NOTE: When configure to RGMII mode at 3.3V, only 10/100 Mbps operation is supported. 3.3V I/O supply voltage for GMII and MII/MMII interfaces. 3.3V I/O supply voltage for MPP[35:20]. 1.8V or 3.3V I/O supply voltage for RGMII and SMI interfaces 3.3V I/O supply voltage for GMII, MII/MMII, and SMI interfaces NOTE: When configure to RGMII mode at 3.3V, only 10/100 Mbps operation is supported. I/O power for MPP[35:20] 1.8V or 3.3V I/O supply voltage for RGMII interfaces 3.3V I/O supply voltage for GMII and MII/MMII interfaces NOTE: When configure to RGMII mode at 3.3V, only 10/100 Mbps operation is supported. 1.8V I/O supply voltage for the DDR2 SDRAM interface VSS 1.8V analog quiet power to CPU PLL NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for power supply filtering recommendations. 1.8V analog quiet power to Core PLL NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for power supply filtering recommendations. 1.8V quiet power supply to the internal Spread Spectrum Clock Generator 1.8V analog quiet power to on-chip clock inverter for supporting external crystal, and on-chip current reference for SATA and USB PHYs NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for power supply filtering recommendations.
For the 88F6190 – VDD_GE_B For the 88F6192 – VDD_GE_A
I
Power
I
Power
For the 88F6192 – VDD_GE_B
I
Power
VDD_M VSS CPU_PLL_AVDD
I I I
Power GND Power
CORE_PLL_AVDD
I
Power
SSCG_AVDD
I
Power
XTAL_AVDD
I
Power
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Doc. No. MV-S104987-U0 Rev. F Page 25
88F619x Hardware Specifications
Table 4:
Power Pin Assignments (Continued)
I /O Pi n Ty p e Power D es c r ip t i o n
Pin Name
VHV
I
I/O supply voltage for eFuse: • 2.5V for eFuse burning only • 1.0V for eFuse reading only PCI Express PHY quiet power supply 1.8V NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for power supply filtering recommendations. SATA II port quiet 3.3V power supply NOTE: See 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for power supply filtering recommendation. SATA II port0/1 quiet 3.3V power supply NOTE: See 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for power supply filtering recommendation. USB 2.0 PHY quiet 3.3V power supply NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for power supply filtering recommendation. 1.5V (via battery) or 1.8V (via the board) RTC interface voltage RTC ground
PEX_AVDD
I
Power
88F6190 – SATA_AVDD
I
Power
88F6192– SATA0_AVDD SATA1_AVDD USB_AVDD
I
Power
I
Power
RTC_AVDD RTC_AVSS
I I
Power GND
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Pin and Signal Descriptions
Pin Descriptions
2.2.2
Table 5:
Miscellaneous Pin Assignment
The Miscellaneous signal list contains clock and reset, test, and related signals.
Miscellaneous Pin Assignments
I /O Pi n Ty pe Analog P ow e r Rail XTAL_AVDD D e s c r i p t io n
Pin Name
REF_CLK_XIN
I
Reference clock input from external oscillator or input from external crystal. Used as input to core, CPU, SATA, and USB PLLs. XTAL_OUT Feedback signal to external crystal. When not used, leave this pin floating. System reset Main reset signal of the device clock. Used to reset all units to their initial state. When in the reset state, most output pins are in Tri-State. Reset request from the device to the board reset logic. This pin is multiplexed on the MPP pins (see Section 6, Pin Multiplexing, on page 61). Optional PCI Express Endpoint card reset output This pin is multiplexed on the MPP pins (see Section 6, Pin Multiplexing, on page 61). Analog Test Point for SATA, USB, and PCI Express interfaces For internal use. Leave this pin unconnected. Current reference for both the USB and SATA PHYs. Terminate this pin with a 6.04 kΩ resistor, pulled down. Reserved for Marvell¬Æ future usage. Leave unconnected externally.
XOUT
O
Analog
XTAL_AVDD
SYSRSTn
I
CMOS
VDDO
SYSRST_OUTn
O
CMOS
VDDO
PEX_RST_OUTn
O
CMOS
VDDO
TP
O
Analog
ISET
I
Analog
NC (88F6190 only)
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Doc. No. MV-S104987-U0 Rev. F Page 27
88F619x Hardware Specifications
2.2.3
Table 6:
DDR SDRAM Interface Pin Assignments
DDR SDRAM Interface Pin Assignments
I /O Pi n Ty pe SSTL P ow e r Rail VDD_M D e s cr ip t i o n
Pin Name
M_CLKOUT M_CLKOUTn M_CKE
O
SDRAM Differential Clock Pair
O
SSTL
VDD_M
Driven high to enable SDRAM clock. Driven low when setting the SDRAM to Self-refresh mode. SDRAM Row Address Select Asserted to indicate an active ROW address driven on the SDRAM address lines. SDRAM Column Address Select Asserted to indicate an active column address driven on the SDRAM address lines. SDRAM Write Enable Asserted to indicate a write command to the SDRAM. SDRAM Address Driven during RASn and CASn cycles to generate—together with M_BA[2:0]—the SDRAM address. Driven during M_RASn and M_CASn cycles to select one of the eight SDRAM virtual banks. NOTE: If an SDRAM device does not support the BA[2] pin, leave the M_BA[2] unconnected. SDRAM Chip Selects Asserted to select a specific SDRAM Physical bank. SDRAM Data Bus Driven during write. Driven by SDRAM during reads. SDRAM Data Strobe Driven by the 88F619x during write. Driven by SDRAM during reads. SDRAM Data Mask Asserted by the 88F619x to select the specific byte out of the 16-bit data to be written to the SDRAM. SDRAM On Die Termination control. Driven high to connect the SDRAM on die termination. Driven low to disconnect the SDRAM’s termination. NOTE: For the recommended setting, refer to the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide.
M_RASn
O
SSTL
VDD_M
M_CASn
O
SSTL
VDD_M
M_WEn
O
SSTL
VDD_M
M_A[13:0]
O
SSTL
VDD_M
M_BA[2:0]
O
SSTL
VDD_M
M_CSn[1:0]
O
SSTL
VDD_M
M_DQ[15:0]
t/s I/O
SSTL
VDD_M
M_DQS[1:0], M_DQSn[1:0]
t/s I/O
SSTL
VDD_M
M_DM[1:0]
O
SSTL
VDD_M
M_ODT
O
SSTL
VDD_M
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Pin and Signal Descriptions
Pin Descriptions
Table 6:
DDR SDRAM Interface Pin Assignments (Continued)
I /O Pi n Ty pe SSTL P ow e r Rail VDD_M D e s cr ip t i o n
Pin Name
M_STARTBURST
O
Start Burst 88F619x indication of starting a burst read transaction. Asserted with the first M_CASn cycle of SDRAM access. NOTE: Must be routed on board to the SDRAM, and back to the 88F619x as M_STARTBURST_IN. For the recommended length calculation for this routing and termination requirements, see the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide. Start Burst Input
M_START BURST_IN M_PCAL
I
SSTL
VDD_M
I
Calib
SDRAM interface P channel output driver calibration. Connect to VSS through a resistor. The resistor value can vary between 30–70 ohm. NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for the recommended values of the calibration resistors. SDRAM interface N channel output driver calibration. Connect to M_VDD through a resistor. The resistor value can vary between 30–70 ohm. NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for the recommended values of the calibration resistors.
M_NCAL
I
Calib
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Doc. No. MV-S104987-U0 Rev. F Page 29
88F619x Hardware Specifications
2.2.4
Table 7:
PCI Express Interface Pin Assignments
PCI Express Interface Pin Assignments
I/O P in Ty p e HCSL Power R a il PEX_AVDD D e s c r i p t io n
Pin Name
PEX_CLK_P/N
I/O
PCI Express Reference Clock 100 MHz, differential This clock can be configured as input or output according to the reset strap (see Table 38, Reset Configuration, on page 77). NOTE: For Output mode, 50-ohm, pull-down resistors are required. Transmit Lane Differential pair of PCI Express transmit data Receive Lane Differential pair of PCI Express receive data Current reference. Pull down to VSS through a 5 kΩ resistor. See the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for the recommended resistor value.
PEX_TX_P/N
O
CML
PEX_AVDD
PEX_RX_P/N
I
CML
PEX_AVDD
PEX_ISET
I
Analog
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Pin and Signal Descriptions
Pin Descriptions
2.2.5
Table 8:
SATA Interface Pin Assignments
SATA Port Interface Pin Assignment
I /O Pi n Ty p e P ow e r R a i l D e s c r i p t io n
Pin Name
88F6190 – Single SATA Port SATA_T_P/N SATA_R_P/N SATA_PRESENTn O I O CML CML CMOS SATA_AVDD SATA_AVDD VDD_GE_B Transmit Data: Differential analog output of SATA II port Receive Data: Differential analog input of SATA II port When this signal is asserted there is an active link between the SATA II port and the external device (disk). NOTE: This signal is multiplexed on the MPP pins (see Section 6, Pin Multiplexing, on page 61). When this signal is asserted, there is an active and used link between the SATA II port and the external device (disk). NOTE: This signal is multiplexed on the MPP pins (see Section 6, Pin Multiplexing, on page 61).
SATA_ACTn
O
CMOS
VDD_GE_B
88F6192 – SATA Ports 0 and 1 SATA0_T_P/N SATA1_T_P/N SATA0_R_P/N SATA1_R_P/N SATA0_PRESENTn SATA1_PRESENTn O CML SATA0/1_AVDD Transmit Data: Differential analog output of SATA II port0/1 Receive Data: Differential analog input of SATA II port0/1
I
CML
SATA0/1_AVDD
O
CMOS
VDD_GE_B
When this signal is asserted there is an active link between the SATA II port and the external device (disk). NOTE: These signals are multiplexed on the MPP pins (see Section 6, Pin Multiplexing, on page 61). When this signal is asserted, there is an active and used link between the SATA II port and the external device (disk). NOTE: These signals are multiplexed on the MPP pins (see Section 6, Pin Multiplexing, on page 61).
SATA0_ACTn SATA1_ACTn
O
CMOS
VDD_GE_B
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Doc. No. MV-S104987-U0 Rev. F Page 31
88F619x Hardware Specifications
2.2.6
Gigabit Ethernet Port Interface Pin Assignments
For additional information about the Gigabit Ethernet port pin functions refer to Section 6.2, Gigabit Ethernet (GbE) Pins Multiplexing on MPP, on page 68. For the 88F6190, Table 9 lists the Gigabit Ethernet port interface pin assignments. For the 88F6192, Table 10 lists the Gigabit Ethernet port interface pin assignments.
Table 9:
88F6190 Gigabit Ethernet Interface Pin Assignments
I/O P in Ty p e Power R a il D e s c r i p t io n
Pin Name
Dedicated Ethernet Pins GE_TXCLKOUT t/s O CMOS VDD_GE_A RGMII Transmit Clock RGMII transmit reference output clock for GE_TXD[3:0] and GE_TXCTL. Provides 125 MHz, 25 MHz or 2.5 MHz clock. Not used in MII/MMII mode. GMII Transmit Clock Provides the timing reference for the transfer of the transmit enable, transmit error and transmit data signals. This clock operates at 125 MHz. GE_TXD[3:0] t/s O CMOS VDD_GE_A RGMII Transmit Data Contains the transmit data nibble outputs that run at double data rate with bits [3:0] driven on the rising edge of GE_TXCLKOUT and bits [7:4] driven on the falling edge. GMII Transmit Data Contains the transmit data nibble outputs. GE_TXCTL t/s O CMOS VDD_GE_A RGMII Transmit Control Transmit control synchronous to the GE_TXCLKOUT output rising/falling edge. GE_TXEN is driven on the rising edge of GE_TXCLKOUT. A logical derivative of transmit enable and transmit error is driven on the falling edge of GE_TXCLKOUT. GMII Transmit Enable Indicates that the packet is being transmitted to the PHY. It Is synchronous to GE_TXCLKOUT. GE_RXD[3:0] I CMOS VDD_GE_A RGMII Receive Data Contains the receive data nibble inputs that are synchronous to GE_RXCLK input rising/falling edge. GMII Receive Data Contains the receive data nibble inputs. GE_RXCTL I CMOS VDD_GE_A RGMII Receive Control GE_RXCTL is presented on the rising edge of GE_RXCLK. A logical derivative of receive data valid and receive data error is presented on the falling edge of RXCLK. GMII Receive Data Valid.
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Pin and Signal Descriptions
Pin Descriptions
Table 9:
88F6190 Gigabit Ethernet Interface Pin Assignments (Continued)
I/O P in Ty p e CMOS Power R a il VDD_GE_A D e s c r i p t io n
Pin Name
GE_RXCLK
I
RGMII Receive Clock The receive clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference clock derived from the received data stream. GMII Receive Clock Provides the timing reference for the reception of the GE_RXDV, receive error and receive data signals. This clock operates at 125 MHz
Multiplexed Ethernet Pins MPP[23:20]/ GE1[3:0] t/s O CMOS VDD_GE_B MII/MMII Transmit Data Contains the transmit data nibble outputs that are synchronous to the transmit clock input. GMII Transmit Data Contains the transmit data nibble outputs. MPP[27:24]/ GE1[7:4] I CMOS VDD_GE_B MII/MMII Receive Data Contains the receive data nibble inputs that are synchronous to GE_RXCLK input. GMII Receive Data Contains the receive data nibble inputs. MPP[28]/GE1[8] I CMOS VDD_GE_B MII/MMII Collision Detect Indicates a collision has been detected on the wire. This input is ignored in full-duplex mode. Collision detect is not synchronous to any clock. GMII Collision Detect MPP[29]/GE1[9] I CMOS VDD_GE_B MII/MMII Transmit Clock MII/MMII transmit reference clock from PHY. Provides the timing reference for the transmission of the GMII transmit clock, transmit enable, and GE_TXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz. GMII Transmit Clock Provides the timing reference for the transfer of the transmit enable, transmit error and transmit data signals. This clock operates at 125 MHz. CMOS VDD_GE_B MII/MMII Receive Data Valid GMII Receive Error MPP[31]/GE1[11] I CMOS VDD_GE_B MII/MMII Receive Clock Provides the timing reference for the reception of the receive data valid, receive error, and GE_RXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz.
t/s O
MPP[30]/GE1[10]
I
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88F619x Hardware Specifications
Table 9:
88F6190 Gigabit Ethernet Interface Pin Assignments (Continued)
I/O P in Ty p e CMOS Power R a il VDD_GE_B D e s c r i p t io n
Pin Name
MPP[32]/GE1[12]
I/O
MII/MMII Carrier Sense Indicates that the receive medium is non-idle. In half-duplex mode, GE_CRS is also asserted during transmission. Carrier sense is not synchronous to any clock. GMII Carrier Sense
MPP[33]/GE1[13]
t/s O
CMOS
VDD_GE_B
MII/MMII Transmit Error It is synchronous to transmit clock. NOTE: Multiplexed on MPP. GMII Transmit Error It Is synchronous to GE_TXCLKOUT. NOTE: Multiplexed on MPP.
MPP[34]/GE1[14]
O
CMOS
VDD_GE_B
MII/MMII Transmit Enable Indicates that the packet is being transmitted to the PHY. It Is synchronous to transmit clock. MII/MMII Receive Error Indicates that an error symbol, a false carrier, or a carrier extension symbol is detected on the cable. It is synchronous to GE_RXCLK input. NOTE: Multiplexed on MPP.
MPP[35]/GE1[15]
I
CMOS
VDD_GE_B
Table 10: 88F6192 Gigabit Ethernet Port0/1 Interface Pin Assignments
Pin Name I/O P in Ty p e Power R a il D e s c r i p t io n
Port0—Dedicated GbE Pins GE_TXCLKOUT t/s O CMOS VDD_GE_A RGMII Transmit Clock RGMII transmit reference output clock for GE_TXD[3:0] and GE_TXCTL. Provides 125 MHz, 25 MHz or 2.5 MHz clock. Not used in MII/MMII mode. MII/MMII Transmit Clock MII/MMII transmit reference clock from PHY. Provides the timing reference for the transmission of the MII transmit clock, transmit enable, and GE_TXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz. GMII Transmit Clock Provides the timing reference for the transfer of the transmit enable, transmit error and transmit data signals. This clock operates at 125 MHz.
I
t/s O
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Pin and Signal Descriptions
Pin Descriptions
Table 10: 88F6192 Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued)
Pin Name I/O P in Ty p e CMOS Power R a il VDD_GE_A D e s c r i p t io n
GE_TXD[3:0]
t/s O
RGMII Transmit Data Contains the transmit data nibble outputs that run at double data rate with bits [3:0] driven on the rising edge of GE_TXCLKOUT and bits [7:4] driven on the falling edge. MII/MMII Transmit Data Contains the transmit data nibble outputs that are synchronous to the transmit clock input. GMII Transmit Data Contains the transmit data nibble outputs.
GE_TXCTL
t/s O
CMOS
VDD_GE_A
RGMII Transmit Control Transmit control synchronous to the GE_TXCLKOUT output rising/falling edge. GE_TXEN is driven on the rising edge of GE_TXCLKOUT. A logical derivative of transmit enable and transmit error is driven on the falling edge of GE_TXCLKOUT. MII/MMII Transmit Enable Indicates that the packet is being transmitted to the PHY. It Is synchronous to transmit clock. GMII Transmit Enable Indicates that the packet is being transmitted to the PHY. It Is synchronous to GE_TXCLKOUT.
GE_RXD[3:0]
I
CMOS
VDD_GE_A
RGMII Receive Data (Only relevant for the 88F6192.) Contains the receive data nibble inputs that are synchronous to GE_RXCLK input rising/falling edge. MII/MMII Receive Data Contains the receive data nibble inputs that are synchronous to GE_RXCLK input. GMII Receive Data Contains the receive data nibble inputs.
GE_RXCTL
I
CMOS
VDD_GE_A
RGMII Receive Control GE_RXCTL is presented on the rising edge of GE_RXCLK. A logical derivative of receive data valid and receive data error is presented on the falling edge of RXCLK. MII/MMII Receive Data Valid GMII Receive Data Valid.
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Doc. No. MV-S104987-U0 Rev. F Page 35
88F619x Hardware Specifications
Table 10: 88F6192 Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued)
Pin Name I/O P in Ty p e CMOS Power R a il VDD_GE_A D e s c r i p t io n
GE_RXCLK
I
RGMII Receive Clock The receive clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference clock derived from the received data stream. MII/MMII Receive Clock Provides the timing reference for the reception of the receive data valid, receive error, and GE_RXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz. GMII Receive Clock Provides the timing reference for the reception of the GE_RXDV, receive error and receive data signals. This clock operates at 125 MHz
Port1—Multiplexed GbE Pins MPP[23:20]/ GE1[3:0] t/s O CMOS VDD_GE_B RGMII Transmit Data Contains the transmit data nibble outputs that run at double data rate with bits [3:0] presented on the rising edge of GE_TXCLKOUT and bits [7:4] presented on the falling edge. MII/MMII Transmit Data Contains the transmit data nibble outputs that are synchronous to the transmit clock input. GMII Transmit Data Contains the transmit data nibble outputs. MPP[27:24]/ GE1[7:4] I CMOS VDD_GE_B RGMII Receive Data Contains the receive data nibble inputs that are synchronous to GE_RXCLK input rising/falling edge. MII/MMII Receive Data Contains the receive data nibble inputs that are synchronous to GE_RXCLK input. GMII Receive Data Contains the receive data nibble inputs.
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Pin and Signal Descriptions
Pin Descriptions
Table 10: 88F6192 Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued)
Pin Name I/O P in Ty p e CMOS Power R a il VDD_GE_B D e s c r i p t io n
MPP[28]/GE1[8]
I
MII/MMII Collision Detect Indicates a collision has been detected on the wire. This input is ignored in full-duplex mode. Collision detect is not synchronous to any clock. GMII Collision Detect
MPP[29]/GE1[9]
I
CMOS
VDD_GE_B
MII/MMII Transmit Clock MII/MMII transmit reference clock from PHY. Provides the timing reference for the transmission of the MII transmit clock, transmit enable, and GE_TXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz. GMII Transmit Clock Provides the timing reference for the transfer of the transmit enable, transmit error and transmit data signals. This clock operates at 125 MHz.
t/s O
MPP[30]/GE1[10]
I
CMOS
VDD_GE_B
RGMII Receive Control GE_RXCTL is presented on the rising edge of GE_RXCLK. A logical derivative of receive data valid and receive data error is presented on the falling edge of RXCLK. MII/MMII Receive Data Valid GMII Receive Error
MPP[31]/GE1[11]
I
CMOS
VDD_GE_B
RGMII Receive Clock The receive clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference clock derived from the received data stream. MII/MMII Receive Clock Provides the timing reference for the reception of the receive data valid, receive error, and GE_RXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz.
MPP[32]/GE1[12]
I/O
CMOS
VDD_GE_B
RGMII Transmit Clock RGMII transmit reference output clock for GE_TXD[3:0] and GE_TXCTL Provides 125 MHz, 25 MHz or 2.5 MHz clock. Not used in MII/MMII mode. MII/MMII Carrier Sense Indicates that the receive medium is non-idle. In half-duplex mode, GE_CRS is also asserted during transmission. Carrier sense is not synchronous to any clock. GMII Carrier Sense
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Doc. No. MV-S104987-U0 Rev. F Page 37
88F619x Hardware Specifications
Table 10: 88F6192 Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued)
Pin Name I/O P in Ty p e CMOS Power R a il VDD_GE_B D e s c r i p t io n
MPP[33]/GE1[13]
t/s O
RGMII Transmit Control Transmit control synchronous to the GE_TXCLKOUT output rising/falling edge. GE_TXEN is presented on the rising edge of GE_TXCLKOUT. A logical derivative of transmit enable transmit error is presented on the falling edge of GE_TXCLKOUT. MII/MMII Transmit Error It is synchronous to transmit clock. NOTE: Multiplexed on MPP. GMII Transmit Error It Is synchronous to GE_TXCLKOUT. NOTE: Multiplexed on MPP.
MPP[34]/GE1[14]
O
CMOS
VDD_GE_B
MII/MMII Transmit Enable Indicates that the packet is being transmitted to the PHY. It Is synchronous to transmit clock. MII/MMII Receive Error Indicates that an error symbol, a false carrier, or a carrier extension symbol is detected on the cable. It is synchronous to GE_RXCLK input. NOTE: Multiplexed on MPP.
MPP[35]/GE1[15]
I
CMOS
VDD_GE_B
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Pin and Signal Descriptions
Pin Descriptions
2.2.7
Serial Management Interface (SMI) Interface Pin Assignments
Table 11: Serial Management Interface (SMI) Pin Assignments
Pin Name I/O P in Ty p e CMOS/ Power R a il VDD_GE_A D e s c r i p t io n
GE_MDC
t/s O
Management Data Clock MDC is derived from TCLK divided by 128. Provides the timing reference for the transfer of the MDIO signal. Management Data In/Out Used to transfer control and status information between PHY devices and the GbE controller. NOTE: An external pull-up is required.
GE_MDIO
t/s I/O
CMOS
VDD_GE_A
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Doc. No. MV-S104987-U0 Rev. F Page 39
88F619x Hardware Specifications
2.2.8
USB 2.0 Interface Pin Assignments
Table 12: USB 2.0 Interface Pin Assignments
Pin Name I/O Pi n Ty p e CML P ow e r R ai l USB_AVDD D e s c r ip t i o n
USB_DP USB_DM
I/O
USB 2.0 Data Differential Pair
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Pin and Signal Descriptions
Pin Descriptions
2.2.9
JTAG Interface Pin Assignment
Table 13: JTAG Pin Assignment
Pin Name I/O P in Ty p e CMOS Power R a il VDDO D e s c r i p t io n
JT_CLK
I
JTAG Clock Clock input for the JTAG controller. NOTE: This pin is internally pulled down to 0. JTAG Reset When asserted, resets the JTAG controller. NOTE: This pin is internally pulled down to 0.1 CPU JTAG Mode Select Controls CPU JTAG controller state. Sampled with the rising edge of JT_CLK. NOTE: This pin is internally pulled up to 1. Core JTAG Mode Select Controls the Core JTAG controller state. Sampled with the rising edge of JT_CLK. NOTE: This pin is internally pulled up to 1. JTAG Data Out Driven on the falling edge of JT_CLK. JTAG Data In JTAG serial data input. Sampled with the JT_CLK rising edge. NOTE: This pin is internally pulled up to 1.
JT_RSTn
I
CMOS
VDDO
JT_TMS_CPU
I
CMOS
VDDO
JT_TMS_CORE
I
CMOS
VDDO
JT_TDO
O
CMOS
VDDO
JT_TDI
I
CMOS
VDDO
1. If this pull-down conflicts with other devices, the JTAG tool must not use this signal. This signal is not mandatory for the JTAG interface, since the TAP (Test Access Port) can be reset by driving the JT_TMS signal HIGH for 5 JT_CLK cycles.
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88F619x Hardware Specifications
2.2.10
Real Time Clock (RTC) Interface Pin Assignments
Table 14: RTC Interface Pin Assignments
Pin Name RTC_XIN RTC_XOUT I/O I O P in Ty p e Analog Analog Power R a il RTC_AVDD RTC_AVDD D e s c r i p t io n RTC Crystal Clock Input RTC Crystal Clock Feedback
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Pin and Signal Descriptions
Pin Descriptions
2.2.11
NAND Flash Interface Pin Assignment
Table 15: NAND Flash Interface Pin Assignment
Pin Name I/O P in Ty p e CMOS Power R a il VDDO D e s c r i p t io n
NF_IO[7:0]
I/O
Data Input/Output Used to output command, address and data, and to input data during read operations. NOTE: All of the NF_IO pins are multiplexed on the MPP pins (see Section 6, Pin Multiplexing, on page 61) Command Latch Enable Controls the activating path for commands sent to the command register. Address Latch Enable Controls the activating path for the address to the internal address registers. Chip Enable Controls the device selection. Read Enable Controls the serial data-in. Write Enable Controls writes to the NF_IO[7:0] ports.
NF_CLE
O
CMOS
VDDO
NF_ALE
O
CMOS
VDDO
NF_CEn
O
CMOS
VDDO
NF_REn
O
CMOS
VDDO
NF_WEn
O
CMOS
VDDO
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Doc. No. MV-S104987-U0 Rev. F Page 43
88F619x Hardware Specifications
2.2.12
MPP Interface Pin Assignment
Table 16: MPP Interface Pin Assignment
Pin Name I/O P in Ty p e CMOS Power R a il VDDO D e s c r i p t io n
MPP[19:0]
t/s I/O t/s I/O
Multi Purpose Pin Various functionalities Multi Purpose Pin Various functionalities
MPP[35:20]
CMOS
VDD_GE_B
Note
The various functionalities of the MPP pins are detailed in Section 6, Pin Multiplexing, on page 61.
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Pin and Signal Descriptions
Pin Descriptions
2.2.13
Two-Wire Serial Interface (TWSI) Interface
All of the TWSI signals are multiplexed on the MPP pins (see Section 6, Pin Multiplexing, Note
on page 61).
Table 17: Two-Wire Serial Interface (TWSI) Interface Pin Assignment
Pin Name TW_SDA I/O o/d I/O P in Ty p e CMOS Power R a il VDDO D e s c r i p t io n TWSI Port Serial Data Address or write data driven by the TWSI master or read response data driven by the TWSI slave. NOTE: Requires a pull-up resistor to VDDO. TWSI Port Serial Clock Serves as output when acting as an TWSI master. Serves as input when acting as an TWSI slave. NOTE: Requires a pull-up resistor to VDDO.
TW_SCK
o/d I/O
CMOS
VDDO
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88F619x Hardware Specifications
2.2.14
UART Interface
Note
All of the UART signals are multiplexed on the MPP pins (see Section 6, Pin Multiplexing, on page 61).
Table 18: UART Port 0/1 Interface Pin Assignment
Pin Name UA0/1_RXD UA0/1_TXD UA0/1_CTS UA0/1_RTS I/O I O I O P in Ty p e CMOS CMOS CMOS CMOS Power R a il VDDO VDDO VDDO VDDO D e s c r i p t io n UART Port 0/1 RX Data UART Port 0/1 TX Data Clear to Send Request to Send
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Pin and Signal Descriptions
Pin Descriptions
2.2.15
Audio (S/PDIF / I2S) Interface
The Audio interface is only relevant for the 88F6192. All of the Audio signals are multiplexed on the MPP pins (see Section 6, Pin Multiplexing, on page 61). If the Audio interface is not used, leave all of the signals unconnected. The Audio signals are powered on VDDO or on VDD_GE_B, based on the pin multiplexing option.
Note
Table 19: Audio (S/PDIF / I2S) Interface Signal Assignment
Pin Name AU_SPDIFI AU_SPDIFO AU_ SPDFRMCLK I/O I O O P in Ty p e CMOS CMOS CMOS Power R a il VDD_GE_B VDD_GE_B VDD_GE_B D e s c r i p t io n S/PDIF In S/PDIF Out S/PDIF Recovered Master Clock (256 x Fs)1 For the frequency of this clock, see the Audio External Reference Clock section of Table 51, Reference Clock AC Timing Specifications, on page 97. I2S Bit Clock (64 x Fs) Transmitter Data Out I2S Left/Right Clock (1 x Fs) I2S Master Clock (256 x Fs) I2S Receiver Data In External Audio Clock For the frequency of this clock, see the Audio External Reference Clock section of Table 51, Reference Clock AC Timing Specifications, on page 97.
AU_I2SBCLK AU_I2SDO AU_I2SLRCLK AU_I2SMCLK AU_I2SDI AU_EXTCLK
O O O O I I
CMOS CMOS CMOS CMOS CMOS CMOS
VDD_GE_B VDD_GE_B VDD_GE_B VDD_GE_B VDD_GE_B VDD_GE_B
1. Fs is the audio sample rate.
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88F619x Hardware Specifications
2.2.16
Serial Peripheral Interface (SPI) Interface
All of the SPI signals are multiplexed on the MPP pins (see Section 6, Pin Multiplexing, Note
on page 61).
Table 20: Serial Peripheral Interface (SPI) Interface Signal Assignment
Pin Name I/O Pin Type Power Rail Description
SPI_MOSI1 SPI_MISO2 SPI_SCK SPI_CSn
O I O O
CMOS CMOS CMOS CMOS
VDDO VDDO VDDO VDDO
SPI Data Output Data is output from the master and input to the slave. SPI Data Input Data is input to the master and output from the slave. SPI Clock SPI Chip Select NOTE: This pin requires an external pull up.
1. MOSI = Master Out Slave In. 2. MISO = Master In Slave Out.
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Pin and Signal Descriptions
Pin Descriptions
2.2.17
Secure Digital Input/Output (SDIO) Interface
All of the SDIO signals are multiplexed on the MPP pins (see Section 6, Pin Multiplexing, Note
on page 61).
Table 21: Secure Digital Input/Output (SDIO) Interface Signal Assignment
Pin Name I/O Pin Type Power Rail Description
SD_CLK SD_CMD
O I/O
CMOS CMOS
VDDO VDDO
SDIO Clock SDIO Command Used to transfer a command serially from the SDIO host to the SDIO device. Used to transfer a command response serially from the SDIO device to the SDIO host. NOTE: This pin requires a pull up on board. SDIO Data Input/Output Used to transfer data from the SDIO host to the SDIO device or vice versa. NOTE: These pins require a pull up on board.
SD_D[3:0]
I/O
CMOS
VDDO
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88F619x Hardware Specifications
2.2.18
Time Division Multiplexing (TDM) Interface
The TDM interface is only relevant for the 88F6192. All of the TDM signals are multiplexed on the MPP pins (see Section 6, Pin Multiplexing, on page 61). The TDM signals are powered on VDDO or on VDD_GE_B, based on the pin multiplexing option (see Section 6, Pin Multiplexing, on page 61).
Note
Table 22: Time Division Multiplexing (TDM) Interface Signal Assignment
Pin Name I/O Pin Type Power Rail Description
TDM_CH0_TX_ QL TDM_CH2_TX_ QL TDM_CH0_RX_ QL TDM_CH2_RX_ QL TDM_CODEC_ INTn TDM_CODEC_ RSTn TDM_PCLK TDM_FS TDM_DRX TDM_DTX TDM_SPI_CS[1:0]
O O O O I O I/O I/O I O O
CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
VDD_GE_B VDD_GE_B VDD_GE_B VDD_GE_B VDD_GE_B VDD_GE_B VDD_GE_B VDD_GE_B VDD_GE_B VDD_GE_B VDD_GE_B
TDM Channel0 Transmit Qualifier TDM Channel2 Transmit Qualifier TDM Channel0 Receive Qualifier TDM Channel2 Receive Qualifier Interrupt Signal FROM the SLIC/codec SLIC/codec Reset Signal PCM Audio Bit Clock TDM Frame Sync Signal PCM Audio Input Data (for recording) PCM Audio Output Data (for playback) Active low SPI chip selects driven by the host to the codec for register access. Always asserted for eight SCLK cycles at a time. Only Byte-by-Byte mode codec register read/write is supported. Serial SPI clock from the host to the codec for register access. This is an RTO (return to one) clock. It toggles for eight cycles at a time (for 1 byte transfer) during codec register access, then it returns to high. The host drives write data on TDM_SPI_MOSI on the negative edge of TDM_SPI_SCK, and captures read data from the codec on the positive edge of TDM_SPI_SCK.
TDM_SPI_SCK
O
CMOS
VDD_GE_B
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Pin Descriptions
Table 22: Time Division Multiplexing (TDM) Interface Signal Assignment (Continued)
Pin Name I/O Pin Type Power Rail Description
TDM_SPI_MOSI
O
CMOS
VDD_GE_B
Serial SPI data from the host to the codec for register access. When TDM_SPI_CS is asserted low, the data is driven from the host on the negative edge of TDM_SPI_SCK. It is always driven for eight TDM_SPI_SCK cycles at a time. In a byte, the data can be driven MSB or LSB first. Serial SPI read data from the CODEC to the host for register access. When TDM_SPI_CS is asserted low, this data is driven from CODEC on negative edge of TDM_SPI_SCK. It is always driven for eight TDM_SPI_SCK cycles at a time. The CODEC drives data on this line only for a read operation, when it gets command and address in previous bytes from the host on TDM_SPI_MOSI In a byte, the data can be driven MSB or LSB first.
TDM_SPI_MISO
I
CMOS
VDD_GE_B
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88F619x Hardware Specifications
2.2.19
Transport Stream (TS) Interface
The TS interface is only relevant for the 88F6192 only. All of the TS signals are multiplexed on the MPP pins (see Section 6, Pin Multiplexing, on page 61). The TS signals are powered on VDDO or on VDD_GE_B based on the pin multiplexing option (see Section 6, Pin Multiplexing).
Note
Table 23: Transport Stream (TS) Interface Signal Assignment
Pin Name I/O Pin Type Power Rail Description
TSMP[0]
I
CMOS
VDD_GE_B
EXT_CLK External clock that can be used to drive the TS0_CLK and TS1_CLK TS0_CLK Port0 TS clock. • If TS0_VAL is used, the clock may be continuous. • If TS0_VAL is not used, the clock may toggle only when valid data is available on TS0_DATA. TS0_SYNC Port0 Sync/Frame Start Indicator or Packet Clock. The TS0_SYNC in parallel mode is a pulse that is active during the first (Sync) byte of the TS packet. In serial mode, the TS0_SYNC pulse may be active for the entire byte or only for the first bit. The polarity is programmable to be either active high or active low. TS0_VAL Port0 Valid Data Indicator When this signal is used and is valid, it indicates that valid data is present on TS0_DATA. TS0_VAL is active during the TS frame packet data and inactive when there is no TS synchronization. In output mode, the polarity of TS0_VAL is programmable to be either active high or active low. TS0_ERR Port0 Uncorrectable Packet Error When this signal is used, an error indicates that the packet contains an uncorrectable error, and therefore should not be used. In output mode, the TS0_ERR is active during the entire TS frame. TS0_DATA[0] Port0 TS Data bit 0 in both parallel and serial modes. In Serial mode TS0_DATA[0] is used as data input or output. • • Parallel Mode: TS0_DATA[1]: Port0 TS Data bit 1 Serial Mode: TS1_CLK: Port1 TS clock. - If TS1_VAL is used, the clock may be continuous. - If TS1_VAL is not used, the clock may toggle only when valid data is available on TS1_DATA
TSMP[1]
I/O
CMOS
VDD_GE_B
TSMP[2]
I/O
CMOS
VDD_GE_B
TSMP[3]
I/O
CMOS
VDD_GE_B
TSMP[4]
I/O
CMOS
VDD_GE_B
TSMP[5]
I/O
CMOS
VDD_GE_B
TSMP[6]
I/O
CMOS
VDD_GE_B
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Pin and Signal Descriptions
Pin Descriptions
Table 23: Transport Stream (TS) Interface Signal Assignment (Continued)
Pin Name I/O Pin Type Power Rail Description
TSMP[7]
I/O
CMOS
VDD_GE_B
• •
Parallel Mode: TS0_DATA[2]: Port0 TS Data bit 2 Serial Mode: TS1_SYNC: Port1 Sync/Frame Start Indicator or Packet Clock. The TS1_SYNC pulse may be active for the entire byte or only for the first bit. The polarity is programmable to be either active high or active low Parallel Mode: TS0_DATA[3]: Port0 TS Data bit 3 Serial Mode: TS1_VAL: Port1Valid Data Indicator When this signal is used and is valid, it indicates that valid data is present on TS1_DATA[0]. TS1_VAL is active during the TS frame packet data and inactive when there is no TS synchronization. In output mode, the polarity of TS1_VAL is programmable to be either active high or active low. Parallel Mode: TS0_DATA[4]: Port0 TS Data bit 4 Serial Mode: TS1_ERR: Port1 Uncorrectable Packet Error When this signal is used, an error indicates that the packet contains an uncorrectable error, and, therefore, should not be used. In output mode the TS1_ERR is active during the entire TS frame. Parallel Mode: TS0_DATA[5]: Port0 TS Data bit 5 Serial Mode: TS1_DATA[0]: Port1 TS Data bit 0, used as data input or output.
TSMP[8]
I/O
CMOS
VDD_GE_B
• •
TSMP[9]
I/O
CMOS
VDD_GE_B
• •
TSMP[10]
I/O
CMOS
VDD_GE_B
• •
TSMP[11]
I/O
CMOS
VDD_GE_B
TS0_DATA[6] Port0 TS Data bit 6 This pin is only valid in Parallel mode. TS0_DATA[7] Port0 TS Data bit 7 This pin is only valid in Parallel mode.
TSMP[12]
I/O
CMOS
VDD_GE_B
Copyright © 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S104987-U0 Rev. F Page 53
88F619x Hardware Specifications
2.2.20
Precise Timing Protocol (PTP) Interface
Note
All of the PTP signals are multiplexed on the MPP pins (see Section 6, Pin Multiplexing, on page 61).
Table 24: Precise Timing Protocol (PTP) Interface Signal Assignment
Pin Name I/O Pin Type Power Rail Description
PTP_CLK PTP_EVENT_REQ PTP_TRIG_GEN
I I O
CMOS CMOS CMOS
VDDO VDDO VDDO
PTP Clock Trigger generation to the PTP core. Trigger generated by the PTP core.
Doc. No. MV-S104987-U0 Rev. F Page 54 Document Classification: Proprietary Information
Copyright © 2008 Marvell December 2, 2008, Preliminary
Pin and Signal Descriptions
Internal Pull-up and Pull-down Pins
2.3
Internal Pull-up and Pull-down Pins
Some pins of the device package are connected to internal pull-up and pull-down resistors. When these pins are Not Connected (NC) on the system board, these resistors set the default value for input and sample at reset configuration pins. The internal pull-up and pull-down resistor value is 50 kΩ. An external resistor with a lower value can override this internal resistor.
Table 25: Internal Pull-up and Pull-down Pins
P in N a m e GE_TXD[0] GE_TXD[1] GE_TXD[2] GE_TXD[3] 88F6190 – GE_TXEN 88F6192 – GE_TXCTL GE_MDC JT_TMS_CORE JT_RSTn JT_TDI JT_TMS_CPU NF_ALE NF_REn NF_CLE NF_CEn NF_WEn MPP[1] MPP[2] MPP[3] MPP[4] MPP[5] MPP[7] MPP[10] MPP[11] MPP[12] MPP[14] MPP[18] MPP[19] MPP[33] P in N u m be r 22 21 20 19 23 33 114 109 115 112 90 93 92 91 94 81 80 82 85 86 75 72 74 97 99 88 89 45 Pu l l up / Pu l l do w n Pull down Pull down Pull up Pull up Pull down Pull up Pull up Pull down Pull up Pull up Pull up Pull down Pull down Pull up Pull up Pull down Pull down Pull down Pull up Pull up Pull up Pull down Pull up Pull down Pull up Pull up Pull up Pull down
Copyright © 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S104987-U0 Rev. F Page 55
88F619x Hardware Specifications
3
Ethernet SMI MPP
Unused Interface Strapping
Table 26 lists the signal strapping to be used for systems in which some of the device interfaces are unused (not connected).
Table 26: Unused Interface Strapping
Unused Interface Str a pp i ng Pull up GE_MDIO. Configure any unused MPP pin to GPIO output. Leave the power supply connected. • If the related power supply is VDDO, leave it connected to 3.3V. • If the related power supply is VDD_GE_B, leave it connected to either 3.3V or 1.8V. Discard the power filter. Leave USB_AVDD connected to 3.3V. All other signals can be left unconnected. Discard the analog power filters. Leave PEX_AVDD connected to 1.8V. Pull down the PEX_CLK_N signal through a 50 kΩ resistor to GND. Pull up the PEX_CLK_P signal through a 16 kΩ resistor to 1.8V. All other signals can be left unconnected. Configure the PEX_CLK_P and PEX_CLK_N signals as inputs, as indicated in Table 38, Reset Configuration, on page 77. Discard the analog power filters. SATA_AVDD can be left unconnected. Discard the analog power filters. SATA0_AVDD/SATA1_AVDD can be left unconnected. Connect RTC_AVDD, RTC_AVSS, RTC_XIN, and RTC_XOUT to GND. Discard the power filter. Leave SSCG_AVDD connected to 1.8V. Connect VHV to VDD
USB
PCI Express
88F6190 – SATA
88F6192 – SATA
RTC SSCG
eFuse
Doc. No. MV-S104987-U0 Rev. F Page 56 Document Classification: Proprietary Information
Copyright © 2008 Marvell December 2, 2008, Preliminary
88F6190 Pinout
4
88F6190 Pinout
This section provides the pin map and pin list for the 88F6190.
Figure 3: 88F6190 Pin Map Top View
VDD_M M_CLKOUT M_CLKOUTn VDD_M M_STARTBURST M_NCAL VDD M_STARTBURST_IN M_PCAL VSS RTC_XOUT RTC_XIN RTC_AVDD PEX_AVDD PEX_CLK_P PEX_CLK_N TP PEX_RX_P PEX_RX_N PEX_AVDD PEX_TX_P VSS PEX_TX_N VSS PEX_ISET CORE_PLL_AVDD VDD XOUT REF_CLK_XIN XTAL_AVDD XTAL_AVSS ISET VDD VSS VDD VSS VDD VSS VDD VDD VSS VDD VSS VDD VSS VDD SSCG_AVDD JT_TDI JT_TMS_CORE JT_TDO JT_TMS_CPU VDDO SYSRSTn JT_RSTn M_ODT[0] M_CSn[1] M_RASn M_CSn[0] VDD_M M_CASn M_A[0] M_A[2] M_A[4] VDD_M M_A[6] M_A[8] M_A[13] M_A[11] VDD_M VDD M_DQ[5] M_DQ[0] VDD_M M_DQ[2] M_DQ[7] VDD_M M_DQS[0] M_DQSn[0] M_DM[0] VDD_M M_DQ[6] M_DQ[1] VDD_M M_DQ[3] M_DQ[4] VDD VDD_M M_A[9] M_A[12] M_A[5] M_A[7] VDD_M M_A[1] M_A[3] M_BA[1] M_A[10] VDD_M M_BA[2] M_WEn M_BA[0] M_CKE VDD_M VDD M_DQ[12] M_DQ[11] VDD_M M_DQ[14] M_DQ[9] 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
88F6190
Top View
JT_CLK VDD VSS VDD CPU_PLL_AVDD VDD VDDO MPP[17] MPP[16] MPP[14] MPP[15] MPP[12] MPP[13] VDDO NF_WEn NF_REn NF_CLE NF_CEn NF_ALE MPP[19] MPP[18] VSS MPP[5] MPP[4] VSS MPP[0] MPP[3] MPP[1] MPP[2] VDDO MPP[9] MPP[8] VSS MPP[7] MPP[11] MPP[6] MPP[10] VDD VSS SATA_T_P VSS SATA_T_N SATA_AVDD SATA_R_N SATA_R_P VDD NC NC NC NC NC NC NC VDD
Copyright © 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information
VDD_M 1 M_DM[1] 2 M_DQS[1] 3 M_DQSn[1] 4 VDD_M 5 M_DQ[15] 6 M_DQ[8] 7 VDD_M 8 M_DQ[10] 9 M_DQ[13] 10 VSS 11 VDD 12 USB_AVDD 13 USB_DP 14 USB_DM 15 VDD 16 VHV 17 VDD_GE_A 18 19 GE_TXD[3] 20 GE_TXD[2] 21 GE_TXD[1] 22 GE_TXD[0] 23 GE_TXCTL GE_TCLKOUT24 VDD_GE_A 25 GE_RXCLK 26 GE_RXCTL 27 28 GE_RXD[0] 29 GE_RXD[1] 30 GE_RXD[2] 31 GE_RXD[3] 32 VSS 33 GE_MDC 34 GE_MDIO 35 VSS 36 MPP[28] 37 MPP[29] 38 MPP[34] 39 MPP[35] VDD_GE_B 40 41 MPP[23] 42 MPP[22] 43 MPP[20] 44 MPP[21] 45 MPP[33] 46 MPP[32] VDD_GE_B 47 48 MPP[31] 49 MPP[30] 50 MPP[24] 51 MPP[25] 52 MPP[26] 53 MPP[27] 54 VDD
Doc. No. MV-S104987-U0 Rev. F Page 57
88F619x Hardware Specifications
Table 27: 88F6190 Pinout Sorted by Pin Number
Pin # Pin Nam e Pin # Pin Nam e Pin # Pin Nam e Pin # Pin Nam e Pin # Pin Nam e
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
VDD_M M_DM[1] M_DQS[1] M_DQSn[1] VDD_M M_DQ[15] M_DQ[8] VDD_M M_DQ[10] M_DQ[13] VSS VDD USB_AVDD USB_DP USB_DM VDD VHV VDD_GE_A GE_TXD[3] GE_TXD[2] GE_TXD[1] GE_TXD[0] GE_TXCTL GE_TCLKOUT VDD_GE_A GE_RXCLK GE_RXCTL GE_RXD[0] GE_RXD[1] GE_RXD[2] GE_RXD[3] VSS GE_MDC GE_MDIO VSS MPP[28] MPP[29] MPP[34] MPP[35] VDD_GE_B MPP[23] MPP[22] MPP[20] MPP[21] MPP[33]
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
MPP[32] VDD_GE_B MPP[31] MPP[30] MPP[24] MPP[25] MPP[26] MPP[27] VDD VDD NC NC NC NC NC NC NC VDD SATA_R_P SATA_R_N SATA_AVDD SATA_T_N VSS SATA_T_P VSS VDD MPP[10] MPP[6] MPP[11] MPP[7] VSS MPP[8] MPP[9] VDDO MPP[2] MPP[1] MPP[3] MPP[0] VSS MPP[4] MPP[5] VSS MPP[18] MPP[19] NF_ALE
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135
NF_CEn NF_CLE NF_REn NF_WEn VDDO MPP[13] MPP[12] MPP[15] MPP[14] MPP[16] MPP[17] VDDO VDD CPU_PLL_AVDD VDD VSS VDD JT_CLK JT_RSTn SYSRSTn VDDO JT_TMS_CPU JT_TDO JT_TMS_CORE JT_TDI SSCG_AVDD VDD VSS VDD VSS VDD VSS VDD VDD VSS VDD VSS VDD VSS VDD ISET XTAL_AVSS XTAL_AVDD REF_CLK_XIN XOUT
136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
VDD CORE_PLL_AVDD PEX_ISET VSS PEX_TX_N VSS PEX_TX_P PEX_AVDD PEX_RX_N PEX_RX_P TP PEX_CLK_N PEX_CLK_P PEX_AVDD RTC_AVDD RTC_XIN RTC_XOUT VSS M_PCAL M_STARTBURST_IN VDD M_NCAL M_STARTBURST VDD_M M_CLKOUTn M_CLKOUT VDD_M M_ODT[0] M_CSn[1] M_RASn M_CSn[0] VDD_M M_CASn M_A[0] M_A[2] M_A[4] VDD_M M_A[6] M_A[8] M_A[13] M_A[11] VDD_M VDD M_DQ[5] M_DQ[0]
181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216
VDD_M M_DQ[2] M_DQ[7] VDD_M M_DQS[0] M_DQSn[0] M_DM[0] VDD_M M_DQ[6] M_DQ[1] VDD_M M_DQ[3] M_DQ[4] VDD VDD_M M_A[9] M_A[12] M_A[5] M_A[7] VDD_M M_A[1] M_A[3] M_BA[1] M_A[10] VDD_M M_BA[2] M_WEn M_BA[0] M_CKE VDD_M VDD M_DQ[12] M_DQ[11] VDD_M M_DQ[14] M_DQ[9]
Doc. No. MV-S104987-U0 Rev. F Page 58 Document Classification: Proprietary Information
Copyright © 2008 Marvell December 2, 2008, Preliminary
88F6192 Pinout
5
88F6192 Pinout
This section provides the pin map and pin list for the 88F6192.
Figure 4: 88F6192 Pin Map Top View
VDD_M M_CLKOUT M_CLKOUTn VDD_M M_STARTBURST M_NCAL VDD M_STARTBURST_IN M_PCAL VSS RTC_XOUT RTC_XIN RTC_AVDD PEX_AVDD PEX_CLK_P PEX_CLK_N TP PEX_RX_P PEX_RX_N PEX_AVDD PEX_TX_P VSS PEX_TX_N VSS PEX_ISET CORE_PLL_AVDD VDD XOUT REF_CLK_XIN XTAL_AVDD XTAL_AVSS ISET VDD VSS VDD VSS VDD VSS VDD VDD VSS VDD VSS VDD VSS VDD SSCG_AVDD JT_TDI JT_TMS_CORE JT_TDO JT_TMS_CPU VDDO SYSRSTn JT_RSTn M_ODT[0] M_CSn[1] M_RASn M_CSn[0] VDD_M M_CASn M_A[0] M_A[2] M_A[4] VDD_M M_A[6] M_A[8] M_A[13] M_A[11] VDD_M VDD M_DQ[5] M_DQ[0] VDD_M M_DQ[2] M_DQ[7] VDD_M M_DQS[0] M_DQSn[0] M_DM[0] VDD_M M_DQ[6] M_DQ[1] VDD_M M_DQ[3] M_DQ[4] VDD VDD_M M_A[9] M_A[12] M_A[5] M_A[7] VDD_M M_A[1] M_A[3] M_BA[1] M_A[10] VDD_M M_BA[2] M_WEn M_BA[0] M_CKE VDD_M VDD M_DQ[12] M_DQ[11] VDD_M M_DQ[14] M_DQ[9] 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
88F6192
Top View
JT_CLK VDD VSS VDD CPU_PLL_AVDD VDD VDDO MPP[17] MPP[16] MPP[14] MPP[15] MPP[12] MPP[13] VDDO NF_WEn NF_REn NF_CLE NF_CEn NF_ALE MPP[19] MPP[18] VSS MPP[5] MPP[4] VSS MPP[0] MPP[3] MPP[1] MPP[2] VDDO MPP[9] MPP[8] VSS MPP[7] MPP[11] MPP[6] MPP[10] VDD VSS SATA0_T_P VSS SATA0_T_N SATA0_AVDD SATA0_R_N SATA0_R_P VDD SATA1_T_P VSS SATA1_T_N SATA1_AVDD SATA1_R_N SATA1_R_P VSS VDD
Copyright © 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information
1 VDD_M 2 M_DM[1] 3 M_DQS[1] 4 M_DQSn[1] 5 VDD_M 6 M_DQ[15] 7 M_DQ[8] 8 VDD_M 9 M_DQ[10] 10 M_DQ[13] 11 VSS 12 VDD USB_AVDD 13 14 USB_DP 15 USB_DM 16 VDD 17 VHV VDD_GE_A 18 19 GE_TXD[3] 20 GE_TXD[2] 21 GE_TXD[1] 22 GE_TXD[0] 23 GE_TXCTL GE_TCLKOUT24 VDD_GE_A 25 GE_RXCLK 26 GE_RXCTL 27 GE_RXD[0] 28 GE_RXD[1] 29 GE_RXD[2] 30 GE_RXD[3] 31 VSS 32 GE_MDC 33 GE_MDIO 34 VSS 35 MPP[28] 36 MPP[29] 37 MPP[34] 38 MPP[35] 39 VDD_GE_B 40 MPP[23] 41 MPP[22] 42 MPP[20] 43 MPP[21] 44 MPP[33] 45 MPP[32] 46 VDD_GE_B 47 MPP[31] 48 MPP[30] 49 MPP[24] 50 MPP[25] 51 MPP[26] 52 MPP[27] 53 VDD 54
Doc. No. MV-S104987-U0 Rev. F Page 59
88F619x Hardware Specifications
Table 28: 88F6192 Pinout Sorted by Pin Number
Pin # Pin Nam e Pin # Pin Nam e Pin # Pin Nam e Pin # Pin Nam e Pin # Pin Nam e
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
VDD_M M_DM[1] M_DQS[1] M_DQSn[1] VDD_M M_DQ[15] M_DQ[8] VDD_M M_DQ[10] M_DQ[13] VSS VDD USB_AVDD USB_DP USB_DM VDD VHV VDD_GE_A GE_TXD[3] GE_TXD[2] GE_TXD[1] GE_TXD[0] GE_TXCTL GE_TCLKOUT VDD_GE_A GE_RXCLK GE_RXCTL GE_RXD[0] GE_RXD[1] GE_RXD[2] GE_RXD[3] VSS GE_MDC GE_MDIO VSS MPP[28] MPP[29] MPP[34] MPP[35] VDD_GE_B MPP[23] MPP[22] MPP[20] MPP[21] MPP[33]
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
MPP[32] VDD_GE_B MPP[31] MPP[30] MPP[24] MPP[25] MPP[26] MPP[27] VDD VDD VSS SATA1_R_P SATA1_R_N SATA1_AVDD SATA1_T_N VSS SATA1_T_P VDD SATA0_R_P SATA0_R_N SATA0_AVDD SATA0_T_N VSS SATA0_T_P VSS VDD MPP[10] MPP[6] MPP[11] MPP[7] VSS MPP[8] MPP[9] VDDO MPP[2] MPP[1] MPP[3] MPP[0] VSS MPP[4] MPP[5] VSS MPP[18] MPP[19] NF_ALE
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135
NF_CEn NF_CLE NF_REn NF_WEn VDDO MPP[13] MPP[12] MPP[15] MPP[14] MPP[16] MPP[17] VDDO VDD CPU_PLL_AVDD VDD VSS VDD JT_CLK JT_RSTn SYSRSTn VDDO JT_TMS_CPU JT_TDO JT_TMS_CORE JT_TDI SSCG_AVDD VDD VSS VDD VSS VDD VSS VDD VDD VSS VDD VSS VDD VSS VDD ISET XTAL_AVSS XTAL_AVDD REF_CLK_XIN XOUT
136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
VDD CORE_PLL_AVDD PEX_ISET VSS PEX_TX_N VSS PEX_TX_P PEX_AVDD PEX_RX_N PEX_RX_P TP PEX_CLK_N PEX_CLK_P PEX_AVDD RTC_AVDD RTC_XIN RTC_XOUT VSS M_PCAL M_STARTBURST_IN VDD M_NCAL M_STARTBURST VDD_M M_CLKOUTn M_CLKOUT VDD_M M_ODT[0] M_CSn[1] M_RASn M_CSn[0] VDD_M M_CASn M_A[0] M_A[2] M_A[4] VDD_M M_A[6] M_A[8] M_A[13] M_A[11] VDD_M VDD M_DQ[5] M_DQ[0]
181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216
VDD_M M_DQ[2] M_DQ[7] VDD_M M_DQS[0] M_DQSn[0] M_DM[0] VDD_M M_DQ[6] M_DQ[1] VDD_M M_DQ[3] M_DQ[4] VDD VDD_M M_A[9] M_A[12] M_A[5] M_A[7] VDD_M M_A[1] M_A[3] M_BA[1] M_A[10] VDD_M M_BA[2] M_WEn M_BA[0] M_CKE VDD_M VDD M_DQ[12] M_DQ[11] VDD_M M_DQ[14] M_DQ[9]
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Copyright © 2008 Marvell December 2, 2008, Preliminary
Pin Multiplexing
Multi-Purpose Pins Functional Summary
6
6.1
Pin Multiplexing
Multi-Purpose Pins Functional Summary
The 88F6190/88F6192 device contains 36 Multi-Purpose Pins (MPP). Each one can be assigned to a different functionality through the MPP Control register. General Purpose pins: MPP[5:0] and MPP[35:7]:
• GPIO (input/output): MPP[0], MPP[4], MPP[9:8], MPP[11], MPP[17:13], MPP[32:20], and
MPP[35:34]
• GPO (output): MPP[3:1], MPP[5], MPP[7], MPP[10], MPP[12], MPP[19:18], and MPP[33]
SYSRST_OUTn: Reset request from the device to the board reset logic. This pin is an output. SYSRST_OUTn is the default setting for MPP[6]. PEX_RST_OUTn: Optional PCI Express Endpoint card reset output. MII/MMII/GMII/RGMII interface signals For the 88F6190 only, SATA_ACTn/SATA_PRESENTn: SATA active and SATA present indications—see the SATA section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. For the 88F6192 only, SATA0/1_ACTn/SATA0/1_PRESENTn (port 0 and port 1): SATA active and SATA present indications—see the SATA section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. NF_IO[7:0] (NAND Flash data [7:0]) SPI interface: SPI_MOSI, SPI_MISO, SPI_SCK, SPI_CSn UART interface (port 0 and port 1): Transmit and receive functions: UA0_TXD, UA0_RXD, UA1_TXD, UA1_RXD, and Modem control functions: UA0_RTSn, UA0_CTSn, UA1_RTSn, UA1_CTSn SDIO interface: SD_CLK, SD_CMD, SD_D[3:0] For the 88F6192 only, Audio interface signals: AU_SPDIFI, AU_SPDIFO, AU_SPDIFRMCLK, AU_I2SBCLK, AU_I2SDO, AU_I2SLRCLK, AU_I2SMCLK, AU_I2SDI, AU_EXTCLK TS (Transport Stream) interface signals (88F6192 only): TSMP[12:0] TDM/SPI interface signals (88F6192 only): TDM_CH0/2_TX_QL, TDM_CH0/2_RX_QL, TDM_SPI_CS0/1, TDM_SPI_SCK, TDM_SPI_MOSI, TDM_SPI_MISO, TDM_CODEC_INTn, TDM_CODEC_RSTn, TDM_PCLK, TDM_FS, TDM_DRX, TDM_DTX PTP signals: PTP_EVENT_REQ, PTP_TRIG_GEN, PTP_CLK TWSI signals: TW_SDA, TW_SCK
Copyright © 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S104987-U0 Rev. F Page 61
88F619x Hardware Specifications
MPP pins can be assigned to different functionalities through the MPP Control register, as shown in Table 29.
Table 29: MPP Functionality
MPP[19:0] GPIO SATA LEDs NAND flash TWSI UART SPI PTP SDIO MPP[35:20] GPIO SATA LEDs GbE Audio (88F6192 only) TDM (88F6192 only) TS (88F6192 only) PTP
Table 30 and Table 31 lists the functionality of the MPP pins, as determined by the MPP Multiplex register, see the Pins Multiplexing Interface Registers section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications.
Doc. No. MV-S104987-U0 Rev. F Page 62 Document Classification: Proprietary Information
Copyright © 2008 Marvell December 2, 2008, Preliminary
Pin Multiplexing
Multi-Purpose Pins Functional Summary
Table 30: 88F6190 MPP Function Summary
Pin name 0x0 GPIO[0] (in/out) GPO[1] (out only) GPO[2] (out only) GPO[3] (out only) GPIO[4] (in/out) GPO[5] (out only) 0x1 NF_IO[2] (in/out) NF_IO[3] (in/out) NF_IO[4] (in/out) NF_IO[5] (in/out) NF_IO[6] (in/out) NF_IO[7] (in/out) 0x2 SPI_SCn (out) SPI_MOSI (out) SPI_SCK (out) SPI_MISO (in) UA0_RXD (in) UA0_TXD (out) 0x3 0x4 0x5 0xC 0xD
MPP[0]
-
-
-
-
-
MPP[1]
-
-
-
-
-
MPP[2]
-
-
-
-
-
MPP[3]
-
-
-
-
PTP_CLK (in) -
MPP[4]
-
-
-
-
MPP[5]
-
PTP_TRIG_ SATA_ACT GEN (out) n (out) -
-
MPP[6]
SYSRST_O SPI_MOSI PTP_TRIG_ UTn (out) (out) GEN (out) SPI_SCn (out) UA0_RTS (out) UA0_CTS (in) SPI_SCK (out) SPI_MISO (in) PTP_TRIG_ GEN (out) UA1_RTS (out) UA1_CTS (in) UA0_TXD (out)
-
-
MPP[7]
GPO[7] (out PEX_RST_ only) OUTn (out) GPIO[8] (in/out) GPIO[9] (in/out) GPO [10] (out only) GPIO[11] (in/out) GPO[12] (out only) GPIO[13] (in/out) GPIO[14] (in/out) GPIO[15] (in/out) GPIO[16] (in/out) GPIO[17] (in/out) TW_SDA (in/out) TW_SCK (in/out) -
MII0_RXER R (in) -
-
PTP_CLK (in)
MII0_COL (in)
MPP[8]
-
MPP[9]
SATA_PRE PTP_EVEN MII0_CRS SE NTn T_REQ (in) (in) (out) PTP_TRIG_ GEN (out) PTP_clk (in) -
MPP[10]
-
MPP[11]
SD_CLK (out) SD_CMD (in/out) SD_D[0] (in/out) SD_D[1] (in/out) SD_D[2] (in/out) SD_D[3] (in/out)
UA0_RXD PTP_EVEN SATA_ACT PTP_TRIG_ (in) T_REQ (in) n (out) GEN (out) UA1_TXD (out) UA1_RXD (in) UA1_TXD (out) UA1_RXD (in) -
MPP[12]
MPP[13]
-
-
-
-
MII0_COL (in) MII0_CRS (in) -
MPP[14]
UA0_RTS (out) UA0_CTS (in) -
SATA_ACT n (out) SATA_PRE SE NTn (out)
-
-
MPP[15]
-
-
MPP[16]
-
-
MPP[17]
-
-
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Doc. No. MV-S104987-U0 Rev. F Page 63
88F619x Hardware Specifications
Table 30: 88F6190 MPP Function Summary (Continued)
Pin name 0x0 GPO[18] (out only) GPO[19] (out only) GPIO[20] (in/out) GPIO[21] (in/out) GPIO[22] (in/out) GPIO[23] (in/out) GPIO[24] (in/out) GPIO[25] (in/out) GPIO[26] (in/out) GPIO[27] (in/out) GPIO[28] (in/out) GPIO[29] (in/out) GPIO[30] (in/out) GPIO[31] (in/out) GPIO[32] (in/out) GPO[33] (out only) GPIO[34] (in/out) GPIO[35] (in/out) 0x1 NF_IO[0] (in/out) NF_IO[1] (in/out) 0x2 0x3 0x4 0x5 0xC 0xD
MPP[18]
-
-
-
-
-
-
MPP[19]
-
-
-
-
-
-
MPP[20]
-
GE1[0]
-
SATA_ACT n (out) SATA_PRE SE NTn (out) -
-
-
MPP[21]
-
-
GE1[1]
-
-
-
MPP[22]
-
-
GE1[2]
-
-
-
MPP[23]
-
-
GE1[3]
-
-
-
MPP[24]
-
-
GE1[4]
-
-
-
MPP[25]
-
-
GE1[5]
-
-
-
-
MPP[26]
-
-
GE1[6]
-
-
-
-
MPP[27]
-
-
GE1[7]
-
-
-
-
MPP[28]
-
-
GE1[8]
-
-
-
-
MPP[29]
-
-
GE1[9]
-
-
-
-
MPP[30]
-
-
GE1[10]
-
-
-
-
MPP[31]
-
-
GE1[11]
-
-
-
-
MPP[32]
-
-
GE1[12]
-
-
-
-
MPP[33]
-
-
GE1[13]
-
-
-
-
MPP[34]
-
-
GE1[14]
-
-
-
-
MPP[35]
-
-
GE1[15]
-
SATA_ACT MII0_RXER n (out) R (in)
-
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Copyright © 2008 Marvell December 2, 2008, Preliminary
Pin Multiplexing
Multi-Purpose Pins Functional Summary
Table 31: 88F6192 MPP Function Summary
Pin name 0x0 GPIO[0] (in/out) GPO[1] (out only) GPO[2] (out only) GPO[3] (out only) GPIO[4] (in/out) GPO[5] (out only) 0x1 NF_IO[2] (in/out) NF_IO[3] (in/out) NF_IO[4] (in/out) NF_IO[5] (in/out) NF_IO[6] (in/out) NF_IO[7] (in/out) 0x2 SPI_SCn (out) SPI_MOSI (out) SPI_SCK (out) SPI_MISO (in) UA0_RXD (in) UA0_TXD (out) 0x3 0x4 0x5 0xC 0xD
MPP[0]
-
-
-
-
-
MPP[1]
-
-
-
-
-
MPP[2]
-
-
-
-
-
MPP[3]
-
-
SATA1_AC Tn (out)
-
PTP_CLK (in) -
MPP[4]
-
-
-
MPP[5]
-
PTP_TRIG_ SATA0_AC GEN (out) Tn (out) -
-
MPP[6]
SYSRST_O SPI_MOSI PTP_TRIG_ UTn (out) (out) GEN (out) SPI_SCn (out) UA0_RTS (out) UA0_CTS (in) SPI_SCK (out) SPI_MISO (in) PTP_TRIG_ GEN (out) UA1_RTS (out) UA1_CTS (in) UA0_TXD (out)
-
-
MPP[7]
GPO[7] (out PEX_RST_ only) OUTn (out) GPIO[8] (in/out) GPIO[9] (in/out) GPO [10] (out only) GPIO[11] (in/out) GPO[12] (out only) GPIO[13] (in/out) GPIO[14] (in/out) GPIO[15] (in/out) GPIO[16] (in/out) GPIO[17] (in/out) TW_SDA (in/out) TW_SCK (in/out) -
MII0_RXER R (in) -
-
-
-
MPP[8]
MPP[9]
SATA1_PR PTP_CLK MII0_COL ESE NTn (in) (in) (out) SATA0_PR PTP_EVEN MII0_CRS ESE NTn T_REQ (in) (in) (out) SATA1_AC PTP_TRIG_ Tn (out) GEN (out) PTP_clk (in) -
MPP[10]
-
MPP[11]
SD_CLK (out) SD_CMD (in/out) SD_D[0] (in/out) SD_D[1] (in/out) SD_D[2] (in/out) SD_D[3] (in/out)
UA0_RXD PTP_EVEN SATA0_AC PTP_TRIG_ (in) T_REQ (in) Tn (out) GEN (out) UA1_TXD (out) UA1_RXD (in) UA1_TXD (out) UA1_RXD (in) -
MPP[12]
MPP[13]
-
SATA1_PR ESE NTn (out) SATA0_AC Tn (out) SATA1_AC Tn (out) SATA0_PR ESE NTn (out)
-
-
MII0_COL (in) MII0_CRS (in) -
MPP[14]
UA0_RTS (out) UA0_CTS (in) -
-
-
MPP[15]
-
-
MPP[16]
-
-
MPP[17]
-
-
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Doc. No. MV-S104987-U0 Rev. F Page 65
88F619x Hardware Specifications
Table 31: 88F6192 MPP Function Summary (Continued)
Pin name 0x0 GPO[18] (out only) GPO[19] (out only) GPIO[20] (in/out) GPIO[21] (in/out) GPIO[22] (in/out) GPIO[23] (in/out) GPIO[24] (in/out) GPIO[25] (in/out) GPIO[26] (in/out) GPIO[27] (in/out ) GPIO[28] (in/out) GPIO[29] (in/out) GPIO[30] (in/out) GPIO[31] (in/out) GPIO[32] (in/out) GPO[33] (out only) GPIO[34] (in/out) GPIO[35] (in/out) 0x1 NF_IO[0] (in/out) NF_IO[1] (in/out) TSMP[0] (in/out) TSMP[1] (in/out) TSMP[2] (in/out) TSMP[3] (in/out) TSMP[4] (in/out) TSMP[5] (in/out) TSMP[6] (in/out) TSMP[7] (in/out) TSMP[8] (in/out) TSMP[9] (in/out) 0x2 0x3 0x4 0x5 0xC 0xD
MPP[18]
-
-
-
-
-
-
MPP[19]
TDM_CH0_ TX_QL (out) TDM_CH0_ RX_QL (out) TDM_CH2_ TX_QL (out) TDM_CH2_ RX_QL (out) TDM_SPI_ CS0 (out) TDM_SPI_ SCK (out) TDM_SPI_ MISO (in) TDM_SPI_ MOSI (out) TDM_COD EC_INTn (in) TDM_COD EC_RSTn (out)
-
-
-
-
-
MPP[20]
GE1[0]
AU_SPDIFI SATA1_AC (in) Tn (out) AU_SPDIF SATA0_AC O (out) Tn (out) AU_SPDIF SATA1_PR RMCLK(out ESENTn ) (out) SATA0_PR AU_I2SBCL ESENTn K (out) (out) AU_I2SDO (out) AU_I2SLRC LK (out) AU_I2SMC LK (out) AU_I2SDI (in) AU_EXTCL K (in) -
-
-
MPP[21]
GE1[1]
-
-
MPP[22]
GE1[2]
-
-
MPP[23]
GE1[3]
-
-
MPP[24]
GE1[4]
-
-
MPP[25]
GE1[5]
-
-
-
MPP[26]
GE1[6]
-
-
-
MPP[27]
GE1[7]
-
-
-
MPP[28]
GE1[8]
-
-
-
MPP[29]
GE1[9]
-
-
-
MPP[30]
TSMP[10] TDM_PCLK (in/out) (in/out) TSMP[11] (in/out) TSMP[12] (in/out) TDM_FS (in/out) TDM_DRX (in) TDM_DTX (out) TDM_SPI_ CS1 (out) TDM_CH0_ TX_QL (out)
GE1[10]
-
-
-
-
MPP[31]
GE1[11]
-
-
-
-
MPP[32]
GE1[12]
-
-
-
-
MPP[33]
GE1[13]
-
SATA1_AC Tn (out)
-
-
MPP[34]
-
GE1[14]
-
-
-
MPP[35]
-
GE1[15]
-
SATA0_AC MII0_RXER Tn (out) R (in)
-
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Copyright © 2008 Marvell December 2, 2008, Preliminary
Pin Multiplexing
Multi-Purpose Pins Functional Summary
For MPPs assigned as NAND flash and SPI flash, wake-up mode after reset depends on Boot mode (see the Boot Device field in Table 38, Reset Configuration, on page 77): Note
• When Boot mode is NAND Flash, MPP[5:0] and MPP[19:18] wake up after reset
in NAND Flash mode.
• When Boot mode is SPI Flash, either MPP[3:0] or {MPP[3:1] and MPP[7]} wake
up after reset in SPI mode, (according to boot mode configured by reset strap pins). Pin MPP[6] wakes up after reset in 0x1 mode (SYSRST_OUTn) Pin MPP[7] wakes up after reset:
• As SPI_CSn, if the boot device—selected according to boot device reset
strapping—is 0x2 (boot from SPI flash, SPI_CSn on MPP[7]).
• As PEX_RST_OUTn, if the boot device—selected according to boot device
reset strapping—is any option other than 0x2. When TWSI serial ROM initialization is enabled (see TWSI Serial ROM Initialization in Table 38, Reset Configuration, on page 77), MPP[8] and MPP[9] wake up as TWSI data and clock pins, respectively. All other MPP interface pins wake up after reset in 0x0 mode (GPIO/GPO) and are default set to Data Output disabled (Tri-State). Therefore, those MPPs that are GPIO are in fact inputs, and those that are GPO are Tri-State. The SPI interface can be configured using one of the following sets of MPP pins:
• MPP[3:0] • MPP[11], MPP[10], MPP[7], and MPP[6] • MPP[3:1] and MPP[7]
Do not configure both MPP[3] and MPP[11] as SPI_MISO. UART0 and UART1 signals are duplicated on a few MPPs. The UART0 or UART1 signals must not be configured to more than one MPP. Some of the MPP pins are sampled during SYSRSTn de-assertion to set the device configuration. These pins must be set to the correct value during reset (see Section 8.5, Pins Sample Configuration, on page 76). Pins that are left as GPIO and are not connected should be set to output after SYSRSTn de-assertion.
Copyright © 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S104987-U0 Rev. F Page 67
88F619x Hardware Specifications
6.2
Gigabit Ethernet (GbE) Pins Multiplexing on MPP
88F6190 Contains 14 dedicated pins for its GbE port (12 GMII pins, an MDC pin, and an MDIO pin). Includes additional GbE interface pins that are multiplexed on the MPPs, to serve as the remaining pin interfaces to an external PHY or switch: RGMII MII/MMII GMII Contains 14 dedicated pins for its GbE ports. (12 RGMII/GMII pins, an MDC pin, and an MDIO pin). Includes additional GbE interface pins that are multiplexed on the MPPs, to serve as the following interfaces to an external PHY or switch: GMII 2 x RGMII RGMII + MII/MMII
88F6192
Table 32 summarizes the GbE port pins multiplexing for the 88F6190.
Table 32: 88F6190 Ethernet Ports Pins Multiplexing
Pin Name
GE_TXCLKOUT GE_TXD[3:0] GE_TXCTL GE_RXD[3:0] GE_RXCTL GE_RXCLK MPP [23:20] / GE1[3:0] MPP_[27:24] / GE1[7:4] MPP_28 / GE1[8] MPP_29 / GE1[9] MPP_30 / GE1[10] MPP_31 / GE1[11] MPP_32 / GE1[12] MPP_33 / GE1[13] MPP_34 / GE1[14] MPP_35 / GE1[15]
GMII
GMII_TXCLKOUT (out) GMII_TXD[3:0] (out) GMII_TXEN (out) GMII_RXD[3:0] (in) GMII_RXDV (in) GMII_RXCLK (in) GMII_TXD[7:4] (out) GMII_RXD[7:4] (in) GMII_COL (in) GMII_TXCLK (in) GMII_RXERR (in) NA GMII_CRS (in) GMII_TXERR (out) NA NA
RGMI I0 +MII 1/ MMI I 1
RGMII0_TXCLKOUT (out) RGMII0_TXD[3:0] (out) RGMII0_TXCTL (out) RGMII0_RXD[3:0] (in) RGMII0_RXCTL (in) RGMII0_RXCLK (in) MII1_TXD[3:0] (out) MII1_RXD[3:0] (in) MII1_COL (in) MII1_TXCLK (in) MII1_RXDV (in) MII1_RXCLK (in) MII1_CRS (in) MII1_TXERR (out) MII1_TXEN (out) MII1_RXERR (in)
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Copyright © 2008 Marvell December 2, 2008, Preliminary
Pin Multiplexing
Gigabit Ethernet (GbE) Pins Multiplexing on MPP
Table 33 summarizes the GbE port pins multiplexing for the 88F6192.
Table 33: 88F6192 Ethernet Ports Pins Multiplexing
Pin Name
GE_TXCLKOUT GE_TXD[3:0] GE_TXCTL GE_RXD[3:0] GE_RXCTL GE_RXCLK MPP[8] or MPP[35] MPP[8] or MPP[14] MPP[9] or MPP[16] MPP [23:20] / GE1[3:0] MPP_[27:24] / GE1[7:4] MPP_28 / GE1[8] MPP_29 / GE1[9] MPP_30 / GE1[10] MPP_31 / GE1[11] MPP_32 / GE1[12] MPP_33 / GE1[13] MPP_34 / GE1[14] MPP_35 / GE1[15]
1x GMII
GMII0_TXCLKOUT (out) GMII0_TXD[3:0] (out) GMII0_TXEN (out) GMII0_RXD[3:0] (in) GMII0_RXDV (in) GMII0_RXCLK (in) NA NA NA GMII0_TXD[7:4] (out) GMII0_RXD[7:4] (in) GMII0_COL (in) GMII0_TXCLK (in) GMII0_RXERR (in) NA GMII0_CRS (in) GMII0_TXERR (out) NA NA
RGMII0 +MII1/ MM I I1
RGMII0_TXCLKOUT (out) RGMII0_TXD[3:0] (out) RGMII0_TXCTL (out) RGMII0_RXD[3:0] (in) RGMII0_RXCTL (in) RGMII0_RXCLK (in) NA NA NA MII1_TXD[3:0] (out) MII1_RXD[3:0] (in) MII1_COL (in) MII1_TXCLK (in) MII1_RXDV (in) MII1_RXCLK (in) MII1_CRS (in) MII1_TXERR (out) MII1_TXEN (out) MII1_RXERR (in)
2x RGMII
RGMII0_TXCLKOUT (out) RGMII0_TXD[3:0] (out) RGMII0_TXCTL (out) RGMII0_RXD[3:0] (in) RGMII0_RXCTL (in) RGMII0_RXCLK (in) NA NA NA RGMII1_TXD[3:0] (out) RGMII1_RXD[3:0] (in) NA NA RGMII1_RXCTL (in) RGMII1_RXCLK (in) RGMII1_TXCLKOUT (out) RGMII1_TXCTL (out) NA NA
MII0/MMII0+ R GM I I1
MII0_TXCLK (in) MII0_TXD[3:0] (out) MII0_TXEN (out) MII0_RXD[3:0] (in) MII0_RXDV (in) MII0_RXCLK (in) MII0_RXERR (in) MII0_COL (in) MII0_CRS (in) RGMII1_TXD[3:0] (out) RGMII1_RXD[3:0] (in) NA NA RGMII1_RXCTL (in) RGMII1_RXCLK (in) RGMII1_TXCLKOUT (out) RGMII1_TXCTL (out) NA NA
Note
When using Gigabit Ethernet signals on MPPs, all relevant Gigabit Ethernet signals (except those marked as NA) must be implemented. For example, if using MII, and the chosen PHY does not have an MII_RXERR out signal, the MII_RX_ERR (in) (MPP[35]) must still be configured accordingly and must have a pull-down resistor.
Copyright © 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information
Doc. No. MV-S104987-U0 Rev. F Page 69
88F619x Hardware Specifications
6.3
TSMP (TS Multiplexing Pins) on MPP
The TSMP multiplexing information is only relevant for the 88F6192. Note The TS interface can be configured to one of five modes: One or two serial in interfaces One or two serial out interfaces Serial in and serial out interface Parallel in interface Parallel out interface In parallel in or serial in mode, all TS signals are inputs. In parallel out or serial out mode, all TS signals are outputs. Table 34 summarizes the TS port pins multiplexing.
Table 34: TS Port Pin Multiplexing
Pin Name
TSMP[0] TSMP[1] TSMP[2] TSMP[3] TSMP[4] TSMP[5] TSMP[6] TSMP[7] TSMP[8] TSMP[9] TSMP[10] TSMP[11] TSMP[12]
Fu nc t io na li t y in TS s e r i a l m od e s 2x in/2x o ut/in + ou t
EXT_CLK (in) TS0_CLK (in/out)) TS0_SYNC(in/out)) TS0_VAL (in/out)) TS0_ERR (in/out)) TS0_DATA[0] (in/out) TS1_CLK (in/out)) TS1_SYNC(in/out)) TS1_VAL (in/out)) TS1_ERR (in/out)) TS1_DATA[0] (in/out) NA NA
F un c t i on a l ity i n TS pa r a l le l i n/ o ut m od e
EXT_CLK (in) TS0_CLK (in/out)) TS0_SYNC(in/out)) TS0_VAL (in/out)) TS0_ERR (in/out)) TS0_DATA[0] (in/out) TS0_DATA[1] (in/out)) TS0_DATA[2] (in/out)) TS0_DATA[3] (in/out)) TS0_DATA[4] (in/out)) TS0_DATA[5] (in/out)) TS0_DATA[6] (in/out)) TS0_DATA[7] (in/out))
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Clocking
7
Clocking
Table 35 lists the clocks in the 88F619x.
Table 35: 88F619x Clocks
C l o ck Ty p e CPU PLL Description Reference clock: REF_CLK_XIN (25 MHz) • Derivative clocks: - CPU clock - L2 cache clock - DDR Clock (the Mbus-L uses the DDR clock.) NOTE: See Table 38, Reset Configuration, on page 77 for CPU, L2 cache and DDR frequency configuration. L2 cache clock frequency must be equal or higher then DDR clock frequency. If the SSCG enable bit in the Sampled at Reset register is set, then the SSCG circuit is applied for the CPU PLL reference clock (refer to the Sampled at Reset register in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications). Core PLL Reference clock: REF_CLK_XIN (25 MHz) • Derivative clocks: - TCLK (core clock, 166 MHz) - SDIO Clock (100 MHz) - Gigabit Ethernet Clock (125 MHz) - TS unit Clock(100/91/83/77MHz) (88F6192 only) - SPI clock (TCLK/30–TCLK/4 MHz) - SMI clock (TCLK/128 MHz) - TWSI clock (up to TCLK/1600) NOTE: See Table 38, Reset Configuration, on page 77 for TCLK frequency configuration. NOTE: See the TS Interface Configuration register in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications for TS clock frequency configuration (88F6192 only). There are two options for the reference clock configuration, depending on the PCI Express clock 100 MHz differential clock: • The device uses an external source for PCI Express clock. The PEX_CLK_P pin is an input. • The device uses an internal generated clock for PCI Express clock. The PEX_CLK_P pin is an output, driving out the PCI Express differential clock. • Reference clock: REF_CLK_XIN (25 MHz) • •
PEX PHY
USB PHY PLL
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Doc. No. MV-S104987-U0 Rev. F Page 71
88F619x Hardware Specifications
Table 35: 88F619x Clocks (Continued)
C l o ck Ty p e SATA PHY PLL Description • • Reference clock: REF_CLK_XIN (25 MHz) Derivative clock: SATA Clock (150 MHz)
RTC
Reference clock: RTC_XIN (32.768 kHz) Used for real time clock functionality, see the Real Time Clock section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. Reference clock: PTP_CLK (125 MHz) The PTP_CLK can be used for the following functions: • PTP time stamp clock Two options for reference clock: - PTP_CLK - Gigabit Ethernet Clock (125 MHz) • TS unit clock Two options for reference clock: - PTP_CLK/2 - Core PLL • Audio unit clock Two options for reference clock: - PTP_CLK - REF_CLK_XIN (25 MHz) For clocking configuration registers, see the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. •
•
PTP
The following table lists the supported combinations of the CPU_CLK Frequency select, CPU_CLK to DDR CLK ratio, and to CPU_CLK to CPU L2 clock ratio (see Section 8.5, Pins Sample Configuration, on page 76).
Table 36: Supported Clock Combinations
Device DDR Clock (MHz) 200 200 CPU to DDR C l o c k R at io 3:1 4:1 C P U C lo c k (MHz) 600 800 C PU t o L 2 C lo c k R a ti o 2:1 2:1 L 2 C lo c k (MHz) 300 400
88F6190: 88F6192:
7.1
Spread Spectrum Clock Generator (SSCG)
The SSCG (Spread Spectrum Clock Generator) may be used to generate the spread spectrum clock for the PLL input. See SSCG Disable in Table 38, Reset Configuration, on page 77, for SSCG enable/bypass configuration settings. The SSCG block can be configured to perform up spread, down spread and center spread. The modulation frequency is configurable. Typical frequency is 30 kHz. The spread percentage can also be configured up to 1%. For additional details, see the SSCG Configuration Register description in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications.
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System Power Up/Down and Reset Settings
Power-Up/Down Sequence Requirements
8
8.1
8.1.1
System Power Up/Down and Reset Settings
This section provides information about the device power-up/down sequence and configuration at reset.
Power-Up/Down Sequence Requirements
Power-Up Sequence Requirements
These guidelines must be applied to meet the 88F619x device power-up requirements: The non-core voltages (I/O and Analog) as listed in Table 37 must reach 70% of their voltage level before the core voltages reach 70% of their voltage level. The order of the power-up sequence between the non-core voltages is unimportant so long as the non-core voltages power up before the core voltages reach 70% of their voltage level (shown in Figure 5). The reset signal(s) must be asserted before the core voltages reach 70% of their voltage level (shown in Figure 5). The reference clock(s) inputs must toggle with their respective voltage levels before the core voltages reach 70% of their voltage level (shown in Figure 5). If VHV is set to burning mode (2.5V), which is a higher voltage than the VDD voltage, VDD must be powered before VHV, to prevent the fuse from being accidentally burned.
Table 37: I/O and Core Voltages
N o n - C o r e Vo lta g e s I/ O Vo lta ge s VDD_GE_A VDD_GE_B VDD_M VDDO A n a lo g P o w e r Su p pl i es CPU_PLL_AVDD CORE_PLL_AVDD PEX_AVDD RTC_AVDD 88F6190 – SATA_AVDD 88F6192 – SATA0_AVDD 88F6192 – SATA1_AVDD SSCG_AVDD XTAL_AVDD USB_AVDD VDD C or e Vo l ta g es
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88F619x Hardware Specifications
Figure 5: Power-Up Sequence Example
Voltage Non-Core Voltage 70% of Non-Core Voltage Core Voltage
70% of Core Voltage
Reset(s)
Clock(s)
Note
It is the designer's responsibility to verify that the power sequencing requirements of other components are also met. Although the non-core voltages can be powered up any time before the core voltages, allow a reasonable time limitation (for example, 100 ms) between the first non-core voltage power-up and the last core voltage power-up.
8.1.2
Power-Down Sequence Requirements
There are no special requirements for the core supply to go down before non-core power, or for reset assertion when powering down (except for VHV, as described below). However, allow a reasonable time limitation (no more than 100 ms) between the first and last voltage power-down. When using the eFuse in Burning mode, VHV must be powered down before VDD.
8.2
Hardware Reset
The device has one reset input pin—SYSRSTn. When asserted, the entire chip is placed in its initial state. Most outputs are placed in high-z, except for the following output pins, that are still active during SYSRSTn assertion: M_CLKOUT, M_CLKOUTn M_CKE M_ODT M_STARTBURST SYSRST_OUTn
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System Power Up/Down and Reset Settings
Hardware Reset
Note
Reset (SYSRSTn signal) must be active for a minimum length of 5 ms. core power, I/O power, and analog power must be stable (VDD +/- 5%) during that time and onward.
8.2.1
Reset Out Signal
The device has an optional SYSRST_OUTn output signal, multiplexed on an MPP pin, that is used as a reset request from the device to the board reset logic. SYSRST_OUTn is the default option for that MPP pin. This signal is asserted low for 20 ms, when one of the following maskable events occurs: Received hot reset indication from the PCI Express link (only relevant when used as a PCI Express endpoint), and bit is set to 1 in the RSTOUTn Mask Register (see the Reset register section of the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications). PCI Express link failure (only relevant when used as a PCI Express endpoint), and bit is set to 1 in the RSTOUTn Mask Register. Watchdog timer expiration and bit is set to 1 in the RSTOUTn Mask Register. Bit is set to 1 in System Soft Reset Register and bit is set to 1 in RSTOUTn Mask Register. This signal is asserted low for 20 ms, when the POR (power on reset) non-maskable event occurs.—the device includes a power on reset circuit for VDD power.
8.2.2
Power On Reset (POR)
The SYSRST_OUTn output signal is asserted low for 20 ms, when the power-on-reset (POR) circuit is triggered. POR is triggered when VDD power up (digital core voltage) reaches a VDD threshold (threshold maximum value 0.8V). Hysteresis: Another trigger will only occur after the power first drops to 50 mV, and then a power up occurs.
8.2.3
SYSRSTn Duration Counter
When SYSRSTn is asserted low, a SYSRSTn duration counter is running. The counter clock is the 25 MHz reference clock. It is a 29-bit counter, yielding a maximum counting duration of 2^29/25 MHz (21.4 seconds). The host software can read the counter value and reset the counter. When the counter reach its maximum value, it remains at this value until counter reset is triggered by software.
Note
The SYSRSTn duration counter is useful for implementing manufacturer/factory reset. Upon a long reset assertion, greater than a pre-configured threshold, the host software may reset all settings to the factory default values.
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88F619x Hardware Specifications
8.3
8.3.1
PCI Express Reset
PCI Express Root Complex Reset
As a Root Complex, the device may generate a Hot Reset to the PCI Express port. Upon CPU setting the PCI Express Control register’s bit, the PCI Express unit sends a Hot Reset indication to the Endpoint, see the PCI Express Interface section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications.
8.3.2
PCI Express Endpoint Reset
When a Hot Reset packet is received: A maskable interrupt is asserted. If the field in the PCI Express Debug Control register is cleared, the device also resets the PCI Express register file to its default values. The device triggers an internal reset, if not masked by the field in the PCI Express Debug Control register. Link failure is detected if the PCI Express link was up (LTTSSM L0 state) and dropped back to an inactive state (LTSSM Detect state). When Link failure is detected: A maskable interrupt is asserted. If the field in the PCI Express Debug Control register is cleared, the device also resets the PCI Express register file to its default values. The device triggers an internal reset, if the field is not masked by PCI Express Debug Control register. Both link fail and hot reset conditions trigger a chip internal reset (if not masked in the PCI Express interface). All the chip logic is reset to the default values, except for sticky registers and the sample on reset logic. In addition, these events can trigger reset to the board, using one of the following: PEX_RST_OUTn signal (multiplexed on MPP). SYSRST_OUTn output (multiplexed on MPP)—if not masked by the bit. The external reset logic (on the board) may assert the SYSRSTn input pin and reset the entire chip.
8.4 8.5
Sheeva™ CPU TAP Controller Reset
The Sheeva™ CPU Test Access Port (TAP) controller is reset when JT_RSTn is set and JT_TMS_CPU is active.
Pins Sample Configuration
The following pins are sampled during SYSRSTn de-assertion: Internal pull up/down resistors set the default mode (see Section 2.3, Internal Pull-up and Pull-down Pins, on page 55). Higher value, external pull up/down resistors are required to change the default mode of operation. These signals must remain pulled up or down until SYSRSTn de-assertion (zero hold time in respect to SYSRSTn de-assertion).
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System Power Up/Down and Reset Settings
Pins Sample Configuration
Note
If external logic is used instead of pull-up and pull-down resistors, the logic must drive all of these signals to the desired values during SYSRSTn assertion. To prevent bus contention on these pins, the external logic must float the bus no later than the third TCLK cycle after SYSRSTn de-assertion. All reset sampled values are registered in the Sample at Reset register (see the MPP Registers in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications). This is useful for board debug purposes and identification of board and system settings for the host software. If a signal is pulled up on the board, it must be pulled to the proper voltage level. In the devices, certain reset configuration pins are powered by VDD_GE_A and VDD_GE_B. In the 88F6190 VDD_GE_A has multiple voltage options, and in the 88F6192, VDD_GE_A and VDD_GE_B have multiple voltage options (see Table 42, Recommended Operating Conditions, on page 87).
In each row of Table 38, the order of the pins is from MSb to LSb (e.g., for in the row CPU_CLK Frequency Select, MPP[2] is the MSB and MPP[10] is the LSB).
Table 38: Reset Configuration
P in MPP[1] C on fi g ur a tio n F u n ct io n TWSI Serial ROM Initialization 0 = Disabled 1 = Enabled NOTE: Internally pulled down to 0x0. When this pin is set to 0x1, MPP[8] and MPP[9] wake up as TWSI data and clock pins, respectively (see Section 6.1, Multi-Purpose Pins Functional Summary, on page 61). MPP[2], Used for internal testing Must be 0x0 during reset. Either leave the signal floating (internally pulled down to 0x0) or pull the signal to 0x0 during reset. MPP[5] Reserved For the 88F6190: NOTE: Must be externally pulled down to 0x0 during reset. For the 88F6192: Must be 0x1 during reset. Either leave the signal floating (internally pulled up to 0x1) or pull the signal to 0x1 during reset. MPP[10] Used for internal testing Must be 0x0 during reset. Either leave the signal floating (internally pulled down to 0x0) or pull the signal to 0x0 during reset. MPP[19] Reserved Must be 0x1 during reset. Either leave the signal floating (internally pulled up to 0x1) or pull the signal. MPP[33], Reserved Must be 0x0 during reset. Either leave the signal floating (internally pulled down to 0x0) or pull the signal to 0x0 during reset.
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88F619x Hardware Specifications
Table 38: Reset Configuration (Continued)
P in NF_ALE C on fi g ur a tio n F u n ct io n Reserved Must be 0x1 during reset. Either leave the signal floating (internally pulled up to 0x1) or pull the signal to 0x1 during reset. NF_REn Reserved For the 88F6190: Must be 0x0 during reset. Either leave the signal floating (internally pulled down to 0x0) or pull the signal to 0x0 during reset. For the 88F6192: NOTE: Must be externally pulled up to 0x1 during reset. NF_CLE Reserved Must be 0x0 during reset. Either leave the signal floating (internally pulled down to 0x0) or pull the signal to 0x0 during reset. MPP[3] Reserved Must be 0x0 during reset. Either leave the signal floating (internally pulled down to 0x0) or pull the signal to 0x0 during reset. MPP[12] Reserved Must be 0x0 during reset. Either leave the signal floating (internally pulled down to 0x0) or pull the signal to 0x0 during reset. NF_WEn Reserved Must be 0x1 during reset. Either leave the signal floating (internally pulled up to 0x1) or pull the signal to 0x1 during reset.
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System Power Up/Down and Reset Settings
Pins Sample Configuration
Table 38: Reset Configuration (Continued)
P in GE_TXD[2:0] C on fi g ur a tio n F u n ct io n Boot Device 0x0 = Reserved 0x1 = Reserved 0x2 = Boot from SPI flash (SPI_CSn on MPP[7]) 0x3 = Reserved 0x4 = Boot from SPI flash (SPI_CSn on MPP[0]) 0x5 = Boot from NAND flash 0x6 = Boot from SATA 0x7 = Boot from the PCI Express port NOTE: • Internally pulled to 0x4. • Only SPI signals configured on pins MPP[3:0] or on pins MPP[7] and MPP[3:1] can be used for booting from SPI. SPI signals that are multiplexed on other MPPs can only be used after booting (see Section 6.1, Multi-Purpose Pins Functional Summary, on page 61). • When GE_TXD[2:0] is set to 0x4, MPP[3:0] wake up as SPI signals. • When GE_TXD[2:0] is set to 0x2, MPP[7] and MPP[3:1] wake up as SPI signals. • When GE_TXD[2:0] is set to 0x5, MPP[5:0] and MPP[19:18] wake up as NAND Flash signals. • For a more detailed description of the bootROM, see the BootROM section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. • For a more detailed description of the boot from SPI flash or NAND flash, see the SPI Interface and NAND Flash Interface sections in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. • There is an option to boot from UART when GE_TXD[2:0] = 0x2–0x7. For a more detailed description of the boot from UART, see the BootROM section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. GE_TXD[3] SSCG Disable 0 = Enable 1 = Disable NOTE: Internally pulled to 0x1. GE_MDC PCI Express Clock (100 MHz Differential Clock) Configuration 0x0 = The device use external source for PCI Express clock. Pins PEX_CLK_P/PEX_CLK_N are inputs. 0x1 = The device uses internal generated clock for PCI Express clock. Pins PEX_CLK_P/PEX_CLK_N pins are outputs, driving out the PCI Express differential clock. NOTE: Internally pulled to 0x1. 88F6190 – GE_TXEN 88F6192 – GE_TXCTL MPP[7]
Used for internal testing Must be 0x0 during reset. Either leave the signal floating (internally pulled down to 0x0) or pull the signal to 0x0 during reset.
Reserved Must be 0x1 during reset. Either leave the signal floating (internally pulled up to 0x1) or pull the signal to 0x1 during reset.
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88F619x Hardware Specifications
Table 38: Reset Configuration (Continued)
P in MPP[18] C on fi g ur a tio n F u n ct io n Reserved Must be 0x1 during reset. Either leave the signal floating (internally pulled up to 0x1) or pull the signal to 0x1 during reset.
8.6
Serial ROM Initialization
The device supports initialization of ALL of its internal and configuration registers through the TWSI master interface. If serial ROM initialization is enabled, the device TWSI master starts reading initialization data from serial ROM and writes it to the appropriate registers, upon de-assertion of SYSRSTn. When using Serial ROM Initialization, the MPP[9:8] pins must be configured to as TW_SCK (MPP[9]) and TW_SDA (MPP[8]).
8.6.1
Serial ROM Data Structure
Serial ROM data structure consists of a sequence of 32-bit address and 32-bit data pairs, as shown in Figure 6.
Figure 6: Serial ROM Data Structure
MSB LSB address0[31:24] address0[23:16] address0[15:8] address0[7:0] data0[31:24] data0[23:16] data0[15:8] data0[7:0] address1[31:24] address1[23:16] address1[15:8] address1[7:0] data1[31:24] data1[23:16] data1[15:8] data1[7:0]
Start
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System Power Up/Down and Reset Settings
Boot Sequence
The serial ROM initialization logic reads eight bytes at a time. It performs address decoding on the 32-bit address being read, and based on address decoding result, writes the next four bytes to the required target. The Serial Initialization Last Data Register contains the expected value of last serial data item (default value is 0xFFFFFFFF). When the device reaches last data, it stops the initialization sequence.
8.6.2
Serial ROM Initialization Operation
On SYSRSTn de-assertion, the device starts the initialization process. It first performs a dummy write access to the serial ROM, with data byte(s) of 0x0, to set the ROM byte offset to 0x0. Then, it performs the sequence of reads, until it reaches last data item, as shown in Figure 7.
Figure 7: Serial ROM Read Example
s t a r t w r i t e s t a r t r e a d Data from ROM
Upper Byte Offset
Lower Byte Offset
s10100000 a c k ROM Address
00000000 a c k
00000000 a c k
s10100001 a c k ROM Address Last Data from ROM
AAAAAAAA a c k
AAAA
s t o p xxxxxxxx a c k n a c k p
11111111 a c k
11111111 a c k
11111111 a c k
11111111
For a detailed description of TWSI implementation, see the Two-Wire Serial Interface section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. Initialization data must be programmed in the serial ROM starting at offset 0x0. The device assumes 7-bit serial ROM address of ‘b1010000. After receiving the last data identifier (default value is 0xFFFFFFFF), the device receives an additional byte of dummy data. It responds with no-ack and then asserts the stop bit. The serial EEPROM must contain two address offset bytes (It must not be less than a 256 byte ROM.).
8.7
Boot Sequence
The device requires that SYSRSTn stay asserted for at least 300 μs after power and clocks are stable. The following procedure describes the boot sequence starting with the reset assertion: 1. While SYSRSTn is asserted, the CPU PLL and the core PLL are locked. 2. Upon SYSRSTn de-assertion, the pad drive auto-calibration process starts. It takes 512 TCLK cycles. 3. If Serial ROM initialization is enabled, an initialization sequence is started. 4. If configured to boot from NAND flash (and BootROM is disabled), the device also performs a NAND Flash boot sequence to prepare page 0 in the NAND flash device for read.
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88F619x Hardware Specifications
Upon completing the above sequence, the internal CPU reset is de-asserted, and the CPU starts executing boot code from the boot device (SPI flash, NAND flash, or internal Boot ROM), according to sample at reset setting, see Table 38, Reset Configuration, on page 77. For bootROM details, see the BootROM section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. As part of the CPU boot code, the CPU typically performs the following: Configures the PCI Express address map. Configures the proper SDRAM controller parameters, and then triggers SDRAM initialization (sets bit [0] to 1 in the SDRAM Initialization Control register). Sets the bits in the CPU Control and Status register to wake up the PCI Express link.
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JTAG Interface
TAP Controller
9
9.1
JTAG Interface
To enable board testing, the device supports a test mode operation through its JTAG boundary scan interface. The JTAG interface is IEEE 1149.1 standard compliant. It supports mandatory and optional boundary scan instructions.
TAP Controller
The Test Access Port (TAP) is constructed with a 5-pin interface and a 16-state Finite State Machine (FSM), as defined by IEEE JTAG standard 1149.1. To place the device in a functional mode, reset the JTAG state machine to disable the JTAG interface. According to the IEEE 1149.1 standard, the JTAG state machine is not reset when the 88F619xSYSRSTn is asserted. The JTAG state machine can only be reset by one of the following methods: Asserting JT_RSTn. Setting JT_TMS_CORE for at least five JT_CLK cycles. To place the device in one of the boundary scan test mode, the JTAG state machine must be moved to its control states. JT_TMS_CORE and JT_TDI inputs control the state transitions of the JTAG state machine, as specified in the IEEE 1149.1 standard. The JTAG state machine will shift instructions into the Instruction register while in SHIFT-IR state and shift data into and from the various data registers when in SHIFT-DR state.
9.2
Instruction Register
The Instruction register (IR) is a 4-bit, two-stage register. It contains the command that is shifted in when the TAP FSM is in the Shift-IR state. When the TAP FSM is in the Capture-IR state, the IR outputs all four bits in parallel. Table 39 lists the instructions supported by the device.
Table 39: Supported JTAG Instructions
In s t r u c t io n HIGHZ IDCODE EXTEST C o de 0011 0010 0000 D es c r ip t i o n Select the single bit Bypass register between TDI and TDO. Sets the device output pins to high-impedance state. Selects the Identification register between TDI and TDO. This 32-bit register is used to identify the device. Selects the Boundary Scan register between TDI and TDO. Outputs the boundary scan register cells to drive the output pins of the device. Inputs the boundary scan register cell to sample the input pin of the device. Selects the Boundary Scan register between TDI and TDO. Samples input pins of the device to input boundary scan register cells. Preloads the output boundary scan register cells with the Boundary Scan register value. Selects the single bit Bypass register between TDI and TDO. This allows for rapid data movement through an untested device.
SAMPLE/PRE LOAD
0001
BYPASS
1111
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88F619x Hardware Specifications
9.3
Bypass Register
The Bypass register (BR) is a single bit serial shift register that connects TDI to TDO, when the IR holds the Bypass command, and the TAP FSM is in Shift-DR state. Data that is driven on the TDI input pin is shifted out one cycle later on the TDO output pin. The Bypass register is loaded with 0 when the TAP FSM is in the Capture-DR state.
9.4
JTAG Scan Chain
The JTAG Scan Chain is a serial shift register used to sample and drive all of the device pins during the JTAG tests. It is a 2-bit per pin shift register in the device, thereby allowing the shift register to sequentially access all of the data pins both for driving and strobing data. For further details, refer to the BSDL Description file for the device.
9.5
ID Register
The ID register is a 32-bit deep serial shift register. The ID register is loaded with vendor and device information when the TAP FSM is in the Capture-DR state. The Identification code format of the ID register is shown in Table 40, which describes the various ID Code fields.
Table 40: IDCODE Register Map
B i ts 31:28 27:12 11:1 0 Va l u e 0x0 0x6192 0x1AB 1 Description Version (4'b0010 for version A0, 4'b0011 for A1, etc.) Part number Manufacturer ID Mandatory
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Electrical Specifications (Preliminary)
Absolute Maximum Ratings
10
10.1
Electrical Specifications (Preliminary)
The numbers specified in this section are PRELIMINARY and SUBJECT TO CHANGE. Note
Absolute Maximum Ratings
Table 41: Absolute Maximum Ratings
Parameter VDD CPU_PLL_AVDD CORE_PLL_AVDD SSCG_AVDD Min -0.5 -0.5 Max 1.2 2.2 U n its V V C om m e n ts Core and CPU voltage Analog supply for the internal PLL
-0.5
2.2
V
Analog supply for: Internal Spread Spectrum Clock Generator I/O voltage for: RGMII/GMII/MII/MMII/SMI interface I/O voltage for: SDRAM interface I/O voltage for: MPP, TWSI, JTAG, SDIO, I2S, SPI, TS, and TDM interfaces NOTE: The I2S, TS, and TDM interfaces are only relevant for the 88F6192. I/O voltage for eFuse burning Analog supply for: PCI Express interface Analog supply for: USB interface Analog supply for: SATA interface
VDD_GE_A VDD_GE_B VDD_M
-0.5
4.0
V
-0.5
2.2
V
VDDO
-0.5
4.0
V
VHV PEX_AVDD
-0.5 -0.5
3.0 2.2
V V
USB_AVDD
-0.5
4.0
V
88F6190 – SATA_AVDD 88F6192 – SATA0_AVDD SATA1_AVDD
-0.5
4.0
V
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88F619x Hardware Specifications
Table 41: Absolute Maximum Ratings (Continued)
Parameter XTAL_AVDD Min -0.5 Max 2.2 U n its V C om m e n ts Analog supply for internal clock inverter for crystal support and current source for SATA and USB PHYs Analog supply for: RTC interface Case temperature Storage temperature
RTC_AVDD
-0.5
2.2
V
TC TSTG
-40 -40
125 125
°C °C
Caution
Exposure to conditions at or beyond the maximum rating may damage the device. Operation beyond the recommended operating conditions (Table 42) is neither recommended nor guaranteed.
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Electrical Specifications (Preliminary)
Recommended Operating Conditions
10.2
Recommended Operating Conditions
Table 42: Recommended Operating Conditions
Parameter VDD CPU_PLL_AVDD CORE_PLL_AVDD SSCG_AVDD M in 0.95 1.7 Ty p 1.0 1.8 Max 1.05 1.9 Units V V C om m e n ts Core and CPU voltage Analog supply for the internal PLL
1.7
1.8
1.9
V
Analog supply for: Internal Spread Spectrum Clock Generator I/O voltage for: RGMII(10/100 RGMII only)/ GMII/MII/MMII/SMI interfaces I/O voltage for: RGMII/SMI interfaces I/O voltage for: GMII/MII/MMII/SMI interfaces I/O voltage for: SDRAM interface I/O voltage for: MPP, TWSI, JTAG, SDIO, I2S, SPI, TS, and TDM interfaces NOTE: The I2S, TS, and TDM interfaces are only relevant for the 88F6192.
88F6190 – VDD_GE_A 88F6192 – VDD_GE_A VDD_GE_B 88F6190 – VDD_GE_B
3.15
3.3
3.45
V
1.7
1.8
1.9
V
3.15
3.3
3.45
V
VDD_M
1.7
1.8
1.9
V
VDDO
3.15
3.3
3.45
V
VHV (during eFuse Burning mode)
2.375
2.5
2.625
V
I/O voltage for eFuse burning NOTE: If the VHV voltage is higher than VDD voltage (burning mode), VDD must be powered before VHV, to prevent the fuse from being accidentally burned. I/O voltage for eFuse reading NOTE: It is recommended that if only a read operation is required, VHV would be connected to the device VDD power. Analog supply for: PCI Express interface Analog supply for: USB interface
VHV (during eFuse Reading mode)
0.95
1.0
1.05
V
PEX_AVDD
1.7
1.8
1.9
V
USB_AVDD
3.15
3.3
3.45
V
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88F619x Hardware Specifications
Table 42: Recommended Operating Conditions (Continued)
Parameter 88F6190 – SATA_AVDD 88F6192 – SATA0_AVDD SATA1_AVDD XTAL_AVDD 1.7 1.8 1.9 V Analog supply for: Internal clock inverter for crystal support and current source for SATA and USB PHYs Analog supply for RTC in Regular mode Analog supply for RTC in Battery Back-up mode Junction Temperature M in 3.15 Ty p 3.3 Max 3.45 Units V C om m e n ts Analog supply for: SATA interface
RTC_AVDD
1.7
1.8
1.9
V
1.3
1.5
1.7
V
TJ
0
105
°C
Caution
Operation beyond the recommended operating conditions is neither recommended nor guaranteed.
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Electrical Specifications (Preliminary)
Thermal Power Dissipation
10.3
Thermal Power Dissipation
Before designing a system, Marvell recommends reading application note AN-63: Thermal Management for Marvell Technology Products. This application note presents basic concepts of thermal management for integrated circuits (ICs) and includes guidelines to ensure optimal operating conditions for Marvell Technology's products.
Note
The purpose of the Thermal Power Dissipation table is to support system engineering in thermal design.
.
Table 43: Thermal Power Dissipation
In t e r f a c e Core (including CPU)—VDD 1.0V For the 88F6190: S y m bo l PVDD CPU @ 600 MHz, L2 @ 300 MHz, Core @ 166 MHz CPU @ 800 MHz, L2 @ 400 MHz, Core @ 166 MHz PRGMII PRGMII PGMII PMII PMISC 930 mW Te s t C on d it io n s Ty p Units
For the 88F6192:
1000
mW
RGMII 1.8V interface RGMII (10/100 RGMII only) 3.3V interface GMII 3.3V interface MII/MMII 3.3V interface Miscellaneous interfaces (JTAG, TWSI, UART, NAND flash, Audio, SDIO, TDM, TS, and SPI) NOTE: The Audio, TDM, and TS interfaces only apply to the 88F6192. DDR2 SDRAM interface (On Board, 16-bit, 200 MHz) eFuse during Burning mode NOTE: Since the eFuse burn is performed only once, there is no thermal effect after the burn has finished. eFuse during Reading mode PCI Express interface USB interface SATA interface
30 50 50 10 50
mW mW mW mW mW
PDDR2 PFUSE
Two on board devices, 75 ohm ODT termination
180
mW
50
mW
PFUSE PPEX PUSB PSATA 88F6190 – A single SATA port 88F6192 – Two SATA ports
25 100 120 205 410
mW mW mW mW mW
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Notes: 1. The values are for nominal voltage. 2. Power in mW is calculated using the typical recommended VDDIO specification for each power rail.
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Electrical Specifications (Preliminary)
Current Consumption
10.4
Current Consumption
The purpose of the Current Consumption table is to support board power design and power module selection.
.
Table 44: Current Consumption
In t e r f a c e Core (including CPU)—VDD 1.0V For the 88F6190: S y m bo l IVDD CPU @ 600 MHz, L2 @ 300@ MHz, Core @ 166 MHz CPU @ 800 MHz, L2 @ 400@ MHz, Core @ 166 MHz IRGMII IGMII IMII_MMII IMISC 1930 mA Te s t C on d it io n s Max Units
For the 88F6192:
2000
mA
RGMII 1.8V or 3.3V interface GMII 3.3V interface MII/MMII 3.3V interface Miscellaneous interfaces (JTAG, TWSI, UART, NAND flash, Audio, SDIO, TDM, TS, and SPI) NOTE: The Audio, TDM, TS interfaces only apply to the 88F6192. DDR2 SDRAM interface (On Board 16-bit 200 MHz) eFuse during Burning mode eFuse during Reading mode PCI Express interface USB interface SATA interface
25 25 25 25
mA mA mA mA
IDDR2 IFUSE IFUSE IPEX IUSB ISATA
Two on board devices, 75 ohm ODT termination
450
mA
20 25 50 40 88F6190 – A single SATA port 88F6192 – Two SATA ports 65 130
mA mA mA mA mA mA
Notes: 1. Current in mA is calculated using maximum recommended VDDIO specification for each power rail. 2. All output clocks toggling at their specified rate. 3. Maximum drawn current from the power supply.
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88F619x Hardware Specifications
10.5
DC Electrical Specifications
See Section 2.3, Internal Pull-up and Pull-down Pins, on page 55 for internal pullup/pulldown information.
Note
10.5.1
General 3.3V (CMOS) DC Electrical Specifications
The S/PDIF / I2S and Transport Stream interfaces are only relevant for the 88F6192. Note The DC electrical specifications in Table 45 are applicable for the following interfaces and signals: JTAG RGMII (10/100 Mbps)/GMII/MII/MMII Secure Digital Input/Output (SDIO) S/PDIF / I2S (Audio) Transport Stream (TS) NAND flash UART MPP PTP SYSRSTn In the following table, for the JTAG, SDIO, S/PDIF / I2S, TS, NAND flash, UART, PTP, and MPP interfaces, VDDIO means the VDDO power rail. For the 88F6190 RGMII interface VDDIO means the VDD_GE_A power rail, and for the GMII/MII/MMII interface, VDDIO means the VDD_GE_A and VDD_GE_B power rails. For the 88F6192 RGMII/GMII/MII/MMII interface, VDDIO means the VDD_GE_A and VDD_GE_B power rails.
Table 45: General 3.3V Interface (CMOS) DC Electrical Specifications
Param eter Input low level Input high level Output low level Output high level Input leakage current Pin capacitance Sym bol VIL VIH VOL VOH IIL Cpin IOL = 2 mA IOH = -2 mA 0 < VIN < VDDIO Test Condition Min -0.3 2.0 2.4 -10 5 Typ Max 0.8 VDDIO+0.3 0.4 10 Units Notes V V V V uA pF 1, 2 -
Notes: General comment: See the Pin Description section for internal pullup/pulldow n. 1. While I/O is in High-Z. 2. This current does not include the current flow ing through the pullup/pulldow n resistor.
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Electrical Specifications
DC Electrical Specifications
10.5.2
RGMII, SMI and REF_CLK_XIN 1.8V (CMOS) DC Electrical Specifications
In the following table, for the RGMII interface, VDDIO means the VDD_GE_A power rail or VDD_GE_B power rail (88F6192 only). In the following table, for the REF_CLK_XIN pin, VDDIO means the XTAL_AVDD power rail.
Table 46: RGMII 1.8V Interface (CMOS) DC Electrical Specifications
Param eter Input low level Input high level Output low level Output high level Input leakage current Pin capacitance Sym bol VIL VIH VOL VOH IIL Cpin IOL = 2 mA IOH = -2 mA 0 < VIN < VDDIO Test Condition Min -0.3 0.65*VDDIO VDDIO-0.45 -10 5 Typ Max 0.35*VDDIO VDDIO+0.3 0.45 10 Units Notes V V V V uA pF 1, 2 -
Notes: General comment: See the Pin Description section for internal pullup/pulldow n. 1. While I/O is in High-Z. 2. This current does not include the current flow ing through the pullup/pulldow n resistor.
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88F619x Hardware Specifications
10.5.3
SDRAM DDR2 Interface DC Electrical Specifications
In the following table, VREF is VDD_M/2 and VDDIO means the VDD_M power rail.
Table 47: SDRAM DDR2 Interface DC Electrical Specifications
Parameter Input low level Input high level Output low level Output high level Rtt effective impedance value Symbol VIL VIH VOL VOH RTT IOL = 13.4 mA IOH = -13.4 mA See note 2 1.42 120 60 40 Deviation of VM w ith respect to VDDQ/2 Input leakage current Pin capacitance dVm IIL Cpin See note 3 0 < VIN < VDDIO -6 -10 5 150 75 50 180 90 60 6 10 Test Condition Min -0.3 VREF + 0.125 Typ Max VREF - 0.125 VDDIO + 0.3 0.28 Units Notes V V V V ohm ohm ohm % uA pF 1,2 1,2 1,2 3 4, 5 -
Notes: General comment: See the Pin Description section for internal pullup/pulldow n. 1. See SDRAM functional description section for ODT configuration. 2. Measurement definition for RTT: Apply VREF +/- 0.25 to input pin separately, then measure current I(VREF + 0.25) and I(VREF - 0.25) respectively.
RTT =
0 .5 I (VREF + 0.25 ) − I (VREF
− 0.25 )
3. Measurement definition for VM: Measured voltage (VM) at input pin (midpoint) w ith no load.
⎛ 2 × Vm ⎞ dVM = ⎜ − 1 ⎟ × 100 % ⎝ VDDIO ⎠
4. While I/O is in High-Z. 5. This current does not include the current flow ing through the pullup/pulldow n resistor.
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Electrical Specifications
DC Electrical Specifications
10.5.4
Two-Wire Serial Interface (TWSI) 3.3V DC Electrical Specifications
In the following table, VDDIO means the VDDO power rail.
Table 48: TWSI Interface 3.3V DC Electrical Specifications
Param eter Input low level Input high level Output low level Input leakage current Pin capacitance Sym bol VIL VIH VOL IIL Cpin IOL = 3 mA 0 < VIN < VDDIO Test Condition Min -0.5 0.7*VDDIO -10 5 Typ Max 0.3*VDDIO VDDIO+0.5 0.4 10 Units Notes V V V uA pF 1, 2 -
Notes: General comment: See the Pin Description section for internal pullup/pulldow n. 1. While I/O is in High-Z. 2. This current does not include the current flow ing through the pullup/pulldow n resistor.
10.5.5
Serial Peripheral Interface (SPI) 3.3V DC Electrical Specifications
In the following table VDDIO means the VDDO power rail.
Table 49: SPI Interface 3.3V DC Electrical Specifications
Param eter Input low level Input high level Output low level Output high level Input leakage current Pin capacitance Sym bol VIL VIH VOL VOH IIL Cpin IOL = 4 mA IOH = -4 mA 0 < VIN < VDDIO Test Condition Min -0.5 0.7*VDDIO VDDIO-0.6 -10 5 Typ Max 0.3*VDDIO VDDIO+0.5 0.4 10 Units Notes V V V V uA pF 1, 2 -
Notes: General comment: See the Pin Description section for internal pullup/pulldow n. 1. While I/O is in High-Z. 2. This current does not include the current flow ing through the pullup/pulldow n resistor.
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88F619x Hardware Specifications
10.5.6
Time Division Multiplexing (TDM) 3.3V DC Electrical Specifications
The TDM interface is only relevant for the 88F6192. Note In the following table VDDIO means the either the VDDO or the VDD_GE_B power rail, depending on which MPP pins are configured for the TDM interface.
Table 50: TDM Interface 3.3V DC Electrical Specifications
Param eter Input low level Input high level Output low level Output high level Input leakage current Pin capacitance Sym bol VIL VIH VOL VOH IIL Cpin IOL = 4 mA IOH = -4 mA 0 < VIN < VDDIO Test Condition Min -0.5 0.7*VDDIO VDDIO-0.6 -10 5 Typ Max 0.3*VDDIO VDDIO+0.5 0.4 10 Units Notes V V V V uA pF 1, 2 -
Notes: General comment: See the Pin Description section for internal pullup/pulldow n. 1. While I/O is in High-Z. 2. This current does not include the current flow ing through the pullup/pulldow n resistor.
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Electrical Specifications
AC Electrical Specifications
10.6
10.6.1
AC Electrical Specifications
See Section 10.7, Differential Interface Electrical Characteristics, on page 127 for differential interface specifications.
Reference Clock AC Timing Specifications
Table 51: Reference Clock AC Timing Specifications
D e s c r i p t io n CPU and Core Reference Clock Frequency Clock duty cycle Slew rate Pk-Pk jitter E t h er n e t R e f e r e n c e C lo c k Frequency in MII/MMII-MAC mode FGE_TXCLK_OUT FGE_RXCLK MII/MMII-MAC mode clock duty cycle DCGE_TXCLK_OUT DCGE_RXCLK Slew rate SRGE_TXCLK_OUT SRGE_RXCLK Audio external reference clock FAU_EXTCLK 2.5 100 ppm 35 50 + 100 ppm 65 MHz 7 FREF_CLK_XIN DCREF_CLK_XIN SRREF_CLK_XIN JRREF_CLK_XIN 25 50 ppm 40 0.7 200 25 + 50 ppm 60 MHz % V/ns ps 1 Sy m b o l Min Max Units Notes
%
7
0.7
V/ns
1, 7
A u d io E x t e r n a l R e f e r e n c e C lo c k ( O n ly r e l e va n t f o r t h e 8 8 F 6 1 9 2 ) 256 X Fs kHz 3
S / P D I F R e c o v e r e d M a s t e r C loc k ( O n ly r e l e v an t f o r t h e 8 8 F 6 1 9 2 ) S/PDIF recovered master clock
2
FAU_SPDFRMCLK FI2S_BCLK FSPI_SCK FRTC_XIN FTS0_CLK, FTS1_CLK FTS0_CLK, FTS1_CLK FTS0_CLK, FTS1_CLK FTS0_CLK, FTS1_CLK FEXT_CLK FEXT_CLK 9.61 9.61 9.61 9.61
256 X Fs 64 X Fs TCLK/30 TCLK/4
kHz
3
I S R e f e r e n c e C lo c k ( O n l y r e l e v a n t f o r t h e 88 F 6 1 9 2 ) I2S clock SP I O ut pu t C l o c k SPI output clock RTC Reference Clock RTC_XIN crystal frequency 32.768 kHz 4 MHz 2 kHz 3
Tra n s p o r t St r e a m ( T S ) O u t pu t M o d e R e f e r e n ce C l o c k ( O n l y r e le v a n t f o r t h e 8 8 F 6 19 2 ) TS output clock in parallel mode TS output clock in serial mode 12.5 83 MHz MHz 5 5
Tr a n s p o r t St r e a m In p u t M o d e R e f e r en c e C lo c k ( O n ly r e le v a n t f o r t h e 8 8 F 6 1 9 2 ) TS input clock in parallel mode TS input clock in serial mode 13.5 83 MHz MHz
Tr a n s p o r t St r e a m E x t e r n a l R e f e r e nc e C lo c k ( O n ly r e l e v an t f o r t h e 8 8 F 6 1 9 2 ) TS external clock in parallel mode TS external clock in serial mode 12.5 83 MHz MHz 5 5
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Table 51: Reference Clock AC Timing Specifications (Continued)
D e s c r i p t io n Sy m b o l Min Max Units Notes
T D M _ S P I O u t p u t C lo c k ( O n ly r e l ev a n t f o r t h e 8 8 F 6 1 9 2 ) TDM_SPI output clock S M I M a s t e r M o d e R e f e r e n c e C l o ck SMI output MDC clock T WS I M a s t er M o d e R e fe re n c e C lo c k SCK output clock PT P R e fe r e n c e C lo c k Frequency Clock duty cycle Slew rate Pk-Pk jitter FPTP_CLK DCPTP_CLK SRPTP_CLK JRPTP_CLK 125 100 ppm 40 0.7 100 125 + 100 ppm 60 MHz % V/ns ps 1 FTW_SCK TCLK/ 1600 kHz 6 FGE_MDC TCLK/128 MHz FTDM_SPI_SCK 8.192 MHz
Notes: 1. Slew rate is defined from 20% to 80% of the reference clock signal. 2. For additional information regarding configuring this clock, see the Serial Memory Interface Control Register in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. 3. Fs is the audio sample rate, which can be configured to 44.1 kHz, 48 kHz, or 96 kHz (see the Audio (I2S / S/PDIF) Interface section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications). 4. The RTC design was optimized for a standard CL = 12.5 pF crystal. No passive components are provided internally. Connect the crystal and the passive network as recommended by the crystal manufacturer. The frequency can be set using the TS Interface Configuration register (see the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications). For the minimum value refer to the Baud Rate Register section of the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. The Ethernet Reference Clock parameters refer both to the reference clock for an Ethernet port configured using the dedicated port pins and for an Ethernet port configured using the multiplexed port pins.
5. 6. 7.
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Electrical Specifications
AC Electrical Specifications
10.6.2
10.6.2.1
SDRAM DDR2 Interface AC Timing
SDRAM DDR2 Interface AC Timing Table
200 MHz @ 1.8V Description Sym bol fCK tDOVB tDOVA tDIPW tDQSH tDQSL tDSS tDSH tDQSS tWPRE tWPST tCH tCL tDSI tDHI tAOVB tAOVA tIPW Min Max 200.00 0.50 0.50 0.37 0.37 0.37 0.34 0.34 -0.11 0.35 0.42 0.45 0.45 -0.55 1.50 1.70 1.70 0.67 0.11 0.55 0.55 Units MHz ns ns tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK ns ns ns ns tCK Notes 1 1 1 1 1, 2 1, 2 -
Table 52: SDRAM DDR2 Interface AC Timing Table
Clock frequency DQ and DM valid output time before DQS transition DQ and DM valid output time after DQS transition DQ and DM output pulse w idth DQS output high pulse w idth DQS output low pulse w idth DQS falling edge to CLK-CLKn rising edge DQS falling edge from CLK-CLKn rising edge CLK-CLKn rising edge to DQS output rising edge DQS w rite preamble DQS w rite postamble CLK-CLKn high-level w idth CLK-CLKn low -level w idth DQ input setup time relative to DQS in transition DQ input hold time relative to DQS in transition Address and Control valid output time before CLK-CLkn rising edge Address and Control valid output time after CLK-CLKn rising edge Address and control output pulse w idth
Notes: General comment: All timing values w ere measured from vref to vref, unless otherw ise specified. General comment: All input timing values assume minimum slew rate of 1 V/ns (slew rate measured from Vref +/-125 mV). General comment: tCK = 1/fCK. General comment: For all signals, the load is CL = 8 pF. 1. This timing value is defined on CLK / CLKn crossing point. 2. This timing value is defined w hen Address and Control signals are output w ith CLK-CLKn falling edge. For more information, see register settings.
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88F619x Hardware Specifications
10.6.2.2
SDRAM DDR2 Interface Test Circuit
Figure 8: SDRAM DDR2 Interface Test Circuit
VTT Test Point 50 ohm
CL
10.6.2.3
SDRAM DDR2 Interface AC Timing Diagrams
Figure 9: SDRAM DDR2 Interface Write AC Timing Diagram
tDSH CLK CLKn DQS tWPRE DQSn tCH tCL tDSS
tDQSH
tDQSL
tWPST
tDIPW DQ
tDOVB tDOVA
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AC Electrical Specifications
Figure 10: SDRAM DDR2 Interface Address and Control AC Timing Diagram
CLK CLKn
tCH
tCL
ADDRESS/ CONTROL
tIPW
tAOVB
tAOVA
Figure 11: SDRAM DDR2 Interface Read AC Timing Diagram
DQS DQSn
DQ tDSI tDHI
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10.6.3
10.6.3.1
Reduced Gigabit Media Independent Interface (RGMII) AC Timing
RGMII AC Timing Table
Table 53: RGMII 10/100/1000 AC Timing Table at 1.8V
Description Clock frequency Data to Clock output skew Data to Clock input skew Clock cycle duration Duty cycle for Gigabit Duty cycle for 10/100 Megabit Notes: General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified. General comment: tCK = 1/fCK. General comment: If the PHY does not support internal-delay mode, the PC board design requires routing clocks so that an additional trace delay of greater than 1.5 ns and less than 2.0 ns is added to the associated clock signal. For 10/100 Mbps RGMII, the Max value is unspecified. 1. For RGMII at 10 Mbps and 100 Mbps, Tcyc w ill scale to 400 ns +/-40 ns and 40 ns +/-4 ns, respectively. 2. For all signals, the load is CL = 5 pF. Sym bol fCK Tskew T Tskew R Tcyc Duty_G Duty_T Min -0.50 1.00 7.20 0.45 0.40 Max 125.0 0.50 2.60 8.80 0.55 0.60 Units Notes MHz ns ns ns tCK tCK 2 1,2 2 2
Table 54: RGMII 10/100 AC Timing Table at 3.3V
Description Clock frequency Data to Clock output skew Data to Clock input skew Clock cycle duration Duty cycle for Gigabit Duty cycle for 10/100 Megabit Notes: General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified. General comment: tCK = 1/fCK. General comment: If the PHY does not support internal-delay mode, the PC board design requires routing clocks so that an additional trace delay of greater than 1.5 ns is added to the associated clock signal. For 10/100 Mbps RGMII, the Max value is unspecified. 1. For RGMII at 10 Mbps and 100 Mbps, Tcyc w ill scale to 400 ns +/-40 ns and 40 ns +/-4 ns, respectively. 2. For all signals, the load is CL = 5 pF. Sym bol fCK Tskew T Tskew R Tcyc Duty_G Duty_T 1.00 7.20 0.45 0.40 Min 25.0 -0.50 0.50 2.60 8.80 0.55 0.60 Max Units Notes MHz ns ns ns tCK tCK 2 1,2 2 2
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Electrical Specifications
AC Electrical Specifications
10.6.3.2
RGMII Test Circuit
Figure 12: RGMII Test Circuit
Test Point
CL
10.6.3.3
RGMII AC Timing Diagram
Figure 13: RGMII AC Timing Diagram
TX CLOCK (At Transmitter) TX DATA TskewT
RX CLOCK (At Receiver) RX DATA
TskewR
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10.6.4
10.6.4.1
Gigabit Media Independent Interface (GMII) AC Timing
GMII AC Timing Table
125 MHz Description Sym bol tCK tCKrx tHIGH tLOW tR tF tSETUP tHOLD tOVB tOVA Min 7.5 7.5 2.5 2.5 2.0 0.0 2.5 0.5 Max 8.5 1.0 1.0 Units ns ns ns ns ns ns ns ns ns ns Notes 1 1 1, 2 1, 2 1 1
Table 55: GMII AC Timing Table
GTX_CLK cycle time RX_CLK cycle time GTX_CLK and RX_CLK high level w idth GTX_CLK and RX_CLK low level w idth GTX_CLK and RX_CLK rise time GTX_CLK and RX_CLK fall time Data input setup time relative to RX_CLK rising edge Data input hold time relative to RX_CLK rising edge Data output valid before GTX_CLK rising edge Data output valid after GTX_CLK rising edge
Notes: General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified. 1. For all signals, the load is CL = 5 pF. 2. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max).
10.6.4.2
GMII Test Circuit
Figure 14: GMII Test Circuit
Test Point
CL
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AC Electrical Specifications
10.6.4.3
GMII AC Timing Diagrams
Figure 15: GMII Output AC Timing Diagram
tLOW tHIGH
VIH(min) GTX_CLK VIL(max) VIH(min) TXD, TX_EN, TX_ER VIL(max)
tOVB
tOVA
Figure 16: GMII Input AC Timing Diagram
tLOW tHIGH
VIH(min) RX_CLK VIL(max) VIH(min) RXD, RX_EN, RX_ER tSETUP VIL(max)
tHOLD
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10.6.5
10.6.5.1
Media Independent Interface/Marvell Media Independent Interface (MII/MMII) AC Timing
MII/MMII MAC Mode AC Timing Table
Description Sym bol tSU tHD tOV Min 3.5 2.0 0.0 Max 10.0 Units ns ns ns Notes 1
Table 56: MII/MMII MAC Mode AC Timing Table
Data input setup relative to RX_CLK rising edge Data input hold relative to RX_CLK rising edge Data output delay relative to MII_TX_CLK rising edge
Notes: General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified. 1. For all signals, the load is CL = 5 pF.
10.6.5.2
MII/MMII MAC Mode Test Circuit
Figure 17: MII/MMII MAC Mode Test Circuit
Test Point
CL
10.6.5.3
MII/MMII MAC Mode AC Timing Diagrams
Figure 18: MII/MMII MAC Mode Output Delay AC Timing Diagram
Vih(min) MII_TX_CLK Vil(max) Vih(min) TXD, TX_EN, TX_ER
TOV
Vil(max)
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Figure 19: MII/MMII MAC Mode Input AC Timing Diagram
Vih(min) RX_CLK
Vih(min) RXD, RX_EN, RX_ER
tSU tHD
Vil(max)
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10.6.6
10.6.6.1
Serial Management Interface (SMI) AC Timing
SMI Master Mode AC Timing Table
Description Sym bol fCK tDC tSU tHO tOVB tOVA Min Max Units MHz tCK ns ns ns ns Notes 2 1 1
Table 57: SMI Master Mode AC Timing Table
MDC clock frequency MDC clock duty cycle MDIO input setup time relative to MDC rise time MDIO input hold time relative to MDC rise time MDIO output valid before MDC rise time MDIO output valid after MDC rise time
See note 2 0.4 40.0 0.0 15.0 15.0 0.6 -
Notes: General comment: All timing values w ere measured from VIL(max) and VIH(min) levels, unless otherw ise specified. General comment: tCK = 1/fCK. 1. For MDC signal, the load is CL = 390 pF, and for MDIO signal, the load is CL = 470 pF. 2. See "Reference Clocks" table for more details.
10.6.6.2
SMI Master Mode Test Circuit
Figure 20: MDIO Master Mode Test Circuit
VDDIO Test Point 2 kilohm
MDIO CL
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Figure 21: MDC Master Mode Test Circuit
Test Point
MDC CL
10.6.6.3
SMI Master Mode AC Timing Diagrams
Figure 22: SMI Master Mode Output AC Timing Diagram
VIH(min) MDC
VIH(min) MDIO VIL(max)
tOVB tOVA
Figure 23: SMI Master Mode Input AC Timing Diagram
VIH(min) MDC
VIH(min) MDIO VIL(max)
tSU
tHO
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10.6.7
10.6.7.1
JTAG Interface AC Timing
JTAG Interface AC Timing Table
Table 58: JTAG Interface AC Timing Table
30 MHz Description JTClk frequency JTClk minimum pulse w idth JTClk rise/fall slew rate JTRSTn active time TMS, TDI input setup relative to JTClk rising edge TMS, TDI input hold relative to JTClk rising edge JTClk falling edge to TDO output delay Sym bol fCK Tpw Sr/Sf Trst Tsetup Thold Tprop 0.45 0.50 1.0 6.67 13.0 1.0 Min 30.0 0.55 8.33 Max Units MHz tCK V/ns ms ns ns ns Notes 2 1
Notes: General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified. General comment: tCK = 1/fCK. 1. For TDO signal, the load is CL = 10 pF. 2. Defined from VIL to VIH for rise time, and from VIH to VIL for fall time.
10.6.7.2
JTAG Interface Test Circuit
Figure 24: JTAG Interface Test Circuit
Test Point
CL
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10.6.7.3
JTAG Interface AC Timing Diagrams
Figure 25: JTAG Interface Output Delay AC Timing Diagram
Tprop
(max)
VIH VIL
JTCK
TDO
Tprop (min)
Figure 26: JTAG Interface Input AC Timing Diagram
JTCK
TMS,TDI
Tsetup
Thold
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10.6.8
10.6.8.1
Two-Wire Serial Interface (TWSI) AC Timing
TWSI AC Timing Table
Description Sym bol fCK tLOW tHIGH tSU tHD tr tf tOV Min Max Units kHz tCK tCK ns ns ns ns tCK Notes 1 2 2 2, 3 2, 3 2
Table 59: TWSI Master AC Timing Table
SCK clock frequency SCK minimum low level w idth SCK minimum high level w idth SDA input setup time relative to SCK rising edge SDA input hold time relative to SCK falling edge SDA and SCK rise time SDA and SCK fall time SDA output delay relative to SCK falling edge
See note 1 0.47 0.40 250.0 0.0 0.0 1000.0 300.0 0.4
Notes: General comment: All values referred to VIH(min) and VIL(max) levels, unless otherw ise specified. General comment: tCK = 1/fCK. 1. See "Reference Clocks" table for more details. 2. For all signals, the load is CL = 100 pF, and RL value can be 500 ohm to 8 kilohm. 3. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max).
Table 60: TWSI Slave AC Timing Table
100 kHz Description SCK minimum low level w idth SCK minimum high level w idth SDA input setup time relative to SCK rising edge SDA input hold time relative to SCK falling edge SDA and SCK rise time SDA and SCK fall time SDA output delay relative to SCK falling edge Sym bol tLOW tHIGH tSU tHD tr tf tOV Min 4.7 4.0 250.0 0.0 0.0 Max 1000.0 300.0 4.0 Units us us ns ns ns ns us Notes 1 1 1, 2 1, 2 1
Notes: General comment: All values referred to VIH(min) and VIL(max) levels, unless otherw ise specified. 1. For all signals, the load is CL = 100 pF, and RL value can be 500 ohm to 8 kilohm. 2. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max).
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10.6.8.2
TWSI Test Circuit
Figure 27: TWSI Test Circuit
VDDIO Test Point RL
CL
10.6.8.3
TWSI AC Timing Diagrams
Figure 28: TWSI Output Delay AC Timing Diagram
tHIGH tLOW
Vih(min) SCK Vil(max)
Vih(min) SDA
tOV(min)
Vil(max)
tOV(max)
Figure 29: TWSI Input AC Timing Diagram
tLOW tHIGH
Vih(min) SCK Vil(max)
Vih(min) SDA Vil(max)
tSU
tHD
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10.6.9
Sony/Philips Digital Interconnect Format (S/PDIF) AC Timing
The S/PDIF interface is only relevant for the 88F6192. Note
10.6.9.1
S/PDIF AC Timing Table
Description Sym bol Ftxtol Frxtol Txjit Txjitgain Rxjit Min -50.0 -100.0 Max 50.0 100.0 0.05 3.0 10.0 0.25 0.2 Units ppm ppm UI dB UI UI UI Notes 1 1, 2 3 4 5 6
Table 61: S/PDIF AC Timing Table
Output frequency accuracy Input frequency accuracy Output jitter - total peak-to-peak Jitter transfer gain Input jitter - total peak-to-peak
-
Notes: General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified. General comment: For more information, refer to the Digital Audio Interface - Part 3: Consumer Applications, IEC 60958-3:2003(E), Chapter 7.3, January 2003. 1. For all signals, the load is CL = 10 pF. 2. Using inristic jitter filter. 3. Refer to Figure-8 in IEC 60958-3:2003(E), Chapter 7.3, January 2003. 4. Defined for up to 5 Hz. 5. Defined from 200 Hz to 400 kHz. 6. Defined for above 400 kHz.
Note
For additional information about working with a coax connection, see the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide.
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Electrical Specifications
AC Electrical Specifications
10.6.9.2
S/PDIF Test Circuit
Figure 30: S/PDIF Test Circuit
Test Point
CL
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10.6.10
Inter-IC Sound Interface (I2S) AC Timing
The I2S interface is only relevant for the 88F6192. Note
10.6.10.1
Inter-IC Sound (I2S) AC Timing Table
Description Sym bol fCK tCH/tCL tSU tHO tOD Min Max Units MHz tCK tCK ns tCK Notes 2 1 1
Table 62: Inter-IC Sound (I2S) AC Timing Table
I2SBCLK clock frequency I2SBCLK clock high/low level pulse w idth I2SDI input setup time relative to I2SBCLK rise time I2SDI input hold time relative to I2SBCLK rise time I2SDO, I2SLRCLK output delay relative to I2SBCLK rise time
See note 2 0.37 0.10 0.00 0.10 0.70
Notes: General comment: All timing values w ere measured from VIL(max) and VIH(min) levels, unless otherw ise specified. General comment: tCK = 1/fCK. 1. For all signals, the load is CL = 15 pF. 2. See "Reference Clocks" table for more details.
10.6.10.2
Inter-IC Sound (I2S) Test Circuit
Figure 31: Inter-IC Sound (I2S) Test Circuit
Test Point
CL
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10.6.10.3
Inter-IC Sound (I2S) AC Timing Diagrams
Figure 32: Inter-IC Sound (I2S) Output Delay AC Timing Diagram
tCL
tCH
VIH(min) I2SBCLK VIL(max)
VIH(min) I2SDO, I2SLRCLK VIL(max)
tODmin tODmax
Figure 33: Inter-IC Sound (I2S) Input AC Timing Diagram
tCL tCH
VIH(min) I2SBCLK VIL(max)
VIH(min) I2SDI VIL(max)
tSU
tHO
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10.6.11
Time Division Multiplexing (TDM) Interface AC Timing
The TDM interface is only relevant for the 88F6192. Note
10.6.11.1
TDM Interface AC Timing Table
8.192 MHz Description Sym bol 1/tC tDTY tR/tF tD tSU tHD M in 0.256 0.4 0.0 10.0 10.0 Max 8.192 0.6 3.0 20.0 Units MHz tC ns ns ns ns Notes 1, 3 1 1, 2, 8 1, 4, 6 5, 7 5, 7
Table 63: TDM Interface AC Timing Table
PCLK cycle time PCLK duty cycle PCLK rise/fall time DTX and FSYNC valid after PCLK rising edge DRX and FSYNC setup time relative to PCLK falling edge DRX and FSYNC hold time relative to PCLK falling edge
Notes: General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified. 1. For all signals, the load is CL = 20 pF. 2. Rise and Fall times are referenced to the 20% and 80% levels of the w aveform. 3. PCLK can be configured to 0.256, 0.512, 0.768, 1.024, 1.536, 2.048, 4.096, 8.192 MHz frequencies only. 4. This parameter is relevant to FSYNC signal in master-mode only. 5. This parameter is relevant to FSYNC signal in slave-mode only. 6. In negative-mode, the DTX signal is relative to PCLK falling edge. 7. In negative-mode, the DRX signal is relative to PCLK rising edge. 8. This parameter is relevant w hen the PCLK pin is output.
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Electrical Specifications
AC Electrical Specifications
10.6.11.2
TDM Interface Test Circuit
Figure 34: TDM Interface Test Circuit
Test Point
CL
10.6.11.3
TDM Interface Timing Diagrams
Figure 35: TDM Interface Output Delay AC Timing Diagram
tC
PCLK
DTX
tD tD
Figure 36: TDM Interface Input Delay AC Timing Diagram
tC
PCLK
DRX
tSU tHD
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10.6.12
10.6.12.1
Serial Peripheral Interface (SPI) AC Timing
SPI (Master Mode) AC Timing Table
SPI Description Sym bol fCK tCH tCL tSR tDOV tCSB tCSA tSU tHD M in Max Units MHz tCK tCK V/ns ns ns ns tCK ns Notes 3 1 1 1 1 1 1 2 2
Table 64: SPI (Master Mode) AC Timing Table
SCLK clock frequency SCLK high time SCLK low time SCLK slew rate Data out valid relative to SCLK falling edge CS active before SCLK rising edge CS not active after SCLK rising edge Data in setup time relative to SCLK rising edge Data in hold time relative to SCLK rising edge
See Note 3 0.46 0.46 0.5 -2.5 8.0 8.0 0.2 5.0 2.5 -
Notes: General comment: All values w ere measured from 0.3*vddio to 0.7*vddio, unless otherw ise specified. General comment: tCK = 1/fCK. 1. For all signals, the load is CL = 10 pF. 2. Defined from vddio/2 to vddio/2. 3. See "Reference Clocks" table for more details.
10.6.12.2
SPI (Master Mode) Test Circuit
Figure 37: SPI (Master Mode) Test Circuit
Test Point
CL
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AC Electrical Specifications
10.6.12.3
SPI (Master Mode) Timing Diagrams
Figure 38: SPI (Master Mode) Output AC Timing Diagram
tCH SCLK
tCL
Data Out tDOVmin tDOVmax CS
tCSB
tCSA
Figure 39: SPI (Master Mode) Input AC Timing Diagram
SCLK
Data in
tSU
tHD
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10.6.13
10.6.13.1
Secure Digital Input/Output (SDIO) Interface AC Timing
Secure Digital Input/Output (SDIO) AC Timing Table
Description Symbol fCK tWL/tWH tTLH/tTHL tDOVB tDOVA tISU tIHD Min 0 0.35 6.5 2.5 7.0 0.0 Max 50 3.0 Units MHz tCK ns ns ns ns ns Notes 1, 3 1, 3 2, 3 2, 3 2 2
Table 65: SDIO Host in High Speed Mode AC Timing Table
Clock frequency in Data Transfer Mode Clock high/low level pulse w idth Clock rise/fall time CMD, DAT output valid before CLK rising edge CMD, DAT output valid after CLK rising edge CMD, DAT input setup relative to CLK rising edge CMD, DAT input hold relative to CLK rising edge
Notes: General comment: tCK = 1/fCK. 1. Defined on VIL(max) and VIH(min) levels. 2. Defined on VDDIO/2 for Clock signal, and VIL(max) / VIH(min) for CMD & DAT signals. 3. For all signals, the load is CL = 10 pF.
10.6.13.2
Secure Digital Input/Output (SDIO) Test Circuit
Figure 40: Secure Digital Input/Output (SDIO) Test Circuit
VDDIO Test Point 50 KOhm
CL
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10.6.13.3
Secure Digital Input/Output (SDIO) AC Timing Diagrams
Figure 41: SDIO Host in High Speed Mode Output AC Timing Diagram
tWL
tWH
VIH(min) CLK VDDIO/2 VIL(max) VIH(min) D AT, CMD VIL(max)
tDOVB tDOVA
Figure 42: SDIO Host in High Speed Mode Input AC Timing Diagram
tWL
tWH
VIH(min) CLK VDDIO/2 VIL(max) VIH(min) DAT, CMD VIL(max)
tISU tIHD
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10.6.14
Transport Stream (TS) Interface AC Timing
The TS interface is only relevant for the 88F6192. Note
10.6.14.1
Description Clock frequency
Transport Stream Interface AC Timing Table
Sym bol fCK tLOW tHIGH tOV Min Max Units MHz tCK tCK tCK Notes 1 2 2 2, 3
Table 66: Transport Stream Output Interface AC Timing Table
See note 1 0.4 0.4 0.4 0.6 0.6 0.6
Clock minimum low level w idth Clock minimum high level w idth Data output valid after Clock rising edge
Notes: General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified. General comment: tCK = 1/fCK. 1. See "Reference Clocks" table for more details. 2. For all signals, the load is CL = 5 pF. 3. When configured to falling edge, the tOV parameter is relative to Clock falling edge.
Table 67: Transport Stream Input Interface AC Timing Table
Description Clock frequency Clock minimum low level w idth Clock minimum high level w idth Data input setup time relative to Clock rising edge Data input setup time relative to Clock rising edge Sym bol fCK tLOW tHIGH tSU tHD Min Max Units MHz tCK tCK tCK tCK Notes 1 2 2
See note 1 0.35 0.35 0.30 0.30 0.65 0.65 -
Notes: General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified. General comment: tCK = 1/fCK. 1. See "Reference Clocks" table for more details. 2. When configured to falling edge, the tSU/tHD parameters are relative to Clock falling edge.
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10.6.14.2
Transport Stream Interface Test Circuit
Figure 43: Transport Stream Interface Test Circuit
Test Point
CL
10.6.14.3
Transport Stream Interface Timing Diagrams
Figure 44: Transport Stream Output Interface AC Timing Diagram
tHIGH
tLOW
Vih(min) Clock Vil(max)
Vih(min) Data Out
tOV(min) tOV(max)
Vil(max)
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Figure 45: Transport Stream Input Interface AC Timing Diagram
tLOW
tHIGH
V ih(min) Clock Vil(max)
Vih(min) Data In Vil(max)
tSU
tHD
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Differential Interface Electrical Characteristics
10.7
Differential Interface Electrical Characteristics
This section provides the reference clock, AC, and DC characteristics for the following differential interfaces: PCI Express Interface Electrical Characteristics SATA Interface Electrical Characteristics USB Electrical Characteristics
10.7.1
10.7.1.1
Differential Interface Reference Clock Characteristics
PCI Express Interface Differential Reference Clock Characteristics
Description Sym bol fCK DCrefclk SRrefclk VIHrefclk VILrefclk Vcross Vcrs_dlta Tperavg Tperabs Tccjit 0.4 0.6 150.0 250.0 -300.0 9.8 Min 100.0 0.6 4.0 -150.0 550.0 140.0 2800.0 10.2 150.0 Max Units MHz tCK V/nS mV mV mV mV ppm nS pS Notes 3 1 1 2 -
Table 68: PCI Express Interface Differential Reference Clock Characteristics
Clock frequency Clock duty cycle Differential rising/falling slew rate Differential high voltage Differential low voltage Absolute crossing point voltage Variation of Vcross over all rising clock edges Average differential clock period accuracy Absolute differential clock period Differential clock cycle-to-cycle jitter Notes:
General Comment: The reference clock timings are based on 100 ohm test circuit. General Comment: Refer to the PCI Express Card Electromechanical Specification, Revision 1.1, March 2005, section 2.1.3 for more information. 1. Defined on a single-ended signal. 2. Including jitter and spread spectrum. 3. Defined from -150 mV to +150 mV on the differential w aveform.
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PCI Express Interface Spread Spectrum Requirements
Table 69: PCI Express Interface Spread Spectrum Requirements
Sym bol Fmod Fspread Min 0.0 -0.5 Max 33.0 0.0 Units kHz % Notes 1 1
Notes: 1. Defined on linear sw eep or “Hershey’s Kiss” (US Patent 5,631,920) modulations.
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Differential Interface Electrical Characteristics
10.7.2
10.7.2.1
PCI Express Interface Electrical Characteristics
PCI Express Interface Driver and Receiver Characteristics
Description Sym bol BR UI Bppm
Driver parameters
Table 70: PCI Express Interface Driver and Receiver Characteristics
Min 2.5 400.0 -300.0 300.0 Max Units Gbps ps ppm Notes 2
Baud rate Unit interval Baud rate tolerance
Differential peak to peak output voltage Minimum TX eye w idth Differential return loss Common mode return loss DC differential TX impedance
VTXpp TTXeye TRLdiff TRLcm ZTXdiff
Receiver parameters
0.8 0.75 10.0 6.0 80.0
1.2 120.0
V UI dB dB Ohm
1 1 -
Differential input peak to peak voltage Minimum receiver eye w idth Differential return loss Common mode return loss DC differential RX impedance DC common input impedance Notes:
VRXpp TRXeye RRLdiff RRLcm ZRXdiff ZRXcm
0.175 0.4 10.0 6.0 80.0 40.0
1.2 120.0 60.0
V UI dB dB Ohm Ohm
1 1 -
General Comment: For more information, refer to the PCI Express Base Specification, Revision 1.1, March, 2005. 1. Defined from 50 MHz to 1.25 GHz. 2. Does not account for SSC dictated variations.
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10.7.2.2
PCI Express Interface Test Circuit
Figure 46: PCI Express Interface Test Circuit
Test Points + C_TX D+
D-
C_TX
50 ohm
50 ohm
When measuring Transmitter output parameters, C_TX is an optional portion of the Test/Measurement load. When used, the value of C_TX must be in the range of 75 nF to 200 nF. C_TX must not be used when the Test/Measurement load is placed in the Receiver package reference plane.
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10.7.3
SATA Interface Electrical Characteristics
The driver and receiver characteristics for the SATA-I Interface Gen1i Mode and the SATA-II Interface Gen2i Mode are provided in the following sections.
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10.7.3.1
SATA-I Interface Gen1i Mode Driver and Receiver Characteristics
Description Sym bol BR Bppm Fssc SSCtol UI Driver Parameters Zdifftx Zsetx RLOD RLOD RLOD RLOD RLOD Vdifftx TJ5 DJ5 TJ250 DJ250 Zdiffrx Zsetx RLID RLID RLID RLID RLID RLID Vdiffrx TJ5 DJ5 TJ250 DJ250 Receiver Parameters -350.0 30.0 -5000.0 666.67 85.0 40.0 14.0 8.0 6.0 3.0 1.0 400.0 85.0 40.0 18.0 14.0 10.0 8.0 3.0 1.0 325.0 115.0 600.0 0.355 0.175 0.470 0.220 115.0 600.0 0.430 0.250 0.600 0.350 Min 1.5 350.0 33.0 0.0 Max Units Gbps ppm kHz ppm ps Ohm Ohm dB dB dB dB dB mV UI UI UI UI Ohm Ohm dB dB dB dB dB dB mV UI UI UI UI Notes 2 1 1 1 1 -
Table 71: SATA-I Interface Gen1i Mode Driver and Receiver Characteristics
Baud Rate Baud rate tolerance Spread spectrum modulation frequency Spread spectrum modulation Deviation Unit Interval Differential impedance Single ended impedance Differential return loss (75 MHz-150 MHz) Differential return loss (150 MHz-300 MHz) Differential return loss (300 MHz-1.2 GHz) Differential return loss (1.2 GHz-2.4 GHz) Differential return loss (2.4 GHz-3.0 GHz) Output differential voltage Total jitter at connector data-data, 5UI Deterministic jitter at connector data-data, 5UI Total jitter at connector data-data, 250UI Deterministic jitter at connector data-data, 250UI Differential impedance Single ended impedance Differential return loss (75 MHz-150 MHz) Differential return loss (150 MHz-300 MHz) Differential return loss (300 MHz-600 MHz) Differential return loss (600 MHz-1.2 GHz) Differential return loss (1.2 GHz-2.4 GHz) Differential return loss (2.4 GHz-3.0 GHz) Input differential voltage Total jitter at connector data-data, 5UI Deterministic jitter at connector data-data, 5UI Total jitter at connector data-data, 250UI Deterministic jitter at connector data-data, 250UI
Notes: General Comment: For more information, refer to SATA II Revision 2.6 Specification, February, 2007. General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified. General Comment: To comply w ith the values presented in this table, refer to your local Marvell representative for register settings. 1. Total jitter is defined as TJ = (14 * RJσ) + DJ w here Rjσ is random jitter. 2. Output Differential Amplitude and Pre-Emphasis are configurabile. See functional register description for more details.
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10.7.3.2
SATA-II Interface Gen2i Mode Driver and Receiver Characteristics
Description Sym bol BR Bppm Fssc SSCtol UI Driver Parameters Vdifftx RLOD RLOD RLOD RLOD RLOD TJ10 DJ10 TJ500 DJ500 Receiver Parameters Vdiffrx RLID RLID RLID RLID RLID RLID TJ10 DJ10 TJ500 DJ500 -350.0 30.0 -5000.0 333.33 400.0 14.0 8.0 6.0 3.0 1.0 275.0 18.0 14.0 10.0 8.0 3.0 1.0 700.0 0.30 0.17 0.37 0.19 750.0 0.46 0.35 0.60 0.42 Min 3.0 350.0 33.0 0.0 Max Units Gbps ppm kHz ppm ps mV dB dB dB dB dB UI UI UI UI mV dB dB dB dB dB dB UI UI UI UI Notes 1,2 3 3 4 4 5 3 3 4 4
Table 72: SATA-II Interface Gen2i Mode Driver and Receiver Characteristics
Baud Rate Baud rate tolerance Spread spectrum modulation frequency Spread spectrum modulation Deviation Unit Interval Output differential voltage Differential return loss (150 MHz-300 MHz) Differential return loss (300 MHz-600 MHz) Differential return loss (600 MHz-2.4 GHz) Differential return loss (2.4 GHz-3.0 GHz) Differential return loss (3.0 GHz-5.0 GHz) Total jitter at connector clock-data Deterministic jitter at connector clock-data Total jitter at connector clock-data Deterministic jitter at connector clock-data Input differential voltage Differential return loss (150 MHz-300 MHz) Differential return loss (300 MHz-600 MHz) Differential return loss (600 MHz-1.2 GHz) Differential return loss (1.2 GHz-2.4 GHz) Differential return loss (2.4 GHz-3.0 GHz) Differential return loss (3.0 GHz-5.0 GHz) Total jitter at connector clock-data Deterministic jitter at connector clock-data Total jitter at connector clock-data Deterministic jitter at connector clock-data
Notes: General Comment: For more information, refer to SATA II Revision 2.6 Specification, February, 2007. General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified. General Comment: To comply w ith the values presented in this table, refer to your local Marvell representative for register settings. 1. 0.45-0.55 UI is the range w here the signal meets the minimum level. 2. Output Differential Amplitude and Pre-Emphasis are configurabile. See functional register description for more details. 3. Defined for BR/10. 4. Defined for BR/500. 5. 0.5 UI is the point w here the signal meets the minimum level.
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10.7.4
10.7.4.1
USB Electrical Characteristics USB Driver and Receiver Characteristics
Low Speed Description
Table 73: USB Low Speed Driver and Receiver Characteristics
Sym bol BR Bppm Driver Parameters VOH VOL VCRS TLR TLF TLRFM TUDJ1 TUDJ2 Receiver Parameters VIH VIL VDI Max 1.5 -15000.0 15000.0 2.8 0.0 1.3 75.0 75.0 80.0 -95.0 -150.0 2.0 0.2 3.6 0.3 2.0 300.0 300.0 125.0 95.0 150.0 0.8 Min Units Mbps ppm V V V ns ns % ns ns V V V Notes 1 2 3 3, 4 3, 4 5 5 -
Baud Rate Baud rate tolerance Ouput single ended high Ouput single ended low Output signal crossover voltage Data fall time Data rise time Rise and fall time matching Source jitter total: to next transition Source jitter total: for paired transitions Input single ended high Input single ended low Differential input sensitivity
Notes: General Comment: For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000. General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified. General Comment: To comply w ith the values presented in this table, refer to your local Marvell representative for register settings. 1. Defined w ith 1.425 kilohm pull-up resistor to 3.6V. 2. Defined w ith 14.25 kilohm pull-dow n resistor to ground. 3. See "Data Signal Rise and Fall Time" w aveform. 4. Defined from 10% to 90% for rise time and 90% to 10% for fall time. 5. Including frequency tolerance. Timing difference betw een the differential data signals. Defined at crossover point of differential data signals.
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Table 74: USB Full Speed Driver and Receiver Characteristics
Full Speed Sym bol BR Bppm Driver Parameters Ouput single ended high VOH Ouput single ended low VOL Output signal crossover voltage VCRS Output rise time TFR Output fall time TFL Source jitter total: to next transition TDJ1 Source jitter total: for paired transitions TDJ2 Source jitter for differential transition to SE0 transition TFDEOP Receiver Parameters Input single ended high VIH Input single ended low VIL Differential input sensitivity VDI Receiver jitter : to next transition tJR1 Receiver jitter: for paired transitions tJR2 Baud Rate Baud rate tolerance Description Max 12.0 -2500.0 2500.0 2.8 0.0 1.3 4.0 4.0 -3.5 -4.0 -2.0 2.0 0.2 -18.5 -9.0 3.6 0.3 2.0 20.0 20.0 3.5 4.0 5.0 0.8 18.5 9.0 Min Units Mbps ppm V V V ns ns ns ns ns V V V ns ns Notes 1 2 4 3, 4 3, 4 5, 6 5, 6 6 6 6
Notes: General Comment: For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000. General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified. General Comment: To comply w ith the values presented in this table, refer to your local Marvell representative for register settings. 1.. Defined w ith 1.425 kilohm pull-up resistor to 3.6V. 2.. Defined w ith 14.25 kilohm pull-dow n resistor to ground. 3. Defined from 10% to 90% for rise time and 90% to 10% for fall time. 4. See "Data Signal Rise and Fall Time" w aveform. 5. Including frequency tolerance. Timing difference betw een the differential data signals. 6. Defined at crossover point of differential data signals.
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88F619x Hardware Specifications
Table 75: USB High Speed Driver and Receiver Characteristics
High Speed Description Baud Rate Baud rate tolerance Data signaling high Data signaling low Data rise time Data fall time Data source jitter Differential input signaling levels Data signaling common mode voltage range Receiver jitter tolerance Sym bol BR Bppm Driver Parameters VHSOH VHSOL THSR THSF Receiver Parameters VHSCM See note 3 -50.0 500.0 See note 3 mV 3 3 Max 480.0 -500.0 500.0 360.0 440.0 -10.0 10.0 500.0 500.0 See note 2 M in Units Mbps ppm mV mV ps ps Notes 1 1 2
Notes: General Comment: For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000. General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified. General Comment: To comply w ith the values presented in this table, refer to your local Marvell representative for register settings. 1. Defined from 10% to 90% for rise time and 90% to 10% for fall time. 2. Source jitter specified by the "TX eye diagram pattern template" figure. 3. Receiver jitter specified by the "RX eye diagram pattern template" figure.
10.7.4.2
USB Interface Driver Waveforms
Figure 47: Low/Full Speed Data Signal Rise and Fall Time
Rise Time 90% VCRS 10% 10% 90% Fall Time
Differential Data Lines
TR
TF
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Electrical Specifications
Differential Interface Electrical Characteristics
Figure 48: High Speed TX Eye Diagram Pattern Template
+525mV +475mV + 400mV Differential +300mV
0 Volts Differential
-300mV - 400mV Differential -475mV -525mV 7.5% 0% 37.5% 62.5% 92.5% 100%
Figure 49: High Speed RX Eye Diagram Pattern Template
+525mV +475mV +400mV Differential
+175mV
0 Volts Differential
-175mV
- 400mV Differential -475mV -525mV 12.5% 0% 35 65 87.5% 100%
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88F619x Hardware Specifications
11
Thermal Data (Preliminary)
Table 76 provides the package thermal data for the device. This data is derived from simulations that were run according to the JEDEC standard.
The thermal parameters are preliminary and subject to change. Note
TET
The documents listed below provide a basic understanding of thermal management of integrated circuits (ICs) and guidelines to ensure optimal operating conditions for Marvell products. Before designing a system it is recommended to refer to these documents: Application Note, AN-63 Thermal Management for Selected Marvell® Products, Document Number MV-S300281-00 White Paper, ThetaJC, ThetaJA, and Temperature Calculations, Document Number MV-S700019-00.
Table 76: Thermal Data for the 88F619x in the QFP 216-pin Package (Preliminary)
Sy m b o l θJA ΨJT θJC ΨJB D e fin i ti on Ai rf lo w Va lu e ( C / W ) 0[m/s] Thermal resistance: junction to ambient. Thermal characterization parameter: junction to case center. Thermal resistance: junction to case (not air-flow dependent) Thermal characterization parameter: junction to the bottom of the package. Thermal resistance: junction to the bottom of the package (not air-flow dependent) 11.84 24.2 1.04 1 [ m /s ] 21.7 1.16 9.7 11.95 16.1 11.93 2 [ m /s ] 20.7 1.26
θJB
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Package
12
Package
This section provides the 88F619x package drawing and dimensions.
Figure 50: LQFP 216-pin Package and Dimensions
1. 2.
3.
4. 5.
To be determined at seating plane —C—. Dimensions D1 and E1 do not include mold protrusions. D1 and E1 are maximum plastic body size dimensions including mold mismatch. Dimension b does not include Dambar protrusions. Dambar can not be located on the lower radius or the foot. Exact shape of each corner is optional. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
6. 7. 8. 9.
A1 is defined as the distance from the seating plane to the lowest point of the package body. Controlling dimension: millimeter. Reference document: JEDEC MS-026 Special characteristics C class: ccc
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88F619x Hardware Specifications
Table 77: LQFP 216-pin Package Dimensions
Symbol M in A A1 A2 b b1 c c1 D D1 E E1 |e| L L1 R1 R2 S 0.08 0.08 0.20 0o 0
o o o
D i m e ns i on in m m N om i n a l — — 1.40 0.18 0.16 0.14 0.12 26.00 24.00 26.00 24.00 0.40 BSC 0.60 1.00 REF — — — 3.5o — 12 12
o o
Max 1.60 0.15 1.45 0.23 0.19 0.20 0.16 26.15 24.10 26.15 24.10 0.75 — — — 7o — 13 13
o o
Min — 0.002 0.053 0.005 0.005 0.004 0.004 1.018 0.941 1.018 0.941 0.018 0.003 0.003 0.008 0o 0 0 0
o o o
D im en s i on in i n c he s Nominal M ax — — 0.055 0.007 0.006 0.006 0.005 1.024 0.945 1.024 0.945 0.016 BSC 0.24 0.039 REF — — — 3.5o — 12 12
o o
— 0.05 1.35 0.13 0.13 0.09 0.09 25.85 23.90 25.85 23.90 0.45
0.063 0.006 0.057 0.009 0.007 0.008 0.006 1.030 0.949 1.030 0.949 0.030 — — — 7o — 13o 13o
θ θ1 θ2 θ3
ccc
11 11
0.08
0.003
Table 78:
S y m b ol
LQFP 216-pin Package Exposed Pad (ePAD) Size
E x p os e d Pa d S i z e mm In c h e s 0.225 REF 0.225 REF
D2 E2
5.715 REF 5.715 REF
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Part Order Numbering/Package Marking
Part Order Numbering
13
13.1
Part Order Numbering/Package Marking
Part Order Numbering
Figure 51 shows the part order numbering scheme for the 88F6190 and 88F6192. Refer to Marvell Field Application Engineers (FAEs) or representatives for further information when ordering parts.
Figure 51: Sample Part Number
88F619x–xx–LGO2Cxxx–xxxx
Custom code (optional)
Part number 88F6190 88F6192
Speed code 060 = 600 MHz (88F6190) 080 = 800 MHz (88F6192) Temperature code C = Commercial I = Industrial
Die revision Environmental code 2 = Green (RoHS 6/6 and Halogen-free)
Custom code
Package code LGO = 216-pin LQFP
r
Table 79: Part Order Options
P a c k a g e Ty p e 216-pin LQFP 216-pin LQFP P a r t O rd e r N u m b e r 88F6190-xx-LGO2C060 (Green, RoHS 6/6 and Halogen-free package), 600 MHz 88F6192-xx-LGO2C080 (Green, RoHS 6/6 and Halogen-free package), 800 MHz
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88F619x Hardware Specifications
13.2
Package Marking
Figure 52 shows a sample Commercial package marking and pin 1 location for the device.
Figure 52: Package Marking and Pin 1 Location
Marvell logo
Country of origin
(Contained in the mold ID or marked as the last line on the package.)
88F6-LGOe Lot Number YYWW xx@ Country of Origin 88F6190-xx XXXX
Part number prefix, package code, environmental code
88F6 = Part number prefix LGO = Package code e = Environmental code: 2 = Green
Part number and die revision code
88F6190 = Part number XX = Die revision
Date code, custom code, assembly plant code
YYWW = Date code (YY = year, WW = Work Week) xx = Custom code @ = Assembly plant code
Pin 1 location
Temperature and speed code
C060 = Commercial, 600 MHz
88F6-LGOe Lot Number YYWW xx@ Country of Origin 88F6192-xx XXXX
Part number and die revision code
88F6192 = Part number XX = Die revision
Temperature and speed code
C080 = Commercial, 800 MHz
Note: The above drawings are not drawn to scale. Location of markings is approximate.
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Revision History
A
Table 80:
R e v i s io n F
Revision History
Revision History
D a te December 2, 2008 C o m m e n ts Revision
1. For the 88F6190, added a Fast Ethernet port, in addition for the Gigabit Ethernet port. 2. In Figure 2, 88F6192 Pin Logic Diagram, on page 22: • Changed the GE_TXCLKOUT pin to input/output and added a note under the figure, stating that the pin is an input when used the MII/MMII Transmit Clock. • Changed the name of pins GE_TXEN to GE_TXCTL and GE_RXDV to GE_RXCTL. • Deleted the VDD_GE pin and replaced it with pins VDD_GE_A and VDD_GE_B. Also changed the VDD_GE pin to VDD_GE_A/VDD_GE_B throughout the document. 3. In Table 4, Power Pin Assignments, on page 25, changed the name of the VDD_GE pin to VDD_GE_A and VDD_GE_B and added new descriptions for those pins. 4. In Table 7, PCI Express Interface Pin Assignments, on page 30, revised the description of the PEX_CLK_P/N pins to state that they can be configured as input or output according to the reset strap. 5. • • • In Table 9, 88F6190 Gigabit Ethernet Interface Pin Assignments, on page 32: Revised most of the pin descriptions. Revised the I/O designations for GE_TXCLKOUT and MPP[29]/GE1[9]. Changed the name of GE_TXEN to GE_TXCTL and GE_RXDV to GE_RXCTL.
6. In Table 10, 88F6192 Gigabit Ethernet Port0/1 Interface Pin Assignments, on page 34, indicated that: • When the GE_TXCLKOUT pin is used as an MII/MMII Transmit Clock, it is an input pin. • When the MPP[29]/GE1[9] pin is used as a GMII Transmit Clock, it is a Tri-State output pin. 7. In Table 14, RTC Interface Pin Assignments, on page 42, changed the type for RTC_XOUT to analog. 8. In the description of signal AU_SPDFRMCLK in Table 19, Audio (S/PDIF / I2S) Interface Signal Assignment, on page 47, added a reference to the new AU_SPDFRMCLK information in the Reference Clock AC Timing Specifications table. 9. In Table 26, Unused Interface Strapping, on page 56, revise the description for configuring the: • MPP signals. • PCI Express clock signals. 10. In Table 37, I/O and Core Voltages, on page 73, for the 88F6190, revise the I/O Voltage column to remove pin VDD_GE and replace it with pins VDD_GE_A and VDD_GE_B. 11. In Figure 3, 88F6190 Pin Map Top View, on page 57 and Table 27, 88F6190 Pinout Sorted by Pin Number, on page 58: • Changed pins 18 and 25 from VDD_GE to VDD_GE_A. • Changed pin 23 from GE_TXEN to GE_TXCTL and changed pin 27 from GE_RXDV to GE_RXCTL. • Changed pins 40 and 47 from VDD_GE to VDD_GE_B. 12. In Table 32, 88F6190 Ethernet Ports Pins Multiplexing, on page 68, revised the RGMII column. 13. Revised the configurations options described in Section 6.2, Gigabit Ethernet (GbE) Pins Multiplexing on MPP, on page 68 and added a note stating that all relevant Gigabit Ethernet signals must be implemented. 14. In Table 36, Supported Clock Combinations, on page 72, added a column showing the device number. 15. In Section 8.5, Pins Sample Configuration, on page 76, revised the note describing the pins with multiple voltage options. 16. In Table 38, Reset Configuration, on page 77, revised the rows relating to the following signals: MPP[2], MPP[3], MPP[5], MPP[10], MPP[12], MPP[19], MPP[33], NF_ALE, NF_REn, NF_CLE, NF_WEn.
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Table 80:
R e v i s io n
Revision History (Continued)
D a te C o m m e n ts
17. In Table 42, Recommended Operating Conditions, on page 87: • For the 88F6190, revised the VDD_GE pin to VDD_GE_A and added a separate row for VDD_GE_B. • For parameter RTC_AVDD Analog supply for RTC in Battery Back-up mode, revised the values for the minimum to 1.3V from 1.4V and for the maximum to 1.7V from 1.6V. 18. In Table 43, Thermal Power Dissipation, on page 89, for the eFuse during Burning mode parameter added a note: The eFuse burn is done once, and there should be no thermal effect, after it has been burned. 19. Revised the introduction to Section 10.5.2, RGMII, SMI and REF_CLK_XIN 1.8V (CMOS) DC Electrical Specifications, on page 93. 20. • • • • In Table 51, Reference Clock AC Timing Specifications, on page 97: Revised the names of the Ethernet transmit symbols to FGE_TXCLK_OUT, DCGE_TXCLK_OUT, and SRGE_TXCLK_OUT. Added the S/PDIF Recovered Master Clock. Added the Transport Stream External Reference Clock. For the PTP Reference Clock, revised the values for the Frequency, Duty Cycle, and Pk-Pk jitter parameters.
21. Revised the description of the power rails in the paragraph before Table 45, General 3.3V Interface (CMOS) DC Electrical Specifications, on page 92. 22. Revised the description of the power rails in the paragraph before Table 46, RGMII 1.8V Interface (CMOS) DC Electrical Specifications, on page 93. E October 5, 2008 Revision 1. In Table 38, Reset Configuration, on page 77, for CPU_CLK Frequency Select, revised the description of values 0x4 and 0x6. 2. In Table 7, PCI Express Interface Pin Assignments, on page 30, revised the note in the description of the PEX_CLK_P/N pins. 3. In Table 26, Unused Interface Strapping, on page 56, added the eFuse strapping. 4. In Section 8.1.1, Power-Up Sequence Requirements, on page 73 and Section 8.1.2, Power-Down Sequence Requirements, on page 74, added a power up/down requirements for when VHV is in eFuse Burning mode. 5. In Table 42, Recommended Operating Conditions, on page 87: • For VHV, revised the two parameters to VHV (during eFuse Burning mode) and VHV (during eFuse Reading mode) and added notes in the comments column for both VHV voltages. • For VDD_M, PEX_AVDD, and USB_AVDD, revised the comments column. • for RTC_AVDD, revised the values for minimum to 1.4V from 1.3V and for maximum to 1.6V from 1.7V. 6. In Table 43, Thermal Power Dissipation, on page 89, revised the row for the SDRAM and added a row for the eFuse. 7. In Table 44, Current Consumption, on page 91, revised the row for the SDRAM and added a row for the eFuse. 8. In Table 51, Reference Clock AC Timing Specifications, on page 97: • For the CPU and Core Reference Clock frequency, revised the values. • For the PTP Reference Clock, added the Slew rate and Pk-Pk jitter parameters. D 2. • • • August 18, 2008 Revision 1. Added the XOR engine to the block diagrams in the Product Overview on page 3. In Table 4, Power Pin Assignments, on page 25: Changed the voltage for XTAL_AVDD from 2.5V to 1.8V. Changed the voltage for SATA_AVDD (88F6190) and SATA0_AVDD/SATA1_AVDD (88F6192) from 2.5V to 3.3V. Added pin VHV.
3. In Figure 1, 88F6190 Pin Logic Diagram, on page 21, Figure 2, 88F6192 Pin Logic Diagram, on page 22, and Table 7, PCI Express Interface Pin Assignments, on page 30, changed PEX_CLK_P/N for input to input/output (I/O). Also added VHV to both pin logic diagrams. 4. In Table 6, DDR SDRAM Interface Pin Assignments, on page 28, revised the description of M_NCASL and M_PCAL to indicate the range of the resistor. 5. Added present and active pins to Table 8, SATA Port Interface Pin Assignment, on page 31.
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Revision History
Table 80:
R e v i s io n
Revision History (Continued)
D a te C o m m e n ts
6. In Section 2.2.6, Gigabit Ethernet Port Interface Pin Assignments, on page 32, added a note: For the TXCLK, use the GE_RXCLK pin. Also indicated which pins are for port0 and which for port1. 7. Revised Table 21, Secure Digital Input/Output (SDIO) Interface Signal Assignment, on page 49 to indicate the pins requiring pull up. 8. Added Table 23, Transport Stream (TS) Interface Signal Assignment, on page 52. 9. Added Section 2.2.20, Precise Timing Protocol (PTP) Interface, on page 54. 10. In Table 25, Internal Pull-up and Pull-down Pins, on page 55, changed pins GE_MDC, MPP[7] and MPP[18] from pull down to pull up and removed MPP[13], MPP[15], and MPP[17] from the table, since they do not require a pull up/down. 11. In Table 3, Unused Interface Strapping, on page 56, revised the description of the strapping for the SATA_AVDD pin in the 88F6190 and the SATA0_AVDD/SATA1_AVDD pins in the 88F6192. 12. • • • In Section 6.1, Multi-Purpose Pins Functional Summary, on page 61: Changed the MPP[6] row in the table to remove the 0x0 option. Revised the description of SYSRST_OUTn. Added a bullet: Pin MPP[6] wakes up after reset in 0x1 mode (SYSRST_OUTn)
13. In Section 6.3, TSMP (TS Multiplexing Pins) on MPP, on page 70, added to the description of the TSMP pins. 14. In Table 35, 88F619x Clocks, on page 71, added the PTP clock and changed references to the Core clock to be the TCLK. 15. Revised Section 7.1, Spread Spectrum Clock Generator (SSCG), on page 72. 16. Revised Table 37, I/O and Core Voltages, on page 73. 17. In Section 8.2, Hardware Reset, on page 74, added SYSRST_OUTn to the list of pins that are still active during SYSRSTn assertion. 18. Revised Section 8.2.1, Reset Out Signal, on page 75 and Section 8.2.3, SYSRSTn Duration Counter, on page 75 and added Section 8.2.2, Power On Reset (POR), on page 75. 19. In Section 8.3.2, PCI Express Endpoint Reset, on page 76 revised the bulleted items. 20. Revised Section 8.5, Pins Sample Configuration, on page 76. 21. Made major revisions to Table 38, Reset Configuration, on page 77. 22. Revised the first two paragraphs in Section 8.6, Serial ROM Initialization, on page 80. 23. In Section 8.7, Boot Sequence, on page 81 revised the paragraph following step 4. 24. Revised Table 35, 88F619x Clocks, on page 71 and Table 36, Supported Clock Combinations, on page 72. 25. In Table 40, IDCODE Register Map, on page 84, revised the description of bits [31:28]. 26. 27. • • • • 28. In Table 41, Absolute Maximum Ratings, on page 85, revised the voltage for the SATA and XTAL AVDD pins. In the Table 42, Recommended Operating Conditions, on page 87: Revised the voltage for the SATA and XTAL AVDD pins Added values for VDD_CPU and for the 3.3V interfaces Revised the minimum value to 3.15V and the maximum value to 3.45V (+/-5%) Revised the values for PEX_AVDD to minimum 1.7V, typical 1.8V, and maximum 1.9V. In Section 10.3, Thermal Power Dissipation, on page 89, revised values for Core, PCI Express, USB, and SATA parameters and revised the notes under the table. 29. In Section 10.4, Current Consumption, on page 91, revised values for the Core (including CPU), PCI Express, USB, and SATA parameters and revised the notes under the table. 30. In Section 10.5.1, General 3.3V (CMOS) DC Electrical Specifications, on page 92, added reference to PTP and RGMII. 31. Deleted Section 8.5.2 REF_CLK_XIN 2.5V (CMOS) DC Electrical Specifications and added pin REF_CLK_XIN to Section 10.5.2, RGMII, SMI and REF_CLK_XIN 1.8V (CMOS) DC Electrical Specifications, on page 93, since the power rail for the REF_CLK_XIN pin was changed from 2.5V to 1.8V. 32. Revised Table 51, Reference Clock AC Timing Specifications, on page 97.
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Table 80:
R e v i s io n
Revision History (Continued)
D a te C o m m e n ts
33. Revised Table 68, PCI Express Interface Differential Reference Clock Characteristics, on page 127 and Table 69, PCI Express Interface Spread Spectrum Requirements, on page 128. 34. Revised Figure 28, TWSI Output Delay AC Timing Diagram, on page 113 so that it shows SDA tOV relative to the SCK falling edge, as shown in the two tables that proceed the figure. 35. Revised all of Section 13, Part Order Numbering/Package Marking, on page 141. C June 16, 2008 Revision 1. Added information for the 88F6190 device throughout this specification. This includes the addition of two new sections: Section 1, Overview, on page 18 and Section 4, 88F6190 Pinout, on page 57. 2. Added AN-249: Configuring the Marvell® SATA PHY to Transmit Predefined Test Patterns to the list of Related Documentation on page 16. 3. In Table 4, Power Pin Assignments, on page 25, revised the description of VDD_GE_A and VDD_GE_B to add additional information about RGMII. Also added pin VDD_GE for the 88F6190 and revised the description of VDD to indicate that it provides the CPU voltage. 4. In Table 10, 88F6192 Gigabit Ethernet Port0/1 Interface Pin Assignments, on page 34, added a description for MII/MMII to the GE_TXD[3:0], GE_TXCTL, GE_RXCTL, GE_RXCLK, GE_RXD[3:0] rows. Also for pin MPP[30]/GE1[10] added a description for MII/MMII Receive Data Valid. 5. In Table 11, Serial Management Interface (SMI) Pin Assignments, on page 39 and in Table 16, MPP Interface Pin Assignment, on page 44, revised the power rail information to indicate the power rail for each device. 6. In Table 19, Audio (S/PDIF / I2S) Interface Signal Assignment, on page 47 and Table 22, Time Division Multiplexing (TDM) Interface Signal Assignment, on page 50, revised the power rail to VDD_GE_B. 7. In Section 6.1, Multi-Purpose Pins Functional Summary, on page 61: • Changed all reference to MPP[0] and MPP[11] from GPI to GPIO. • Added the following bullet at the end of the section, after the tables: When TWSI serial ROM initialization is enabled, MPP[8] and MPP[9] wake up as TWSI data and clock pins, respectively. 8. Revised the supported clock combinations in Table 36, Supported Clock Combinations, on page 72. 9. Revised Section 6.2, Gigabit Ethernet (GbE) Pins Multiplexing on MPP, on page 68 to describe the differences in the Gigabit Ethernet multiplexing for the 88F6190 and 88F6192. 10. Revised Table 32, 88F6190 Ethernet Ports Pins Multiplexing, on page 68 and Table 33, 88F6192 Ethernet Ports Pins Multiplexing, on page 69 including the addition of a new configuration option for the Gigabit Ethernet ports: Port 0 MII/MMII, Port 1 RGMII. 11. In Table 35, 88F619x Clocks, on page 71, revised the PEX PHY and USB PHY PLL rows and added the PTP clock. 12. In Table 38, Reset Configuration, on page 77, revised the description of TWSI Serial ROM Initialization to indicate that MPP[8] and MPP[9] wake up as TWSI data and clock pins, respectively. 13. In Table 41, Absolute Maximum Ratings, on page 85, Table 42, Recommended Operating Conditions, on page 87, Table 43, Thermal Power Dissipation, on page 89, and Table 44, Current Consumption, on page 91, changed all occurrences of VDD_CPU to VDD. 14. In Table 42, Recommended Operating Conditions, on page 87, revised the description of the VDD_GE_A/VDD_GE_B row to show that RGMII can also operate with a voltage of 3.3V. 15. In Table 43, Thermal Power Dissipation, on page 89, added the row RGMII 3.3V interface. 16. In Table 44, Current Consumption, on page 91, revised the interface RGMII 1.8V interface to RGMII 1.8V or 3.3V interface. Also added the parameter DDR2 SDRAM interface (On Board 16-bit 200 MHz). 17. Added Table 54, RGMII 10/100 AC Timing Table at 3.3V, on page 102. B April 8, 2008 Revision 1. In the features list, added the functional block diagram and the usage model diagram. 2. Throughout this specification, LVCMOS and LVTTL were changed to CMOS. 3. In Figure 2, 88F6192 Pin Logic Diagram, on page 22 revised the power pins section, changed the MPP pins to MPP[35:0] from MPP[34:0] and removed the interfaces that are multiplexed on the MPP pins.
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Revision History
Table 80:
R e v i s io n
Revision History (Continued)
D a te C o m m e n ts
4. Revised Table 2, Pin Functions and Assignments Table Key, on page 23 to show only terms relevant for this device. 5. In Table 4, Power Pin Assignments, on page 25, added pin SSCG_AVDD and added the SMI interface at 1.8V and the MII/MMII interface at 3.3V to the description of the interfaces supported by pin VDD_GE_A. 6. In Table 10, 88F6192 Gigabit Ethernet Port0/1 Interface Pin Assignments, on page 34, removed pins GE_MDC and GE_MDIO. 7. Added Section 2.2.7, Serial Management Interface (SMI) Interface Pin Assignments, on page 39, with a description of the GE_MDC and GE_MDIO pins. 8. In Table 14, RTC Interface Pin Assignments, on page 42, changed the pin type for RTC_XIN to analog from CMOS. 9. In Table 17, Two-Wire Serial Interface (TWSI) Interface Pin Assignment, on page 45, changed the note to: Requires a pull-up resistor to VDDO. 10. Added Section 3, Unused Interface Strapping, on page 56. 11. In Figure 4, 88F6192 Pin Map Top View, on page 59 and Table 28, 88F6192 Pinout Sorted by Pin Number, on page 60: • Changed pin 100 to MPP[16] from MPP[17]. • Changed pin 101 to MPP[17] from MPP[16]. • Changed pin 149 to PEX_AVDD from VSS. 12. In Table 35, 88F619x Clocks, on page 71, revised the description of CPU PLL to mention SSCG. 13. Added Section 7.1, Spread Spectrum Clock Generator (SSCG), on page 72. 14. Added Section 8.1, Power-Up/Down Sequence Requirements, on page 73 and revised the title of Section 8 to reflect this changed. 15. In Section 8.4, Sheeva™ CPU TAP Controller Reset, on page 76, revised the note referring to sample at reset and added the note: If a signal is pulled up on the board, it must be pulled to the proper voltage level. Certain reset configuration pins are powered by VDD_GE_A and VDD_GE_B. Those pins have multiple voltage options (see Table 42, Recommended Operating Conditions, on page 87). 16. In Table 41, Absolute Maximum Ratings, on page 85 and Table 42, Recommended Operating Conditions, on page 87, added the parameter SSCG_VDD. 17. In Table 43, Thermal Power Dissipation, on page 89 added the following: The purpose of the Thermal Power Dissipation table is to support system engineering in thermal design. 18. In Table 44, Current Consumption, on page 91 added the following: The purpose of the Current Consumption table is to support board power design and power module selection. 19. • • • • • In Table 51, Reference Clock AC Timing Specifications, on page 97: Revised the symbols for the Transport Stream (TS) output and input mode reference clocks Revised the symbols for the SMI master mode reference clock Revised the symbols for the TWSI master mode reference clock Revised the description for symbol FRTC_XIN. Removed the RGMII, GMII, MII 100 Mbps, and MII 10 Mbps rows from this table since they are not relevant to this device.
20. In Table 71, SATA-I Interface Gen1i Mode Driver and Receiver Characteristics, on page 132, added driver and receiver return loss parameters, according to updated standard. 21. In Table 64, Thermal Data for the 88F6190/88F6192 in the QFP 216-pin Package, on page 102, added values for all of the parameters. 22. Replaced Figure 50, LQFP 216-pin Package and Dimensions, on page 139 with a revised package drawing, revised Table 77, LQFP 216-pin Package Dimensions, on page 140, and added Table 78, LQFP 216-pin Package Exposed Pad (ePAD) Size, on page 140.
A
January 28, 2008
Initial release
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