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MV78100
Discovery™ Innovation Series CPU Family
Hardware Specifications
MV-S104552-U0, Rev. D December 6, 2008
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Document Classification: Proprietary Information
MV78100 Hardware Specifications
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Disclaimer No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use Marvell products in these types of equipment or applications. With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees: 1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2; 2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are controlled for national security reasons by the EAR; and, 3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant, not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons by the EAR, or is subject to controls under the U.S. Munitions List ("USML"). At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. Copyright © 2008. Marvell International Ltd. All rights reserved. Marvell, the Marvell logo, Moving Forward Faster, Alaska, Fastwriter, Datacom Systems on Silicon, Libertas, Link Street, NetGX, PHYAdvantage, Prestera, Raising The Technology Bar, The Technology Within, Virtual Cable Tester, and Yukon are registered trademarks of Marvell. Ants, AnyVoltage, Discovery, DSP Switcher, Feroceon, GalNet, GalTis, Horizon, Marvell Makes It All Possible, RADLAN, UniMAC, and VCT are trademarks of Marvell. All other trademarks are the property of their respective owners.
MV-S104552-U0 Rev. D Page 2 Document Classification: Proprietary Information
Copyright © 2008 Marvell December 6, 2008, Preliminary
MV78100
Discovery™ Innovation Series CPU Family
Hardware Specifications
PRODUCT OVERVIEW
Building upon the Marvell® high-performance Sheeva™ CPU core, the MV78100 is part of the Discovery™ Innovation series CPU family. The MV78100 is optimally designed for a broad range of applications ranging from sophisticated routers, switches, and wireless-base stations to high-volume storage and laser printer applications. The MV78100 incorporates a fully ARMv5TE-compliant dual-issue CPU core with a double-precision, IEEE compliant Floating-point Unit (FPU), and 512 KB of L2 cache. Its innovative crossbar architecture, advanced communications peripherals, and performance-tuned interfaces, make it a perfect, high-performance solution for embedded applications such as:
• Integrated Storage Accelerator engine (two XOR
DMA or iSCSI CRC engines)
• Timers • Interrupt controller
Sheeva™ Dual-Issue CPU with FPU support • Up to 1.2 GHz • Super-scalar, dual-issue CPU • Single-precision and double-precision FPU support • 32-bit and 16-bit RISC architecture • Compliant with v5TE architecture, published in the ARM Architect Reference Manual, Second Edition • Supports 32-bit instruction set for performance and flexibility • Supports 16-bit Thumb instruction set for code density • Supports DSP instructions to boost performance for signal processing applications • Includes MMU to support virtual memory features • MPU can be used instead of MMU • 32-KB I-Cache and 32-KB D-Cache, parity protected • 512-KB unified L2 cache, ECC protected • 64-bit internal data bus • Variable pipeline stages—six to nine stages • Out-of-order execution for increased performance • In-order retire via Reordering Buffer (ROB) • Branch Prediction Unit • Supports JTAG/ARM-compatible ICE • Supports both Big and Little Endian modes DDR2 SDRAM controller • 40/72-bit interface (32/64-bit data + 8-bit ECC) • Up to 400 MHz clock frequency (DDR2–800 MHz data rate) • DDR SDRAM with a clock ratio of 1:N and 2:N (up to 1:5) between the DDR SDRAM and the Sheeva™ core, respectively • SSTL 1.8V I/Os • Auto-calibration of I/Os output impedance • Supports four DRAM banks • Supports all DDR devices, densities up to 2 Gb • Up to 4 GB address space
MV-S104552-U0 Rev. D
• • • • • •
Printers Core and edge routers Cellular base stations Ethernet switch management Storage arrays Network Attached Storage (NAS) devices
The MV78100 Includes • High-performance Sheeva™ dual-issue CPU with IEEE compliant FPU support • 512 KB L2 cache • High bandwidth DDR II memory interface (32/64-bit DDR2–800 MHz data rate with an 8-bit ECC option) • 8/16/32-bit device bus with up to five chip selects, and with NAND and NOR Flash support • Two x4 wide PCI Express ports with integrated PHY; each one can also act as four x1 ports • Two Gigabit Ethernet MAC controllers • Three USB 2.0 ports with integrated PHYs • Two SATA 2.0 ports with integrated 3 Gbps SATA II PHY • Security Cryptographic engine • Four 16550 compatible UARTs • Two channels SLIC/Codec TDM interface • Four IDMA engines
Copyright © 2008 Marvell December 6, 2008, Preliminary Document Classification: Proprietary Information
Page 3
MV78100 Hardware Specifications
• Supports all DIMMs configurations (registered and • • • •
un-buffered, x8 or x16 DRAM devices) Supports 2T mode to enable high-frequency operation, even under heavy load configuration Supports DRAM bank interleaving Supports up to 32 open pages Supports up to 128-byte burst per single memory access
PCI Express Target specific features • Supports reception of up to four read requests • Maximum read request of up to 4 KB • Maximum write request of up to 128 bytes • Supports PCI Express access to all of the device’s internal registers Two Gigabit Ethernet MACs • Support 10/100/1000 Mbps • Full wire speed receive and transmit of short packets • GMII/MII interface when using a single port • RGMII interface when using dual ports • Priority queueing on receive based on DA, VLAN-Tag, IP-TOS • Also supports queuing based on Marvell DSA Tag • Layer2/3/4 frame encapsulation detection • Supports long frames (up to 9K) on both receive and transmit • Hardware TCP/IP checksum on receive and transmit Three USB 2.0 ports • Each port can act as USB host or peripheral • USB 2.0 compliant • Integrated USB 2.0 PHY • EHCI compatible as a host • As a host, supports direct connection to all peripheral types (LS, FS, HS) • As a peripheral, connects to all host types (HS, FS) and hubs • Up to six independent endpoints supporting control, interrupt, bulk, and isochronous data transfers • Dedicated DMA for data movement between memory and port Integrates Two Marvell 3 Gbps SATA PHYs • Compliant with SATA II Phase 1 specifications - Supports SATA II Native Command Queuing (NCQ), up to 128 outstanding commands per port - First party DMA (FPDMA) full support - Backwards compatible with SATA I devices
Device Bus controller • 32-bit multiplexed address/data bus • Supports different types of standard memory devices such as Flash, ROM, and SRAM • Supports NAND Flash • Five chip selects with programmable timing • Optional external wait-state support • 8-, 16-, or 32-bit width device support • Up to 128-byte burst per single device bus access • Support for boot ROMs Two PCI Express interfaces (x4) • PCI Express Base 1.1 compliant • Integrated low-power SERDES PHY, based on proven Marvell SERDES technology • Can be configured as an Endpoint or as Root Complex • x1/x4 link width, 2.5 GHz signalling • Lane polarity reversal support • Maximum payload size of 128 bytes • Single Virtual Channel (VC-0) • Replay buffer support • Extended PCI Express configuration space • Advanced Error Reporting (AER) support • Power management: L0s and SW L1 support • Interrupt emulation message support • Error message support Configurable PCI Express x4 or Quad x1 port • Each one of the PCI Express ports can be configured to act as four independent x1 ports; this is useful for interfacing multiple off-the-shelf PCI-Express devices. • Each of the x1 ports is PCI Express Base 1.1 compliant, has its own register file, and supports the full feature set as the x4 port. PCI Express Master specific features • Host to PCI Express bridge—translates CPU cycles to PCI Express Memory or configuration cycles • Supports DMA bursts between memory and PCI-Express • Supports up to four outstanding read transactions • Maximum read request of up to 128 bytes • Maximum write request of up to 128 bytes
• Supports SATA II Phase 2 advanced features - 3 Gbps SATA II speed - Port Multiplier (PM)—Performs FIS-Based
Switching as defined in SATA working group PM definition - Port Selector (PS)—Issues the protocol-based OOB sequence to select the active host port
• Supports device 48-bit addressing • Supports ATA Tag Command Queuing
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Copyright © 2008 Marvell December 6, 2008, Preliminary
Product Overview
SATA II Host controller • Two SATA 2.0 ports • Enhanced-DMA [EDMA] for the SATA ports • Automatic command execution without host intervention • Command queuing support, for up to 128 outstanding commands • Separate SATA request/response queues • 64-bit addressing support for descriptors and data buffers in system memory • Read ahead • Advanced interrupt coalescing
Two XOR DMAs • Useful for RAID application • Supports XOR operation on up to eight source blocks • Supports also iSCSI CRC-32 calculation Interrupt controller Maskable interrupts to CPU core (and PCI Express in the case of PCI Express Endpoint) Four General Purpose 32-bit Timer/Counters SPI port • General purpose SPI interface • Also support boot from SPI ROM Two TWSI interfaces General purpose TWSI master/slave 24 Multi-Purpose pins dedicated for peripheral functions and General Purpose I/O • Each pin can be configured independently • GPIO inputs can be used to register interrupts from external devices, and to generate maskable interrupts Clock Generation • Supports internal generation of CPU core clock, DRAM clock, core clock, GbE clock, USB clock, and SATA clock from a single 25 MHz reference clock • Also supports spread spectrum reference clock Power Down support • Supports CPU Wait for Interrupt mode (shut down CPU core clock) • Selectable gating of clock trees of different interfaces • Supports DRAM self-refresh • Supports PCI-Express, USB, and SATA PHYs shut down 27 x 27 mm FCBGA package, 1mm ball pitch
• Target mode operation—Two Marvell® devices can
be attached through the SATA ports, enabling data communication between the MV78100 and another Marvell SATA device • Advanced drive diagnostics via the ATA SMART command Cryptographic engine • Hardware implementation on encryption and authentication engines to boost packet processing speed • Dedicated DMA to feed the hardware engines with data from the internal SRAM memory or from the DDR memory • Implements AES, DES, and 3DES encryption algorithms • Implements SHA1 and MD5 authentication algorithms Four UART interfaces • 16550 UART compatible • Each port has two pins for transmit and receive operations, and two pins for modem control functions • One channel also supports DMA Time Division Multiplexing (TDM) Interface • Generic interface to standard SLIC/Codec devices • Compatible with standard PCM highway formats • TDM protocol support for two channels, up to 128 time slots • SPI interface for codec registers read/write access • Integrated DMA to transfer voice data to/from memory buffer Four Channel Independent DMA controller • Chaining via linked-lists of descriptors • Moves data from any interface to any interface • DMA trigger by software or external hardware • Supports increment or hold on both Source and Destination Address
Copyright © 2008 Marvell December 6, 2008, Preliminary Document Classification: Proprietary Information
MV-S104552-U0 Rev. D Page 5
MV78100 Hardware Specifications
Table of Contents
Preface.......................................................................................................................................................12
About this Document .......................................................................................................................................12 Related Documentation...................................................................................................................................12 Document Conventions ...................................................................................................................................13
1 2
2.1 2.2
Overview....................................................................................................................................... 14 Pin Information ............................................................................................................................ 16
Pin Logic .........................................................................................................................................................17 Pin Descriptions ..............................................................................................................................................18
3 4 5
5.1 5.2
Unused Interface Strapping........................................................................................................ 39 MV78100 Pin Map and Pin List ................................................................................................... 40 Clocking ....................................................................................................................................... 41
Clock Domains ................................................................................................................................................41 PLLs and Clock Pins .......................................................................................................................................41
6
6.1
Pin Multiplexing ........................................................................................................................... 44
MPP Multiplexing ............................................................................................................................................44
7
7.1 7.2 7.3 7.4 7.5
System Power Up and Reset Settings ....................................................................................... 49
Power Up/Down Sequence Requirements......................................................................................................49 Hardware Reset ..............................................................................................................................................51 PCI Express Reset ..........................................................................................................................................51 Pins Sample Configuration..............................................................................................................................52 Power Up and Boot Sequence ........................................................................................................................57
8 9
9.1 9.2 9.3 9.4 9.5 9.6 9.7
JTAG Interface ............................................................................................................................. 59 Electrical Specifications (Preliminary) ...................................................................................... 60
Absolute Maximum Ratings ............................................................................................................................60 Recommended Operating Conditions .............................................................................................................62 Thermal Power Dissipation (Preliminary) ........................................................................................................64 Current Consumption (Preliminary).................................................................................................................65 DC Electrical Specifications ............................................................................................................................66 AC Electrical Specifications ............................................................................................................................70 Differential Interface Electrical Characteristics..............................................................................................104
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Table of Contents
10 11 12 13
Thermal Data (Preliminary) .......................................................................................................116 Package Mechanical Dimensions ............................................................................................117 Part Order Numbering/Package Marking ................................................................................118 Revision History ........................................................................................................................120
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MV78100 Hardware Specifications
List of Tables
1 2 Overview............................................................................................................................................ 14 Pin Information ................................................................................................................................. 16
Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Pin Functions and Assignments Table Key ......................................................................................18 Interface Pin Prefixes........................................................................................................................18 Power Supply Pins............................................................................................................................20 Miscellaneous Pin Assignments .......................................................................................................21 DDR SDRAM Interface Pin Assignments .........................................................................................23 Device Bus Interface Pin Assignments .............................................................................................26 PCI Express Port 0/1 Interface Pin Assignments .............................................................................28 PCI Express Common Pin Assignments ..........................................................................................28 Gigabit Ethernet Port Interface Pin Assignments .............................................................................29 USB 2.0 Ports 0/1/2 Interface Pin Assignments ...............................................................................33 SATA II Port 0/1 Interface Pin Assignments .....................................................................................33 TWSI Interface Pin Assignments ......................................................................................................34 SPI Interface Pin Assignments .........................................................................................................34 UART 0/1/2/3 Interfaces Pin Assignments .......................................................................................35 TDM Interface Pin Assignments .......................................................................................................36 MPP Interface Pin Assignments .......................................................................................................38 JTAG Pin Assignments .....................................................................................................................38
3 4 5 6 7
Unused Interface Strapping............................................................................................................. 39
Table 18: Unused Interface Strapping ..............................................................................................................39
MV78100 Pin Map and Pin List ........................................................................................................ 40 Clocking............................................................................................................................................. 41
Table 19: HCLK and PCLK Frequencies ..........................................................................................................41
Pin Multiplexing ................................................................................................................................ 44
Table 20: MPP Function Summary ...................................................................................................................45
System Power Up and Reset Settings ............................................................................................49
Table 21: Table 22: I/O and Core Voltages ......................................................................................................................49 Reset Configuration ..........................................................................................................................52
8 9
JTAG Interface .................................................................................................................................. 59 Electrical Specifications (Preliminary) ........................................................................................... 60
Table 23: Table 24: Table 25: Table 26: Absolute Maximum Ratings ..............................................................................................................60 Recommended Operating Conditions...............................................................................................62 Thermal Power Dissipation ...............................................................................................................64 Current Consumption........................................................................................................................65
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List of Tables
Table 27: Table 28: Table 29: Table 30: Table 31: Table 32: Table 33: Table 34: Table 35: Table 36: Table 37: Table 38: Table 39: Table 40: Table 41: Table 42: Table 43: Table 44: Table 45: Table 46: Table 47: Table 48: Table 49: Table 50: Table 51: Table 52: Table 53: Table 54: Table 55: Table 56: Table 57: Table 58: Table 59: Table 60:
General 3.3V Interface (CMOS) DC Electrical Specifications...........................................................66 General 1.8V Interface (CMOS) DC Electrical Specifications...........................................................67 SDRAM DDR2 Interface DC Electrical Specifications ......................................................................68 TWSI Interface 3.3V DC Electrical Specifications.............................................................................69 Reference Clock and Reset AC Timing Specifications .....................................................................70 RGMII AC Timing Table....................................................................................................................73 MII AC Timing Table ........................................................................................................................75 GMII AC Timing Table ......................................................................................................................77 SMI Master Mode AC Timing Table..................................................................................................79 SDRAM DDR2 400 MHz Interface AC Timing Table ........................................................................81 SDRAM DDR2 400 MHz Interface Address and Control Timing Table ............................................82 SDRAM DDR2 400 MHz Clock Specifications..................................................................................83 SDRAM DDR2 333 MHz Interface AC Timing Table ........................................................................84 SDRAM DDR2 333 MHz Interface Address and Control Timing Table ............................................85 SDRAM DDR2 333 MHz Clock Specifications..................................................................................86 SDRAM DDR2 266 MHz Interface AC Timing Table ........................................................................87 SDRAM DDR2 200 MHz Interface AC Timing Table ........................................................................88 SPI (Master Mode) AC Timing Table ................................................................................................91 TWSI Master AC Timing Table .........................................................................................................94 TWSI Slave AC Timing Table ...........................................................................................................94 Device Bus Interface AC Timing Table (when using TCLK_OUT as the reference clock) ...............97 Device Bus Interface AC Timing Table (when using TCLK_IN as the reference clock) ...................97 JTAG Interface 30 MHz AC Timing Table ......................................................................................100 TDM Interface AC Timing Table .....................................................................................................102 PCI Express Interface Differential Reference Clock Characteristics ..............................................104 PCI Express Interface Spread Spectrum Requirements.................................................................105 PCI Express Interface Driver and Receiver Characteristics ...........................................................106 SATA I Interface Gen1i Mode Driver and Receiver Characteristicss..............................................108 SATA I Interface Gen1m Mode Driver and Receiver Characteristics .............................................109 SATA II Interface Gen2i Mode Driver and Receiver Characteristics ..............................................110 SATA II Interface Gen2m Mode Driver and Receiver Characteristics ............................................111 USB Low Speed Driver and Receiver Characteristics ....................................................................112 USB Full Speed Driver and Receiver Characteristics.....................................................................113 USB High Speed Driver and Receiver Characteristics ...................................................................114
10 11 12 13
Thermal Data (Preliminary) ............................................................................................................116
Table 61: Thermal Data for the MV78100 in FCBGA Package ......................................................................116
Package Mechanical Dimensions .................................................................................................117 Part Order Numbering/Package Marking......................................................................................118
Table 62: MV78100 Part Order Options .........................................................................................................118
Revision History .............................................................................................................................120
Table 63: Revision History ..............................................................................................................................120
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MV78100 Hardware Specifications
List of Figures
1 Overview........................................................................................................................................... 14
Figure 1: MV78100 Application Example ........................................................................................................15
2
Pin Information ................................................................................................................................ 16
Figure 2: MV78100 Interface Pin Logic Diagram ............................................................................................17
3 4 5
Unused Interface Strapping............................................................................................................ 39 MV78100 Pin Map and Pin List ....................................................................................................... 40 Clocking............................................................................................................................................ 41
Figure 3: MV78100 Clocks...............................................................................................................................42
6 7
Pin Multiplexing ............................................................................................................................... 44 System Power Up and Reset Settings ........................................................................................... 49
Figure 4: Power Up Sequence Example ..........................................................................................................50
8
JTAG Interface ................................................................................................................................. 59
Figure 5: MV78100 TAP Controller ..................................................................................................................59
9
Electrical Specifications (Preliminary) .......................................................................................... 60
Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: TCLK_Out Reference Clock Test Circuit ..........................................................................................71 TCLK_Out AC Timing Diagram ........................................................................................................72 RGMII Test Circuit ............................................................................................................................73 RGMII AC Timing Diagram ...............................................................................................................74 MII Test Circuit..................................................................................................................................75 MII Output Delay AC Timing Diagram ..............................................................................................75 MII Input AC Timing Diagram ...........................................................................................................76 GMII Test Circuit ...............................................................................................................................77 GMII Output AC Timing Diagram ......................................................................................................78 GMII Input AC Timing Diagram.........................................................................................................78 MDIO Master Mode Test Circuit .......................................................................................................79 MDC Master Mode Test Circuit ........................................................................................................80 SMI Master Mode Output AC Timing Diagram .................................................................................80 SMI Master Mode Input AC Timing Diagram ....................................................................................80 SDRAM DDR2 Interface Test Circuit ................................................................................................89 SDRAM DDR2 Interface Write AC Timing Diagram .........................................................................89 SDRAM DDR2 Interface Address and Control AC Timing Diagram .................................................89 SDRAM DDR2 Interface Read AC Timing Diagram .........................................................................90 SPI (Master Mode) Test Circuit ........................................................................................................91 SPI (Master Mode) Normal Output AC Timing Diagram ...................................................................92
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List of Figures
Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41:
SPI (Master Mode) Normal Input AC Timing Diagram......................................................................92 SPI (Master Mode) Opposite Output AC Timing Diagram ................................................................93 SPI (Master Mode) Opposite Input AC Timing Diagram ...................................................................93 TWSI Test Circuit..............................................................................................................................95 TWSI Output Delay AC Timing Diagram...........................................................................................95 TWSI Input AC Timing Diagram .......................................................................................................96 Device Bus Interface Test Circuit .....................................................................................................98 Device Bus Interface Output Delay AC Timing Diagram ..................................................................98 Device Bus Interface Input AC Timing Diagram ...............................................................................99 JTAG Interface Test Circuit ............................................................................................................100 JTAG Interface Output Delay AC Timing Diagram .........................................................................101 JTAG Interface Input AC Timing Diagram ......................................................................................101 TDM Interface Test Circuit ..............................................................................................................102 TDM Interface Output Delay AC Timing Diagram...........................................................................103 TDM Interface Input Delay AC Timing Diagram..............................................................................103 PCI Express Interface Test Circuit..................................................................................................107
10 11
Thermal Data (Preliminary) ........................................................................................................... 116 Package Mechanical Dimensions ................................................................................................ 117
Figure 45: 655 Pin FCBGA Package and Dimensions ....................................................................................117
12
Part Order Numbering/Package Marking..................................................................................... 118
Figure 46: Figure 47: Sample Part Number ......................................................................................................................118 MV78100 Commercial Package Marking and Pin 1 Location.........................................................119
13
Revision History ............................................................................................................................ 120
Copyright © 2008 Marvell December 6, 2008, Preliminary Document Classification: Proprietary Information
MV-S104552-U0 Rev. D Page 11
MV78100 Hardware Specifications
Preface
About this Document
The MV78100 Hardware Specifications provides a features list, overview, pin description, ball map, and electrical specifications for the MV78100 device. This datasheet also includes information on configuration settings and physical specifications. It is intended to be the basic source of information for designers of new systems. In this document, the MV78100 is often referred to as “the device”.
Related Documentation
The following documents contain additional information related to the MV78100: MV76100, MV78100, and MV78200 Functional Specification (Doc. No. MV-S800598-U0) MV76100, MV78100, and MV78200 Design Guide (Doc. No. MV-S301291-00)1 TB-235: Differences Between the MV76100, MV78100, and MV78200 Revisions A0 and A1 (Doc. No. MV-S105821-00)1 See the Marvell® Extranet website for the latest product documentation.
1. This document is a Marvell proprietary confidential document requiring an NDA and can be downloaded from the Marvell Extranet.
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Copyright © 2008 Marvell December 6, 2008, Preliminary
Preface
Document Conventions
Document Conventions
The following conventions are used in this document:
Signal Range A signal name followed by a range enclosed in brackets represents a range of logically related signals. The first number in the range indicates the most significant bit (MSb) and the last number indicates the least significant bit (LSb). Example: DB_Addr[12:0] Active Low Signals # An n letter at the end of a signal name indicates that the signal’s active state occurs when voltage is low. Example: INTn State Names State names are indicated in italic font. Example: linkfail Register Naming Conventions Register field names are indicated by angle brackets. Example: Register field bits are enclosed in brackets. Example: Field [1:0] Register addresses are represented in hexadecimal format. Example: 0x0 Reserved: The contents of the register are reserved for internal use only or for future use. A lowercase in angle brackets in a register indicates that there are multiple registers with this name. Example: Multicast Configuration Register Reset Values Reset values have the following meanings: 0 = Bit clear 1 = Bit set Gb: gigabit GB: gigabyte Kb: kilobit KB: kilobyte Mb: megabit MB: megabyte Unless otherwise indicated, all numbers in this document are decimal (base 10). An 0x prefix indicates a hexadecimal number. An 0b prefix indicates a binary number.
Abbreviations
Numbering Conventions
Copyright © 2008 Marvell December 6, 2008, Preliminary Document Classification: Proprietary Information
MV-S104552-U0 Rev. D Page 13
MV78100 Hardware Specifications
1
Overview
The MV78100 device is part of the Discovery™ Innovation series CPU family. It provides a single-chip, high-performance, cost-effective solution for different types of applications, such as printers, routers, web switches, storage applications, and wireless infrastructure. The MV78100 integrates a dual-issue, ARMv5 compatible CPU, with integrated double-precision FPU, and 512 KB of L2 cache. The MV78100 supports the following interfaces: 32-bit/64-bit DDR2 SDRAM interface with an additional 8-bit ECC option 8/16/32-bit device bus interface Two PCI Express x4 interfaces; each one can also act as four x1 interfaces Three USB 2.0 ports Two SATA II ports Two Gigabit Ethernet MACs Additionally, the MV78100 integrates: A cryptographic hardware accelerator Two XOR DMA engines Four IDMA engines Four 16550 compatible UARTs; one interface can support DMA-based transmit A two channel SLIC/Codec TDM interface SPI port Two TWSI ports Four general purpose timers/counters A watchdog timer An interrupt controller The MV78100 architecture is based on an Mbus fabric connecting all of the units. Each unit is connected to the Mbus via a full duplex 64-bit data path. The Mbus architecture enables concurrency of transactions between multiple units, resulting in high accumulative throughput. It also supports split transactions with out-of-order completion. For low latency CPU-to-DRAM access, the MV78100 also implements a dedicated point-to-point, 128-bit full duplex data path, between the ARM compliant CPU core and the DRAM controller. The CPU Bus Interface Unit (BIU) and DRAM controller complex run synchronously. This implementation guarantees minimum CPU-to-DRAM latency, which is critical in embedded applications.
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Copyright © 2008 Marvell December 6, 2008, Preliminary
Overview
A typical application is shown in Figure 1.
Figure 1: MV78100 Application Example
DDR2 DIMM
USB Host USB Client USB Client
MV78100
Alaska PHY
®
RGMII
L a t c h
Boot ROM
SATA
x4
x1 PCI-E PCI-E PCI-E device PCIe device device device
PCIe ASIC
Copyright © 2008 Marvell December 6, 2008, Preliminary Document Classification: Proprietary Information
MV-S104552-U0 Rev. D Page 15
MV78100 Hardware Specifications
2
Pin Information
This section provides the pin logic diagram for MV78100 and a detailed description of the pin assignments and their functionality.
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Copyright © 2008 Marvell December 6, 2008, Preliminary
Pin Information
Pin Logic
2.1
Pin Logic
Figure 2: MV78100 Interface Pin Logic Diagram
PEX_CLK_P PEX_CLK_N PEX_TX_P[3:0] PEX_TX_N[3:0] PEX_RX_P[3:0] PEX_RX_N[3:0] PEX0/1_ISET PEX_TP PEX_HSDACN PEX_HSDACP
REF_CLK_SSC
Misc. PCI Express0/1 USB0/1/2
REF_CLK_PT SYSRSTn TCLK_OUT TCLK_IN
USB_DP USB_DM
DEV_CSn[3:0] TWSIx_SDA TWSIx_SCK DEV_BootCSn DEV_OEn DEV_WEn[3:0]
TWSI Device
MPP[23:0]
MPP
DEV_ALE[1:0] DEV_AD[31:0] DEV_A[2:0] DEV_READYn DEV_BURSTn/ DEV_LASTn
UA0_RXD UA0_TXD UA1_RXD UA1_TXD
UART
GE0_TXCLKOUT GE0_TXCLK GE0_TXD[3:0] GE0_TXD[7:4] GE0_TXERR GE0_TXCTL/GE0_TXEN GE0_RXD[3:0] GE0_RXD[7:4] GE0_RXERR GE0_RXCTL/GE0_RXDV GE0_RXCLK GE0_COL GE_MDC GE_MDIO
JT_CLK JT_TDI JT_TDO JT_TMS_CPU JT_TMS_CORE JT_RSTn
Gigabit Ethernet JTAG
SATAx_TX_P SATAx_TX_N SATAx_RX_P SATAx_RX_N SATA_USB_TP SATA_USB_RES
M_VREF M_CLKOUT[2:0]
SATA0/1
M_CLKOUTn[2:0] M_CKE[3:0] M_RASn M_CASn M_WEn M_A[14:0] M_BA[2:0]
SDRAM
SPI_CSn SPI_CLK SPI_MOSI SPI_MISO
M_CSn[3:0] M_DQ[63:0] M_CB[7:0] M_DQS[8:0] M_DQSn[8:0] M_DM[8:0] M_ODT[3:0] M_STARTBURST M_STARTBURST_IN M_PCAL M_NCAL
SPI
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MV-S104552-U0 Rev. D Page 17
MV78100 Hardware Specifications
2.2
Pin Descriptions
This section details all the pins for the different interfaces providing a functional description of each pin and pin attributes. Table 1 lists the conventions used to identify I/O or O type pins.
Table 1:
Te r m Analog Calib CML CMOS DDR GND HCSL I I/O O o/d
Pin Functions and Assignments Table Key
D e fi n it io n Represents port number Analog Driver/Receiver or Power Supply Calibration pad type Common Mode Logic Complementary Metal-Oxide-Semiconductor Double Data Rate Ground Supply High-speed Current Steering Logic Input Input/Output Output Open Drain pin The pin allows multiple drivers simultaneously (wire-OR connection). A pull-up is required to sustain the inactive value. VDD Power Supply Single Data Rate Stub Series Terminated Logic for 1.8V Tri-State pin Tri-State Value n - Suffix represents an Active Low Signal
Power SDR SSTL t/s TS XXXn
Table 2:
In t e r f a c e
Interface Pin Prefixes
Prefix M_ PEX_ GE_ USB_ TWSI_ SPI_
DDR SDRAM PCI Express Gigabit Ethernet USB 2.0 TWSI SPI
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Pin Information
Pin Descriptions
Table 2:
In t e r f a c e UART Device Bus MPP JTAG Misc SATA TDM
Interface Pin Prefixes (Continued)
Prefix UA_ DEV_ N/A JT_ N/A SATA_ TDM_
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MV-S104552-U0 Rev. D Page 19
MV78100 Hardware Specifications
2.2.1
Power Supply Pins
Table 3 provides the voltage levels for the various interface pins. These also include the analog power supplies for the PLLs or PHYS.
Table 3:
Power Supply Pins
Pi n Ty p e Power Power Power Power Power Power Power D es c r ip t i o n 1.1V CPU voltage 1.0V core voltage 1.8V or 3.3V I/O supply voltage for the Ethernet interface (for the exact reset configuration, refer to Section 7.4, Pins Sample Configuration) 1.8V I/O supply voltage for the DRAM interface 3.3V I/O supply voltage for the TWSI1, SPI, JTAG interfaces 1.8V or 3.3V I/O supply voltage for Device Bus[31:16], TWSI0 (for the exact reset configuration, refer to Section 7.4, Pins Sample Configuration) 1.8V or 3.3V I/O supply voltage for the Device Bus[15:0], Device Bus controls, MPP[23:12], UART, and system signals: • REF_CLK_SSC • REF_CLK_PT • SYSRSTn • TCLK_OUT • TCLK_IN (For the exact reset configuration, refer to Section 7.4, Pins Sample Configuration.) 1.8V or 3.3V I/O supply voltage for MPP[11:0] (for the exact reset configuration, refer to Section 7.4, Pins Sample Configuration)
Pin Name VDD_CPU VDD VDD_GE VDD_M VDDO_A VDDO_B VDDO_C
VDDO_D VSS PLL_AVDD
Power GND Power
PCLK PLL quiet power supply 1.8V NOTE: Implement the PLL filter as described in the MV76100, MV78100, and MV78200 Design Guide. PCLK PLL quiet VSS NOTE: Implement the PLL filter as described in the MV76100, MV78100, and MV78200 Design Guide. SATA and USB PHYs current source voltage filtered 1.8V NOTE: Implement the PLL filter as described in the MV76100, MV78100, and MV78200 Design Guide. SSTL Reference Voltage Reference voltage for SSTL interface, typically VDD_M/2. Note: See the MV76100, MV78100, and MV78200 Design Guide for the VREF recommended topology. PCI Express PHY quiet power supply 1.8V. NOTE: See the MV76100, MV78100, and MV78200 Design Guide for power supply filtering recommendations. USB 2.0 PHY quiet 3.3V power supply. NOTE: See the MV76100, MV78100, and MV78200 Design Guide for power supply filtering recommendation. SATA quiet 2.5V power supply NOTE: See MV76100, MV78100, and MV78200 Design Guide for power supply filtering recommendation.
PLL_AVSS
GND
IREF_AVDD
Power
M_VREF
Power
PEX0_AVDD PEX1_AVDD USB0_AVDD USB1_AVDD USB2_AVDD SATA0_AVDD SATA1_AVDD
Power
Power
Power
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Pin Descriptions
2.2.2
Miscellaneous Pin Assignment
The Miscellaneous signal list contains clocks, reset, and PLL related signals.
Table 4:
Miscellaneous Pin Assignments
I/O P in Ty p e CMOS Power Rail VDDO_C D e s cr ip t i o n
Pin Name
REF_CLK_SSC
I
25 MHz reference clock input for TCLK PLL and PCLK (CPU core, Mbus-L, and SDRAM clock) PLL. Supports a SSC source clock. NOTE: REF_CLK_SSC voltage swing is according to VDDO_C. 25 MHz reference clock input for USB 2.0 PHY, GbE interface, and SATA PHY. Must be a pure tone clock. NOTES: • If the SSC clock is not required, REF_CLK_PT can be configured via reset strapping to also drive the PCLK and TCLK PLLs. In this configuration, tie REF_CLK_SSC to VSS. • REF_CLK_PT voltage swing is according to VDDO_C. System Reset Main reset signal of the device. Used to reset all units to their initial state. NOTE: For reset timing, see in the MV76100, MV78100, and MV78200 Design Guide. Open Drain Reset Output Reset request from the device to the board reset logic. The power rail in use is determined by the MPP pin used for SYSRST_OUTn: • VDDO_B (DEV_AD[21], DEV_AD[24], DEV_AD[29], DEV_AD[30], DEV_AD[31]) • VDDO_C (MPP[13]) TCLK PLL Output. NOTES: • TCLK_OUT pin can be configured to drive a clock running at 1:N of TCLK rate, rather than TCLK PLL output. • If using an external TCLK_IN core clock input rather than the internally generated TCLK, leave TCLK_OUT not connected. TCLK_OUT voltage swing is according to VDDO_C. Core Clock Input (150 MHz–200 MHz). An alternative to the internally generated TCLK. De-skewed inside the chip to 0 skew between the input to the internal clock tree. Useful for high speed synchronous interface operation. NOTES: • If using the internally generated TCLK, connect TCLK_IN to VSS. • The TCLK_IN voltage swing is according to VDDO_C. Temperature diode anode/cathode THERMAL_A and THERMAL_C provide connectivity to the on-chip temperature diode that can be used to determine the die junction temperature. NOTE: When unused can be left unconnected.
REF_CLK_PT
I
CMOS
VDDO_C
SYSRSTn
I
CMOS
VDDO_C
SYSRST_OUTn
O
CMOS
See descrpition
TCLK_OUT
O
CMOS
VDDO_C
TCLK_IN
I
CMOS
VDDO_C
THERMAL_A THERMAL_C
I
Analog
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MV-S104552-U0 Rev. D Page 21
MV78100 Hardware Specifications
Table 4:
Miscellaneous Pin Assignments (Continued)
I/O P in Ty p e Analog Power Rail D e s cr ip t i o n
Pin Name
SATA_USB_TP
O
SATA and USB test point NOTE: Can be left unconnected. Pull-down resistor for the SATA and USB reference current. 6.04 kilohm pull-down to VSS with resistor accuracy of 1%.
SATA_USB_RES
I
Analog
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Pin Descriptions
2.2.3
Table 5:
DDR SDRAM Interface Pin Assignments
DDR SDRAM Interface Pin Assignments
I/ O P in Ty p e P ow e r Rail VDD_M Description
Pin Name
M_CLKOUT[2:0] M_CLKOUTn[2:0]
O
SSTL
Three pairs of DRAM differential clocks. When not using all clock pairs use one of the following strapping configurations and register setting for the unused pair/s: • Leave the unused pair unconnected. In addition, for the unused pair, set bit[12] or bit[13] to 1 (driven normally), in the DDR Controller Control (Low) (Offset: 0x1404). • Connect the unused pair to pull down. In addition, for the unused pair, set bit[12] or bit[13] to 0 (high-z). NOTE: M_CLKOUT[0] and M_CLKOUTn[0] cannot be disabled and is always driven.
M_CKE[3:0]
O
SSTL
VDD_M
Driven by the MV78100 device high to enable DRAM clock. Driven low when setting the DRAM in self refresh mode. NOTES: • All four CKE pins are driven together (no separate self refresh per each DRAM bank). • When unused can be left unconnected. SDRAM Row Address Select Asserted to indicate an active ROW address driven on the SDRAM address lines. SDRAM Column Address Select Asserted to indicate an active column address driven on the SDRAM address lines. SDRAM Write Enable Asserted to indicate a write command to the SDRAM. SDRAM Address Driven during RASn and CASn cycles to generate, together with the bank address bits, the SDRAM address. Driven by the MV78100 device during M_RASn and M_CASn cycles to select one of the eight DRAM virtual banks. NOTE: If an SDRAM device does not support the BA[2] pin, leave the M_BA[2] unconnected. SDRAM Chip Selects Asserted to select a specific SDRAM bank. NOTE: When unused can be left unconnected. SDRAM Data Bus Driven during write to SDRAM. Driven by SDRAM during reads. NOTE: When configured to 32-bit mode, M_DQ[63:32] can be left unconnected.
M_RASn
O
SSTL
VDD_M
M_CASn
O
SSTL
VDD_M
M_WEn
O
SSTL
VDD_M
M_A[14:0]
O
SSTL
VDD_M
M_BA[2:0]
O
SSTL
VDD_M
M_CSn[3:0]
O
SSTL
VDD_M
M_DQ[63:0]
t/s I/O
SSTL
VDD_M
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MV-S104552-U0 Rev. D Page 23
MV78100 Hardware Specifications
Table 5:
DDR SDRAM Interface Pin Assignments (Continued)
I/ O P in Ty p e P ow e r Rail VDD_M Description
Pin Name
M_CB[7:0]
t/s I/O
SSTL
DRAM ECC Driven by the MV78100 during write to SDRAM. Driven by SDRAM during reads. NOTE: When ECC is unused, leave M_CB[7:0] unconnected. SDRAM Data Strobe Driven by the MV78100 during write to SDRAM. Driven by SDRAM during reads. NOTES: • When ECC is unused, leave M_DQS[8] unconnected. • When configured to 32-bit mode, M_DQS[7:4] and M_DQSn[7:4] can be left unconnected. SDRAM Data Mask Asserted by the MV78100 to select the specific bytes out of the 72-bit data/ECC to be written to the SDRAM. NOTES: • When ECC is unused, leave M_DM[8]/M_DQSn[8] unconnected. • When configured to 32-bit mode, M_DM[7:4] can be left unconnected. SDRAM On Die Termination Control Driven by the MV78100 device high to connect DRAM on die termination, and low to disconnect the DRAM termination. NOTES: • For the recommended setting, refer to the MV76100, MV78100, and MV78200 Design Guide. • When unused can be left unconnected. MV78100 indication of starting a burst. NOTE: For the exact length calculation for routing and termination requirements, see the MV76100, MV78100, and MV78200 Design Guide. M_STARTBURST signal routed back to MV78100. Used as a reference signal for the incoming read data driven by the SDRAM. NOTE: For the exact length calculation for routing and termination requirements, see the MV76100, MV78100, and MV78200 Design Guide.
M_DQS[8:0], M_DQSn[8:0]
t/s I/O
SSTL
VDD_M
M_DM[8:0]
O
SSTL
VDD_M
M_ODT[3:0]
O
SSTL
VDD_M
M_STARTBURST
O
SSTL
VDD_M
M_START BURST_IN
I
SSTL
VDD_M
M_BB
I
CMOS
VDDO_C
SDRAM battery backup trigger
NOTE: This signal is multiplexed on the MPP pins, see Section 6, Pin Multiplexing, on page 44.
M_PCAL
I
Calib
DRAM interface signals P channel output driver calibration. Connect to VSS through a 35–70 Ω resistor. NOTE: See the MV76100, MV78100, and MV78200 Design Guide for the recommended values of the calibration resistors.
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Pin Information
Pin Descriptions
Table 5:
DDR SDRAM Interface Pin Assignments (Continued)
I/ O P in Ty p e P ow e r Rail Description
Pin Name
M_NCAL
I
Calib
DRAM interface signals N channel output driver calibration. Connect to VDD_M through a 35–70 Ω resistor.. NOTE: See the MV76100, MV78100, and MV78200 Design Guide for the recommended values of the calibration resistors.
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MV-S104552-U0 Rev. D Page 25
MV78100 Hardware Specifications
2.2.4
Device Bus Interface Pin Assignments
If using a 16-bit Device Bus, DEV_AD[23:16] and DEV_WEn[3:2] can be used for pins multiplexing (as MPP pins). If using an 8-bit Device Bus also DEV_AD[15:9] and DEV_WEn[1] can be used for pins multiplexing (see Section 6, Pin Multiplexing, on page 44 for more details). NAND Flash interface signals are multiplexed on the Device Bus interface and on MPP pins. Refer to the NAND Flash section in the MV76100, MV78100, and MV78200 Functional Specifications for more information.
Note
Table 6:
Device Bus Interface Pin Assignments
I/ O P in Ty p e P ow e r Rail VDDO_C Description
Pin Name
DEV_CSn[3:0]
O
CMOS
Device Bus Chip Select corresponds to Bank [3:0]. NOTE: These pins have internal pullup resistors. Device Bus Boot Chip Select corresponds to Boot Bank. NOTE: This pin has an integrated pullup resistor. Device Bus Output Enable NOTE: This pin has an integrated pullup resistor. Used as DEV_A[15] (device address bus) during first ALE cycle (DEV_ALE[1]).
DEV_BootCSn
O
CMOS
VDDO_C
DEV_OEn/ DEV_A[15]
O
CMOS
VDDO_C
DEV_WEn[3:0]/ DEV_A[16]
O
CMOS
VDDO_C
Device Bus Byte Write Enable (bit per byte) NOTE: These pins have integrated pullup/pulldown resistors. See details in Table 22, Reset Configuration, on page 52. DEV_WEn[0] is used as DEV_A[16] (device address bus) during first ALE cycle (DEV_ALE[1]).
DEV_ALE[1:0]
O
CMOS
VDDO_C
Device Bus Address Latch Enable NOTE: These pins have integrated pullup/pulldown resistors. See details in Table 22, Reset Configuration, on page 52. Used as DEV_AD[7:0] (device data bus) during the data phase. Driven by MV78100 on write access, and by the device on read access. NOTE: These pins have integrated pullup/pulldown resistors. See details in Table 22, Reset Configuration, on page 52. Used as DEV_A[13:6] (device address bus) during first ALE cycle (DEV_ALE[1]). Used as DEV_A[26:19] (device address bus) during second ALE cycle (DEV_ALE[0]).
DEV_AD[7:0]/ DEV_A[13:6]/ DEV_A[26:19]
t/s I/O
CMOS
VDDO_C
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Table 6:
Device Bus Interface Pin Assignments (Continued)
I/ O P in Ty p e P ow e r Rail VDDO_C Description
Pin Name
DEV_AD[15:8]/ DEV_A[14]/ DEV_A[15])
t/s I/O
CMOS
Used as DEV_AD[15:8] (device data bus) during the data phase. Driven by MV78100 on write access, and by the device on read access. NOTE: These pins have integrated pullup/pulldown resistors. See details in Table 22, Reset Configuration, on page 52. DEV_AD[8] is used as DEV_A[14] (device address bus) during first ALE cycle (DEV_ALE[1]). DEV_AD[8] is used as DEV_A[15] (device address bus) during second ALE cycle (DEV_ALE[0]).
DEV_AD[31:16]
t/s I/O
CMOS
VDDO_B
Used as DEV_AD[31:16] (device data bus) during the data phase. Driven by MV78100 on write access, and by the device on read access. NOTE: When using Device Bus as a 8/16b interface, DEV_AD[23:16] can be used for other functions. See Section 6, Pin Multiplexing. These pins have integrated pullup/pulldown resistors. See details in Table 22, Reset Configuration, on page 52. Device Bus Address Bus
Used as DEV_A[2:0] during the data phase.
DEV_A[2:0]/ DEV_A[5:3]/ DEV_A[18:16]
t/s I/O
CMOS
VDDO_C
DEV_A[2:0] is not latched, but connected directly to the device. It is an incrementing address in case of burst access. NOTE: These pins have integrated pullup/pulldown resistors. See details in Table 22, Reset Configuration, on page 52. Device Bus Address Used as DEV_A[5:3] during the first ALE cycle (DEV_ALE[1]). Device Bus address Used as DEV_A[18:16] during the second ALE cycle (DEV_ALE[0]).
DEV_READYn
I
CMOS
VDDO_C
Device READY
Used as cycle extender when interfacing a slow device.
NOTE: When inactive during a device access, access is extended until DEV_READYn assertion. This pin has an integrated pulldown resistor. DEV_BURSTn/ DEV_LASTn O CMOS VDDO_C Device Burst/Device Last
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MV78100 Hardware Specifications
2.2.5
Table 7:
PCI Express Interface Pin Assignments
PCI Express Port 0/1 Interface Pin Assignments
I/ O P in Ty p e P ow e r R a il D e s c r i p t io n
Pin Name Port0 PEX0_CLK_P PEX0_CLK_N PEX0_TX_P1 PEX0_TX_N PEX0_RX_P PEX0_RX_N PEX0_ISET
I
HCSL
PEX0_AVDD
PCI Express Port0 Reference Clock Input 100 MHz, differential pair Port0 Transmit Lane 0/1/2/3 Differential pair of PCI Express transmit data Port0 Receive Lane 0/1/2/3 Differential pair of PCI Express receive data Reference Current 4.99 kilohm pull-down to VSS with resistor accuracy of 1%.
O
CML
PEX0_AVDD
I
CML
PEX0_AVDD
Analog
Port1 PEX1_CLK_P PEX1_CLK_N PEX1_TX_P1 PEX1_TX_N PEX1_RX_P PEX1_RX_N PEX1_ISET I HCSL PEX1_AVDD PCI Express Port1 Reference Clock Input 100 MHz, differential pair Port1 Transmit Lane 0/1/2/3 Differential pair of PCI Express transmit data Port1 Receive Lane 0/1/2/3 Differential pair of PCI Express receive data Reference Current 4.99 kilohm pull-down to VSS with resistor accuracy of 1%.
O
CML
PEX1_AVDD
I
CML
PEX1_AVDD
Analog
1. This port contains four lanes. It can be configured to x4 or to Quad x1. For details on this port’s configuration, see Table 22, Reset Configuration, on page 52.
Table 8:
PCI Express Common Pin Assignments
I/ O O P in Ty p e Analog P ow e r R a il D e s c r i p t io n Analog Test Point Test point signals should be left unconnected High Speed DAC NOTE: See the MV76100, MV78100, and MV78200 Design Guide for the recommended connectivity.
Pin Name PEX_TP
PEX_HSDACP PEX_HSDACN
O
CML
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2.2.6
Gigabit Ethernet Port Interface Pin Assignments
Note
Some GbE interface pins are connected to the VDD_GE power rail and some pins are connected to the VDDO_D power rail.
Table 9:
Gigabit Ethernet Port Interface Pin Assignments
I/O P in Ty p e CMOS Power R a il VDD_GE Description
Pin Name
GE0_TXCLKOUT
t/s O
RGMII Transmit Clock RGMII transmit reference output clock for GE0_TXD[3:0] and GE0_TXCTL Provides 125 MHz, 25 MHz or 2.5 MHz clock. Not used in MII mode. GMII Transmit Clock Provides the timing reference for the transfer of the GE0_TXEN, GE0_TXERR, and GE0_TXD[7:0] signals. This clock operates at 125 MHz.
GE0_TXCLK
I
CMOS
VDD_GE
MII Transmit Clock MII transmit reference clock from PHY. Provides the timing reference for the transmission of the GE0_TXEN, GE0_TXERR, and GE0_TXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz. RGMII Transmit Data Contains the transmit data nibble outputs that run at double data rate with bits [3:0] presented on the rising edge of GE0_TXCLKOUT and bits [7:4] presented on the falling edge. NOTE: These pins have integrated pullup/pulldown resistors. See details in Table 22, Reset Configuration, on page 52. MII Transmit Data Contains the transmit data nibble outputs that are synchronous to the GE0_TXCLK input. GMII Transmit Data Contains the transmit data nibble outputs that are synchronized to GE0_TXCLKOUT.
GE0_TXD[3:0]
t/s O
CMOS
VDD_GE
GE0_TXD[7:4]
t/s O
CMOS
VDDO_D
GMII Transmit Data Contains the transmit data nibble outputs that are synchronized to GE0_TXCLKOUT. NOTE: Multiplexed on MPP.
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MV78100 Hardware Specifications
Table 9:
Gigabit Ethernet Port Interface Pin Assignments (Continued)
I/O P in Ty p e CMOS Power R a il VDD_GE Description
Pin Name
GE0_TXCTL/ GE0_TXEN
t/s O
RGMII Transmit Control Transmit control synchronous to the GE0_TXCLKOUT output rising/falling edge. GE0_TXCTL is presented on the rising edge of GE0_TXCLKOUT. A logical derivative of GE0_TXEN and GE0_TxER is presented on the falling edge of GE0_TXCLKOUT. NOTE: Internally pulled down to 0x0. MII Transmit Enable Indicates that the packet is being transmitted to the PHY. It Is synchronous to GE0_TXCLK. GMII Transmit Enable Indicates that the packet is being transmitted to the PHY. It Is synchronous to GE0_TXCLKOUT.
GE0_TXERR
t/s O
CMOS
VDDO_D
MII Transmit Error It is synchronous to GE0_TXCLK. NOTE: Multiplexed on MPP. GMII Transmit Error It Is synchronous to GE0_TXCLKOUT. NOTE: Multiplexed on MPP.
GE0_CRS
I
CMOS
VDDO_D
MII Carrier Sense Indicates that the receive medium is non-idle. In half-duplex mode, GE0_CRS is also asserted during transmission. GE0_CRS is not synchronous to any clock. NOTE: Multiplexed on MPP. GMII Carrier Sense NOTE: Multiplexed on MPP.
GE0_RXD[3:0]
I
CMOS
VDD_GE
RGMII Receive Data Contains the receive data nibble inputs that are synchronous to GE0_RXCLK input rising/falling edge. MII Receive Data Contains the receive data nibble inputs that are synchronous to GE0_RXCLK input. GMII Receive Data Contains the receive data nibble inputs that are synchronous to GE0_RXCLK input.
GE0_RXD[7:4]
I
CMOS
VDDO_D
GMII Receive Data Contains the receive data nibble inputs that are synchronous to GE0_RXCLK input. NOTE: Multiplexed on MPP.
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Table 9:
Gigabit Ethernet Port Interface Pin Assignments (Continued)
I/O P in Ty p e CMOS Power R a il VDDO_D Description
Pin Name
GE0_RXERR
I
MII Receive Error Indicates that an error symbol, a false carrier, or a carrier extension symbol is detected on the cable. It is synchronous to GE0_RXCLK input. NOTE: Multiplexed on MPP. GMII Receive Error It is synchronous to GE0_RXCLK input. NOTE: Multiplexed on MPP.
GE0_RXCTL/ GE0_RXDV
I
CMOS
VDD_GE
RGMII Receive Control GE0_RXCTL is presented on the rising edge of GE0_RXCLK. A logical derivative of GE0_RXDV and GE0_RXERR is presented on the falling edge of RXCLK. MII Receive Data Valid Indicates that valid data is present on the GE0_RXD lines. It is synchronous to GE0_RXCLK. GMII Receive Data Valid It is synchronous to GE0_RXCLK input.
GE0_RXCLK
I
CMOS
VDD_GE
RGMII Receive Clock The receive clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference clock derived from the received data stream. MII Receive Clock Provides the timing reference for the reception of the GE0_RXDV, GE0_RXERR, and GE0_RXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz. GMII Receive Clock Provides the timing reference for the reception of the GE0_RXDV, GE0_RXERR, and GE0_RXD[7:0] signals. This clock operates at 125 MHz.
GE0_COL
I
CMOS
VDDO_D
MII Collision Detect Indicates a collision has been detected on the wire. This input is ignored in full-duplex mode. GE0_COL is not synchronous to any clock. NOTE: If not using the MII interface, this pin must be left unconnected. Multiplexed on MPP. Management Data Clock MDC is derived from TCLK divided by 128. Provides the timing reference for the transfer of the MDIO signal. Management Data In/Out Used to transfer control information and status between PHY devices and the GbE controller. NOTE: A 2 kilohm pullup resistor is required.
GE_MDC
t/s O
CMOS
VDD_GE
GE_MDIO
t/s I/O
CMOS
VDD_GE
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MV78100 Hardware Specifications
Note
GE0_TXD[7:4], GE0_RXD[7:4], GE0_TXERR, GE0_RXERR, GE0_CRS, and GE0_COL are multiplexed on MPP pins. Also, GbE port 1 is multiplexed on MPP pins. See Section 6, Pin Multiplexing, on page 44.
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2.2.7
USB 2.0 Port Interface Pin Assignments
Table 10: USB 2.0 Ports 0/1/2 Interface Pin Assignments
Pin Name I /O / P i n Ty p e Power Rails D e s c r ip t i o n
Where represents USB Port0, Port1, or Port2. USB_DP USB_DM I/O CML USB0/1/2 _AVDD USB 2.0 Port0/1/2 data+ and data- pair
2.2.8
SATA II Port Interface Pin Assignments
Table 11: SATA II Port 0/1 Interface Pin Assignments
Pin Name I/O P in Ty p e Power R a il s D e sc r ip ti o n
Port0 SATA0_TX_P SATA0_TX_N SATA0_RX_P SATA0_RX_N O CML SATA0_ AVDD SATA0_ AVDD VDDO_C Transmit data: Differential analog output of SATA II Port0
I
CML
Receive data: Differential analog input of SATA II Port0
SATA0_ PRESENTn
O
CMOS
When this signal is asserted there is an active link between the SATA II port and the external device (disk). NOTE: This signal is multiplexed on the MPP pins, see Section 6, Pin Multiplexing, on page 44. When this signal is asserted, there is an active and used link between the SATA II port and the external device (disk). NOTE: This signal is multiplexed on the MPP pins, see Section 6, Pin Multiplexing, on page 44.
SATA0_ACTn
O
CMOS
VDDO_C
Port1 SATA1_TX_P SATA1_TX_N SATA1_RX_P SATA1_RX_P O CML SATA1_ AVDD SATA1_ AVDD VDDO_C Transmit data: Differential analog output of SATA II Port1
I
CML
Receive data: Differential analog input of SATA II Port1
SATA1_ PRESENTn
O
CMOS
When this signal is asserted there is an active link between the SATA II port and the external device (disk). NOTE: This signal is multiplexed on the MPP pins, see Section 6, Pin Multiplexing, on page 44. When this signal is asserted, there is an active and used link between the SATA II port and the external device (disk). NOTE: This signal is multiplexed on the MPP pins, see Section 6, Pin Multiplexing, on page 44.
SATA1_ACTn
O
CMOS
VDDO_C
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MV-S104552-U0 Rev. D Page 33
MV78100 Hardware Specifications
2.2.9
TWSI Interface Pin Assignment
Table 12: TWSI Interface Pin Assignments
Pin Name I/O P in Ty p e CMOS Power R a il s VDDO_B Description
TWSI0_SDA
o/d I/O
TWSI port0 SDA Address or write data driven by the TWSI master or read response data driven by the TWSI slave. NOTE: Requires a pullup resistor to VDDO_B. TWSI port0 Serial Clock Serves as output when acting as an TWSI master. Serves as input when acting as an TWSI slave. NOTE: Requires a pullup resistor to VDDO_B. TWSI port1 SDA Address or write data driven by the TWSI master or read response data driven by the TWSI slave. NOTE: Requires a pull-up 4.7 kΩ resistor to VDDO_A. TWSI port1 Serial Clock Serves as output when acting as an TWSI master. Serves as input when acting as an TWSI slave. NOTE: Requires a pull-up 4.7 kΩ resistor to VDDO_A.
TWSI0_SCK
o/d I/O
CMOS
VDDO_B
TWSI1_SDA
o/d I/O
CMOS
VDDO_A
TWSI1_SCK
o/d I/O
CMOS
VDDO_A
2.2.10
SPI Interface Pin Assignment
Table 13: SPI Interface Pin Assignments
Pin Name I/O P in Ty p e CMOS CMOS CMOS CMOS Power R a il s VDDO_A VDDO_A VDDO_A VDDO_A Description
SPI_CSn SPI_CLK SPI_MOSI SPI_MISO
O O O I
SPI chip select SPI clock SPI data output SPI data input
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Pin Information
Pin Descriptions
2.2.11
UART Interface Pin Assignment
Table 14: UART 0/1/2/3 Interfaces Pin Assignments
Pin Name I/O P in Ty p e CMOS Power R a il s VDDO_C Description
UA0_RXD UA1_RXD UA0_TXD UA1_TXD UA0_CTSn UA1_CTSn UA0_RTSn UA1_RTSn UA2_RXD UA3_RXD
I
UART0/1 RX Data
O
CMOS
VDDO_C
UART0/1 TX Data
I
CMOS
VDDO_C
UART0/1 Clear To Send NOTE: Multiplexed on MPP. UART0/1 Request To Send NOTE: Multiplexed on MPP. UART2/3 RX Data NOTE: Multiplexed on MPP.
O
CMOS
VDDO_C
I
CMOS
VDDO_C or VDDO_B VDDO_C or VDDO_B VDDO_C or VDDO_B VDDO_C or VDDO_B
UA2_TXD UA3_TXD
O
CMOS
UART2/3 TX Data NOTE: Multiplexed on MPP.
UA2_CTSn UA3_CTSn
I
CMOS
UART2/3 Clear To Send NOTE: Multiplexed on MPP.
UA2_RTSn UA3_RTSn
O
CMOS
UART2/3 Request To Send NOTE: Multiplexed on MPP.
Note
For the UART pins that are multiplexed, see Section 6, Pin Multiplexing, on page 44 for details.
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MV-S104552-U0 Rev. D Page 35
MV78100 Hardware Specifications
2.2.12
TDM Interface Pin Assignment
Note
According to the pin multiplexing setting (see Table 20, MPP Function Summary, on page 45), the power rails for the TDM pins can be VDDO_B or VDDO_C.
Table 15: TDM Interface Pin Assignments
Pin Name I/O P in Ty p e CMOS Power Rails VDDO_B or VDDO_C VDDO_B or VDDO_C VDDO_B or VDDO_C Description
TDM_INTn
I
Interrupt input from the SLIC device NOTE: Multiplexed on MPP.
TDM_RSTn
O
CMOS
SLIC reset input Driven by the MV78100. NOTE: Multiplexed on MPP. PCM audio bit clock Driven by the MV78100 if configured as PCLK master. Input to MV78100 (driven by the SLIC device) if configured as PCLK slave. NOTE: Multiplexed on MPP. Frame Sync signal Driven by the MV78100 if configured as FSYNC master. Input to MV78100 (driven by the SLIC device) if configured as FSYNC slave. NOTE: Multiplexed on MPP. PCM audio input data NOTE: Multiplexed on MPP.
TDM_PCLK
I/O
CMOS
TDM_FSYNC
I/O
CMOS
VDDO_B or VDDO_C
TDM_DRX
I
CMOS
VDDO_B or VDDO_C VDDO_B or VDDO_C VDDO_B or VDDO_C
TDM_DTX
O
CMOS
PCM audio output data NOTE: Multiplexed on MPP.
TDM0_RXQ TDM1_RXQ
O
CMOS
TDM channel0/1 Rx qualifier Driven by MV78100 to the SLIC device. Useful when interfacing with a SLIC device that does not support time slot multiplexing (indicates the exact time slot in which the SLIC device should drive PCM data on TDM_DRX). NOTE: Multiplexed on MPP. TDM channel0/1 Tx qualifier Driven by MV78100 to the SLIC device. Useful when interfacing with a SLIC device that does not support time slot multiplexing (indicates the exact time slot in which the SLIC device should sample PCM data on TDM_DTX). NOTE: Multiplexed on MPP.
TDM0_TXQ TDM1_TXQ
O
CMOS
VDDO_B or VDDO_C
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Pin Information
Pin Descriptions
Table 15: TDM Interface Pin Assignments (Continued)
Pin Name I/O P in Ty p e CMOS Power Rails VDDO_B or VDDO_C Description
TDM0_SCSn TDM1_SCSn
O
SPI chip select0/1 Driven by MV78100 to the SLIC device. Useful when the MV78100 interfaces two SLIC devices and uses two SPI chip select signals (one to each SLIC device) rather than chaining of the devices. NOTE: Multiplexed on MPP. SPI clock Driven by the MV78100 to the SLIC device. NOTE: Multiplexed on MPP. SPI write data Driven by the MV78100 to the SLIC device. NOTE: Multiplexed on MPP. SPI read data Driven by the SLIC device to the MV78100 NOTE: Multiplexed on MPP.
TDM_SCLK
O
CMOS
VDDO_B or VDDO_C VDDO_B or VDDO_C VDDO_B or VDDO_C
TDM_SMOSI
O
CMOS
TDM_SMISO
I
CMOS
Note
The SLIC device has a dedicated SPI interface for SLIC registers access. This is not the MV78100 SPI interface listed in Section 2.2.10, SPI Interface Pin Assignment, on page 34.
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MV-S104552-U0 Rev. D Page 37
MV78100 Hardware Specifications
2.2.13
MPP Interface Pin Assignment
Table 16: MPP Interface Pin Assignments
Pin Name I/O P in Ty p e CMOS Power R a il s VDDO_D D e sc r ip ti on
MPP[11:0]
t/s I/O
Multi Purpose Pin Various functionalities NOTE: These pins have internal pullup resistors. Multi Purpose Pin Various functionalities NOTE: These pins have internal pullup resistors.
MPP[23:12]
t/s I/O
CMOS
VDDO_C
2.2.14
JTAG Interface Pin Assignment
Table 17: JTAG Pin Assignments
Pin Name I/O P in Ty p e CMOS Power R a il s VDDO_A Description
JT_CLK
I
JTAG Clock Clock input for the JTAG controller. NOTE: This pin is internally pulled down to 0. JTAG Reset When asserted, resets the JTAG controller. NOTE: This pin is internally pulled down to 0.1 CPU JTAG Mode Select Controls CPU JTAG controller state. Sampled with the rising edge of JT_CLK. NOTE: This pin is internally pulled up to 1. Core JTAG Mode Select Controls the Core JTAG controller state. Sampled with the rising edge of JT_CLK. NOTE: This pin is internally pulled up to 1. JTAG Data Out Driven on the falling edge of JT_CLK. JTAG Data In JTAG serial data input. Sampled with the JT_CLK rising edge. NOTE: This pin is internally pulled up to 1.
JT_RSTn
I
CMOS
VDDO_A
JT_TMS_CPU
I
CMOS
VDDO_A
JT_TMS_CORE
I
CMOS
VDDO_A
JT_TDO
O
CMOS
VDDO_A
JT_TDI
I
CMOS
VDDO_A
1. If this pull-down conflicts with other devices, the JTAG tool must not use this signal. This signal is not mandatory for the JTAG interface, since the TAP (Test Access Port) can be reset by driving the JT_TMS signal HIGH for 5 JT_CLK cycles. If JT_RSTn is not used it should be connected to reset signal. Otherwise the internal pull down will keep the TAP controller in reset.
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Unused Interface Strapping
3
Ethernet RGMII
Unused Interface Strapping
Table 18 lists the signal strapping for systems in which some of the MV78100 interfaces are unused, not connected.
Table 18: Unused Interface Strapping
Unused Interface St r ap p in g If not using Port0, use a 1–4.7 kilohm pull down for the following signals: GE0_TXCLK, GE0_RXCLK, GE0_RXD[3:0], GE0_RXDV GE_MDIO must be 2 kilohm pulled up. TWSI0_SCK and TWSI0_SDA must be pulled up through a 1–4.7 kilohm resistor to VDDO_B. TWSI1_SCK and TWSI1_SDA must be pulled up through a 1–4.7 kilohm resistor to VDDO_A. VDDO_B and VDDO_C power balls must be connected to 3.3V or to 1.8V according to the corresponding reset strap setting. Discard the power filter. Leave USBx_AVDD connected to 3.3V. All other signals can be left unconnected. Configure it to x4 reset_sampling Dev_AD[3] = 0. Discard the analog power filters. Connect PEX1_AVDD to VDD (1V), to save power suppliers. Pull down the PEX0_CLK_N signal through a 50 kilohm resistor to GND. Pull up the PEX0_CLK_P signal through a 16 kilohom resistor to VDD. All other signals can be left unconnected. Configure it to X4 reset sampling DEV_AD[4] = 0. Discard the analog power filters. Connect PEX1_AVDD to VDD (1V),, to save power suppliers. Pull down the PEX1_CLK_N signal through a 50 kilohm resistor to GND. Pull up the PEX1_CLK_P signal through a 16 kilohm to VDD. All other signals can be left unconnected. Discard the analog power filters and connect it to VDD (1V) Connect the SATA_USB_RES to 6.04 kilohm resistor to pull down. All other signals can be left unconnected.
Ethernet SMI TWSI
Device
USB
PCI Express 0
PCI Express 1
SATA
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MV-S104552-U0 Rev. D Page 39
MV78100 Hardware Specifications
4
MV78100 Pin Map and Pin List
The MV78100 pin lists are provided as Excel file attachments.
To open the attached Excel pin list files, double-click the pin icons below:
MV78100_Pinout_External.xls
File attachments are only supported by Adobe Reader 6.0 and above. Note To download the latest version of free Adobe Reader go to http://www.adobe.com.
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Clocking
Clock Domains
5
5.1
Clocking
Clock Domains
The MV78100 device has multiple clock domains: PCLK: Sheeva™ CPU clock—up to 1 GHz HCLK: The Sheeva™ CPU bus (MbusL) clock. Also used as the DRAM interface clock—up to 400 MHz TCLK: The MV78100 core clock, also used as the reference clock for the MV78100 device bus. Runs at 166 MHz or 200 MHz. PCI-Express clock: Runs at 250 MHz GbE ports clock: 125 MHz for 1000 Mbps, 25 MHz for 100 Mbps, and 2.5 MHz for 10 Mbps operation SATA clock: Runs at 150 Mhz USB clock: Runs at 480 MHz UART clock. Up to TCLK frequency divided by 16 SPI clock: Up to 50 MHz TWSI clock: Up to 100 kHz The supported PCLK to HCLK clock ratios are 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, and 5 determined via reset strapping. Table 19 summarizes the possible frequencies.
Table 19: HCLK and PCLK Frequencies
HCLK/Ratio 200 250 267 300 333 400 1 NA NA NA NA NA 400 1 .5 NA NA 400 450 500 600 2 400 500 533 600 667 800 2.5 500 625 667 750 833 1000 3 600 750 800 900 1000 NA 3.5 700 875 933 NA N/A NA 4 800 1000 NA NA N/A NA 4 .5 900 NA NA NA NA NA 5 1000 NA NA NA NA NA
5.2
PLLs and Clock Pins
The MV78100 has the following on-chip PLLs: PCLK PLL—Generates PCLK (Sheeva™ core clock) and HCLK (Sheeva™ bus and SDRAM I/F clock) TCLK PLL—Generates the internal core frequency GE_CLK125 PLL—Generates 125 MHz reference clock for the GbE MAC PCI Express PHY PLL
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MV-S104552-U0 Rev. D Page 41
MV78100 Hardware Specifications
USB PHY PLL SATA PHY PLL
Note
The different MV78100 PLLs require dedicated quiet power supplies (AVDD/AVSS). See the MV76100, MV78100, and MV78200 Design Guide for a detailed description of these power supplies and required power filtering.
The MV78100 clocking scheme is shown in Figure 3.
Figure 3: MV78100 Clocks
PCLK HCLK
SheevaTM Core DRAM Controller
PCLK PLL
M_CLK_OUT[2:0]/ M_CLK_OUTn[2:0]
TCLK to all of the chip units CLK_25_SSC TCLK PLL 1:N TCLK_OUT
de-skew PLL CLK25_PT
TCLK_IN
USB PHY PLL
CLK125 (GE) PLL
SATA PHY PLL
PEX_0 100 MHz HCSL PEX_1 100 MHz HCSL PCI-E PHYs
The MV78100 supports generation of PCLK, HCLK, and TCLK from a 25 MHz input clock CLK25_SSC. This clock can be generated by a spread spectrum clock generator (SSCG) under the following restrictions: Spread does not exceed -0.5% of the maximum frequency. The modulation frequency does not exceed 33 KHz. The PLLs using this clock source track the spread characteristics of the input clock (meaning TCLK, PCLK, HCLK, and M_CLK_OUT also become spread spectrum clocks). There is a single PCLK PLL that generates PCLK (CPU clock), and HCLK (CPU bus clock which is also DRAM clock). Both clocks are synchronous to each other (edge aligned), resulting in low latency CPU to DRAM path (no synchronization required). The CPU L2 cache clock (named XPCLK) runs relative to the CPU PCLK, with the ratio determined by the reset configuration.
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Clocking
PLLs and Clock Pins
The CPU can be placed in "wait for interrupt" mode. In this mode, most of the PCLK clock tree is turned off (only wake-up logic is kept alive). The TCLK clock tree can be generated from one of two sources: TCLK PLL (selectable 166 MHz or 200 MHz operation) From external TCLK_IN input. In this mode, clock input is de-skewed to have zero skew to the external clock input. This mode is useful when using the chip device bus as a high speed synchronous interface (better AC timing) The MV78100 drives TCLK clock tree output on TCLK_OUT pin. The device can also configured to drive a divided (1:N) TCLK on TCLK_OUT pin. The TCLK clock tree to each of the MV78100 units can be gated via register. This is useful for power saving modes, when most of the chip interfaces are not in use. See the Power Saving section in the Functional Specification for further details. A second 25 MHz input clock, CLK25_PT, is used as a reference clock for the USB PHY PLL, for the CLK125 PLL, and for the SATA PHY PLL. This clock must be pure tone.
Note
If the SSC clock is not required, CLK25_PT can be configured via reset strapping to also drive the PCLK and TCLK PLLs, as shown in Figure 3, MV78100 Clocks, on page 42. If using this configuration, tie CLK25_SSC to VSS via a pull down resistor. The MV78100 SATA PHY generates an SSC signal on its output (TX_P/TX_N) and tolerates an SSC signal on its input (RX_P/RX_N), as defined in the SATA specification.
The PCI Express PHY receives a 100 MHz reference clock. It generates two clocks: A 250 MHz PCLK used by the PCI Express unit (transaction layer, link layer, and PHY MAC layer) A 2.5 GHz clock for the PHY analog part. The PCI Express PLL also tolerates a spread spectrum reference clock, as defined by the PCI Express specification: Spread of -0.5% of the maximum frequency The modulation frequency does not exceed 33 kHz
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MV-S104552-U0 Rev. D Page 43
MV78100 Hardware Specifications
6
6.1
Pin Multiplexing
MPP Multiplexing
The MV78100 device contains 24 Multi Purpose Pins (MPP). When using the device bus as a 16-bit interface, DEV_AD[31:16] and DEV_WEn[3:2] are also used for pins multiplexing, resulting in a total of 42 pins. When using 8-bit device bus, DEV_AD[15:9] and DEV_WEn[1] are also used for pins multiplexing, resulting in total of 50 pins. Each pin can be assigned to a different functionality through the MPP Control register. GPIO: General Purpose In/Out Port, 32 GPIOs available—see the General Purpose I/O Port section in the MV76100, MV78100, and MV78200 Functional Specification. GE0_TXD[7:4], GE0_RXD[7:4], GE0_TXER, GE0_RXER, GE0_CRS, GE0_COL: GbE port0 Signals when configured to MII or GMII interface—see the Gigabit Ethernet Controller section in the MV76100, MV78100, and MV78200 Functional Specification. GE1_TXD[3:0], GE1_RXD[3:0], GE1_TXCLKOUT, GE1_TXCTL, GE1_RXCLK, GE1_RXCTL: GbE port 1 pins. M_BB: SDRAM battery backup trigger—see the DRAM Self Refresh section in the MV76100, MV78100, and MV78200 Functional Specification. UAx_RXD, UAx_TXD, UAx_CTSn, UAx_RTSn - UART pins. SATAn_ACTn/SATAn_PRESENTn: SATA active and SATA present indications—see the SATA section in the MV76100, MV78100, and MV78200 Functional Specification. DEV_NFWEn[3:0], DEV_NFREn[3:0]: NAND Flash additional signals—see the Device Bus section in the MV76100, MV78100, and MV78200 Functional Specification. TDM_INTn, TDM_RSTn, TDM_PCLK, TDM_FSYNC, TDM_DRX, TDM_DTX, TDM_SCSn, TDM_SCLK, TDM_SMOSI, TDM_SMISO: TDM (voice) interface signals—see the TDM section in the MV76100, MV78100, and MV78200 Functional Specification. SYSRST_OUTn - open drain reset output—See Section 7, System Power Up and Reset Settings, on page 49. Table 20 shows each MPP pins’ functionality as determined by the MPP Multiplex registers, refer to the Pins Multiplexing Interface Registers section in the MV76100, MV78100, and MV78200 Functional Specification for more information. The coloring scheme demonstrates the different power segments (yellow = VDDO_B, sky blue = VDDO_C, green = VDDO_D). Note that MPP[23:12] share the same power segment (VDDO_C) as DEV_AD[15:0], all device bus control signals, UART0 and UART1 signals, and system signals (see pin list for more details).
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Pin Multiplexing
MPP Multiplexing
Empty fields in Table 20 indicate non-functional settings. Note
Table 20: MPP Function Summary
MPP Pi n MPP[0] 0x0 0x1 0x 2 0x3 0x 4 0x5 0x6
GPIO[0] (in/out) GPIO[1] (in/out) GPIO[2] (in/out) GPIO[3] (in/out) GPIO[4] (in/out) GPIO[5] (in/out) GPIO[6] (in/out) GPIO[7] (in/out) GPIO[8] (in/out) GPIO[9] (in/out) GPIO[10] (in/out) GPIO[11] (in/out) GPIO[12] (in/out)
GE0_COL (in) GE0_RXERR (in) GE0_CRS (in) GE0_TXERR (out) GE0_TXD[4] (out) GE0_TXD[5] (out) GE0_TXD[6] (out) GE0_TXD[7] (out) GE0_RXD[4] (in) GE0_RXD[5] (in) GE0_RXD[6] (in) GE0_RXD[7] (in)
GE1_TXCLK OUT (out) GE1_TXCTL (out) GE1_RXCTL (in) GE1_RXCLK (in) GE1_TXD[0] (out) GE1_TXD[1] (out) GE1_TXD[2] (out) GE1_TXD[3] (out) GE1_RXD[0] (in) GE1_RXD[1] (in) GE1_RXD[2] (in) GE1_RXD[3] (in) M_BB (in) UA0_CTSn (in) NAND Flash REn[0] (out) NAND Flash WEn[0] (out)
MPP[1]
MPP[2]
MPP[3]
MPP[4]
MPP[5]
MPP[6]
MPP[7]
MPP[8]
MPP[9]
MPP[10]
MPP[11]
MPP[12]
TDM0_ SCSn
(out)
MPP[13]
GPIO[13] (in/out)
SYSRST_ OUTn (out)
UA0_RTSn (out)
TDM_ SCLK
(out)
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MV-S104552-U0 Rev. D Page 45
MV78100 Hardware Specifications
Table 20: MPP Function Summary (Continued)
MPP Pi n MPP[14] 0x0 0x1 0x 2 0x3 0x 4 0x5 0x6
GPIO[14] (in/out)
SATA1_ACT n (out)
UA1_CTSn (in)
NAND Flash REn[1] (out) NAND Flash WEn[1] (out) NAND Flash REn[3] (out) NAND Flash WEn[3] (out) BOOT NAND Flash REn (out) BOOT NAND Flash WEn (out)
TDM_ SMOSI
(out)
MPP[15]
GPIO[15] (in/out)
SATA0_ACT n (out)
UA1_RTSn (out)
TDM_ SMISO
(in) TDM_ INTn (in) TDM_ RSTn (out)
MPP[16]
GPIO[16] (in/out)
SATA1_ PRESENTn (out) SATA0_ PRESENTn (out)
UA2_TXD (out)
MPP[17]
GPIO[17] (in/out)
UA2_RXD [in)
MPP[18]
GPIO[18] (in/out)
UA0_CTSn (in)
MPP[19]
GPIO[19] (in/out)
UA0_RTSn (out)
MPP[20]
GPIO[20] (in/out)
UA1_CTSn (in)
TDM_ PCLK (in/out) TDM_ FSYNC (in/out) NAND Flash REn[2] (out) NAND Flash WEn[2] (out)
MPP[21]
GPIO[21] (in/out)
UA1_RTSn (out)
MPP[22]
GPIO[22] (in/out)
UA3_TXD (out)
TDM_ DRX
(in)
MPP[23]
GPIO[23] (in/out)
UA3_RXD (in)
TDM_ DTX
(out) TDM_ INTn (in) TDM_ RSTn (out) TDM_ PCLK (in/out)
DEV_ AD[16]
GPIO[24] (in/out)
UA2_TXD (out)
DEV_ AD[17]
GPIO[25] (in/out)
UA2_RXD (in)
DEV_ AD[18]
GPIO[26] (in/out)
UA2_CTSn (in)
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Pin Multiplexing
MPP Multiplexing
Table 20: MPP Function Summary (Continued)
MPP Pi n DEV_ AD[19] 0x0 0x1 0x 2 0x3 0x 4 0x5 0x6
GPIO[27] (in/out)
UA2_RTSn (out)
TDM_ FSYNC (in/out)
DEV_ AD[20]
GPIO[28] (in/out)
UA3_TXD (out)
TDM_ DRX
(in) SYSRST_ OUTn (out)
DEV_ AD[21]
GPIO[29] (in/out)
UA3_RXD (in)
TDM_ DTX
(out)
DEV_ AD[22] DEV_ AD[23]
GPIO[30] (in/out) GPIO[31] (in/out)
UA3_CTSn (in) UA3_RTSn (out)
TDM1_ SCSn
(out) SYSRST_ OUTn (out) TDM0_ RXQ (out) TDM0_ TXQ (out) TDM1_ RXQ (out) TDM1_ TXQ (out)
DEV_ AD[24]
GPIO[0] (in/out)
UA3_TXD (out)
DEV_ AD[25]
GPIO[1] (in/out)
UA3_RXD (in)
DEV_ AD[26]
GPIO[2] (in/out)
UA2_TXD (out)
DEV_ AD[27]
GPIO[3] (in/out)
UA2_RXD (in)
DEV_ AD[28]
GPIO[4] (in/out)
UA0_CTSn (in)
UA2_TXD (out)
TDM0_ SCSn
(out) SYSRST_ OUTn (out)
DEV_ AD[29]
GPIO[5] (in/out)
UA0_RTSn (out)
UA2_RXD (in)
TDM_ SCLK
(out)
DEV_ AD[30]
GPIO[6] (in/out)
UA1_CTSn (in)
UA3_TXD (out)
SYSRST_ OUTn (out)
TDM_ SMOSI
(out)
DEV_ AD[31]
GPIO[7] (in/out)
UA1_RTSn (out)
UA3_RXD (in)
SYSRST_ OUTn (out)
TDM_ SMISO
(in) TDM_ INTn (in)
DEV_ AD[9]
GPIO[17] (in/out)
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MV-S104552-U0 Rev. D Page 47
MV78100 Hardware Specifications
Table 20: MPP Function Summary (Continued)
MPP Pi n DEV_ AD[10] 0x0 0x1 0x 2 0x3 0x 4 0x5 0x6
GPIO[18] (in/out)
TDM_ RSTn (out) TDM_ PCLK (in/out) TDM_ FSYNC (in/out)
DEV_ AD[11]
GPIO[19] (in/out)
DEV_ AD[12]
GPIO[20] (in/out)
DEV_ AD[13]
GPIO[21] (in/out)
TDM_ DRX
(in) SATA0_ACT n (out)
DEV_ AD[14]
GPIO[22] (in/out)
TDM_ DTX
(out)
DEV_ AD[15]
GPIO[23] (in/out)
TDM1_ SCSn
(out)
DEV_ WEn[1] DEV_ WEn[2] DEV_ WEn[3]
GPIO[16] (in/out) GPIO[8] (in/out) GPIO[9] (in/out) SATA1_ACT n (out) SATA0_ACT n (out) M_BB (in)
Note
Depending on the pin’s configured functionality, each pin can act as an output or input pin. MPP[23:0] and DEV_AD[23:16] wake up as GPIO. All other pins wake up as non-functional inputs pads (0x0 Column), with one exception. If the chip is configured at reset to boot from CE Care NAND Flash, MPP[19:18] wake up as BOOT NAND Flash output signals. The muxing options on DEV_AD[31:16] and DEV_WEn[3:2] only apply if all five device chip selects are configured as 8- or 16-bit wide. Muxing options on DEV_AD[15:9] and DEV_WEn[1] only apply if all five device chip selects are configured as 8-bit wide. Where device bus pins multiplexing applies, these pins wake up as input (no drive).
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System Power Up and Reset Settings
Power Up/Down Sequence Requirements
7
7.1
7.1.1
System Power Up and Reset Settings
This section provides information about the MV78100 power-up sequence and configuration at reset.
Power Up/Down Sequence Requirements
Power Up Sequence Requirements
These guidelines must be applied to meet the MV78100 device power-up requirements: The Non-Core voltages (I/O and Analog) as listed in Table 21 must reach 70% of their voltage level before the Core voltages reach 70% of their voltage level. The order of the power up sequence between the Non-Core voltages is unimportant so long as the Non-Core voltages power up before the Core voltages reach 70% of their voltage level (shown in Figure 4). The reset signal(s) must be asserted before the Core voltages reach 70% of their voltage level (shown in Figure 4). The reference clock(s) inputs must toggle with their respective voltage levels before the Core Voltages reach 70% of their voltage level (shown in Figure 4).
Table 21: I/O and Core Voltages
N o n - C o r e Vol ta g e s I/ O Vo lta ge s VDD_GE VDD_M VDDO_A VDDO_B VDDO_C VDDO_D A n a lo g P o w e r S up p li e s PLL_AVDD PEX0_AVDD PEX1_AVDD USB0_AVDD, USB1_AVDD, USB2_AVDD SATA0_AVDD, SATA1_AVDD VDD VDD_CPU C o r e Vo l ta g e s
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MV78100 Hardware Specifications
Figure 4: Power Up Sequence Example
Voltage Non-Core Voltage 70% of Non-Core Voltage Core Voltage
70% of Core Voltage
Reset(s)
Clock(s)
Note
It is the designer's responsibility to verify that the power sequencing requirements of other components are also met. Although the non-core voltages can be powered up any time before the core voltages, allow a reasonable time limitation (for example, 100 ms) between the first non-core voltage power-up and the last core voltage power-up.
7.1.2
Power Down Sequence Requirements
There are no special requirements for the core supply to go down first, or for reset assertion when powering down.
Note
Although there is no limitation for power-down sequence between non-core and core voltages, allow a reasonable time limitation (for example, 100 ms) between the first and last voltage power-down.
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System Power Up and Reset Settings
Hardware Reset
7.2
Hardware Reset
The MV78100 has one reset input pin — SYSRSTn. When asserted, the entire chip is placed in its initial state. All outputs are placed in high-z. The following output pins are still active during SYSRSTn assertion: TCLK_OUT GE0_TXCLKOUT M_CLKOUT[2:0], M_CLKOUTn[2:0] M_CKE[3:0] M_ODT[3:0] M_STARTBURST SATAx_TX_P SATAx_TX_N PEXx_TX_N PEXx_TX_P USBx_DM USBx_DP The MV78100 has an optional SYSRST_OUTn open drain output signal, multiplexed on MPP pins, that is used as a reset request from the MV78100 to the board reset logic. This signal is set when one of the following maskable events occurs: Received hot reset indication from the PCI Express port 0.0 link (only relevant when used as a PCI Express endpoint), and bit is set to 1 in the RSTOUTn Mask Register (see the Reset register section of the MV78100 User Manual). In this case, SYSRST_OUTn is asserted for duration of ~300 TCLK cycles. PCI Express port 0.0 link failure (only relevant when used as a PCI Express endpoint), and bit is set to 1 in the RSTOUTn Mask Register (see the Reset register section of the MV78100 User Manual). In this case, SYSRST_OUTn is asserted for duration of ~300 TCLK cycles . Watchdog timer expiration and bit is set to 1 in the RSTOUTn Mask Register (see the Reset register section of the MV78100 User Manual). Bit is set to 1 in System Soft Reset Register and bit is set to 1 in RSTOUTn Mask Register.
Note
Reset must be active for a minimum length of 100ms. Core power, I/O power, and analog power must be stable (VDD +/- 5%) during that time and onward.
7.3
PCI Express Reset
As a Root Complex, the MV78100 can generate a Hot Reset to the PCI Express port. Upon CPU setting the PCI Express Control register’s bit, the PCI Express unit sends a Hot Reset indication to the Endpoint (see the PCI Express Interface section in the MV76100, MV78100, and MV78200 Functional Specification). When the MV78100 works as an Endpoint, and a Hot Reset packet is received: A maskable interrupt is asserted If the PCI Express Debug Control register’s is cleared, the MV78100 also resets the PCI Express register file to its default values. The MV78100 triggers an internal reset, if not masked by PCI Express Debug Control register’s bit.
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MV78100 Hardware Specifications
Link failure is detected if the PCI Express link was up (LTTSSM L0 state) and dropped back to an inactive state (LTSSM Detect state). When Link failure is detected: A maskable interrupt is asserted If the PCI Express Debug Control register’s is cleared, the MV78100 also resets the PCI Express register file to its default values. The MV78100 triggers an internal reset, if not masked by PCI Express Debug Control register’s bit. Whether initiated by a Hot Reset or link failure, this internal reset indication can be routed to SYSRST_OUTn output as explained in Section 7.2, Hardware Reset, on page 51. The external reset logic can assert SYSRSTn in response and reset the entire chip.
Note
Only PEX0 port (or PEX0.0 port in Quad x1 configuration) can act as PCI Express endpoint, and only this port can generate the PCI Express internal reset indication.
7.4
Pins Sample Configuration
The following pins are sampled during SYSRSTn de-assertion. Internal pull up/down resistors set the default mode. External pull up/down resistors are required to change the default mode of operation. These signals must remain pulled up or down until SYSRSTn de-assertion (zero Hold time in respect to SYSRSTn de-assertion).
Note
If external logic is used instead of pull up and pull down resistors, the logic must drive all of the signals to the desired values during SYSRSTn assertion. To prevent bus contention on these pins, the external logic must float the bus no later than the third TCLK cycle after SYSRSTn de-assertion. Refer to the MV76100, MV78100, and MV78200 Design Guide for additional information. All reset sampled values are registered in Reset Sample (Low) and Reset Sample (High) registers (see the Device Interface Registers in the MV76100, MV78100, and MV78200 Functional Specification). This is useful for board debug purposes. Multiple functionality applies to DEV_AD[31:9] and DEV_WEn[3:1], as described in Section 6, Pin Multiplexing, on page 44. If an external device is driving any of these signals, make sure to keep this external device in reset state (prevent it from driving) or use glue logic to disconnect it from the MV78100 as long as the MV78100 SYSRSTn input is asserted.
Table 22: Reset Configuration
Pi n DEV_AD[0] Po w e r R a il VDDO_C C o n fi gu r a t io n F u nc t io n Reserved This signal must be sampled as 0 at reset de-assertion. NOTES: • Internally pulled down to 0x0. • The board design should support future pull up/pull down requirements on this pin. Setting recommendations will be published following silicon samples.
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System Power Up and Reset Settings
Pins Sample Configuration
Table 22: Reset Configuration (Continued)
Pi n DEV_AD[1] Po w e r R a il VDDO_C C o n fi gu r a t io n F u nc t io n Reserved This signal must be sampled as 0 at reset de-assertion. NOTES: • Internally pulled down to 0x0. • The board design should support future pull up/pull down requirements on this pin. Setting recommendations will be published following silicon samples. DEV_AD[2] VDDO_C PCI Express Port0 mode select 0 = Endpoint 1 = Root Complex NOTES: • Internally pulled up to 0x1. • When PCI Express port0 is configured to Quad x 1 (DEV_AD[3]=1), this bit controls Port 0.0 only. DEV_AD[3] VDDO_C PCI Express Port0 configuration 0 = x4 1 = Quad x1 NOTE: Internally pulled down to 0x0. DEV_AD[4] VDDO_C PCI Express Port1 configuration 0 = x4 1 = Quad x1 NOTE: Internally pulled up to 0x1. DEV_AD[7:5] VDDO_C HCLK Frequency select 0x0 = Reserved 0x1 = 200 MHz 0x2 = 267 MHz 0x3 = 333 MHz 0x4 = 400 MHz 0x5 = 250 MHz 0x6 = 300 MHz 0x7 = Reserved NOTE: Internally pulled to 0x2. DEV_AD[11:8] VDDO_C PCLK to HCLK ratio 0x0 = 1 0x1 = 1.5 0x2 = 2 0x3 = 2.5 0x4 = 3 0x5 = 3.5 0x6 = 4 0x7 = 4.5 0x8 = 5 0xB–0xF = Reserved NOTE: Internally pulled to 0x4.
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MV78100 Hardware Specifications
Table 22: Reset Configuration (Continued)
Pi n DEV_AD[13:12] Po w e r R a il VDDO_C C o n fi gu r a t io n F u nc t io n PCLK to CPU L2 ratio 0x0 = 1 0x1 = 2 0x2 = 3 0x3 = Reserved NOTE: Internally pulled to 0x1. DEV_AD[17:14] [15:14] VDDO_C [17:16] VDDO_B VDDO_B Reserved NOTE: Internally pulled to 0x4. DEV_AD[19:18] Reserved NOTE: Internally pulled to 0x1. DEV_AD[20] VDDO_B Reserved This signal must be sampled as 0 at reset de-assertion. NOTE: Internally pulled down to 0x0. DEV_AD[22:21] VDDO_B DEV_BootCEn Device Width 0x0 = 8 bits 0x1 = 16 bits 0x2 = 32 bits 0x3 = Reserved NOTE: Internally pulled down to 0x0. DEV_AD[24:23] VDDO_B Boot DeviceType Selection 0x0 = Boot from device bus 0x1 = Boot from SPI 0x2 = Boot from CE don’t care NAND Flash 0x3 = Boot from CE care NAND Flash If DEV_AD[24:23] is set to 0x3, MPP[19:18] pins wake up as NAND Flash outputs. NOTE: Internally pulled down to 0x0. DEV_AD[26:25] VDDO_B NAND Flash Initialization Sequence Selects if NAND Flash initialization sequence is performed. Required for NAND Flash devices that do not support preload feature. Only relevant if DEV_AD[24] is set to 1 (boot from NAND Flash). 0x0 = No initialization 0x1 = Init sequence enabled, 3 address cycles 0x2 = Init sequence enabled, 4 address cycles 0x3 = Init sequence enabled, 5 address cycles NOTE: Internally pulled down to 0x0. DEV_AD[27] VDDO_B Big Endian/Little Endian mode 0 = Little Endian 1 = Big Endian NOTE: Internally pulled down to 0x0.
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System Power Up and Reset Settings
Pins Sample Configuration
Table 22: Reset Configuration (Continued)
Pi n DEV_AD[28] Po w e r R a il VDDO_B C o n fi gu r a t io n F u nc t io n CLK25 Select 0 = Both CLK25_PT and CLK25_SSC are used. 1 = Only CLK25_PT is used. NOTE: Internally pulled up to 0x1. DEV_AD[29] VDDO_B DRAM Interface Width 0 = 64/72-bits 1 = 32/40-bits NOTE: Internally pulled to 0x0. DEV_AD[30] VDDO_B NAND Flash Initialization Command Selects whether to append command 0x30 to the address cycles of the NAND Flash initialization sequence or not. Relevant only when using the NAND Flash initialization sequence (DEV_AD[26:25] != 0x0). 0 = Do not append command 0x30. 1 = Append command 0x30. NOTE: Internally pulled to 0x0. DEV_AD[31] VDDO_B VDDO_C Voltage Select 0 = 1.8V 1 = 3.3V NOTE: Internally pulled up to 0x1. DEV_ALE[0] VDDO_C VDDO_B Voltage Select 0 = 1.8V 1 = 3.3V NOTE: Internally pulled up to 0x1. DEV_ALE[1] VDDO_C VDDO_D Voltage Select 0 = 1.8V 1 = 3.3V NOTE: Internally pulled up to 0x1. DEV_WEn[0] VDDO_C VDD_GE Voltage Select 0 = 1.8V 1 = 3.3V NOTE: Internally pulled down to 0x0.
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MV78100 Hardware Specifications
Table 22: Reset Configuration (Continued)
Pi n DEV_WEn[1] Po w e r R a il VDDO_C C o n fi gu r a t io n F u nc t io n DEV_WEn and DEV_OEn multiplexing option for A[16:15] bits Defines if OE and WE are latched at first ALE cycle as A[15] and A[16]. This fact influences the OEn and WEn signal as follows: 0 = A[16:15] bits are not multiplexed on OE and WE signals. NOTE: Whenever CS is inactive OE and WE are inactive. 1 = A[16:15] bits are multiplexed on OE and WE signals NOTE: Whenever CS is inactive and ALE[1:0] are high, OE and WE are inactive. NOTE: Internally pulled down to 0x0. DEV_WEn[2] VDDO_C Reserved This signal must be sampled as 0 at reset de-assertion. NOTE: Internally pulled down to 0x0. DEV_WEn[3] VDDO_C Reserved This signal must be sampled as 0 at reset de-assertion. NOTE: Internally pulled down to 0x0. DEV_A[0] VDDO_C TCLK Mode Select 0 = TCLK is driven from TCLK_IN input (De-skew mode) 1 = TCLK generated internally by TCLK PLL NOTE: Internally pulled up to 0x1. DEV_A[2:1] VDDO_C TCLK frequency select/TCLK De-skew PLL Tune If DEV_A[0] is set to 1 - DEV_A[2:1] functions as TCLK frequency select: 0x0 = 166 MHz 0x1 = 200 MHz 0x2, 0x3 = Reserved If DEV_A[0] is set to 0, DEV_A[2:1] functions as TCLK de-skew PLL Tune. A setting recommendation will be released after chip silicon testing. When using TCLK_IN input Board design should support future pull up/pull down requirement on these pins. A final setting recommendation will be published following silicon samples. NOTE: Internally pulled to 0x1. GE0_TXD[0] VDD_GE TCLK De-skewer PLL Frequency Band Select Functions as TCLK De-Skewer PLL Frequency band select. Relevant for De-skew mode only (DEV_A[0] is set to 0) . 0 = 166 MHz 1 = 200 MHz NOTE: Internally pulled down to 0x0.
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System Power Up and Reset Settings
Power Up and Boot Sequence
Table 22: Reset Configuration (Continued)
Pi n GE0_TXD[1] Po w e r R a il VDD_GE C o n fi gu r a t io n F u nc t io n Reserved This signal must be sampled as 1 at reset de-assertion. NOTE: Internally pulled up to 0x1. GE0_TXD[3:2] VDD_GE DEV_ALE Mode Select Defines DEV_ALE[1:0] behaviour in respect to address driven by device bus controller (address setup and hold time in respect to DEV_ALE falling edge). Useful for device bus topologies in which DEV_AD bus is heavily loaded. 0x0 = Address is driven for two TCLK cycles. ALE toggles after one TCLK cycle. 0x1 = Address is driven for three TCLK cycles. ALE toggles after two TCLK cycles. 0x2 = Address is driven for four TCLK cycles. ALE toggles after three TCLK cycles. 0x3 = Reserved NOTE: Internally pulled down to 0x0. GE0_TXCTL VDD_GE Reserved This signal must be sampled as 0 at reset de-assertion. NOTE: Internally pulled down to 0x0.
Even if using a 8/16-bit device, the reset sampling on the upper device bus is still used. Note
7.5
Power Up and Boot Sequence
The MV78100 requires that SYSRSTn remain asserted for at least 1 ms after power and clocks are stable. The following procedure describes the boot sequence starting with the reset assertion: 1. While SYSRSTn is asserted, the PCLK, TCLK, and CLK125 PLLS are locked. SYSRSTn assertion should be at least 1 ms. 2. Upon SYSRSTn de-assertion, the pad drive auto-calibration process starts. It takes 512 TCLK cycles. 3. In parallel, TCLK de-skew PLL locks when working in de-skew mode. 4. If configured to boot from NAND Flash which does not support preload operation, the MV78100 also performs a NAND Flash boot init sequence. Upon completing the above sequence, the CPU reset is deasserted, and CPU starts executing boot code from DEV_BOOTCSn (whether it is a NOR Flash or a NAND Flash or from SPI Flash).
As part of the CPU boot code, the CPU typically performs the following: Change the chip default address map if required, and configure PCI-Express address map. Configure device bus timing parameters according to devices attached to device bus.
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MV78100 Hardware Specifications
Configures the proper DRAM controller parameters, and then triggers DRAM initialization (set DRAM Initialization Control register’s bit [0] to 1). If using DRAM ECC, also initializes DRAM content. Initializes proper ECC to the entire DRAM space. Set the bits in the CPU Control and Status register to wake up the PCI Express link.
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JTAG Interface
8
J_TDI J_TCLK J_TRST J_TMS_CPU
JTAG Interface
The MV78100 JTAG interface is used for chip boundary scan as well as for CPU cores debugger. TAP controllers implementation is described in the diagram below.
Figure 5: MV78100 TAP Controller
CPU TAP Controller
CPU TDO J_TDO
MV78100 TAP Controller J_TMS_CORE Boundary Scan TDO
The MV78100 supports the following test modes: Boundary scan: In this mode, keep J_TMS_CPU high; this will reset the CPUs TAP controllers and mux the boundary scan TDO signal on the J_TDO pin. CPU debugger: In this mode, keep J_TMS_CORE high; this will reset the MV78100 TAP controller and mux the CPU TDO signal on the J_TDO pin.
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MV78100 Hardware Specifications
9
9.1
Electrical Specifications (Preliminary)
The numbers specified in this section are PRELIMINARY and SUBJECT TO CHANGE. Note
Absolute Maximum Ratings
Table 23: Absolute Maximum Ratings
Parameter VDD IREF_AVDD VDD_CPU PLL_AVDD VDD_GE Min -0.5 -0.5 -0.5 -0.5 -0.5 Max 1.32 2.2 1.32 2.2 4.0 U n its V V V V V C o m m e n ts Core voltage SATA and USB PHYs current source voltage filtered 1.8V CPU core voltage Analog supply for the internal PLL I/O voltage for: RGMII/GMII/MII/SMI interfaces I/O voltage for: SDRAM DDR2 interface Reference voltage for: SDRAM DDR2 interface I/O voltage for: TWSI1, JTAG, and SPI interfaces I/O voltage for: Device Bus, TWSI0, UART interfaces, MPP, REF_CLK_SSC, REF_CLK_PT, and SYSRSTn Voltage for: PCI Express interface I/O voltage for: USB interface
VDD_M
-0.5
2.2
V
M_VREF
-0.5
1.1
V
VDDO_A
-0.5
4.0
V
VDDO_B, VDDO_C, VDDO_D PEX0_AVDD, PEX1_AVDD USB0_AVDD, USB1_AVDD, USB2_AVDD SATA0_AVDD, SATA1_AVDD TC TSTG
-0.5
4.0
V
-0.5
2.2
V
-0.5
4.0
V
-0.5
3.0
V
I/O voltage for: SATA interface Case temperature Storage temperature
-40 -40
125 125
°C °C
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Electrical Specifications (Preliminary)
Absolute Maximum Ratings
Caution
Exposure to conditions at or beyond the maximum rating can damage the device. Operation beyond the recommended operating conditions (Table 24) is neither recommended nor guaranteed.
Note
Before designing a system, it is recommended that you read application note AN-63: Thermal Management for Marvell Technology Products. This application note presents basic concepts of thermal management for Integrated Circuits (ICs) and includes guidelines to ensure optimal operating conditions for Marvell Technology's products.
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MV78100 Hardware Specifications
9.2
Recommended Operating Conditions
Table 24: Recommended Operating Conditions
Parameter VDD IREF_AVDD M in 0.95 1.7 Ty p 1.0 1.8 Max 1.05 1.9 Units V V C o m m e nts Core voltage SATA and USB PHYs current source voltage filtered 1.8V CPU core voltage Analog supply for the internal PLL I/O voltage for: RGMII/SMI 1.8V interfaces NOTE: VDD_GE can be set to either 1.8V or 3.3V according to Section 7.2, Hardware Reset, on page 51. I/O voltage for: RGMII/GMII/MII/SMI 3.3V interfaces I/O voltage for: SDRAM DDR2 interface Reference voltage for: SDRAM DDR2 interface I/O voltage for: TWSI1, JTAG, and SPI interfaces I/O voltage for: Device Bus, TWSI0, UART interfaces, and MPP NOTE: VDDO_B, VDDO_C, and VDDO_D can be set to either 1.8V or 3.3V according to Section 7.2, Hardware Reset, on page 51. Voltage for: PCI Express interface I/O voltage for: USB interface
VDD_CPU PLL_AVDD VDD_GE
1.05 1.7 1.7
1.1 1.8 1.8
1.15 1.9 1.9
V V V
3.15
3.3
3.45
V
VDD_M
1.7
1.8
1.9
V
M_VREF
0.49*VDD_ M 3.15
0.5*VDD_M
0.51*VDD_M
V
VDDO_A
3.3
3.45
V
VDDO_B, VDDO_C, VDDO_D
1.7 3.15
1.8 3.3
1.9 3.45
V V
PEX0_AVDD, PEX1_AVDD USB0_AVDD, USB1_AVDD, USB2_AVDD SATA0_AVDD, SATA1_AVDD TJ
1.7
1.8
1.9
V
3.15
3.3
3.45
V
2.375
2.5
2.625
V
Voltage for: SATA interface Junction Temperature
0
105
°C
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Electrical Specifications (Preliminary)
Recommended Operating Conditions
Caution
Operation beyond the recommended operating conditions is neither recommended nor guaranteed.
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MV78100 Hardware Specifications
9.3
Thermal Power Dissipation (Preliminary)
.
Table 25: Thermal Power Dissipation
In t e r f a c e Core Embedded CPU RGMII 1.8V interface DDR2 DIMM interface (72-bit) ODT Miscellaneous (Device Bus interface, TWSI, JTAG, MPP, SPI, UART) PCI Express interface S y m bo l PVDD PVDD_CPU PVDD_GE PVDD_M PMISC 1 GHz, VDD_CPU=1.1V One Port, VDD_GE=1.8V M_CLK=333 MHz Te s t C on d it io n s Ty p 1200 2100 90 1675 300 Un its mW mW mW mW mW
PPEX PUSB PSATA
For one PCI Express interface in x4 mode For one USB port For one SATA port
400
mW
USB interface SATA interface
70 180
mW mW
Notes: 1. 2. 3. The values are for nominal voltage. Trace load is 5 pF unless otherwise specified. Power in mW is calculated using the typical recommended VDDIO specification for each power rail.
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Electrical Specifications (Preliminary)
Current Consumption (Preliminary)
9.4
Current Consumption (Preliminary)
.
Table 26: Current Consumption
In t e r f a c e Core Embedded CPU RGMII 1.8V interface DDR2 DIMM interface (72-bit) ODT Miscellaneous (Device Bus interface, TWSI, JTAG, MPP, SPI, UART) PCI Express interface S y m bo l IVDD IVDD_CPU IVDD_GE IVDD_M IMISC 1 GHz, VDD_CPU=1.1V One Port, VDD_GE=1.8V M_CLK=333 MHz Te s t C on d it io n s Max 1500 2300 50 1200 90 Units mA mA mA mA mA
IPEX IUSB ISATA
For one PCI Express interface in x4 mode For one USB port For one SATA port
220
mA
USB interface SATA interface
25 75
mA mA
Notes: 1. 2. 3. 4. Trace load is 5 pF unless otherwise specified. Current in mA is calculated using maximum recommended VDDIO specification for each power rail. All output clocks toggling at their specified rate. Maximum drawn current from the power supply.
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9.5
DC Electrical Specifications
See the Pin Description Section for internal pullup/pulldown, Note
9.5.1
General 3.3V (CMOS) DC Electrical Specifications
Table 27 is relevant for the following interfaces that only operate at 3.3V: SPI JTAG Table 27 is also relevant if the following interfaces are configured to operate at 3.3V, according to Section 7.2, Hardware Reset, on page 51. Device Bus MPP RGMII GMII MII SMI TDM SYSRSTn UART REF_CLK_PT TCLK_OUT TCLK_IN
Table 27: General 3.3V Interface (CMOS) DC Electrical Specifications
Param eter Input low level Input high level Output low level Output high level Input leakage current Pin capacitance Sym bol VIL VIH VOL VOH IIL Cpin IOL = 2 mA IOH = -2 mA 0 < VIN < VDDIO Test Condition Min -0.3 2.0 2.4 -10 5 Typ Max 0.8 VDDIO+0.3 0.4 10 Units Notes V V V V uA pF 1, 2 -
Notes: 1. While I/O is in High-Z. 2. This current does not include the current flow ing through the pullup/pulldow n resistor.
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Electrical Specifications
DC Electrical Specifications
9.5.2
General 1.8V (CMOS) DC Electrical Specifications
Table 27 is relevant if the following interfaces are configured to operate at 1.8V, according to Section 7.2, Hardware Reset, on page 51. Device Bus MPP GMII MII RGMII SMI TDM SYSRSTn UART REF_CLK_PT REF_CLK_SSC TCLK_OUT TCLK_IN
Table 28: General 1.8V Interface (CMOS) DC Electrical Specifications
Param eter Input low level Input high level Output low level Output high level Input leakage current Pin capacitance Sym bol VIL VIH VOL VOH IIL Cpin IOL = 2 mA IOH = -2 mA 0 < VIN < VDDIO Test Condition Min -0.3 0.65*VDDIO VDDIO-0.45 -10 5 Typ Max 0.35*VDDIO VDDIO+0.3 0.45 10 Units Notes V V V V uA pF 1, 2 -
Notes: 1. While I/O is in High-Z. 2. This current does not include the current flow ing through the pullup/pulldow n resistor.
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9.5.3
SDRAM DDR2 Interface DC Electrical Specifications
Parameter Symbol VIL VIH VOL VOH RTT IOL = 13.4 mA IOH = -13.4 mA See note 2 1.42 120 150 75 50 180 90 60 6 10 5 Test Condition Min -0.3 VREF + 0.125 Typ Max VREF - 0.125 VDDIO + 0.3 0.28 Units Notes V V V V ohm ohm ohm % uA pF 1,2 1,2 1,2 3 4, 5 -
Table 29: SDRAM DDR2 Interface DC Electrical Specifications
Input low level Input high level Output low level Output high level Rtt effective impedance value
60 40
Deviation of VM w ith respect to VDDQ/2 Input leakage current Pin capacitance
dVm IIL Cpin
See note 3 0 < VIN < VDDIO -
-6 -10
Notes: 1. See SDRAM functional description section for ODT configuration. 2. Measurement definition for RTT: Apply VREF +/- 0.25 to input pin separately, then measure current I(VREF + 0.25) and I(VREF - 0.25) respectively.
RTT =
0 .5 I (VREF + 0.25 ) − I (VREF
− 0.25 )
3. Measurement definition for VM: Measured voltage (VM) at input pin (midpoint) w ith no load.
⎛ 2 × Vm ⎞ − 1 ⎟ × 100 % dVM = ⎜ ⎝ VDDIO ⎠
4. While I/O is in High-Z. 5. This current does not include the current flow ing through the pullup/pulldow n resistor.
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DC Electrical Specifications
9.5.4
Two-Wire Serial Interface (TWSI) 3.3V DC Electrical Specifications
Param eter Sym bol VIL VIH VOL IIL Cpin IOL = 3 mA 0 < VIN < VDDIO Test Condition Min -0.5 0.7*VDDIO -10 5 Typ Max 0.3*VDDIO VDDIO+0.5 0.4 10 Units Notes V V V uA pF 1, 2 -
Table 30: TWSI Interface 3.3V DC Electrical Specifications
Input low level Input high level Output low level Input leakage current Pin capacitance
Notes: 1. While I/O is in High-Z. 2. This current does not include the current flow ing through the pullup/pulldow n resistor.
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9.6
9.6.1
AC Electrical Specifications
See Section 9.7, Differential Interface Electrical Characteristics, on page 104 for differential interface specifications.
Reference Clock and Reset AC Timing Specifications
Table 31: Reference Clock and Reset AC Timing Specifications
D e s c r i p t io n Core Reference Clock Frequency FREF_CLK_SSC FREF_CLK_PT DCREF_CLK_SSC DCREF_CLK_PT SRREF_CLK_SSC SRREF_CLK_PT JRREF_CLK_SSC JRREF_CLK_PT 25 100 ppm 40 25 + 100 ppm 60 MHz Symbol Min Max U ni ts N ot e s
Clock duty cycle
%
Slew rate
0.7
V/ns
1
Pk-Pk jitter
200
ps
C o r e R e f e r e n c e C l o c k Sp r e a d Sp e c t r u m R e q u ir em e n ts Modulation Frequency Modulation Index E t h er n e t R e f e r e n c e C lo c k Frequency in MII-MAC mode FGE0_TXCLK FGE0_RXCLK MII clock duty cycle DCGE0_TXCLK DCGE0_RXCLK Slew rate SRGE0_TXCLK SRGE0_RXCLK S M I M a s t e r M o d e R e f e r e n c e C l o ck SMI output MDC clock T WS I M a s t er M o d e R e fe re n c e C lo c k SCK output clock FTWSI0_SCK, FTWSI1_SCK TCLK/1600 kHz FGE_MDC TCLK/128 MHz 0.7 V/ns 1 35 65 % 2.5 100 ppm 25 + 100 ppm MHz FmodREF_CLK_SSC FspreadREF_CLK_SSC 0 -0.5 33 0 kHz % 2 2
SP I O ut pu t C l o c k SPI output clock SPI output clock (Integrated with the TDM interface) FSPI_SCK FTDM_SCLK TCLK/30 TCLK/254 TCLK/4 TCLK/10 MHz MHz 6 7
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AC Electrical Specifications
Table 31: Reference Clock and Reset AC Timing Specifications
D e s c r i p t io n T C L K _ O U T R e fe r e n c e C lo c k Frequency Clock duty cycle TCLK_IN Reference Clock Frequency Clock duty cycle Slew rate Pk-Pk jitter R e s e t Sp e c if ic a t i o n s Refer to Section 7, System Power Up and Reset Settings. FTCLK_IN DCTCLK_IN SRTCLK_IN JRTCLK_IN 150 40 0.7 200 200 60 MHz % V/ns ps 1 4 FTCLK_OUT DCTCLK_OUT 40 166 60 MHz % 3 Symbol Min Max U ni ts N ot e s 5
Notes: 1. 2. 3. 4. 5. 6. 7. Slew rate is defined from 20% to 80% of the reference clock signal. Defined on linear sweep or “Hershey’s Kiss” (US Patent 5,631,920) modulations. The load is CL = 15 pF. See Table 22, Reset Configuration, on page 52 for more details. Relevant only when working in source synchronous device bus mode. For additional information regarding configuring this clock, see the Serial Memory Interface Control Register in the MV76100, MV78100, and MV78200 Functional Specification. For additional information regarding configuring this clock, see the TDM Interface section in the MV76100, MV78100, and MV78200 Functional Specifications.
Figure 6: TCLK_Out Reference Clock Test Circuit
Test Point
CL
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Figure 7: TCLK_Out AC Timing Diagram
Cycle Time
VDDIO/2
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9.6.2
9.6.2.1
Reduced Gigabit Media Independent Interface (RGMII) AC Timing
RGMII AC Timing Table
Description Sym bol fCK Tskew T Tskew R Tcyc Duty_G Duty_T Min -0.50 1.00 7.20 0.45 0.40 Max 125.0 0.50 2.60 8.80 0.55 0.60 Units Notes MHz ns ns ns tCK tCK 2 1,2 2 2
Table 32: RGMII AC Timing Table
Clock frequency Data to Clock output skew Data to Clock input skew Clock cycle duration Duty cycle for Gigabit Duty cycle for 10/100 Megabit Notes:
General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified. General comment: tCK = 1/fCK. General comment: If the PHY does not support internal-delay mode, the PC board design requires routing clocks so that an additional trace delay of greater than 1.5 ns and less than 2.0 ns is added to the associated clock signal. For 10/100 Mbps RGMII, the Max value is unspecified. 1. For RGMII at 10 Mbps and 100 Mbps, Tcyc w ill scale to 400 ns +/-40 ns and 40 ns +/-4 ns, respectively. 2. For all signals, the load is CL = 5 pF.
9.6.2.2
RGMII Test Circuit
Figure 8: RGMII Test Circuit
Test Point
CL
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9.6.2.3
RGMII AC Timing Diagram
Figure 9: RGMII AC Timing Diagram
TX CLOCK (At Transmitter) TX DATA TskewT
RX CLOCK (At Receiver) RX DATA
TskewR
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9.6.3
9.6.3.1
Media Independent Interface (MII) AC Timing
MII AC Timing Table
Description Sym bol tSU tHD tOV Min 8.0 8.0 0.0 Max 20.0 Units ns ns ns Notes 1
Table 33: MII AC Timing Table
Data input setup relative to RX_CLK rising edge Data input hold relative to RX_CLK rising edge Data output delay relative to MII_TX_CLK rising edge
Notes: General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified. 1. For all signals, the load is CL = 5 pF.
9.6.3.2
MII Test Circuit
Figure 10: MII Test Circuit
Test Point
CL
9.6.3.3
MII AC Timing Diagrams
Figure 11: MII Output Delay AC Timing Diagram
Vih(min) MII_TX_CLK Vil(max) Vih(min) TXD, TX_EN, TX_ER
TOV
Vil(max)
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Figure 12: MII Input AC Timing Diagram
Vih(min) RX_CLK
Vih(min) RXD, RX_EN, RX_ER
tSU tHD
Vil(max)
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9.6.4
9.6.4.1
Gigabit Media Independent Interface (GMII) AC Timing
GMII AC Timing Table
125 MHz Description Sym bol tCK tCKrx tHIGH tLOW tR tF tSETUP tHOLD tOVB tOVA Min 7.5 7.5 2.5 2.5 2.0 0.0 2.5 0.5 Max 8.5 1.0 1.0 Units ns ns ns ns ns ns ns ns ns ns Notes 1 1 1, 2 1, 2 1 1
Table 34: GMII AC Timing Table
GTX_CLK cycle time RX_CLK cycle time GTX_CLK and RX_CLK high level w idth GTX_CLK and RX_CLK low level w idth GTX_CLK and RX_CLK rise time GTX_CLK and RX_CLK fall time Data input setup time relative to RX_CLK rising edge Data input hold time relative to RX_CLK rising edge Data output valid before GTX_CLK rising edge Data output valid after GTX_CLK rising edge
Notes: General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified. 1. For all signals, the load is CL = 5 pF. 2. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max).
9.6.4.2
GMII Test Circuit
Figure 13: GMII Test Circuit
Test Point
CL
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9.6.4.3
GMII AC Timing Diagrams
Figure 14: GMII Output AC Timing Diagram
tLOW tHIGH
VIH(min) GTX_CLK VIL(max) VIH(min) TXD, TX_EN, TX_ER VIL(max)
tOVB
tOVA
Figure 15: GMII Input AC Timing Diagram
tLOW tHIGH
VIH(min) RX_CLK VIL(max) VIH(min) RXD, RX_EN, RX_ER tSETUP VIL(max)
tHOLD
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9.6.5
9.6.5.1
Serial Management Interface (SMI) AC Timing
SMI Master Mode AC Timing Table
Description Sym bol
fCK tDC tSU tHO tOVB tOVA
Table 35: SMI Master Mode AC Timing Table
Min Max Units
MHz tCK ns ns ns ns
Notes
2 1 1
MDC clock frequency MDC clock duty cycle MDIO input setup time relative to MDC rise time MDIO input hold time relative to MDC rise time MDIO output valid before MDC rise time MDIO output valid after MDC rise time
See note 2 0.4 40.0 0.0 15.0 15.0 0.6 -
Notes:
General comment: All timing values w ere measured from VIL(max) and VIH(min) levels, unless otherw ise specified. General comment: tCK = 1/fCK. 1. For MDC signal, the load is CL = 390 pF, and for MDIO signal, the load is CL = 470 pF. 2. See "Reference Clocks" table for more details.
9.6.5.2
SMI Master Mode Test Circuit
Figure 16: MDIO Master Mode Test Circuit
VDDIO Test Point 2 kilohm
MDIO CL
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Figure 17: MDC Master Mode Test Circuit
Test Point
MDC CL
9.6.5.3
SMI Master Mode AC Timing Diagrams
Figure 18: SMI Master Mode Output AC Timing Diagram
VIH(min) MDC
VIH(min) MDIO VIL(max)
tOVB tOVA
Figure 19: SMI Master Mode Input AC Timing Diagram
VIH(min) MDC
VIH(min) MDIO VIL(max)
tSU
tHO
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9.6.6
9.6.6.1
SDRAM DDR2 Interface AC Timing
SDRAM DDR2 400 MHz Interface AC Timing Table
400 MHz @ 1.8V Description Sym bol
fCK tDOVB tDOVA tDIPW tDQSH tDQSL tDSS tDSH tDQSS tWPRE tWPST tCH tCL tDSI tDHI tIPW 0.38 0.38 0.35 0.35 0.35 0.34 0.34 -0.11 0.35 0.41 0.48 0.48 -0.40 0.60 0.67
Table 36: SDRAM DDR2 400 MHz Interface AC Timing Table
Min
400.0 0.11 0.52 0.52 -
Max
Units
MHz ns ns tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) ns ns tCK(avg)
Notes
1 1 1, 2, 3 1, 2, 4 -
Clock frequency DQ and DM valid output time before DQS transition DQ and DM valid output time after DQS transition DQ and DM output pulse w idth DQS output high pulse w idth DQS output low pulse w idth DQS falling edge to CLK-CLKn rising edge DQS falling edge from CLK-CLKn rising edge CLK-CLKn rising edge to DQS output rising edge DQS w rite preamble DQS w rite postamble CLK-CLKn high-level w idth CLK-CLKn low -level w idth DQ input setup time relative to DQS in transition DQ input hold time relative to DQS in transition Address and control output pulse w idth
Notes:
General comment: All timing values w ere measured from vref to vref, unless otherw ise specified. General comment: All input timing values assume minimum slew rate of 1 V/ns (slew rate measured from Vref +/-125 mV). General comment: All timing parameters w ith DQS signal are defined on DQS-DQSn crossing point. General comment: For Address and Control output timing parameters, refer to the Address Timing table. General comment: tCK = 1/fCK. General comment: For all signals, the load is CL = 14 pF. 1. This timing value is defined on CLK / CLKn crossing point. 2. Refer to SDRAM DDR2 clock specifications table for more information. 3. tCH(avg) is defined as the average HIGH pulse w idth, as calculated across any consecutive 200 HIGH pulses. 4. tCL(avg) is defined as the average LOW pulse w idth, as calculated across any consecutive 200 LOW pulses.
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Table 37: SDRAM DDR2 400 MHz Interface Address and Control Timing Table
400 MHz @ 1.8V Description Address and Control invalid output time before CLK-CLkn rising edge Address and Control invalid output time after CLK-CLKn rising edge Address and Control valid output time before CLK-CLkn rising edge Address and Control valid output time after CLK-CLKn rising edge Address and Control valid output time before CLK-CLkn rising edge Address and Control valid output time after CLK-CLKn rising edge Sym bol tAOIB tAOIA tAOVB tAOVA tAOVB tAOVA Min 0.95 0.95 1.50 0.45 Max 0.20 0.40 Units ns ns ns ns ns ns Notes 1, 3 1, 3 1, 2 1, 2 1, 4 1, 4
Notes: General comment: All timing values w ere measured from vref to vref, unless otherw ise specified. General comment: For all signals, the load is CL = 14 pF. 1. This timing value is defined on CLK / CLKn crossing point. 2. This timing value is defined w hen Address and Control signals are output on CLK-CLKn falling edge. For more information, see register settings. 3. This timing value is defined w hen Address and Control signals are output on CLK-CLKn rising edge (1T and 2T configurations). For more information, see register settings. 4. This timing value is defined w hen Address and Control signals are output ¼ cycle after CLK-CLKn rising edge.
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9.6.6.2
SDRAM DDR2 400 MHz Clock Specifications
Description Sym bol tJIT(per) tJIT(per,lck) tJIT(cc) tJIT(cc,lck) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6-10per) tERR(11-50per) tJIT(duty) tCK(abs) tCH(abs) tCL(abs) Min -100 -80 -200 -160 -150 -175 -200 -200 -300 -450 -100 Max 100 80 200 160 150 175 200 200 300 450 100 Units ps ps ps ps ps ps ps ps ps ps ps ps ps ps Notes 1 2 3 4 5 5 5 5 5 5 6 7 8 9
Table 38: SDRAM DDR2 400 MHz Clock Specifications
Clock period jitter Clock perior jitter during DLL locking period Cycle to cycle clock period jitter Cycle to cycle clock period jitter during DLL locking period Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across n cycles, n=6...10, inclusive Cumulative error across n cycles, n=11…50, inclusive Duty cycle jitter Absolute clock period Absolute clock high pulse w idth Absolute clock low pulse w idth
See note 7 See note 8 See note 9
Notes: General comment: All timing values are defined on CLK / CLKn crossing point, unless otherw ise specified. 1. tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = Min/max of {tCKi- tCK(avg) w here i=1 to 200}. tJIT(per) defines the single period jitter w hen the DLL is already locked. 2. tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only. 3. tJIT(cc) is defined as the difference in clock period betw een tw o consecutive clock cycles: tJIT(cc) = Max of |tCKi+1 – tCKi|. tJIT(cc) defines the cycle to cycle jitter w hen the DLL is already locked. 4. tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only. 5. tERR(nper) is defined as the cumulative error across multiple consecutive cycles from tCK(avg). Refer to JEDEC Standard No. 79-2 (DDR2 SDRAM Specification) for more information. 6. tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH(avg). tCL jitter is the largest deviation of any single tCL from tCL(avg). tJIT(duty) = Min/max of {tJIT(CH), tJIT(CL)} w here, tJIT(CH) = {tCHi- tCH(avg) w here i=1 to 200}; tJIT(CL) = {tCLi- tCL(avg) w here i=1 to 200}. 7. tCK(abs),min = tCK(avg),min + tJIT(per),min; tCK(abs),max = tCK(avg),max + tJIT(per),max. 8. tCH(abs),min = tCH(avg),min x tCK(avg),min + tJIT(duty),min; tCH(abs),max = tCH(avg),max x tCK(avg),max + tJIT(duty),max. 9. tCL(abs),min = tCL(avg),min x tCK(avg),min + tJIT(duty),min; tCL(abs),max = tCL(avg),max x tCK(avg),max + tJIT(duty),max.
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9.6.6.3
SDRAM DDR2 333 MHz Interface AC Timing Table
333 MHz @ 1.8V Description Sym bol fCK tDOVB tDOVA tDIPW tDQSH tDQSL tDSS tDSH tDQSS tWPRE tWPST tCH tCL tDSI tDHI tIPW 0.45 0.45 0.35 0.35 0.35 0.34 0.34 -0.11 0.35 0.41 0.48 0.48 -0.50 0.75 0.67 Min 333.0 0.11 0.52 0.52 Max Units MHz ns ns tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) ns ns tCK(avg) Notes 1 1 1, 2, 3 1, 2, 4 -
Table 39: SDRAM DDR2 333 MHz Interface AC Timing Table
Clock frequency DQ and DM valid output time before DQS transition DQ and DM valid output time after DQS transition DQ and DM output pulse w idth DQS output high pulse w idth DQS output low pulse w idth DQS falling edge to CLK-CLKn rising edge DQS falling edge from CLK-CLKn rising edge CLK-CLKn rising edge to DQS output rising edge DQS w rite preamble DQS w rite postamble CLK-CLKn high-level w idth CLK-CLKn low -level w idth DQ input setup time relative to DQS in transition DQ input hold time relative to DQS in transition Address and control output pulse w idth
Notes: General comment: All timing values w ere measured from vref to vref, unless otherw ise specified. General comment: All input timing values assume minimum slew rate of 1 V/ns (slew rate measured from Vref +/-125 mV). General comment: All timing parameters w ith DQS signal are defined on DQS-DQSn crossing point. General comment: For Address and Control output timing parameters, refer to the Address Timing table. General comment: tCK = 1/fCK. General comment: For all signals, the load is CL = 14 pF. 1. This timing value is defined on CLK / CLKn crossing point. 2. Refer to SDRAM DDR2 clock specifications table for more information. 3. tCH(avg) is defined as the average HIGH pulse w idth, as calculated across any consecutive 200 HIGH pulses. 4. tCL(avg) is defined as the average LOW pulse w idth, as calculated across any consecutive 200 LOW pulses.
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Table 40: SDRAM DDR2 333 MHz Interface Address and Control Timing Table
333 MHz @ 1.8V Description Address and Control invalid output time before CLK-CLkn rising edge Address and Control invalid output time after CLK-CLKn rising edge Address and Control valid output time before CLK-CLkn rising edge Address and Control valid output time after CLK-CLKn rising edge Sym bol tAOIB tAOIA tAOVB tAOVA Min 1.00 1.00 Max 0.28 0.28 Units ns ns ns ns Notes 1, 3 1, 3 1, 2 1, 2
Notes: General comment: All timing values w ere measured from vref to vref, unless otherw ise specified. General comment: For all signals, the load is CL = 14 pF. 1. This timing value is defined on CLK / CLKn crossing point. 2. This timing value is defined w hen Address and Control signals are output on CLK-CLKn falling edge. For more information, see register settings. 3. This timing value is defined w hen Address and Control signals are output on CLK-CLKn rising edge (1T and 2T configurations). For more information, see register settings.
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9.6.6.4
SDRAM DDR2 333 MHz Clock Specifications
Description Sym bol tJIT(per) tJIT(per,lck) tJIT(cc) tJIT(cc,lck) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6-10per) tERR(11-50per) tJIT(duty) tCK(abs) tCH(abs) tCL(abs) Min -125 -100 -250 -200 -175 -225 -250 -250 -350 -450 -125 Max 125 100 250 200 175 225 250 250 350 450 125 Units ps ps ps ps ps ps ps ps ps ps ps ps ps ps Notes 1 2 3 4 5 5 5 5 5 5 6 7 8 9
Table 41: SDRAM DDR2 333 MHz Clock Specifications
Clock period jitter Clock perior jitter during DLL locking period Cycle to cycle clock period jitter Cycle to cycle clock period jitter during DLL locking period Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across n cycles, n=6...10, inclusive Cumulative error across n cycles, n=11…50, inclusive Duty cycle jitter Absolute clock period Absolute clock high pulse w idth Absolute clock low pulse w idth
See note 7 See note 8 See note 9
Notes: General comment: All timing values are defined on CLK / CLKn crossing point, unless otherw ise specified. 1. tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = Min/max of {tCKi- tCK(avg) w here i=1 to 200}. tJIT(per) defines the single period jitter w hen the DLL is already locked. 2. tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only. 3. tJIT(cc) is defined as the difference in clock period betw een tw o consecutive clock cycles: tJIT(cc) = Max of |tCKi+1 – tCKi|. tJIT(cc) defines the cycle to cycle jitter w hen the DLL is already locked. 4. tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only. 5. tERR(nper) is defined as the cumulative error across multiple consecutive cycles from tCK(avg). Refer to JEDEC Standard No. 79-2 (DDR2 SDRAM Specification) for more information. 6. tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH(avg). tCL jitter is the largest deviation of any single tCL from tCL(avg). tJIT(duty) = Min/max of {tJIT(CH), tJIT(CL)} w here, tJIT(CH) = {tCHi- tCH(avg) w here i=1 to 200}; tJIT(CL) = {tCLi- tCL(avg) w here i=1 to 200}. 7. tCK(abs),min = tCK(avg),min + tJIT(per),min; tCK(abs),max = tCK(avg),max + tJIT(per),max. 8. tCH(abs),min = tCH(avg),min x tCK(avg),min + tJIT(duty),min; tCH(abs),max = tCH(avg),max x tCK(avg),max + tJIT(duty),max. 9. tCL(abs),min = tCL(avg),min x tCK(avg),min + tJIT(duty),min; tCL(abs),max = tCL(avg),max x tCK(avg),max + tJIT(duty),max.
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9.6.6.5
SDRAM DDR2 266 MHz Interface AC Timing Table
266 MHz @ 1.8V Description Sym bol fCK tDOVB tDOVA tDIPW tDQSH tDQSL tDSS tDSH tDQSS tWPRE tWPST tCH tCL tDSI tDHI tAOVB tAOVA tIPW 0.42 0.42 0.35 0.35 0.35 0.34 0.34 -0.11 0.35 0.41 0.45 0.45 -0.50 1.20 2.90 0.30 0.67 Min 266.0 0.11 0.55 0.55 Max Units MHz ns ns tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK ns ns ns ns tCK Notes 1 1 1 1 1, 2 1, 2 -
Table 42: SDRAM DDR2 266 MHz Interface AC Timing Table
Clock frequency DQ and DM valid output time before DQS transition DQ and DM valid output time after DQS transition DQ and DM output pulse w idth DQS output high pulse w idth DQS output low pulse w idth DQS falling edge to CLK-CLKn rising edge DQS falling edge from CLK-CLKn rising edge CLK-CLKn rising edge to DQS output rising edge DQS w rite preamble DQS w rite postamble CLK-CLKn high-level w idth CLK-CLKn low -level w idth DQ input setup time relative to DQS in transition DQ input hold time relative to DQS in transition Address and Control valid output time before CLK-CLkn rising edge Address and Control valid output time after CLK-CLKn rising edge Address and control output pulse w idth
Notes: General comment: All timing values w ere measured from vref to vref, unless otherw ise specified. General comment: All input timing values assume minimum slew rate of 1 V/ns (slew rate measured from Vref +/-125 mV). General comment: tCK = 1/fCK. General comment: For all signals, the load is CL = 16 pF. 1. This timing value is defined on CLK / CLKn crossing point. 2. This timing value is defined w hen Address and Control signals are output ¼tCK after CLK-CLKn rising edge. For more information, see register settings.
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MV78100 Hardware Specifications
9.6.6.6
SDRAM DDR2 200 MHz Interface AC Timing Table
200 MHz @ 1.8V Description Sym bol fCK tDOVB tDOVA tDIPW tDQSH tDQSL tDSS tDSH tDQSS tWPRE tWPST tCH tCL tDSI tDHI tAOVB tAOVA tIPW 0.50 0.50 0.35 0.35 0.35 0.34 0.34 -0.11 0.35 0.41 0.45 0.45 -0.55 1.50 2.25 0.80 0.67 Min 200.0 0.11 0.55 0.55 Max Units MHz ns ns tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK ns ns ns ns tCK Notes 1 1 1 1 1, 2 1, 2 -
Table 43: SDRAM DDR2 200 MHz Interface AC Timing Table
Clock frequency DQ and DM valid output time before DQS transition DQ and DM valid output time after DQS transition DQ and DM output pulse w idth DQS output high pulse w idth DQS output low pulse w idth DQS falling edge to CLK-CLKn rising edge DQS falling edge from CLK-CLKn rising edge CLK-CLKn rising edge to DQS output rising edge DQS w rite preamble DQS w rite postamble CLK-CLKn high-level w idth CLK-CLKn low -level w idth DQ input setup time relative to DQS in transition DQ input hold time relative to DQS in transition Address and Control valid output time before CLK-CLkn rising edge Address and Control valid output time after CLK-CLKn rising edge Address and control output pulse w idth Notes:
General comment: All timing values w ere measured from vref to vref, unless otherw ise specified. General comment: All input timing values assume minimum slew rate of 1 V/ns (slew rate measured from Vref +/-125 mV). General comment: tCK = 1/fCK. General comment: For all signals, the load is CL = 16 pF. 1. This timing value is defined on CLK / CLKn crossing point. 2. This timing value is defined w hen Address and Control signals are output ¼tCK after CLK-CLKn rising edge. For more information, see register settings.
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9.6.6.7
SDRAM DDR2 Interface Test Circuit
Figure 20: SDRAM DDR2 Interface Test Circuit
VDDIO/2 Test Point 50 ohm
CL
9.6.6.8
SDRAM DDR2 Interface AC Timing Diagrams
Figure 21: SDRAM DDR2 Interface Write AC Timing Diagram
tDSH CLK CLKn DQS tWPRE DQSn tCH tCL tDSS
tDQSH
tDQSL
tWPST
tDIPW DQ
tDOVB tDOVA
Figure 22: SDRAM DDR2 Interface Address and Control AC Timing Diagram
CLK CLKn tCH tCL
ADDRESS/ CONTROL
tIPW
tAOVB
tAOVA
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Figure 23: SDRAM DDR2 Interface Read AC Timing Diagram
DQS DQSn
DQ tDSI tDHI
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AC Electrical Specifications
9.6.7
9.6.7.1
Serial Peripheral Interface (SPI) AC Timing
SPI (Master Mode) AC Timing Table
SPI Description Sym bol fCK tCH tCL tSR tDOV tCSB tCSA tSU tHD M in Max Units MHz tCK tCK V/ns ns ns ns tCK ns Notes 3 1 1 1 1 1 1 2 2
Table 44: SPI (Master Mode) AC Timing Table
SCLK clock frequency SCLK high time SCLK low time SCLK slew rate Data out valid relative to SCLK falling edge CS active before SCLK rising edge CS not active after SCLK rising edge Data in setup time relative to SCLK rising edge Data in hold time relative to SCLK rising edge
See Note 3 0.46 0.46 0.5 -2.5 8.0 8.0 0.2 5.0 2.5 -
Notes: General comment: All values w ere measured from 0.3*vddio to 0.7*vddio, unless otherw ise specified. General comment: tCK = 1/fCK. 1. For all signals, the load is CL = 10 pF. 2. Defined from vddio/2 to vddio/2. 3. See "Reference Clocks" table for more details.
9.6.7.2
SPI (Master Mode) Test Circuit
Figure 24: SPI (Master Mode) Test Circuit
Test Point
CL
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9.6.7.3
SPI (Master Mode) Timing Diagrams
Figure 25: SPI (Master Mode) Normal Output AC Timing Diagram
tCH SCLK tCL
Data Out tDOVmin tDOVmax CS
tCSB
tCSA
Figure 26: SPI (Master Mode) Normal Input AC Timing Diagram
SCLK
Data in
tSU
tHD
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AC Electrical Specifications
Figure 27: SPI (Master Mode) Opposite Output AC Timing Diagram
tCH SCLK
tCL
Data Out tDOVmin tDOVmax CS
tCSB
tCSA
Figure 28: SPI (Master Mode) Opposite Input AC Timing Diagram
SCLK
Data in
tSU
tHD
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9.6.8
9.6.8.1
Two-Wire Serial Interface (TWSI) AC Timing
TWSI AC Timing Table
Description Sym bol fCK tLOW tHIGH tSU tHD tr tf tOV Min Max Units kHz tCK tCK ns ns ns ns tCK Notes 1 2 2 2, 3 2, 3 2
Table 45: TWSI Master AC Timing Table
SCK clock frequency SCK minimum low level w idth SCK minimum high level w idth SDA input setup time relative to SCK rising edge SDA input hold time relative to SCK falling edge SDA and SCK rise time SDA and SCK fall time SDA output delay relative to SCK falling edge See note 1 0.47 0.40 250.0 0.0 0.0 1000.0 300.0 0.4
Notes: General comment: All values referred to VIH(min) and VIL(max) levels, unless otherw ise specified. General comment: tCK = 1/fCK. 1. See "Reference Clocks" table for more details. 2. For all signals, the load is CL = 100 pF, and RL value can be 500 ohm to 8 kilohm. 3. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max).
Table 46: TWSI Slave AC Timing Table
100 kHz (Max) Description SCK minimum low level w idth SCK minimum high level w idth SDA input setup time relative to SCK rising edge SDA input hold time relative to SCK falling edge SDA and SCK rise time SDA and SCK fall time SDA output delay relative to SCK falling edge Sym bol tLOW tHIGH tSU tHD tr tf tOV Min 4.7 4.0 250.0 0.0 0.0 Max 1000.0 300.0 4.0 Units us us ns ns ns ns us Notes 1 1 1, 2 1, 2 1
Notes: General comment: All values referred to VIH(min) and VIL(max) levels, unless otherw ise specified. 1. For all signals, the load is CL = 100 pF, and RL value can be 500 ohm to 8 kilohm. 2. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max).
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9.6.8.2
TWSI Test Circuit
Figure 29: TWSI Test Circuit
VDDIO Test Point RL
CL
9.6.8.3
TWSI AC Timing Diagrams
Figure 30: TWSI Output Delay AC Timing Diagram
tHIGH tLOW
Vih(min) SCK Vil(max)
Vih(min) SDA
tOV(min) tOV(max)
Vil(max)
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Figure 31: TWSI Input AC Timing Diagram
tLOW tHIGH
Vih(min) SCK Vil(max)
Vih(min) SDA Vil(max)
tSU
tHD
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9.6.9
9.6.9.1
Device Bus Interface AC Timing
Device Bus Interface AC Timing Table
Description Sym bol tSU tHD tOV tAOAB tAOAA Min 3.0 1.0 0.8 7.5 3.5 Max 3.5 Units ns ns ns ns ns Notes 1 1,2 1,2
Table 47: Device Bus Interface AC Timing Table (when using TCLK_OUT as the reference clock)
Data/READYn input setup relative to clock rising edge Data/READYn input hold relative to clock rising edge Address/Data output delay relative to clock rising edge Address output valid before ALE signal falling edge Address output valid after ALE signal falling edge
Notes: General comment: All timing values are for interfacing synchronous devices. General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified. 1. For all signals, the load is CL = 10 pF. 2. The AD bus is normally loaded w ith high capacitance. Make sure to w ork according to HW design guidelines or simulations in order to meet the latch AC timing requirements.
Table 48: Device Bus Interface AC Timing Table (when using TCLK_IN as the reference clock)
Description Data/READYn input setup relative to clock rising edge Data/READYn input hold relative to clock rising edge Address/Data output delay relative to clock rising edge Address output valid before ALE signal falling edge Address output valid after ALE signal falling edge Sym bol tSU tHD tOV tAOAB tAOAA Min 1.5 0.5 1.5 5.2 2.8 Max 3.0 Units ns ns ns ns ns Notes 1 1,2 1,2
Notes: General comment: All timing values are for interfacing synchronous devices. General comment: All values are defined on VDDIO/2.2, unless otherw ise specified. 1. For all signals, the load is CL = 5 pF. 2. The AD bus is normally loaded w ith high capacitance. Make sure to w ork according to HW design guide lines or simulations in order to meet the latch AC timing requirements.
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MV78100 Hardware Specifications
9.6.9.2
Device Bus Interface Test Circuit
Figure 32: Device Bus Interface Test Circuit
Test Point
CL
9.6.9.3
Device Bus Interface AC Timing Diagram
Figure 33: Device Bus Interface Output Delay AC Timing Diagram
Vih(min) CLOCK Vil(max) Vih(min) DATA
TOV(min) TOV(max)
Vil(max)
Vih(min) ALE Vil(max) Vih(min) AD Bus
TAOAB TAOAA
Vil(max)
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Figure 34: Device Bus Interface Input AC Timing Diagram
Vih(min) CLOCK Vil(max) Vih(min) DATA tSU
tHO
Vil(max)
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9.6.10
9.6.10.1
JTAG Interface AC Timing
JTAG Interface AC Timing Table
30 MHz Description Sym bol fCK Tpw Sr/Sf Trst Tsetup Thold Tprop 0.45 0.50 1.0 6.67 13.0 1.0 Min 30.0 0.55 8.33 Max Units MHz tCK V/ns ms ns ns ns Notes 2 1
Table 49: JTAG Interface 30 MHz AC Timing Table
JTClk frequency JTClk minimum pulse w idth JTClk rise/fall slew rate JTRSTn active time TMS, TDI input setup relative to JTClk rising edge TMS, TDI input hold relative to JTClk rising edge JTClk falling edge to TDO output delay
Notes: General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified. General comment: tCK = 1/fCK. 1. For TDO signal, the load is CL = 10 pF. 2. Defined from VIL to VIH for rise time, and from VIH to VIL for fall time.
9.6.10.2
JTAG Interface Test Circuit
Figure 35: JTAG Interface Test Circuit
Test Point
CL
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9.6.10.3
JTAG Interface AC Timing Diagrams
Figure 36: JTAG Interface Output Delay AC Timing Diagram
Tprop
(max)
VIH VIL
JTCK
TDO
Tprop (min)
Figure 37: JTAG Interface Input AC Timing Diagram
JTCK
TMS,TDI
Tsetup
Thold
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9.6.11
9.6.11.1
Time Division Multiplexing (TDM) Interface AC Timing
TDM Interface AC Timing Table
16.384 MHz Description Sym bol 1/tC tDTY tR/tF tD tSU tHD M in 0.256 0.4 0.0 5.0 5.0 Max 16.384 0.6 3.0 10.0 Units MHz tC ns ns ns ns Notes 1, 3 1 1, 2, 8 1, 4, 6 5, 7 5, 7
Table 50: TDM Interface AC Timing Table
PCLK cycle time PCLK duty cycle PCLK rise/fall time DTX and FSYNC valid after PCLK rising edge DRX and FSYNC setup time relative to PCLK falling edge DRX and FSYNC hold time relative to PCLK falling edge
Notes: General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified. 1. For all signals, the load is CL = 20 pF. 2. Rise and Fall times are referenced to the 20% and 80% levels of the w aveform. 3. PCLK can be configured to 0.256, 0.512, 0.768, 1.024, 1.536, 2.048, 4.096, 8.192, 16.384 MHz frequencies only. 4. This parameter is relevant to FSYNC signal in master-mode only. 5. This parameter is relevant to FSYNC signal in slave-mode only. 6. In negative-mode, the DTX signal is relative to PCLK falling edge. 7. In negative-mode, the DRX signal is relative to PCLK rising edge. 8. This parameter is relevant w hen the PCLK pin is output.
9.6.11.2
TDM Interface Test Circuit
Figure 38: TDM Interface Test Circuit
Test Point
CL
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AC Electrical Specifications
9.6.11.3
TDM Interface Timing Diagrams
Figure 39: TDM Interface Output Delay AC Timing Diagram
tC
PCLK
DTX
tD tD
Figure 40: TDM Interface Input Delay AC Timing Diagram
tC
PCLK
DRX
tSU tHD
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9.7
Differential Interface Electrical Characteristics
This section provides the reference clock, AC, and DC characteristics for the following differential interfaces: PCI Express (PCIe) Interface Electrical Characteristics SATA Interface Electrical Characteristics USB Interface Electrical Characteristics
9.7.1
9.7.1.1
Differential Interface Reference Clock Characteristics
PCI Express Interface Differential Reference Clock Characteristics
Table 52
Note
The reference clock characteristics in Table 52 is relevant for the PEX0_CLK_P, PEX0_CLK_N, PEX1_CLK_P, PEX1_CLK_N pins.
Table 51: PCI Express Interface Differential Reference Clock Characteristics
Description Clock frequency Clock duty cycle Differential rising/falling slew rate Differential high voltage Differential low voltage Absolute crossing point voltage Variation of Vcross over all rising clock edges Average differential clock period accuracy Absolute differential clock period Differential clock cycle-to-cycle jitter Notes: General Comment: The reference clock timings are based on 100 ohm test circuit. General Comment: Refer to the PCI Express Card Electromechanical Specification, Revision 1.1, March 2005, section 2.1.3 for more information. 1. Defined on a single-ended signal. 2. Including jitter and spread spectrum. 3. Defined from -150 mV to +150 mV on the differential w aveform. Sym bol fCK DCrefclk SRrefclk VIHrefclk VILrefclk Vcross Vcrs_dlta Tperavg Tperabs Tccjit 0.4 0.6 150.0 250.0 -300.0 9.8 Min 100.0 0.6 4.0 -150.0 550.0 140.0 2800.0 10.2 150.0 Max Units MHz tCK V/nS mV mV mV mV ppm nS pS Notes 3 1 1 2 -
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Differential Interface Electrical Characteristics
PCI Express Interface Spread Spectrum Requirements
Table 52: PCI Express Interface Spread Spectrum Requirements
Min 0.0 -0.5 Max 33.0 0.0 Units kHz % Notes 1 1 Sym bol Fmod Fspread
Notes: 1. Defined on linear sw eep or “Hershey’s Kiss” (US Patent 5,631,920) modulations.
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MV78100 Hardware Specifications
9.7.2
9.7.2.1
PCI Express (PCIe) Interface Electrical Characteristics
PCI Express Interface Driver and Receiver Characteristics
Description Sym bol BR UI Bppm Min 2.5 400.0 -300.0 300.0 Max Units Gbps ps ppm Notes 2
Table 53: PCI Express Interface Driver and Receiver Characteristics
Baud rate Unit interval Baud rate tolerance
Driver parameters
Differential peak to peak output voltage Minimum TX eye w idth Differential return loss Common mode return loss DC differential TX impedance VTXpp TTXeye TRLdiff TRLcm ZTXdiff 0.8 0.75 10.0 6.0 80.0 1.2 120.0 V UI dB dB Ohm 1 1 -
Receiver parameters
Differential input peak to peak voltage Minimum receiver eye w idth Differential return loss Common mode return loss DC differential RX impedance DC common input impedance Notes: General Comment: For more information, refer to the PCI Express Base Specification, Revision 1.1, March, 2005. 1. Defined from 50 MHz to 1.25 GHz. 2. Does not account for SSC dictated variations. VRXpp TRXeye RRLdiff RRLcm ZRXdiff ZRXcm 0.175 0.4 10.0 6.0 80.0 40.0 1.2 120.0 60.0 V UI dB dB Ohm Ohm 1 1 -
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9.7.2.2
PCI Express Interface Test Circuit
Figure 41: PCI Express Interface Test Circuit
Test Points + C_TX D+
D-
C_TX
50 ohm
50 ohm
When measuring Transmitter output parameters, C_TX is an optional portion of the Test/Measurement load. When used, the value of C_TX must be in the range of 75 nF to 200 nF. C_TX must not be used when the Test/Measurement load is placed in the Receiver package reference plane.
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9.7.3
9.7.3.1
SATA Interface Electrical Characteristics
SATA I Interface Gen1 Mode Driver and Receiver Characteristics
Description Sym bol BR Bppm Fssc SSCtol UI -350.0 30.0 -5000.0 666.67 85.0 40.0 14.0 8.0 6.0 3.0 1.0 400.0 85.0 40.0 18.0 14.0 10.0 8.0 3.0 1.0 325.0 115.0 600.0 0.355 0.175 0.470 0.220 115.0 600.0 0.430 0.250 0.600 0.350 Min 1.5 350.0 33.0 0.0 Max Units Gbps ppm kHz ppm ps Ohm Ohm dB dB dB dB dB mV UI UI UI UI Ohm Ohm dB dB dB dB dB dB mV UI UI UI UI Notes 2 1 1 1 1 -
Table 54: SATA I Interface Gen1i Mode Driver and Receiver Characteristicss
Baud Rate Baud rate tolerance Spread spectrum modulation frequency Spread spectrum modulation Deviation Unit Interval Differential impedance Single ended impedance Differential return loss (75 MHz-150 MHz) Differential return loss (150 MHz-300 MHz) Differential return loss (300 MHz-1.2 GHz) Differential return loss (1.2 GHz-2.4 GHz) Differential return loss (2.4 GHz-3.0 GHz) Output differential voltage Total jitter at connector data-data, 5UI Deterministic jitter at connector data-data, 5UI Total jitter at connector data-data, 250UI Deterministic jitter at connector data-data, 250UI Differential impedance Single ended impedance Differential return loss (75 MHz-150 MHz) Differential return loss (150 MHz-300 MHz) Differential return loss (300 MHz-600 MHz) Differential return loss (600 MHz-1.2 GHz) Differential return loss (1.2 GHz-2.4 GHz) Differential return loss (2.4 GHz-3.0 GHz) Input differential voltage Total jitter at connector data-data, 5UI Deterministic jitter at connector data-data, 5UI Total jitter at connector data-data, 250UI Deterministic jitter at connector data-data, 250UI
Driver Parameters
Zdifftx Zsetx RLOD RLOD RLOD RLOD RLOD Vdifftx TJ5 DJ5 TJ250 DJ250 Zdiffrx Zsetx RLID RLID RLID RLID RLID RLID Vdiffrx TJ5 DJ5 TJ250 DJ250
Receiver Parameters
Notes: General Comment: For more information, refer to SATA II Revision 2.6 Specification, February, 2007. General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified. General Comment: To comply w ith the values presented in this table, refer to your local Marvell representative for register settings. 1. Total jitter is defined as TJ = (14 * RJσ) + DJ w here Rjσ is random jitter. 2. Output Differential Amplitude and Pre-Emphasis are configurabile. See functional register description for more details.
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Table 55: SATA I Interface Gen1m Mode Driver and Receiver Characteristics
Description Baud Rate Baud rate tolerance Spread spectrum modulation frequency Spread spectrum modulation Deviation Unit Interval Differential impedance Single ended impedance Differential return loss (75 MHz-150 MHz) Differential return loss (150 MHz-300 MHz) Differential return loss (300 MHz-1.2 GHz) Differential return loss (1.2 GHz-2.4 GHz) Output differential voltage Total jitter at connector data-data, 5UI Deterministic jitter at connector data-data, 5UI Total jitter at connector data-data, 250UI Deterministic jitter at connector data-data, 250UI Differential impedance Single ended impedance Differential return loss (75 MHz-150 MHz) Differential return loss (150 MHz-300 MHz) Differential return loss (300 MHz-600 MHz) Differential return loss (600 MHz-1.2 GHz) Differential return loss (1.2 GHz-2.4 GHz) Input differential voltage Total jitter at connector data-data, 5UI Deterministic jitter at connector data-data, 5UI Total jitter at connector data-data, 250UI Deterministic jitter at connector data-data, 250UI Sym bol BR Bppm Fssc SSCtol UI -350.0 30.0 -5000.0 666.67 85.0 40.0 14.0 8.0 6.0 3.0 400.0 85.0 40.0 18.0 14.0 10.0 8.0 3.0 240.0 115.0 600.0 0.355 0.175 0.470 0.220 115.0 600.0 0.430 0.250 0.600 0.350 Min 1.5 350.0 33.0 0.0 Max Units Gbps ppm kHz ppm ps Ohm Ohm dB dB dB dB mV UI UI UI UI Ohm Ohm dB dB dB dB dB mV UI UI UI UI Notes 2 1 1 1 1 -
Driver Parameters
Zdifftx Zsetx RLOD RLOD RLOD RLOD Vdifftx TJ5 DJ5 TJ250 DJ250 Zdiffrx Zsetx RLID RLID RLID RLID RLID Vdiffrx TJ5 DJ5 TJ250 DJ250
Receiver Parameters
Notes: General Comment: For more information, refer to SATA II Revision 2.6 Specification, February, 2007. General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified. General Comment: To comply w ith the values presented in this table, refer to your local Marvell representative for register settings. 1. Total jitter is defined as TJ = (14 * RJσ) + DJ w here Rjσ is random jitter. 2. Output Differential Amplitude and Pre-Emphasis are configurabile. See functional register description for more details.
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9.7.3.2
SATA II Interface Gen2 Mode Driver and Receiver Characteristics
De s cription Sym bol BR Bppm Fssc SSCtol UI Dri ver P a ra meters V dif f tx RLOD RLOD RLOD RLOD RLOD TJ10 DJ10 TJ500 DJ500 Recei ver P a ra meters V dif f rx RLID RLID RLID RLID RLID RLID TJ10 DJ10 TJ500 DJ500 -350.0 30.0 -5000.0 333.33 400.0 14.0 8.0 6.0 3.0 1.0 275.0 18.0 14.0 10.0 8.0 3.0 1.0 700.0 0.30 0.17 0.37 0.19 750.0 0.46 0.35 0.60 0.42 M in 3.0 350.0 33.0 0.0 M ax Units Gbps ppm kHz ppm ps mV dB dB dB dB dB UI UI UI UI mV dB dB dB dB dB dB UI UI UI UI Note s 1,2 3 3 4 4 5 3 3 4 4
Table 56: SATA II Interface Gen2i Mode Driver and Receiver Characteristics
Baud Rate Baud rate tolerance Spread spectrum modulation f requency Spread spectrum modulation Deviation Unit Interval Output dif f erential voltage Dif f erential return loss (150 MHz-300 MHz) Dif f erential return loss (300 MHz-600 MHz) Dif f erential return loss (600 MHz-2.4 GHz) Dif f erential return loss (2.4 GHz-3.0 GHz) Dif f erential return loss (3.0 GHz-5.0 GHz) Total jitter at connector clock-data Deterministic jitter at connector clock-data Total jitter at connector clock-data Deterministic jitter at connector clock-data Input dif f erential voltage Dif f erential return loss (150 MHz-300 MHz) Dif f erential return loss (300 MHz-600 MHz) Dif f erential return loss (600 MHz-1.2 GHz) Dif f erential return loss (1.2 GHz-2.4 GHz) Dif f erential return loss (2.4 GHz-3.0 GHz) Dif f erential return loss (3.0 GHz-5.0 GHz) Total jitter at connector clock-data Deterministic jitter at connector clock-data Total jitter at connector clock-data Deterministic jitter at connector clock-data
Note s : General Comment: For more inf ormation, ref er to SA TA II Revision 2.6 Specif ication, February, 2007. General Comment: The load is 100 ohm dif f erential f or these parameters, unless otherw ise specif ied. General Comment: To comply w ith the values presented in this table, ref er to your local Marvell representative f or register settings. 1. 0.45-0.55 UI is the range w here the signal meets the minimum level. 2. Output Dif f erential A mplitude and Pre-Emphasis are conf igurabile. See f unctional register description f or more details. 3. Def ined f or BR/10. 4. Def ined f or BR/500. 5. 0.5 UI is the point w here the signal meets the minimum level.
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Table 57: SATA II Interface Gen2m Mode Driver and Receiver Characteristics
Description Baud Rate Baud rate tolerance Spread spectrum modulation frequency Spread spectrum modulation Deviation Unit Interval Output differential voltage Differential return loss (150 MHz-300 MHz) Differential return loss (300 MHz-600 MHz) Differential return loss (600 MHz-2.4 GHz) Differential return loss (2.4 GHz-3.0 GHz) Total jitter at connector clock-data Deterministic jitter at connector clock-data Total jitter at connector clock-data Deterministic jitter at connector clock-data Input differential voltage Differential return loss (150 MHz-300 MHz) Differential return loss (300 MHz-600 MHz) Differential return loss (600 MHz-1.2 GHz) Differential return loss (1.2 GHz-2.4 GHz) Differential return loss (2.4 GHz-3.0 GHz) Total jitter at connector clock-data Deterministic jitter at connector clock-data Total jitter at connector clock-data Deterministic jitter at connector clock-data Sym bol BR Bppm Fssc SSCtol UI -350.0 30.0 -5000.0 333.33 400.0 14.0 8.0 6.0 3.0 240.0 18.0 14.0 10.0 8.0 3.0 700.0 0.30 0.17 0.37 0.19 750.0 0.46 0.35 0.60 0.42 Min 3.0 350.0 33.0 0.0 Max Units Gbps ppm kHz ppm ps mV dB dB dB dB UI UI UI UI mV dB dB dB dB dB UI UI UI UI Notes 1,2 3 3 4 4 5 3 3 4 4
Driver Parameters
Vdifftx RLOD RLOD RLOD RLOD TJ10 DJ10 TJ500 DJ500
Receiver Parameters
Vdiffrx RLID RLID RLID RLID RLID TJ10 DJ10 TJ500 DJ500
Notes: General Comment: For more information, refer to SATA II Revision 2.6 Specification, February, 2007. General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified. General Comment: To comply w ith the values presented in this table, refer to your local Marvell representative for register settings. 1. 0.45-0.55 UI is the range w here the signal meets the minimum level. 2. Output Differential Amplitude and Pre-Emphasis are configurabile. See functional register description for more details. 3. Defined for BR/10. 4. Defined for BR/500. 5. 0.5 UI is the point w here the signal meets the minimum level.
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9.7.4
9.7.4.1
USB Interface Electrical Characteristics
USB Driver and Receiver Characteristics
Low Speed Description
Table 58: USB Low Speed Driver and Receiver Characteristics
Sym bol BR Bppm Driver Parameters VOH VOL VCRS TLR TLF TLRFM TUDJ1 TUDJ2 Receiver Parameters VIH VIL VDI Max 1.5 -15000.0 15000.0 2.8 0.0 1.3 75.0 75.0 80.0 -95.0 -150.0 2.0 0.2 3.6 0.3 2.0 300.0 300.0 125.0 95.0 150.0 0.8 Min Units Mbps ppm V V V ns ns % ns ns V V V Notes 1 2 3 3, 4 3, 4 5 5 -
Baud Rate Baud rate tolerance Ouput single ended high Ouput single ended low Output signal crossover voltage Data fall time Data rise time Rise and fall time matching Source jitter total: to next transition Source jitter total: for paired transitions Input single ended high Input single ended low Differential input sensitivity
Notes: General Comment: For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000. General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified. General Comment: To comply w ith the values presented in this table, refer to your local Marvell representative for register settings. 1. Defined w ith 1.425 kilohm pull-up resistor to 3.6V. 2. Defined w ith 14.25 kilohm pull-dow n resistor to ground. 3. See "Data Signal Rise and Fall Time" w aveform. 4. Defined from 10% to 90% for rise time and 90% to 10% for fall time. 5. Including frequency tolerance. Timing difference betw een the differential data signals. Defined at crossover point of differential data signals.
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Electrical Specifications
Table 59: USB Full Speed Driver and Receiver Characteristics
Full Speed Sym bol BR Bppm Driver Parameters Ouput single ended high VOH Ouput single ended low VOL Output signal crossover voltage VCRS Output rise time TFR Output fall time TFL Source jitter total: to next transition TDJ1 Source jitter total: for paired transitions TDJ2 Source jitter for differential transition to SE0 transition TFDEOP Receiver Parameters Input single ended high VIH Input single ended low VIL Differential input sensitivity VDI Receiver jitter : to next transition tJR1 Receiver jitter: for paired transitions tJR2 Baud Rate Baud rate tolerance Description Max 12.0 -2500.0 2500.0 2.8 0.0 1.3 4.0 4.0 -3.5 -4.0 -2.0 2.0 0.2 -18.5 -9.0 3.6 0.3 2.0 20.0 20.0 3.5 4.0 5.0 0.8 18.5 9.0 Min Units Mbps ppm V V V ns ns ns ns ns V V V ns ns Notes 1 2 4 3, 4 3, 4 5, 6 5, 6 6 6 6
Notes: General Comment: For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000. General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified. General Comment: To comply w ith the values presented in this table, refer to your local Marvell representative for register settings. 1.. Defined w ith 1.425 kilohm pull-up resistor to 3.6V. 2.. Defined w ith 14.25 kilohm pull-dow n resistor to ground. 3. Defined from 10% to 90% for rise time and 90% to 10% for fall time. 4. See "Data Signal Rise and Fall Time" w aveform. 5. Including frequency tolerance. Timing difference betw een the differential data signals. 6. Defined at crossover point of differential data signals.
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Table 60: USB High Speed Driver and Receiver Characteristics
High Speed Description Baud Rate Baud rate tolerance Data signaling high Data signaling low Data rise time Data fall time Data source jitter Differential input signaling levels Data signaling common mode voltage range Receiver jitter tolerance Sym bol BR Bppm Driver Parameters VHSOH VHSOL THSR THSF Max 480.0 -500.0 500.0 360.0 440.0 -10.0 10.0 500.0 500.0 See note 2 See note 3 -50.0 500.0 See note 3 M in Units Mbps ppm mV mV ps ps Notes 1 1 2 3 3
Receiver Parameters
VHSCM mV
Notes: General Comment: For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000. General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified. General Comment: To comply w ith the values presented in this table, refer to your local Marvell representative for register settings. 1. Defined from 10% to 90% for rise time and 90% to 10% for fall time. 2. Source jitter specified by the "TX eye diagram pattern template" figure. 3. Receiver jitter specified by the "RX eye diagram pattern template" figure.
9.7.4.2
USB Interface Driver Waveforms
Figure 42: Low/Full Speed Data Signal Rise and Fall Time
Rise Time 90% VCRS 10% 10% 90% Fall Time
Differential Data Lines
TR
TF
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Electrical Specifications
Figure 43: High Speed TX Eye Diagram Pattern Template
+525mV +475mV + 400mV Differential +300mV
0 Volts Differential
-300mV - 400mV Differential -475mV -525mV 7.5% 0% 37.5% 62.5% 92.5% 100%
Figure 44: High Speed RX Eye Diagram Pattern Template
+525mV +475mV +400mV Differential
+175mV
0 Volts Differential
-175mV
- 400mV Differential -475mV -525mV 12.5% 0% 35 65 87.5% 100%
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10
Thermal Data (Preliminary)
Table 61 provides the package thermal data for the MV78100. This data is derived from simulations that were run according to the JEDEC standard.
The thermal parameters are preliminary and subject to change. Note The documents listed below provide a basic understanding of thermal management of integrated circuits (ICs) and guidelines to ensure optimal operating conditions for Marvell® products. Before designing a system it is recommended to refer to these documents: Application Note, AN-63 Thermal Management for Selected Marvell® Products (Doc. No. MV-S300281-00) White Paper, ThetaJC, ThetaJA, and Temperature Calculations(Doc. No. MV-S700019-00)
Table 61: Thermal Data for the MV78100 in FCBGA Package
Sy m b o l D e f in i tio n A i rf lo w Va lu e ( C / W ) 0 [ m /s ] 1[m/s] 15.6 0.8 9.9 0.4 2 [ m /s ] 14.8 0.8 9.7
θJA ψJT ψJB θJC θJB
Thermal resistance: junction to ambient Thermal characterization parameter: junction to top center Thermal characterization parameter: junction to board Thermal resistance: junction to case (not air-flow dependent) Thermal resistance: junction to board (not air-flow dependent)
17.4 0.8 10.2
14.5
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Package Mechanical Dimensions
11
Package Mechanical Dimensions
The MV78100 uses a 655-pin 27 mm x 27 mm FCBGA package with 1 mm pitch.
Figure 45: 655 Pin FCBGA Package and Dimensions
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12
Part Order Numbering/Package Marking
Figure 46 is an example of the part order numbering scheme for the MV78100. Refer to Marvell® Field Application Engineers (FAEs) or representatives for further information on die revisions when ordering parts.
Figure 46: Sample Part Number
MV78100 –xx–BHO–C000–xxxx
Part Number MV78100 Custom Code (optional)
Custom Code
Die Revision
Temperature Code C = Commercial
Package Code BHO = 655-pin FCBGA
Environmental Code – = RoHS 5/6 1 = RoHS 6/6
Table 62: MV78100 Part Order Options
P a c k a g e Ty p e 655-pin FCBGA 655-pin FCBGA 655-pin FCBGA 655-pin FCBGA Part Order Number MV78100-A0-BHO-C080 (RoHS 5/6 compliant package; 800 MHz) MV78100-A0-BHO1C080 (RoHS 6/6 compliant package; 800 MHz) MV78100-A0-BHO-C100 (RoHS 5/6 compliant package; 1.0 GHz) MV78100-A0-BHO1C100 (RoHS 6/6 compliant package; 1.0 GHz)
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Part Order Numbering/Package Marking
Figure 47 shows a sample Commercial package marking and pin 1 location for the MV78100.
Figure 47: MV78100 Commercial Package Marking and Pin 1 Location
Marvell logo
Country of origin (Contained in the mold ID or marked as the last line on the package.) Part number and custom code Pin 1 location Temperature code (C = Commercial, I = Industrial) (080/100 = Custom)
MV7-BHOe Lot Number YYWW xx@ Country of Origin MV78100-xx xxxx
Package code, environmental code Environmental code = e (No code = RoHS 5/6, 1 = RoHS 6/6, 2 = Green) Date code, custom code, assembly plant code Date code (YY = Year, WW = Work week) Custom code = xx Assembly plant code = @
Note: The above drawing is not drawn to scale. The location of markings is approximate.
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13
Release
Revision History
Table 63: Revision History
D o c u m e n t Ty p e R e v is i o n D Date December 6, 2008
Section 2, Pin Information: • Added the SYSRST_OUTn pin to Table 4, Miscellaneous Pin Assignments, on page 21. This signal is multiplexed on the MPP pins. • Added the M_BB pin to Table 5, DDR SDRAM Interface Pin Assignments, on page 23. The SDRAM battery backup signal trigger is multiplexed on the MPP pins. • Changed the value to from 5 kilohm to 4.99 kilohm for PEXn_ISET in Table 7, PCI Express Port 0/1 Interface Pin Assignments, on page 28. • Added the SATA0/1_PRESENTn and SATA0/1_ACTn pins to Table 11, SATA II Port 0/1 Interface Pin Assignments, on page 33. These signals are multiplexed on the MPP pins. Section 3, Unused Interface Strapping: • Updated pull up and pull down resistor values in Table 18, Unused Interface Strapping, on page 39. Section 7, System Power Up and Reset Settings, on page 49. • Added power rail information to Table 22, Reset Configuration, on page 52. • Corrected the configuration settings for DEV_AD[30] (NAND Flash Initialization Command) in Table 22 . Section 9.6.7, Serial Peripheral Interface (SPI) AC Timing • Added AC timing information for this interface. Section 9.6.9, Device Bus Interface AC Timing • Changed the minimum values for tAOAB from 5.0 ns to 7.5 ns and tAOAA from 5.0 ns to 3.5 ns in Table 47, Device Bus Interface AC Timing Table (when using TCLK_OUT as the reference clock), on page 97. Release Added or changed information in the following sections: Product Overview • Changed the name of the Feroceon® CPU to Sheeva™. Section 2, Pin Information: • Updated the IREF_AVDD signal description Table 3, Power Supply Pins, on page 20. • Added a note that some GbE interface pins are connected to the VDD_GE power rail and some pins are connected to the VDDO_D power rail Table 9, Gigabit Ethernet Port Interface Pin Assignments, on page 29. • Added SATA0_AVDD and SATA1_AVDD as the power rail for the SATA pins in Table 11, SATA II Port 0/1 Interface Pin Assignments, on page 33. Section 7, System Power Up and Reset Settings, on page 49. • In Table 22, Reset Configuration, on page 52, added 0x2 setting for DEV_AD[13:12]. Section 9, Electrical Specifications (Preliminary) • Updated the IREF_VDD to minimum -0.5V to maximum 2.2V in Table 23, Absolute Maximum Ratings, on page 60. • Revised the IREF_VDD values and VDDO_A/B/C/D minimum and maximum values in the Table 24, Recommended Operating Conditions, on page 62. Section 9.6.6, SDRAM DDR2 Interface AC Timing • Revised Table 37, SDRAM DDR2 400 MHz Interface Address and Control Timing Table, on page 82. • Added Table 43, SDRAM DDR2 200 MHz Interface AC Timing Table, on page 88. C August 18, 2008
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Revision History
Table 63: Revision History (Continued)
D o c u m e n t Ty p e R e v is i o n Date Section 9.7, Differential Interface Electrical Characteristics • Added note that the spread spectrum requirements are defined on a linear sweep or a Hershey’s kiss modulation in Table 52, PCI Express Interface Spread Spectrum Requirements, on page 105. Section 9.7.3, SATA Interface Electrical Characteristics • Added Table 55, SATA I Interface Gen1m Mode Driver and Receiver Characteristics, on page 109 and Table 57, SATA II Interface Gen2m Mode Driver and Receiver Characteristics, on page 111. Section 10, Thermal Data (Preliminary), on page 116. • Updated thermal data. Section 11, Package Mechanical Dimensions, on page 117. • Updated Figure 45, “655 Pin FCBGA Package and Dimensions in Section 11, Package Mechanical Dimensions, on page 117. The capacitors have been removed from the figure. Release B June 2, 2008
Product Overview • Suppports 40-bit/72-bit DDR2 SDRAM interface • Integrates four 16550-compatible UART ports; also supports DMA based transmit • Integrates a two-channel SLIC/Codec TDM interface • Feroceon® core supports 32-Kbyte I-Cache and 32-Kbyte D-Cache, parity protected • PCI Express port is PCI Express Base 1.1 compliant Section 2, Pin Information: • Added thermal diode pins THERMAL_A/C and TCLK_IN note in TCLK_OUT pin • Added pullups on MPP pins • Added M_CLKOUT[2:0] and M_CLKOUTn[2:0] in Table 5, DDR SDRAM Interface Pin Assignments, on page 23 • Revised Table 6, Device Bus Interface Pin Assignments, on page 26 • Updated Table 7, p. 28 added Table 8, PCI Express Common Pin Assignments, on page 28 • Changed SPI pins names • Updated TDM interface signals • Added power pins to Table 10, USB 2.0 Ports 0/1/2 Interface Pin Assignments, on page 33 and Table 15, TDM Interface Pin Assignments, on page 36 • Changed TWSI1 from VDDO_B to VDDO_A in Table 12, TWSI Interface Pin Assignments, on page 34 Section 4, MV78100 Pin Map and Pin List • Pinout list and map are embedded as an attachment. • Updates are recorded in the pinout Revision History. Section 5, Clocking • Added TCLK:N feature • Updated Figure 3, MV78100 Clocks, on page 42 Section 6, Pin Multiplexing • Updated Note on page 48. • Changed column 0x0 so that device does not wake up in default with multiple pins have same functionality (e.g. multiple pins assigned as GPIO[0]). • Updated UART1 muxing. • • Removed UA1_TXD and UA1_RXD from multiplexing table. • Fixed GPIO muxing. • Updated locations of SYSRST_OUTn. Removed SYSRST_OUTn from Dev_AD[15] and Dev_WEn[2], and put it on Dev_AD[21,24,29,30,31].
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Table 63: Revision History (Continued)
D o c u m e n t Ty p e R e v is i o n Date Section 7, System Power Up and Reset Settings • Added Section 7.1, Power Up/Down Sequence Requirements, on page 49. • Updated Note on page 52. • Added new NF reset strap. • Added DEV_ALE modes strap. • Added more clocking operating points. Section 9, Electrical Specifications (Preliminary) • Updated Section 9.3, Thermal Power Dissipation (Preliminary), on page 64. • Updated Section 9.4, Current Consumption (Preliminary), on page 65. Section 9.6.1, Reference Clock and Reset AC Timing Specifications, on page 70 • Added parameters for an SPI output clock, integrated with the TDM interface. Section 9.6.6, SDRAM DDR2 Interface AC Timing • Replaced 64-bit 333 MHz Interface Timing and Clock Specification tables with 64-bit 400 MHz tables. • Added: • Table 37, SDRAM DDR2 400 MHz Interface Address and Control Timing Table, on page 82 • Table 39, SDRAM DDR2 333 MHz Interface AC Timing Table, on page 84 • Table 41, SDRAM DDR2 333 MHz Clock Specifications, on page 86 • Table 40, SDRAM DDR2 333 MHz Interface Address and Control Timing Table, on page 85 • Table 42, SDRAM DDR2 266 MHz Interface AC Timing Table, on page 87 • Updated Figure 21, SDRAM DDR2 Interface Write AC Timing Diagram, on page 89. • Updated Figure 23, SDRAM DDR2 Interface Read AC Timing Diagram, on page 90. Section 9.6.8, Two-Wire Serial Interface (TWSI) AC Timing • Updated TWSI output waveform Figure 30, TWSI Output Delay AC Timing Diagram, on page 95. Section 9.6.10, JTAG Interface AC Timing, on page 100. • Updated section. Section 9.6.11, Time Division Multiplexing (TDM) Interface AC Timing, on page 102. • Added section. Section 9.7, Differential Interface Electrical Characteristics • Updated Table 51, PCI Express Interface Differential Reference Clock Characteristics, on page 104 to reflect both input and output modes. Section 9.7.3, SATA Interface Electrical Characteristics • In Table 54, SATA I Interface Gen1i Mode Driver and Receiver Characteristicss, on page 108, return loss parameters (TX and RX) were added according to updated standard. Section 10, Thermal Data (Preliminary), on page 116 • Updated section. Section 12, Part Order Numbering/Package Marking, on page 118 • Updated section. Initial Release A October 9, 2007
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Contact Information
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