71M6521FE

19-5370; Rev 2; 11/11 71M6521DE/DH/FE Energy Meter ICs DATA SHEET GENERAL DESCRIPTION The Teridian™ 71M6521DE/DH/FE energy meter ICs are highly integrated systems-on-a-chip (SoCs) with an MPU core, RTC, flash, and LCD driver. The Single Converter Technology® with a 22-bit delta-sigma ADC, four analog inputs, digital temperature compensation, precision voltage reference, battery voltage monitor, and 32-bit computation engine (CE) supports a wide range of residential metering applications with very few low-cost external components. A 32kHz crystal time base for the entire system and internal battery-backup support for RAM and RTC further reduce system cost. The ICs support 2-wire, 3-wire, and 4-wire singlephase and dual-phase residential metering along with tamper-detection mechanisms. Maximum design flexibility is provided by multiple UARTs, I2C, MICROWIRE®, up to 18 DIO pins, and in-system programmable flash memory, which can be updated with data or application code in operation. A complete array of ICE and development tools, programming libraries, and reference designs enable rapid development and certification of TOU, AMR, and prepay meters that comply with worldwide electricity metering standards. FEATURES • Up to 0.1% Wh Accuracy Over 2000:1 Current Range • Exceeds IEC 62053/ANSI C 12.20 Standards • Voltage Reference < 40 ppm/°C (< 20ppm/°C for 71M6521DH) • Four Sensor Inputs—VDD Referenced • Low-Jitter Wh and VARh Pulse Test Outputs (10kHz max) • Pulse Count for Pulse Outputs • Four-Quadrant Metering • Tamper Detection Neutral Current with CT or Shunt • Line Frequency Count for RTC • Digital Temperature Compensation • Sag Detection for Phase A and B • Independent 32-Bit Compute Engine • 46-64Hz Line Frequency Range with Same Calibration • Phase Compensation (±7°) • Battery backup for RTC and battery monitor • Three Battery Modes with Wake-Up on Pushbutton or Timer: Brownout Mode (48µA) LCD Mode (5.7µA) Sleep Mode (2.9µA) • Energy Display on Main Power Failure • Wake-Up with Pushbutton • 22-Bit Delta-Sigma ADC • 8-Bit MPU (80515), 1 Clock Cycle per Instruction with Integrated ICE for MPU Debug • RTC with Temperature Compensation • Auto-Calibration • Hardware Watchdog Timer, Power-Fail Monitor • LCD Driver (Up to 152 Pixels) • Up to 18 General-Purpose I/O Pins • 32kHz Time Base • 16KB (6521DE/DH) or 32KB (6521FE) Flash with Security • 2KB MPU XRAM • Two UARTs for IR and AMR • Digital I/O Pins Compatible with 5V Inputs • 64-Pin LQFP or 68-Pin QFN Package A NEUT B CT/SHUNT LOAD LOAD POWER SUPPLY CONVERTER IA VA IB VB V3.3A V3.3 GNDA GNDD SYS PWR MODE CONTROL WAKE-UP REGULATOR VBAT V2.5 BATTERY TERIDIAN 71M6521 VOLTAGE REF VREF VBIAS SERIAL PORTS TEMP SENSOR DIO, PULSE RAM COM0..3 3.3V LCD AMR TX RX RX/DIO1 SENSE DRIVE/MOD COMPARATOR V1 OSC/PLL XIN FLASH COMPUTE ENGINE SEG0..18 SEG 24..31/ DIO 4..11 SEG 34..37/ DIO 14..17 SEG 32,33, 38/ICE 88.88.8888 IIC or uWire EEPROM IR POWER FAULT 32 kHz TX/DIO2 MPU RTC TIMERS ICE TEST PULSES V3P3D GNDD ICE_E XOUT 07/25/2007 Teridian is a trademark and Single Converter Technology is a registered trademark of Maxim Integrated Products Inc. MICROWIRE is a registered trademark of National Semiconductor Corp. • Lead(Pb)-Free Packages Rev 2 Page: 1 of 107 71M6521DE/DH/FE Data Sheet Table of Contents GENERAL DESCRIPTION ........................................................................................................................ 1 FEATURES ................................................................................................................................................ 1 HARDWARE DESCRIPTION ..................................................................................................................... 10 Hardware Overview ..................................................................................................................... 10 Analog Front End (AFE)............................................................................................................... 10 Input Multiplexer ............................................................................................................ 10 A/D Converter (ADC) ..................................................................................................... 11 FIR Filter ........................................................................................................................ 11 Voltage References ....................................................................................................... 11 Temperature Sensor ...................................................................................................... 12 Battery Monitor .............................................................................................................. 13 Functional Description ................................................................................................... 13 Digital Computation Engine (CE) ................................................................................................. 13 Meter Equations ............................................................................................................ 14 Description ................................................................................................................................... 14 Real-Time Monitor ......................................................................................................... 15 Pulse Generator ............................................................................................................ 15 CE Functional Overview ................................................................................................ 15 80515 MPU Core ........................................................................................................... 17 Memory Organization .................................................................................................... 17 Special Function Registers (SFRs)................................................................................ 19 Special Function Registers (Generic 80515 SFRs) ....................................................... 20 Special Function Registers Specific to the 71M6521DE/DH/FE .................................... 22 Instruction Set................................................................................................................ 23 UART ............................................................................................................................. 23 Timers and Counters ..................................................................................................... 25 WD Timer (Software Watchdog Timer) .......................................................................... 28 Interrupts ....................................................................................................................... 30 On-Chip Resources ..................................................................................................................... 38 Oscillator ....................................................................................................................... 38 PLL and Internal Clocks ................................................................................................ 38 Real-Time Clock (RTC) ................................................................................................. 38 Temperature Sensor ...................................................................................................... 38 Physical Memory ........................................................................................................... 39 Optical Interface ............................................................................................................ 40 Digital I/O ....................................................................................................................... 40 LCD Drivers ................................................................................................................... 42 Battery Monitor .............................................................................................................. 42 EEPROM Interface ........................................................................................................ 43 Page: 2 of 107 Rev 2 71M6521DE/DH/FE Data Sheet Hardware Watchdog Timer ............................................................................................ 46 Program Security ........................................................................................................... 46 Test Ports ...................................................................................................................... 47 FUNCTIONAL DESCRIPTION ................................................................................................................... 48 Theory of Operation ..................................................................................................................... 48 System Timing Summary ............................................................................................................. 49 Battery Modes .............................................................................................................................. 50 MISSION...................................................................................................................................... 51 BROWNOUT Mode ....................................................................................................... 51 LCD Mode ..................................................................................................................... 52 SLEEP Mode ................................................................................................................. 52 Fault and Reset Behavior ............................................................................................................ 57 Wake Up Behavior ....................................................................................................................... 57 Wake on PB................................................................................................................... 58 Wake on Timer .............................................................................................................. 58 Data Flow..................................................................................................................................... 59 CE/MPU Communication ............................................................................................................. 59 APPLICATION INFORMATION ................................................................................................................. 60 Connection of Sensors (CT, Resistive Shunt) .............................................................................. 60 Distinction between 71M6521DE/71M6521FE and 71M6521DH Parts ....................................... 60 Temperature Measurement ......................................................................................................... 61 Temperature Compensation ........................................................................................................ 61 Temperature Compensation and Mains Frequency Stabilization for the RTC ............................. 64 Connecting 5 V Devices............................................................................................................... 65 Connecting LCDs ......................................................................................................................... 66 Connecting I2C EEPROMs .......................................................................................................... 68 Connecting Three-Wire EEPROMs ............................................................................................. 69 UART0 (TX/RX) ........................................................................................................................... 69 Optical Interface ........................................................................................................................... 70 Connecting V1 and Reset Pins .................................................................................................... 70 Connecting the Emulator Port Pins .............................................................................................. 71 Crystal Oscillator .......................................................................................................................... 71 Flash Programming ..................................................................................................................... 72 MPU Firmware Library ................................................................................................................. 72 Meter Calibration ......................................................................................................................... 72 FIRMWARE INTERFACE .......................................................................................................................... 73 I/O RAM MAP – In Numerical Order ............................................................................................ 73 SFR MAP (SFRs Specific to the Teridian 80515) – In Numerical Order ...................................... 74 I/O RAM DESCRIPTION – Alphabetical Order ............................................................................ 75 CE Interface Description .............................................................................................................. 82 CE Program ................................................................................................................... 82 Rev 2 Page: 3 of 107 71M6521DE/DH/FE Data Sheet Formats ......................................................................................................................... 82 Constants ...................................................................................................................... 82 Environment .................................................................................................................. 82 CE Calculations ............................................................................................................. 83 CE STATUS .................................................................................................................. 83 CE TRANSFER VARIABLES ........................................................................................ 85 ELECTRICAL SPECIFICATIONS .............................................................................................................. 89 ABSOLUTE MAXIMUM RATINGS .............................................................................................. 89 RECOMMENDED EXTERNAL COMPONENTS ......................................................................... 90 RECOMMENDED OPERATING CONDITIONS .......................................................................... 90 PERFORMANCE SPECIFICATIONS .......................................................................................... 91 INPUT LOGIC LEVELS ................................................................................................. 91 OUTPUT LOGIC LEVELS ............................................................................................. 91 POWER-FAULT COMPARATOR .................................................................................. 91 BATTERY MONITOR .................................................................................................... 91 SUPPLY CURRENT ...................................................................................................... 92 V3P3D SWITCH ............................................................................................................ 92 2.5 V VOLTAGE REGULATOR ..................................................................................... 92 LOW POWER VOLTAGE REGULATOR....................................................................... 92 CRYSTAL OSCILLATOR .............................................................................................. 93 VREF, VBIAS ................................................................................................................ 93 LCD DRIVERS .............................................................................................................. 94 ADC CONVERTER, V3P3A REFERENCED ................................................................. 94 TEMPERATURE SENSOR ........................................................................................... 95 TIMING SPECIFICATIONS ......................................................................................................... 96 RAM AND FLASH MEMORY ..................................................................................................................... 96 FLASH MEMORY TIMING ............................................................................................ 96 EEPROM INTERFACE .................................................................................................. 96 RESET and V1 .............................................................................................................. 96 RTC ............................................................................................................................... 96 TYPICAL PERFORMANCE DATA ................................................................................ 97 PACKAGE OUTLINE (LQFP 64) ................................................................................................. 98 PACKAGE OUTLINE (QFN 68) ................................................................................................... 98 PINOUT (LQFP-64) ..................................................................................................................... 100 PINOUT (QFN 68) ....................................................................................................................... 100 Recommended PCB Land Pattern for the QFN-68 Package ....................................................... 101 PIN DESCRIPTIONS ................................................................................................................... 102 Power/Ground Pins: ...................................................................................................... 102 Analog Pins: .................................................................................................................. 102 Digital Pins:.................................................................................................................... 103 I/O Equivalent Circuits: .................................................................................................. 104 Page: 4 of 107 Rev 2 71M6521DE/DH/FE Data Sheet ORDERING INFORMATION ...................................................................................................................... 105 REVISION HISTORY ................................................................................................................................. 106 Rev 2 Page: 5 of 107 71M6521DE/DH/FE Data Sheet List of Figures Figure 1: IC Functional Block Diagram ....................................................................................................................................9 Figure 2: General Topology of a Chopped Amplifier .............................................................................................................11 Figure 3: AFE Block Diagram.................................................................................................................................................13 Figure 4: Samples from Multiplexer Cycle ............................................................................................................................16 Figure 5: Accumulation Interval ............................................................................................................................................16 Figure 6: Interrupt Structure .................................................................................................................................................37 Figure 7: Optical Interface ....................................................................................................................................................40 Figure 8: Connecting an External Load to DIO Pins ..............................................................................................................42 Figure 9: 3-Wire Interface. Write Command, HiZ=0..............................................................................................................44 Figure 10: 3-Wire Interface. Write Command, HiZ=1............................................................................................................44 Figure 11: 3-Wire Interface. Read Command........................................................................................................................45 Figure 12: 3-Wire Interface. Write Command when CNT=0 ..................................................................................................45 Figure 13: 3-Wire Interface. Write Command when HiZ=1 and WFR=1. ..............................................................................45 Figure 14: Functions defined by V1 ......................................................................................................................................46 Figure 15: Voltage. Current, Momentary and Accumulated Energy ......................................................................................48 Figure 16: Timing Relationship between ADC MUX, Compute Engine, and Serial Transfers................................................49 Figure 17: RTM Output Format .............................................................................................................................................49 Figure 18: Operation Modes State Diagram ..........................................................................................................................52 Figure 19: Functional Blocks in BROWNOUT Mode (inactive blocks grayed out).................................................................53 Figure 20: Functional Blocks in LCD Mode (inactive blocks grayed out) ..............................................................................54 Figure 21: Functional Blocks in SLEEP Mode (inactive blocks grayed out) ..........................................................................55 Figure 22: Transition from BROWNOUT to MISSION Mode when System Power Returns ..................................................56 Figure 23: Power-Up Timing with V3P3SYS and VBAT tied together ...................................................................................56 Figure 24: Power-Up Timing with VBAT only .......................................................................................................................57 Figure 25: Wake Up Timing...................................................................................................................................................58 Figure 26: MPU/CE Data Flow ...............................................................................................................................................59 Figure 27: MPU/CE Communication .....................................................................................................................................59 Figure 28: Resistive Voltage Divider (Left), Current Transformer (Right) ............................................................................60 Figure 29: Resistive Shunt ....................................................................................................................................................60 Figure 30: Error Band for VREF over Temperature (Regular-Accuracy Parts) ......................................................................62 Figure 31: Error Band for VREF over Temperature (High-Accuracy Parts) ...........................................................................63 Figure 32: Crystal Frequency over Temperature ...................................................................................................................64 Figure 33: Crystal Compensation ..........................................................................................................................................65 Figure 34: Connecting LCDs .................................................................................................................................................66 Figure 35: I2C EEPROM Connection ......................................................................................................................................68 Figure 36: Three-Wire EEPROM Connection.........................................................................................................................69 Figure 37: Connections for the RX Pin ..................................................................................................................................69 Figure 38: Connection for Optical Components ....................................................................................................................70 Figure 39: Voltage Divider for V1 ..........................................................................................................................................70 Figure 40: External Components for RESET: Development Circuit (Left), Production Circuit (Right) .................................. 71 Figure 41: External Components for the Emulator Interface .................................................................................................71 Figure 42: Wh Accuracy, 0.1A to 200A at 240V/50Hz and Room Temperature....................................................................97 Figure 43: Meter Accuracy over Harmonics at 240V, 30A ....................................................................................................97 Figure 44: Typical Meter Accuracy over Temperature Relative to 25°C (71M6521FE) .........................................................98 Page: 6 of 107 Rev 2 71M6521DE/DH/FE Data Sheet List of Tables Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles ..................................................................................11 Table 2: CE DRAM Locations for ADC Results......................................................................................................................14 Table 3: Meter Equations. ....................................................................................................................................................14 Table 4: Memory Map ...........................................................................................................................................................17 Table 5: Stretch Memory Cycle Width ..................................................................................................................................18 Table 6: Internal Data Memory Map......................................................................................................................................19 Table 7: Special Function Registers Locations .....................................................................................................................19 Table 8: Special Function Registers Reset Values ................................................................................................................20 Table 9: PSW Register Flags .................................................................................................................................................21 Table 10: PSW Bit Functions.................................................................................................................................................21 Table 11: Port Registers .......................................................................................................................................................22 Table 12: Special Function Registers ....................................................................................................................................23 Table 13: Baud Rate Generation............................................................................................................................................24 Table 14: UART Modes .........................................................................................................................................................24 Table 15: The S0CON Register .............................................................................................................................................24 Table 16: The S1CON register ..............................................................................................................................................25 Table 17: The S0CON Bit Functions .....................................................................................................................................25 Table 18: The S1CON Bit Functions .....................................................................................................................................25 Table 19: The TCON Register ..............................................................................................................................................26 Table 20: The TCON Register Bit Functions ..........................................................................................................................26 Table 21: The TMOD Register..............................................................................................................................................27 Table 22: TMOD Register Bit Description ............................................................................................................................27 Table 23: Timers/Counters Mode Description ......................................................................................................................27 Table 24: Timer Modes .........................................................................................................................................................28 Table 25: The PCON Register ..............................................................................................................................................28 Table 26: PCON Register Bit Description.............................................................................................................................28 Table 27: The IEN0 Register (see also Table 32) .................................................................................................................29 Table 28: The IEN0 Bit Functions (see also Table 32)..........................................................................................................29 Table 29: The IEN1 Register (see also Tables 30/31) ..........................................................................................................29 Table 30: The IEN1 Bit Functions (see also Tables 30/31) ...................................................................................................29 Table 31: The IP0 Register (see also Table 45) ....................................................................................................................29 Table 32: The IP0 bit Functions (see also Table 45).............................................................................................................30 Table 33: The WDTREL Register .........................................................................................................................................30 Table 34: The WDTREL Bit Functions ..................................................................................................................................30 Table 35: The IEN0 Register ................................................................................................................................................31 Table 36: The IEN0 Bit Functions .........................................................................................................................................31 Table 37: The IEN1 Register ................................................................................................................................................31 Table 38: The IEN1 Bit Functions .........................................................................................................................................31 Table 39: The IEN2 Register ................................................................................................................................................32 Table 40: The IEN2 Bit Functions .........................................................................................................................................32 Table 41: The TCON Register ..............................................................................................................................................32 Table 42: The TCON Bit Functions .......................................................................................................................................32 Table 43: The T2CON Bit Functions .....................................................................................................................................32 Table 44: The IRCON Register .............................................................................................................................................33 Table 45: The IRCON Bit Functions .....................................................................................................................................33 Table 46: External MPU Interrupts ........................................................................................................................................33 Table 47: Interrupt Enable and Flag Bits ..............................................................................................................................34 Table 48: Priority Level Groups ............................................................................................................................................35 Table 49: The IP0 Register ...................................................................................................................................................35 Table 50: The IP1 Register: ..................................................................................................................................................35 Table 51: Priority Levels .......................................................................................................................................................35 Table 52: Interrupt Polling Sequence....................................................................................................................................36 Table 53: Interrupt Vectors ...................................................................................................................................................36 Table 54: Data/Direction Registers and Internal Resources for DIO Pin Groups ..................................................................41 Rev 2 Page: 7 of 107 71M6521DE/DH/FE Data Sheet Table 55: DIO_DIR Control Bit ............................................................................................................................................41 Table 56: Selectable Controls using the DIO_DIR Bits ........................................................................................................42 Table 57: EECTRL Status Bits .............................................................................................................................................43 Table 58: EECTRL bits for 3-wire interface ........................................................................................................................44 Table 59: TMUX[4:0] Selections ..........................................................................................................................................47 Table 60: Available Circuit Functions (“—“ means “not active)............................................................................................51 Table 62: VREF Definition for the High-Accuracy Parts ........................................................................................................62 Table 63: Frequency over Temperature.................................................................................................................................64 Table 64: LCD and DIO Pin Assignment by LCD_NUM for the QFN-68 Package................................................................67 Table 65: LCD and DIO Pin Assignment by LCD_NUM for the LQFP-64 Package ..............................................................68 Page: 8 of 107 Rev 2 71M6521DE/DH/FE Data Sheet VREF V3P3A GNDA V3P3SYS IA VA IB VB VBAT ∆Σ ADC CONVERTER MUX VBIAS VBIAS V3P3D V3P3A + ADC_E FIR VBAT FIR_LEN V3P3D TEMP MUX MUX CTRL EQU MUX_ALT CHOP_E MUX_DIV VREF VREF_CAL VREF_DIS CROSS CK32 VREF VBAT VOLT REG X4MHZ XIN XOUT CKTEST/ SEG19 OSC (32KHz) RTCLK (32KHz) MCK PLL CK32 32KHz DIV ADC CKADC LCD_ONLY SLEEP GNDD V2P5 CKOUT_E 4.9MHz CKOUT_E CK_GEN ECK_DIS MPU_DIV MUX_SYNC CKCE =1 IP1.4/ IP0.4 RI0 UART0 TI0 IEN1.4 EEPROM/ I2C INT5 IRCON.4 IEN1.5 XF ER_ BUSY IE_XFER IRCON.5 INT6 IP1.5/ IP0.5 RTC_1S IE_RTC Figure 6: Interrupt Structure Rev 2 Page: 37 of 107 71M6521DE/DH/FE Data Sheet On-Chip Resources Oscillator The 71M6521DE/DH/FE oscillator drives a standard 32.768kHz watch crystal. These crystals are accurate and do not require a high-current oscillator circuit. The 71M6521DE/DH/FE oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. PLL and Internal Clocks Timing for the device is derived from the 32.768kHz oscillator output. On-chip timing functions include the MPU master clock, a real time clock (RTC), and the delta-sigma sample clock. In addition, the MPU has two general counter/timers (see MPU section). The ADC master clock, CKADC, is generated by an on-chip PLL. It multiplies the oscillator output frequency (CK32) by 150. The CE clock frequency is always CK32 * 150, or 4.9152MHz, where CK32 is the 32kHz clock. The MPU clock frequency is determined by MPU_DIV and can be 4.9152MHz *2-MPU_DIV Hz where MPU_DIV varies from 0 to 7 (MPU_DIV is 0 on power-up). This makes the MPU clock scalable from 4.9152MHz down to 38.4kHz. The circuit also generates a 2x MPU clock for use by the emulator. This clock is not generated when ECK_DIS is asserted by the MPU. The setting of MPU_DIV is maintained when the device transitions to BROWNOUT mode, but the time base in BROWNOUT mode is 28,672Hz. Real-Time Clock (RTC) The RTC is driven directly by the crystal oscillator. It is powered by the net V2P5NV (battery-backed up supply). The RTC consists of a counter chain and output registers. The counter chain consists of seconds, minutes, hours, day of week, day of month, month, and year. The RTC is capable of processing leap years. Each counter has its own output register. Whenever the MPU reads the seconds register, all other output registers are automatically updated. Since the RTC clock is not coherent to the MPU clock, the MPU must read the seconds register until two consecutive reads are the same (requires either 2 or 3 reads). At this point, all RTC output registers will have the correct time. Regardless of the MPU clock speed, RTC reads require one wait state. RTC time is set by writing to the RTC registers in I/O RAM. Each byte written to RTC must be delayed at least 3 RTC cycles from any previous byte written to RTC. Hardware RTC write protection requires that a write to address 0x201F occur before each RTC write. Writing to address 0x201F opens a hardware ‘enable gate’ that remains open until an RTC write occurs and then closes. It is not necessary to disable interrupts between the write operation to 0x201F and the RTC write because the ‘enable gate’ will remain open until the RTC write finally occurs Two time correction bits, RTC_DEC_SEC and RTC_INC_SEC are provided to adjust the RTC time. A pulse on one of these bits causes the time to be decremented or incremented by an additional second at the next update of the RTC_SEC register. Thus, if the crystal temperature coefficient is known, the MPU firmware can integrate temperature and correct the RTC time as necessary. Temperature Sensor The device includes an on-chip temperature sensor for determining the temperature of the bandgap reference. The MPU may request an alternate multiplexer frame containing the temperature sensor output by asserting MUX_ALT. The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system (see section titled “Temperature Compensation”). Page: 38 of 107 Rev 2 71M6521DE/DH/FE Data Sheet Physical Memory Flash Memory: The 71M6521DE/DH/FE includes 16KB (71M6521DE/DH) or 32KB (71M6521FE) of on-chip flash memory. The flash memory primarily contains MPU and CE program code. It also contains images of the CE DRAM, MPU RAM, and I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective locations. Allocated flash space for the CE program cannot exceed 1024 words (2KB). The CE program must begin on a 1KB boundary of the flash address. The CE_LCTN[4:0] word defines which 1KB boundary contains the CE code. Thus, the first CE instruction is located at 1024*CE_LCTN[4:0]. CE_LCTN must be defined before the CE is enabled. The flash memory is segmented into 512 byte individually erasable pages. The CE engine cannot access its program memory when flash write occurs. Thus, the flash write procedure is to begin a sequence of flash writes when CE_BUSY falls (CE_BUSY interrupt) and to make sure there is sufficient time to complete the sequence before CE_BUSY rises again. The actual time for the flash write operation will depend on the exact number of cycles required by the CE program. Typically (CE program is 512 instructions, mux frame is 13 CK32 cycles), there will be 200µs of flash write time, enough for 4 bytes of flash write. If the CE code is shorter, there will be even more time. Two interrupts warn of collisions between the MPU firmware and the CE timing. If a flash write is attempted while the CE is busy, the flash write will not execute and the FW_COL0 interrupt will be issued. If a flash write is still in progress when the CE would otherwise begin a code pass, the code pass is skipped, the write is completed, and the FW_COL1 interrupt is issued. The bit FLASH66Z (see I/O RAM table) defines the speed for accessing flash memory. To minimize supply current draw, this bit should be set to 1. Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence. These special pattern/sequence requirements prevent inadvertent erasure of the flash memory. The mass erase sequence is: 1. 2. Write 1 to the FLSH_MEEN bit (SFR address 0xB2[1]. Write pattern 0xAA to FLSH_ERASE (SFR address 0x94) The mass erase cycle can only be initiated when the ICE port is enabled. The page erase sequence is: 1. 2. Write the page address to FLSH_PGADR (SFR address 0xB7[7:1] Write pattern 0x55 to FLSH_ERASE (SFR address 0x94) The MPU may write to the flash memory. This is one of the non-volatile storage options available to the user in addition to external EEPROM. FLSH_PWE (flash program write enable) differentiates 80515 data store instructions (MOVX@DPTR,A) between flash and XRAM writes. Updating individual bytes in flash memory: The original state of a flash byte is 0xFF (all ones). Once, a value other than 0xFF is written to a flash memory cell, overwriting with a different value usually requires that the cell is erased first. Since cells cannot be erased individually, the page has to be copied to RAM, followed by a page erase. After this, the page can be updated in RAM and then written back to the flash memory. MPU RAM: The 71M6521DE/DH/FE includes 2k-bytes of static RAM memory on-chip (XRAM) plus 256-bytes of internal RAM in the MPU core. The 2K-bytes of static RAM are used for data storage during normal MPU operations. CE DRAM: The CE DRAM is the working data memory of the CE (128 32-bit words). The MPU can read and write the CE DRAM as the primary means of data communication between the two processors. Rev 2 Page: 39 of 107 71M6521DE/DH/FE Data Sheet Optical Interface The device includes an interface to implement an IR/optical port. The pin OPT_Tx is designed to directly drive an external LED for transmitting data on an optical link. The pin OPT_RX is designed to sense the input from an external photo detector used as the receiver for the optical link. These two pins are connected to a dedicated UART port (UART1). The OPT_TX and OPT_RX pins can be inverted with configuration bits OPT_TXINV and OPT_RXINV, respectively. Additionally, the OPT_TX output may be modulated at 38kHz. Modulation is available when system power is present (i.e. not in BROWNOUT mode). The OPT_TXMOD bit enables modulation. Duty cycle is controlled by OPT_FDC[1:0], which can select 50%, 25%, 12.5%, and 6.25% duty cycle. 6.25% duty cycle means OPT_TX is low for 6.25% of the period. Figure 7 illustrates the OPT_TX generator. VARPULSE WPULSE from OPT_TX UART OPT_TXINV OPT_TXMOD OPT_FDC A EN 2 OPT_TXMOD=1, OPT_FDC=2 (25%) A B 1/38kHz MOD DUTY DIO2 B 2 1 0 3 Internal OPT_TX V3P3 OPT_TXE[1:0] OPT_TXMOD=0 A B Figure 7: Optical Interface When not needed for the optical UART, the OPT_TX pin can alternatively be configured as DIO2, WPULSE, or VARPULSE. The configuration bits are OPT_TXE[1:0]. Likewise, OPT_RX can alternately be configured as DIO_1. Its control is OPT_RXDIS. Digital I/O The device includes up to 18 pins (QFN 68 package) or 14 pins (LQFP 64 package) of general purpose digital I/O. These pins are compatible with 5 V inputs (no current-limiting resistors are needed). Some of them are dedicated DIO (DIO3), some are dual-function that can alternatively be used as LCD drivers (DIO4-11, 14-17, 19-21) and some share functions with the optical port (DIO1, DIO2). On reset or power-up, all DIO pins are inputs until they are configured for the desired direction under MPU control. The pins are configured by the DIO registers and by the five bits of the LCD_NUM register (located in I/O RAM). Once declared as DIO, each pin can be configured independently as an input or output with the DIO_DIRn bits. A 3-bit configuration word, DIO_Rx, can be used for certain pins, when configured as DIO, to individually assign an internal resource such as an interrupt or a timer control. Table 54 lists the direction registers and configurability associated with each group of DIO pins. Table 55 shows the configuration for a DIO pin through its associated bit in its DIO_DIR register. Tables showing the relationship between LCD_NUM and the available segment/DIO pins can be found in the Applications section and in the I/O RAM Description under LCD_NUM[4:0]. Page: 40 of 107 Rev 2 71M6521DE/DH/FE Data Sheet DIO Pin no. (64 LQFP) Pin no. (68 QFN) Data Register Direction Register Internal Resources Configurable DIO Pin no. (64 LQFP) Pin no. (68 QFN) Data Register Direction Register Internal Resources Configurable PB 62 65 0 0 Y 16 22 23 0 0 N 1 57 60 1 2 3 4 5 6 3 37 38 39 3 5 39 40 41 2 3 4 5 6 DIO0=P0 (SFR 0x80) 1 2 3 4 5 6 DIO_DIR0 (SFR 0xA2) Y Y Y Y Y 7 40 42 7 7 Y 23 ----8 41 43 0 0 Y 9 42 44 1 10 11 12 13 43 44 --45 46 --2 3 --DIO1=P1 (SFR 0x90) 1 2 3 --DIO_DIR1 (SFR 0x91) Y Y --14 20 21 6 6 -15 21 22 7 7 -- Y 17 12 13 1 Y 18 19 20 21 22 ------24 47 68 -3 4 5 -DIO2=P2 (SFR 0xA0) 1 -3 4 5 -DIO_DIR2 (SFR 0xA1) -N N N -- N Table 54: Data/Direction Registers and Internal Resources for DIO Pin Groups DIO_DIR [n] 0 DIO Pin n Function Input 1 Output Table 55: DIO_DIR Control Bit Additionally, if DIO6 and DIO7 are declared outputs, they can be configured as dedicated pulse outputs (WPULSE = DIO6, VARPULSE = DIO7) using DIO_PW and DIO_PV registers. In this case, DIO6 and DIO7 are under CE control. DIO4 and DIO5 can be configured to implement the EEPROM Interface. The PB pin is a dedicated digital input. If the optical UART is not used, OPT_TX and OPT_RX can be configured as dedicated DIO pins (DIO1, DIO2, see Optical Interface section). A 3-bit configuration word, I/O RAM register, DIO_Rx (0x2009[2:0] through 0x200E[6:4]) can be used for certain pins, when configured as DIO, to individually assign an internal resource such as an interrupt or a timer control (see Table 54 for DIO pins available for this option). This way, DIO pins can be tracked even if they are configured as outputs. Tracking DIO pins configured as outputs is useful for pulse counting without external hardware. When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as shown in Figure 8, right), not source it from V3P3D (as shown in Figure 8, left). This is due to the resistance of the internal switch that connects V3P3D to either V3P3SYS or VBAT. When configured as inputs, the dual-function (DIO/SEG) pins should not be pulled above V3P3SYS in MISSION and above VBAT in LCD and BROWNOUT modes. Doing so will distort the LCD waveforms of the other pins. This limitation applies to any pin that can be configured as a LCD driver. The control resources selectable for the DIO pins are listed in Table 56. If more than one input is connected to the same resource, the resources are combined using a logical OR. The PB pin is a dedicated digital input. In addition, if the optical UART is not used, OPT_TX and OPT_RX can be configured as dedicated DIO pins. Thus, in addition to the 16 general-purpose DIO pins (DIO4…DIO11, DIO14…DIO21), there are three additional pins that can be used for digital input and output. Rev 2 Page: 41 of 107 71M6521DE/DH/FE Data Sheet 71M6521 V3P3SYS VBAT V3P3D DIO1 3.3V 71M6521 V3P3SYS VBAT V3P3D DIO1 3.3V LED R LED DGND Not recommended DGND R Recommended Recommended Figure 8: Connecting an External Load to DIO Pins DIO_R Value 0 1 2 3 4 5 6 7 Resource Selected for DIO Pin NONE Reserved T0 (counter0 clock) T1 (counter1 clock) High priority I/O interrupt (INT0 rising) Low priority I/O interrupt (INT1 rising) High priority I/O interrupt (INT0 falling) Low priority I/O interrupt (INT1 falling) Table 56: Selectable Controls using the DIO_DIR Bits LCD Drivers The device in the 68-pin QFN package contains 20 dedicated LCD segment drivers in addition to the 18 multi-use pins described above. Thus, the device is capable of driving between 80 to 152 pixels of LCD display with 25% duty cycle (or 60 to 114 pixels with 33% duty cycle). At eight pixels per digit, this corresponds to 10 to 19 digits. The device in the 64-pin LQFP package contains 20 dedicated LCD segment drivers in addition to the 15 multi-use pins described above. Thus, the device is capable of driving between 80 to 140 pixels of LCD display with 25% duty cycle (or 60 to 105 pixels with 33% duty cycle). At eight pixels per digit, this corresponds to 10 to 17 digits. The LCD drivers are grouped into four commons and up to 38 segment drivers (68-pin package), or 4 commons and 35 segment drivers (64-pin package). The LCD interface is flexible and can drive either digit segments or enunciator symbols. Segment drivers SEG18 and SEG19 can be configured to blink at either 0.5Hz or 1Hz. The blink rate is controlled by LCD_Y. There can be up to four pixels/segments connected to each of these drivers. LCD_BLKMAP18[3:0] and LCD_BLKMAP19[3:0] identify which pixels, if any, are to blink. LCD interface memory is powered by the non-volatile supply. The bits of the LCD memory are preserved in LCD and SLEEP modes, even if their pin is not configured as SEG. In this case, they can be useful as general-purpose nonvolatile storage. Battery Monitor The battery voltage is measured by the ADC during alternative MUX frames if the BME (Battery Measure Enable) bit is set. While BME is set, an on-chip 45kΩ load resistor is applied to the battery and a scaled fraction of the battery voltage is applied to the ADC input. After each alternative MUX frame, the result of the ADC conversion is available at CE DRAM address 0x07. BME is ignored and assumed zero when system power is not available. See the Battery Monitor section of the Electrical Specification section for details regarding the ADC LSB size and the conversion accuracy. Page: 42 of 107 Rev 2 71M6521DE/DH/FE Data Sheet EEPROM Interface The 71M6521DE/DH/FE provides hardware support for either type of EEPROM interface, a two-pin interface and a three-pin interface. The interfaces use the EECTRL and EEDATA registers for communication. Two-Pin EEPROM Interface The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is multiplexed onto pins DIO4 (SCK) and DIO5 (SDA) controlled by the DIO_EEX bit I/O RAM (see I/O RAM Table). The MPU communicates with the interface through two SFR registers: EEDATA and EECTRL. If the MPU wishes to write a byte of data to EEPROM, it places the data in EEDATA and then writes the ‘Transmit’ command (CMD = 0011) to EECTRL. This initiates the transmit operation. The transmit operation is finished when the BUSY bit falls. Interrupt INT5 is also asserted when BUSY falls. The MPU can then check the RX_ACK bit to see if the EEPROM acknowledged the transmission. A byte is read by writing the ‘Receive’ command (CMD = 0001) to EECTRL and waiting for the BUSY bit to fall. Upon completion, the received data is in EEDATA. The serial transmit and receive clock is 78kHz during each transmission, and the clock is held in a high state until the next transmission. The bits in EECTRL are shown in Table 57. The EEPROM interface can also be operated by controlling the DIO4 and DIO5 pins directly (“bit-banging”). However, controlling DIO4 and DIO5 directly is discouraged, because it may tie up the MPU to the point where it may become too busy to process interrupts. Status Bit 7 6 5 4 Name ERROR BUSY RX_ACK TX_ACK Read/ Write R R R R Reset State 0 0 1 1 Polarity Positive Positive Negative Negative Description 1 when an illegal command is received. 1 when serial data bus is busy. 0 indicates that the EEPROM sent an ACK bit. 0 indicates when an ACK bit has been sent to the EEPROM CMD 0000 Operation No-op. Applying the no-op command will stop the I2C clock (SCK, DIO4). Failure to issue the no-op command will keep the SCK signal toggling. Receive a byte from EEPROM and send ACK. Transmit a byte to EEPROM. Issue a ‘STOP’ sequence. Receive the last byte from EEPROM, do not send ACK. Issue a ‘START’ sequence. No Operation, set the ERROR bit. 3-0 CMD[3:0 ] W 0 Positive, see CMD Table 0001 0011 0101 0110 1001 Others Table 57: EECTRL Status Bits Rev 2 Page: 43 of 107 71M6521DE/DH/FE Data Sheet Three-Wire EEPROM Interface A 500kHz three-wire interface, using SDATA, SCK, and a DIO pin for CS is available. The interface is selected with DIO_EEX=3. The same 2-wire EECTRL register is used, except the bits are reconfigured, as shown in Table 58. When EECTRL is written, up to 8 bits from EEDATA are either written to the EEPROM or read from the EEPROM, depending on the values of the EECTRL bits. Control Bit Name Read/Write Description Wait for Ready. If this bit is set, the trailing edge of BUSY will be delayed until a rising edge is seen on the data line. This bit can be used during the last byte of a Write command to cause the INT5 interrupt to occur when the EEPROM has finished its internal write sequence. This bit is ignored if HiZ=0. Asserted while serial data bus is busy. When the BUSY bit falls, an INT5 interrupt occurs. Indicates that the SD signal is to made high impedance immediately after the last SCK rising edge. Indicates that EEDATA is to be filled with data from EEPROM. Specifies the number of clocks to be issued. Allowed values are 0 through 8. If RD=1, CNT bits of data will be read MSB first, and right justified into the low order bits of EEDATA. If RD=0, CNT bits will be sent MSB first to EEPROM, shifted out of EEDATA’s MSB. If CNT is zero, SDATA will simply obey the HiZ bit. 7 WFR W 6 5 4 BUSY HiZ RD R W W 3-0 CNT[3:0] W Table 58: EECTRL bits for 3-wire interface The timing diagrams in Figure 9 through Figure 13 describe the 3-wire EEPROM interface behavior. All commands begin when the EECTRL register is written. Transactions start by first raising the DIO pin that is connected to CS. Multiple 8-bit or less commands such as those shown in Figure 9 through Figure 13 are then sent via EECTRL and EEDATA. When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM will be driving SDATA, but will transition to HiZ (high impedance) when CS falls. The firmware should then immediately issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to a low-Z state. EECTRL Byte Written CNT Cycles (6 shown) Write -- No HiZ SCLK (output) SDATA (output) SDATA output Z BUSY (bit) D7 D6 D5 (LoZ) D4 D3 D2 INT5 Figure 9: 3-Wire Interface. Write Command, HiZ=0. EECTRL Byte Written CNT Cycles (6 shown) Write -- With HiZ SCLK (output) SDATA (output) SDATA output Z BUSY (bit) D7 D6 D5 (LoZ) D4 D3 D2 (HiZ) INT5 Figure 10: 3-Wire Interface. Write Command, HiZ=1 Page: 44 of 107 Rev 2 71M6521DE/DH/FE Data Sheet EECTRL Byte Written CNT Cycles (8 shown) READ SCLK (output) SDATA (input) SDATA output Z BUSY (bit) D7 D6 (HiZ) D5 D4 D3 D2 D1 D0 INT5 Figure 11: 3-Wire Interface. Read Command. EECTRL Byte Written Write -- No HiZ SCLK (output) SDATA (output) SDATA output Z BUSY (bit) D7 (LoZ) INT5 not issued CNT Cycles (0 shown) EECTRL Byte Written Write -- HiZ SCLK (output) SDATA (output) INT5 not issued CNT Cycles (0 shown) SDATA output Z BUSY (bit) (HiZ) Figure 12: 3-Wire Interface. Write Command when CNT=0 EECTRL Byte Written CNT Cycles (6 shown) Write -- With HiZ and WFR SCLK (output) SDATA (out/in) SDATA output Z BUSY (bit) D7 D6 D5 (From 6520) (LoZ) D4 D3 D2 BUSY (From EEPROM) (HiZ) READY INT5 Figure 13: 3-Wire Interface. Write Command when HiZ=1 and WFR=1. Rev 2 Page: 45 of 107 71M6521DE/DH/FE Data Sheet Hardware Watchdog Timer V1 V3P3 V3P3 - 10mV V3P3 400mV Normal operation, WDT enabled VBIAS WDT disabled In addition to the basic watchdog timer included in the 80515 MPU, an independent, robust, fixed-duration, watchdog timer (WDT) is included in the device. It uses the RTC crystal oscillator as its time base and must be refreshed by the MPU firmware at least every 1.5 seconds. When not refreshed on time the WDT overflows, and the part is reset as if the RESET pin were pulled high, except that the I/O RAM bits will be in the same state as after a wake-up from SLEEP or LCD modes (see the I/O RAM description for a list of I/O RAM bit states after RESET and wake-up). 4100 oscillator cycles (or 125ms) after the WDT overflow, the MPU will be launched from program address 0x0000. A status bit, WD_OVF, is set when WDT overflow occurs. This bit is powered by the non-volatile supply and can be read by the MPU to determine if the part is initializing after a WDT overflow event or after a power-up. After it is read, MPU firmware must clear WD_OVF. The WD_OVF bit is cleared by the RESET pin There is no internal digital state that deactivates the WDT. For debug purposes, however, the WDT can be disabled by tying the V1 pin to V3P3 (see Figure 39). Of course, this also deactivates V1 power fault detection. Since there is no method in firmware to disable the crystal oscillator or the WDT, it is guaranteed that whatever state the part might find itself in, upon WDT overflow, the part will be reset to a known state. Asserting ICE_E will also deactivate the WDT. This is the only method that will disable the WDT in BROWNOUT mode. Battery modes 0V In normal operation, the WDT is reset by periodically writing a one to the WDT_RST bit. The watchdog timer is also reset when the internal signal WAKE=0 (see section on Wake Up Behavior). Figure 14: Functions defined by V1 Program Security When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE operations are blocked. This guarantees the security of the user’s MPU and CE program code. Security is enabled by MPU code that is executed in a 32 cycle preboot interval before the primary boot sequence begins. Once security is enabled, the only way to disable it is to perform a global erase of the flash, followed by a chip reset. The first 32 cycles of the MPU boot code are called the preboot phase because during this phase the ICE is inhibited. A read-only status bit, PREBOOT, identifies these cycles to the MPU. Upon completion of preboot, the ICE can be enabled and is permitted to take control of the MPU. SECURE, the security enable bit, is reset whenever the chip is reset. Hardware associated with the bit permits only ones to be written to it. Thus, preboot code may set SECURE to enable the security feature but may not reset it. Once SECURE is set, the preboot code is protected and no external read of program code is possible Specifically, when SECURE is set: • • • The ICE is limited to bulk flash erase only. Page zero of flash memory, the preferred location for the user’s preboot code, may not be page-erased by either MPU or ICE. Page zero may only be erased with global flash erase. Writes to page zero, whether by MPU or ICE are inhibited. The SECURE bit is to be used with caution! Inadvertently setting this bit will inhibit access to the part via the ICE interface, if no mechanism for actively resetting the part between reset and erase operations is provided (see ICE Interface description). Page: 46 of 107 Rev 2 71M6521DE/DH/FE Data Sheet Test Ports TMUXOUT Pin: One out of 16 digital or 8 analog signals can be selected to be output on the TMUXOUT pin. The function of the multiplexer is controlled with the I/O RAM register TMUX (0x20AA[4:0]), as shown in Table 59. TMUX[4:0] 0 1 2 3-5 6 7 8-0x0F 0x10 – 0x13 0x14 0x15 0x16 – 0x17 0x18 0x19 0x1A 0x1B 0x1C 0X1D 0X1E 0X1F Mode Analog Analog Analog Analog Analog Analog --Digital Digital Digital Digital Digital Digital -Digital Digital Digital Function DGND Reserved DGND Reserved VBIAS Not used Reserved Not used RTM (Real time output from CE) WDTR_EN (Comparator 1 Output AND V1LT3) Not used RXD (from Optical interface, w/ optional inversion) MUX_SYNC CK_10M (10MHz clock) CK_MPU (MPU clock) Reserved RTCLK (output of the oscillator circuit, nominally 32,786Hz) CE_BUSY (busy interrupt generated by CE, 396µs) XFER_BUSY (transfer busy interrupt generated by CE, nominally every 999.7ms) Table 59: TMUX[4:0] Selections Rev 2 Page: 47 of 107 71M6521DE/DH/FE Data Sheet FUNCTIONAL DESCRIPTION Theory of Operation The energy delivered by a power source into a load can be expressed as: t E = ∫ V (t ) I (t )dt 0 Assuming phase angles are constant, the following formulae apply:    P = Real Energy [Wh] = V * A * cos φ* t Q = Reactive Energy [VARh] = V * A * sin φ * t S = Apparent Energy [VAh] = P2 + Q2 For a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic content may change constantly. Thus, simple RMS measurements are inherently inaccurate. A modern solid-state electricity meter IC such as the Teridian 71M6521DE/DH/FE functions by emulating the integral operation above, i.e. it processes current and voltage samples through an ADC at a constant frequency. As long as the ADC resolution is high enough and the sample frequency is beyond the harmonic range of interest, the current and voltage samples, multiplied with the time period of sampling will yield an accurate quantity for the momentary energy. Summing up the momentary energy quantities over time will result in accumulated energy. 500 400 300 200 100 0 0 -100 -200 Current [A] 5 10 15 20 -300 -400 -500 Voltage [V] Energy per Interval [Ws] Accumulated Energy [Ws] Figure 15: Voltage. Current, Momentary and Accumulated Energy Figure 15 shows the shapes of V(t), I(t), the momentary power and the accumulated power, resulting from 50 samples of the voltage and current signals over a period of 20ms. The application of 240VAC and 100A results in an accumulation of 480Ws (= 0.133Wh) over the 20ms period, as indicated by the Accumulated Power curve. The described sampling method works reliably, even in the presence of dynamic phase shift and harmonic distortion. Page: 48 of 107 Rev 2 71M6521DE/DH/FE Data Sheet System Timing Summary Figure 16 summarizes the timing relationships between the input MUX states, the CE_BUSY signal, and the two serial output streams. In this example, MUX_DIV=4 and FIR_LEN=1 (384). The duration of each MUX frame is 1 + MUX_DIV * 2 if FIR_LEN=288, and 1 + MUX_DIV * 3 if FIR_LEN=384. An ADC conversion will always consume an integer number of CK32 clocks. Followed by the conversions is a single CK32 cycle where the bandgap voltage is allowed to recover from the change in CROSS. Each CE program pass begins when ADC0 (channel IA) conversion begins. Depending on the length of the CE program, it may continue running until the end of the ADC3 (VB) conversion. CE opcodes are constructed to ensure that all CE code passes consume exactly the same number of cycles. The result of each ADC conversion is inserted into the CE DRAM when the conversion is complete. The CE code is written to tolerate sudden changes in ADC data. The exact CK count when each ADC value is loaded into DRAM is shown in Figure 16. Figure 16 also shows that the serial RTM data stream begins transmitting at the beginning of state ‘S.’ RTM, consisting of 140 CK cycles, will always finish before the next code pass starts. ADC MUX Frame ADC TIMING CK32 150 MUX_SYNC MUX STATE ADC EXECUTION ADC0 S 0 MUX_DIV Conversions, MUX_DIV=1 (4 conversions) is shown Settle 1 2 3 S ADC1 900 ADC2 1350 ADC3 1800 MAX CK COUNT CE TIMING CE_EXECUTION CE_BUSY XFER_BUSY 0 450 CK COUNT = CE_CYCLES + floor((CE_CYCLES + 2) / 5) INITIATED BY A CE OPCODE AT END OF SUM INTERVAL RTM TIMING RTM NOTES: 1. ALL DIMENSIONS ARE 5MHZ CK COUNTS. 2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz. 3. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS * SUM_CYCLES) CODE PASSES. 140 Figure 16: Timing Relationship between ADC MUX, Compute Engine, and Serial Transfers. CK32 MUX_SYNC CKTEST TMUXOUT/RTM LSB 0 1 30 31 LSB 0 1 30 SIG N 31 LSB 0 1 30 31 LSB 0 1 30 31 SIG N SIG N RTM DATA0 (32 bits) RTM DATA1 (32 bits) RTM DATA2 (32 bits) RTM DATA3 (32 bits) Figure 17: RTM Output Format Rev 2 Page: 49 of 107 SIG N FLAG FLAG FLAG FLAG 71M6521DE/DH/FE Data Sheet Battery Modes Shortly after system power (V3P3SYS) is applied, the part will be in MISSION mode. MISSION mode means that the part is operating with system power and that the internal PLL is stable. This mode is the normal operation mode where the part is capable of measuring energy. When system power is not available (i.e. when V1 1 V3P3SYS rises V3P3SYS rises LCD_ONLY IE_PLLFALL -> 1 RESET V1 > VBIAS V1 1 PB timer IE_WAKE -> 1 RESET & VBAT_OK SLEEP or VBAT_OK LCD timer PB VBAT_OK RESET & VBAT_OK VBAT_OK SLEEP Figure 18: Operation Modes State Diagram LCD Mode In LCD mode, the data contained in the LCD_SEG registers is displayed, i.e. up to four LCD segments connected to each of the pins SEG18 and SEG19 can be made to blink without the involvement of the MPU, which is disabled in LCD mode. This mode can be exited only by system power up, a timeout of the wake-up timer, or a push button. Figure 20 shows the functional blocks active in LCD mode. SLEEP Mode In SLEEP mode, the battery current is minimized and only the Oscillator and RTC functions are active. This mode can be exited only by system power-up, a timeout of the wake-up timer, or a push button event. Figure 21 shows the functional blocks active in SLEEP mode. Page: 52 of 107 Rev 2 71M6521DE/DH/FE Data Sheet VREF V3P3A GNDA V3P3SYS IA VA IB VB VBAT ∆Σ ADC CONVERTER MUX VBIAS VBIAS V3P3D V3P3A + ADC_E FIR VBAT FIR_LEN V3P3D TEMP MUX MUX CTRL EQU MUX_ALT CHOP_E MUX_DIV VREF VREF_CAL VREF_DIS CROSS CK32 VREF VBAT VOLT REG X4MHZ XIN XOUT CKTEST/ SEG19 OSC (32KHz) RTCLK (32KHz) MCK PLL CK32 32KHz DIV ADC CKADC LCD_ONLY SLEEP GNDD V2P5 CKOUT_E 4.9MHz CKOUT_E CK_GEN ECK_DIS MPU_DIV MUX_SYNC CKCE