MAX1110_11

19-1194; Rev 4; 4/11 KIT ATION EVALU BLE AVAILA +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs General Description ____________________________Features o 2.7V to 5.5V Single Supply o Low Power: 85µA at 50ksps 6µA at 1ksps o 8-Channel Single-Ended or 4-Channel Differential Inputs (MAX1110) o 4-Channel Single-Ended or 2-Channel Differential Inputs (MAX1111) o Internal Track/Hold; 50kHz Sampling Rate o Internal 2.048V Reference o SPI/QSPI/MICROWIRE-Compatible Serial Interface o Software-Configurable Unipolar or Bipolar Inputs o Total Unadjusted Error: ±1 LSB (max) ±0.3 LSB (typ) Ordering Information appears at end of data sheet. MAX1110/MAX1111 The MAX1110/MAX1111 low-power, 8-bit, 8-channel analog-to-digital converters (ADCs) feature an internal track/hold, voltage reference, clock, and serial interface. They operate from a single 2.7V to 5.5V supply and consume only 85µA while sampling at rates up to 50ksps. The MAX1110’s 8 analog inputs and the MAX1111’s 4 analog inputs are software-configurable, allowing unipolar/bipolar and single-ended/differential operation. Successive-approximation conversions are performed using either the internal clock or an external serial-interface clock. The full-scale analog input range is determined by the 2.048V internal reference, or by an externally applied reference ranging from 1V to VDD. The 4-wire serial interface is compatible with the SPI™, QSPI™, and MICROWIRE™ serial-interface standards. A serial-strobe output provides the end-of-conversion signal for interrupt-driven processors. The MAX1110/MAX1111 have a software-programmable, 2µA automatic power-down mode to minimize power consumption. Using power-down, the supply current is reduced to 6µA at 1ksps, and only 52µA at 10ksps. Power-down can also be controlled using the SHDN input pin. Accessing the serial interface automatically powers up the device. The MAX1110 is available in a 20-pin SSOP package. The MAX1111 is available in a small 16-pin QSOP package. ________________Functional Diagram CS SCLK DIN SHDN INPUT SHIFT REGISTER INT CLOCK CONTROL LOGIC OUTPUT SHIFT REGISTER ANALOG INPUT MUX T/H CLOCK IN 8-BIT SAR ADC OUT REF DOUT SSTRB ________________________Applications Portable Data Logging Hand-Held Measurement Devices Medical Instruments System Diagnostics Solar-Powered Remote Systems 4mA to 20mA-Powered Remote Data-Acquisition Systems Pin Configurations appear at end of data sheet. CH0 CH1 CH2 CH3 CH4* CH5* CH6* CH7* COM REFOUT REFIN VDD DGND +2.048V REFERENCE MAX1110 MAX1111 AGND *MAX1110 ONLY SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs MAX1110/MAX1111 ABSOLUTE MAXIMUM RATINGS VDD to AGND ..............................................................-0.3V to 6V AGND to DGND .......................................................-0.3V to 0.3V CH0–CH7, COM, REFIN, REFOUT to AGND ......................................-0.3V to (VDD + 0.3V) Digital Inputs to DGND ...............................................-0.3V to 6V Digital Outputs to DGND ............................-0.3V to (VDD + 0.3V) Continuous Power Dissipation (TA = +70°C) QSOP (derate 8.30mW/°C above +70°C) .....................667mW SSOP (derate 8.00mW/°C above +70°C) .....................640mW Operating Temperature Ranges MAX1110CAP/MAX1111CEE...............................0°C to +70°C MAX1110EAP/MAX1111EGE............................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 2.7V to 5.5V; unipolar input mode; VCOM = 0V; fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1µF capacitor at REFOUT; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER DC ACCURACY Resolution Relative Accuracy (Note 1) Differential Nonlinearity Offset Error Gain Error (Note 3) Gain Temperature Coefficient Total Unadjusted Error Channel-to-Channel Offset Matching DYNAMIC SPECIFICATIONS (10.034kHz sine-wave input, 2.048VP-P, 50ksps, 500kHz external clock) Signal-to-Noise and Distortion Ratio Total Harmonic Distortion (up to the 5th harmonic) Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Small-Signal Bandwidth Full-Power Bandwidth SINAD THD SFDR VCH_ = 2.048VP-P, 25kHz (Note 4) -3dB rolloff 49 -70 68 -75 1.5 800 dB dB dB dB MHz kHz TUE INL DNL VDD = 2.7V to 3.6V VDD = 5.5V (Note 2) No missing codes over temperature VDD = 2.7V to 3.6V VDD = 5.5V (Note 2) Internal or external reference External reference, 2.048V ±0.8 ±0.3 ±0.1 ±1 ±0.35 ±0.5 ±1 8 ±0.15 ±0.2 ±1 ±1 ±0.5 Bits LSB LSB LSB LSB ppm/°C LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS 2 _______________________________________________________________________________________ +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs ELECTRICAL CHARACTERISTICS (continued) (VDD = 2.7V to 5.5V; unipolar input mode; VCOM = 0V; fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1µF capacitor at REFOUT; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER CONVERSION RATE Conversion Time (Note 5) Track/Hold Acquisition Time Aperture Delay Aperture Jitter Internal Clock Frequency External Clock-Frequency Range ANALOG INPUT Input Voltage Range, SingleEnded and Differential (Note 7) Multiplexer Leakage Current Input Capacitance INTERNAL REFERENCE REFOUT Voltage REFOUT Short-Circuit Current REFOUT Temperature Coefficient Load Regulation (Note 8) Capacitive Bypass at REFOUT EXTERNAL REFERENCE AT REFIN Input Voltage Range Input Current POWER REQUIREMENTS Supply Voltage VDD VDD = 2.7V to 3.6V Full-scale input CLOAD = 10pF Supply Current (Note 2) IDD VDD = 5.5V Full-scale input CLOAD = 10pF Power-down Power-Supply Rejection (Note 10) PSR Operating mode Reference disabled Operating mode Reference disabled Software SHDN at DGND 2.7 85 45 120 80 2 3.2 ±0.4 10 ±4 mV 250 µA 5.5 250 V (Note 9) 1 1 VDD + 0.05 20 V µA 0 to 0.5mA output load 1 1.968 2.048 3.5 ±50 2.5 2.128 V mA ppm/°C mV µF Unipolar input, VCOM = 0V Bipolar input, VCOM = VREFIN/2 On/off-leakage current, VCH_ = 0V or VDD ±0.01 18 0 VREFIN VCOM ± VREFIN/2 ±1 V V µA pF (Note 6) Used for data transfer only 50 tCONV tACQ Internal clock External clock, 500kHz, 10 clocks/conversion External clock, 2MHz 20 1 10 3.6V 2 3 0.8 V V V µA pF SYMBOL CONDITIONS MIN TYP MAX UNITS 4 _______________________________________________________________________________________ +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs TIMING CHARACTERISTICS (Figures 8 and 9) (VDD = 2.7V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Track/Hold Acquisition Time DIN to SCLK Setup DIN to SCLK Hold SCLK Fall to Output Data Valid CS Fall to Output Enable CS Rise to Output Disable CS to SCLK Rise Setup CS to SCLK Rise Hold SCLK Pulse Width High SCLK Pulse Width Low SCLK Fall to SSTRB CS Fall to SSTRB Output Enable (Note 6) CS Rise to SSTRB output Disable (Note 6) SSTRB Rise to SCLK Rise (Note 6) Wake-Up Time SYMBOL tACQ tDS tDH tDO tDV tTR tCSS tCSH tCH tCL t SSTRB tSDV tSTR tSCK tWAKE CLOAD = 100pF Figure 1, external clock mode only, CLOAD = 100pF Figure 2, external clock mode only, CLOAD = 100pF Figure 11, internal clock mode only External reference Internal reference (Note 11) 0 20 12 Figure 1, CLOAD = 100pF Figure 1, CLOAD = 100pF Figure 2, CLOAD = 100pF 100 0 200 200 240 240 240 CONDITIONS MIN 1 100 0 20 200 240 240 TYP MAX UNITS µs ns ns ns ns ns ns ns ns ns ns ns ns ns µs ms MAX1110/MAX1111 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated. See Typical Operating Characteristics. VREFIN = 2.048V, offset nulled. On-channel grounded; sine wave applied to all off-channels. Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Guaranteed by design. Not subject to production testing. Common-mode range for the analog inputs is from AGND to VDD. External load should not change during the conversion for specified accuracy. External reference at 2.048V, full-scale input, 500kHz external clock. Measured as | VFS (2.7V) - VFS (3.6V) |. 1µF at REFOUT; internal reference settling to 0.5 LSB. _______________________________________________________________________________________ 5 +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs MAX1110/MAX1111 __________________________________________Typical Operating Characteristics (VDD = 2.7V; fSCLK = 500kHz; external clock (50% duty cycle); RL = ∞; TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX1110-01 SUPPLY CURRENT vs. TEMPERATURE OUTPUT CODE = FULL SCALE CLOAD = 10pF MAX1110-02 SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE SHDN = DGND 4.5 4.0 3.5 3.0 2.5 2.0 MAX1110-03 400 OUTPUT CODE = 10101010 350 SUPPLY CURRENT (μA) 300 250 CLOAD = 60pF 200 150 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 CLOAD = 30pF 160 5.0 SHUTDOWN SUPPLY CURRENT (μA) 140 SUPPLY CURRENT (μA) 120 VDD = 5.5V 100 80 VDD = 3.6V 60 6.0 -60 -20 20 60 100 140 SUPPLY VOLTAGE (V) TEMPERATURE (°C) -60 -20 20 60 100 140 TEMPERATURE (°C) OFFSET ERROR vs. SUPPLY VOLTAGE MAX1110-04 INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE MAX1110-05 DIFFERENTIAL NONLINEARITY vs. CODE MAX1110-06 0.8 0.7 OFFSET ERROR (LSB) 0.6 0.5 0.3 0.2 0.1 DNL (LSB) 0.4 INL (LSB) 0.5 0.4 0.3 0.2 0.1 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) 0.3 0 -0.1 0.2 0.1 -0.2 -0.3 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 64 128 DIGITAL CODE 192 256 SUPPLY VOLTAGE (V) 0 OFFSET ERROR vs. TEMPERATURE MAX1110-07 INTEGRAL NONLINEARITY vs. CODE MAX1110-08 FFT PLOT fCH_ = 10.034kHz, 2VP-P fSAMPLE = 50ksps MAX1110-09 0.6 0.5 OFFSET ERROR (LSB) 0.4 0.3 0.2 0.1 0 -60 -20 20 60 100 0.20 0.15 0.10 INL (LSB) 0.05 0 -0.05 -0.10 -0.15 -0.20 20 0 AMPLITUDE (dB) -20 -40 -60 -80 -100 140 0 64 128 DIGITAL CODE 192 256 0 5 10 15 20 25 TEMPERATURE (°C) FREQUENCY (kHz) 6 _______________________________________________________________________________________ +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs ______________________________________________________________Pin Description PIN NAME MAX1110 1–4 5–8 9 MAX1111 1–4 — 5 CH0–CH3 CH4–CH7 COM Sampling Analog Inputs Sampling Analog Inputs Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode. Must be stable to ±0.5 LSB. Three-Level Shutdown Input. Normally high impedance. Pulling SHDN low shuts the MAX1110/MAX1111 down to 10µA (max) supply current; otherwise, the devices are fully operational. Pulling SHDN high shuts down the internal reference. Reference Voltage Input for Analog-to-Digital Conversion. Connect to REFOUT to use the internal reference. Internal Reference Generator Output. Bypass with a 1µF capacitor to AGND. Analog Ground Digital Ground Serial-Data Output. Data is clocked out on SCLK’s falling edge. High impedance when CS is high. Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1110/ MAX1111 begin the A/D conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses high for two clock periods before the MSB is shifted out. High impedance when CS is high (external clock mode only). Serial-Data Input. Data is clocked in at SCLK’s rising edge. The voltage at DIN can exceed VDD (up to 5.5V). Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is high impedance. The voltage at CS can exceed VDD (up to 5.5V). Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets the conversion speed (duty cycle must be 45% to 55%). The voltage at SCLK can exceed VDD (up to 5.5V). Positive Supply Voltage, 2.7V to 5.5V FUNCTION MAX1110/MAX1111 10 6 SHDN 11 12 13 14 15 7 8 9 10 11 REFIN REFOUT AGND DGND DOUT 16 12 SSTRB 17 18 13 14 DIN CS 19 20 15 16 SCLK VDD +3V +3V 3kΩ DOUT 3kΩ DGND a) VOH to High-Z DOUT DOUT 3kΩ DGND a) High-Z to VOH and VOL to VOH DOUT 3kΩ CLOAD CLOAD DGND b) High-Z to VOL and VOH to VOL CLOAD CLOAD DGND b) VOL to High-Z Figure 1. Load Circuits for Enable Time Figure 2. Load Circuits for Disable Time _______________________________________________________________________________________ 7 +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs MAX1110/MAX1111 _______________Detailed Description The MAX1110/MAX1111 analog-to-digital converters (ADCs) use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to an 8-bit digital output. A flexible serial interface provides easy interface to microprocessors (µPs). Figure 3 shows the Typical Operating Circuit. acquisition interval spans two SCLK cycles and ends on the falling SCLK edge after the last bit of the input control word has been entered. At the end of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplexer switching CHOLD from the positive input (IN+) to the negative input (IN-). In single-ended mode, IN- is simply COM. This unbalances node ZERO at the input of the comparator. The capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to 0V within the limits of 8-bit resolution. This action is equivalent to transferring a charge of 18pF x (VIN+ - VIN-) from CHOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal. Pseudo-Differential Input The sampling architecture of the ADC’s analog comparator is illustrated in Figure 4, the equivalent input circuit. In single-ended mode, IN+ is internally switched to the selected input channel, CH_, and IN- is switched to COM. In differential mode, IN+ and IN- are selected from the following pairs: CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure the MAX1110 channels with Table 1 and the MAX1111 channels with Table 2. In differential mode, IN- and IN+ are internally switched to either of the analog inputs. This configuration is pseudo-differential to the effect that only the signal at IN+ is sampled. The return side (IN-) must remain stable within ±0.5 LSB (±0.1 LSB for best results) with respect to AGND during a conversion. To accomplish this, connect a 0.1µF capacitor from IN- (the selected analog input) to AGND. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. The Track/Hold The T/H enters its tracking mode on the falling clock edge after the sixth bit of the 8-bit control byte has been shifted in. It enters its hold mode on the falling clock edge after the eighth bit of the control byte has been shifted in. If the converter is set up for singleended inputs, IN- is connected to COM, and the converter samples the “+” input; if it is set up for differential inputs, IN- connects to the “-” input, and the difference (IN+ - IN-) is sampled. At the end of the conversion, the positive input connects back to IN+, and C HOLD charges to the input signal. +2.7V CH0 ANALOG INPUTS CH7 VDD AGND DGND COM VDD CH0 CH1 REFIN CAPACITIVE DAC COMPARATOR ZERO 0.1μF 1μF CHOLD INPUT MUX – + 18pF CSWITCH TRACK T/H SWITCH CPU MAX1110 MAX1111 REFOUT REFIN 1μ F CS SCLK DIN DOUT SSTRB SHDN VSS I/O SCK (SK) MOSI (SO) MISO (SI) CH2 CH3 CH4* CH5* CH6* CH7* COM 6.5kΩ RIN HOLD AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL. SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = COM. DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CH0/CH1, CH2/CH3, CH4*/CH5*, CH6*/CH7*. *MAX1110 ONLY Figure 3. Typical Operating Circuit 8 Figure 4. Equivalent Input Circuit _______________________________________________________________________________________ +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs Table 1a. MAX1110 Channel Selection in Single-Ended Mode (SGL/DIF = 1) SEL2 0 1 0 1 0 1 0 1 SEL1 0 0 0 0 1 1 1 1 SEL0 0 0 1 1 0 0 1 1 CH0 + + + + + + + + CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM – – – – – – – – MAX1110/MAX1111 Table 1b. MAX1110 Channel Selection in Differential Mode (SGL/DIF = 0) SEL2 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 – + – + – + – + CH0 + CH1 – + – + – + – CH2 CH3 CH4 CH5 CH6 CH7 Table 2a. MAX1111 Channel Selection in Single-Ended Mode (SGL/DIF = 1) SEL2 0 1 0 1 SEL1 0 0 1 1 SEL0 X X X X CH0 + + + + CH1 CH2 CH3 COM – – – – Table 2b. MAX1111 Channel Selection in Differential Mode (SGL/DIF = 0) SEL2 0 0 1 1 SEL1 0 1 0 1 SEL0 X X X X – + – + CH0 + CH1 – + – CH2 CH3 _______________________________________________________________________________________ 9 +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs MAX1110/MAX1111 The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. The acquisition time, tACQ, is the minimum time needed for the signal to be acquired. It is calculated by: tACQ = 6 x (RS + RIN) x 18pF where RIN = 6.5kΩ, RS = the source impedance of the input signal, and tACQ is never less than 1µs. Note that source impedances below 2.4kΩ do not significantly affect the AC performance of the ADC. age. However, for accurate conversions near full scale, the inputs must not exceed VDD by more than 50mV or be lower than AGND by 50mV. If the analog input exceeds 50mV beyond the supplies, do not forward bias the protection diodes of off channels over 2mA. The MAX1110/MAX1111 can be configured for differential or single-ended inputs with bits 2 and 3 of the control byte (Table 3). In single-ended mode, the analog inputs are internally referenced to COM with a full-scale input range from COM to VREFIN + COM. For bipolar operation, set COM to VREFIN/2. In differential mode, choosing unipolar mode sets the differential input range at 0V to V REFIN. In unipolar mode, the output code is invalid (code zero) when a negative differential input voltage is applied. Bipolar mode sets the differential input range to ±VREFIN/2. Note that in this mode, the common-mode input range includes both supply rails. Refer to Table 4 for input voltage ranges. Input Bandwidth The ADC’s input tracking circuitry has a 1.5MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid highfrequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. Analog Inputs Internal protection diodes, which clamp the analog input to VDD and AGND, allow the channel input pins to swing from (AGND - 0.3V) to (VDD + 0.3V) without dam- Quick Look To quickly evaluate the MAX1110/MAX1111’s analog performance, use the circuit of Figure 5. The MAX1110/MAX1111 require a control byte to be written to DIN before each conversion. Tying DIN to +3V feeds Table 3. Control-Byte Format BIT 7 (MSB) START BIT 7 (MSB) 6 5 4 3 BIT 6 SEL2 NAME START SEL2 SEL1 SEL0 UNI/BIP BIT 5 SEL1 BIT 4 SEL0 BIT 3 UNI/BIP BIT 2 SGL/DIF BIT 1 PD1 BIT 0 (LSB) PD0 DESCRIPTION The first logic “1” bit after CS goes low defines the beginning of the control byte. Select which of the input channels are to be used for the conversion (Tables 1 and 2). 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. Select differential operation if bipolar mode is used (Table 4). 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In singleended mode, input signal voltages are referred to COM. In differential mode, the voltage difference between two channels is measured (Tables 1 and 2). 1 = fully operational, 0 = power-down. Selects fully operational or power-down mode. 1 = external clock mode, 0 = internal clock mode. Selects external or internal clock mode. 2 SGL/DIF 1 0 (LSB) PD1 PD0 10 ______________________________________________________________________________________ +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs Table 4. Full-Scale and Zero-Scale Voltages UNIPOLAR MODE Full Scale VREFIN + COM Zero Scale COM Positive Full Scale +VREFIN/2 + COM BIPOLAR MODE Zero Scale COM Negative Full Scale -VREFIN/2 + COM MAX1110/MAX1111 in control bytes of $FF (hex), which trigger singleended, unipolar conversions on CH7 (MAX1110) or CH3 (MAX1111) in external clock mode without powering down between conversions. In external clock mode, the SSTRB output pulses high for two clock periods before the most significant bit of the 8-bit conversion result is shifted out of DOUT. Varying the analog input alters the output code. A total of 10 clock cycles is required per conversion. All transitions of the SSTRB and DOUT outputs occur on SCLK’s falling edge. How to Start a Conversion A conversion is started by clocking a control byte into DIN. With CS low, each rising edge on SCLK clocks a bit from DIN into the MAX1110/MAX1111’s internal shift reg- ister. After CS falls, the first arriving logic “1” bit at DIN defines the MSB of the control byte. Until this first start bit arrives, any number of logic “0” bits can be clocked into DIN with no effect. Table 3 shows the control-byte format. The MAX1110/MAX1111 are compatible with MICROWIRE, SPI, and QSPI devices. For SPI, select the correct clock polarity and sampling edge in the SPI control registers: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI, and QSPI all transmit a byte and receive a byte at the same time. Using the Typical Operating Circuit (Figure 3), the simplest software interface requires three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the 8-bit conversion result). Figure 6 shows the MAX1110/ MAX1111 common serial-interface connections. VDD 0.1µF DGND 1µF +3V OSCILLOSCOPE SCLK SSTRB DOUT* 0V TO +2.048V ANALOG 0.01µF INPUT MAX1110 MAX1111 CH7 (CH3) AGND CS SCLK COM DIN SSTRB +3V 500kHz OSCILLATOR CH1 CH2 CH3 CH4 REFOUT REFIN C1 1µF DOUT SHDN N.C. *FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FF (HEX) ( ) ARE FOR THE MAX1111. Figure 5. Quick-Look Circuit ______________________________________________________________________________________ 11 +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs MAX1110/MAX1111 I/O SCK MISO +3V CS SCLK DOUT MAX1110 MAX1111 SS a) SPI CS SCK MISO +3V CS SCLK DOUT Simple Software Interface Make sure the CPU’s serial interface runs in master mode so the CPU generates the serial clock. Choose a clock frequency from 50kHz to 500kHz. 1) Set up the control byte for external clock mode and call it TB1. TB1 should be of the format 1XXXXX11 binary, where the Xs denote the particular channel and conversion mode selected. 2) Use a general-purpose I/O line on the CPU to pull CS low. 3) Transmit TB1 and, simultaneously, receive a byte and call it RB1. Ignore RB1. 4) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB2. 5) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB3. 6) Pull CS high. Figure 7 shows the timing for this sequence. Bytes RB2 and RB3 contain the result of the conversion padded with two leading zeros and six trailing zeros. The total conversion time is a function of the serial-clock frequency and the amount of idle time between 8-bit transfers. Make sure that the total conversion time does not exceed 1ms, to avoid excessive T/H droop. SS b) QSPI I/O SK SI CS MAX1110 MAX1111 SCLK DOUT MAX1110 MAX1111 c) MICROWIRE Figure 6. Common Serial-Interface Connections to the MAX1110/MAX1111 Digital Inputs CS, SCLK, and DIN can accept input signals up to 5.5V, regardless of the supply voltages. This allows the MAX1110/MAX1111 to accept digital inputs from both 3V and 5V systems. CS tACQ SCLK DIN START 1 4 SEL2 SEL1 SEL0 UNI/ BIP SGL/ PD1 DIF 8 12 16 20 24 PD0 SSTRB RB1 DOUT ACQUISITION 4μs (fSCLK = 500kHz) B7 B6 RB2 B5 B4 B3 B2 B1 B0 RB3 FILLED WITH ZEROS A/D STATE IDLE CONVERSION IDLE Figure 7. Single-Conversion Timing, External Clock Mode, 24 Clocks 12 ______________________________________________________________________________________ +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs Digital Output In unipolar input mode, the output is straight binary (Figure 15). For bipolar inputs, the output is two’s-complement (Figure 16). Data is clocked out at SCLK’s falling edge in MSB-first format. conversion steps. SSTRB pulses high for two clock periods after the last bit of the control byte. Successiveapproximation bit decisions are made and appear at DOUT on each of the next eight SCLK falling edges (Figure 7). After the eight data bits are clocked out, subsequent clock pulses clock out zeros from the DOUT pin. SSTRB and DOUT go into a high-impedance state when CS goes high; after the next CS falling edge, SSTRB outputs a logic low. Figure 9 shows the SSTRB timing in external clock mode. The conversion must complete in 1ms, or droop on the sample-and-hold capacitors can degrade conversion results. Use internal clock mode if the serial-clock frequency is less than 50kHz, or if serial-clock interruptions could cause the conversion interval to exceed 1ms. MAX1110/MAX1111 Clock Modes The MAX1110/MAX1111 can use either an external serial clock or the internal clock to perform the successiveapproximation conversion. In both clock modes, the external clock shifts data in and out of the devices. Bit PD0 of the control byte programs the clock mode. Figures 8–11 show the timing characteristics common to both modes. External Clock In external clock mode, the external clock not only shifts data in and out, it also drives the analog-to-digital CS ••• tCSH SCLK tDS tDH DIN tDV DOUT tDO ••• ••• tCSS tCL tCH ••• tCSH tDO tTR Figure 8. Detailed Serial-Interface Timing CS ••• tSDV ••• ••• ••• tSTR SSTRB tSSTRB tSSTRB SCLK •••• •••• PD0 CLOCKED IN Figure 9. External Clock Mode SSTRB Detailed Timing ______________________________________________________________________________________ 13 +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs MAX1110/MAX1111 CS SCLK DIN SSTRB 1 2 3 4 5 6 7 8 9 10 11 12 15 16 17 18 SEL2 SEL1 SEL0 UNI/ BIP START SGL/ PD1 DIF PD0 tCONV DOUT CONVERSION 25µs TYP B7 B6 B1 B0 FILLED WITH ZEROS IDLE A/D STATE IDLE tACQ 4µs (fSCLK = 500kHz) Figure 10. Internal Clock Mode Timing CS tCSH SSTRB tCONV tSCK tCSS tSSTRB SCLK PD0 CLOCK IN NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION. Figure 11. Internal Clock Mode SSTRB Detailed Timing Internal Clock Internal clock mode frees the µP from the burden of running the SAR conversion clock. This allows the conversion results to be read back at the processor’s convenience, at any clock rate up to 2MHz. SSTRB goes low at the start of the conversion and then goes high when the conversion is complete. SSTRB is low for 25µs (typ), during which time SCLK should remain low for best noise performance. An internal register stores data when the conversion is in progress. SCLK clocks the data out of this register at any time after the conversion is complete. After SSTRB goes high, the second falling clock edge produces the MSB of the conversion at DOUT, followed by the 14 remaining bits in MSB-first format (Figure 10). CS does not need to be held low once a conversion is started. Pulling CS high prevents data from being clocked into the MAX1110/MAX1111 and three-states DOUT, but it does not adversely affect an internal clock-mode conversion already in progress. When internal clock mode is selected, SSTRB does not go into a high-impedance state when CS goes high. Figure 11 shows the SSTRB timing in internal clock mode. In this mode, data can be shifted in and out of the MAX1110/MAX1111 at clock rates up to 2MHz, provided that the minimum acquisition time, tACQ, is kept above 1µs. ______________________________________________________________________________________ +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs MAX1110/MAX1111 CS 1 SCLK DIN DOUT SSTRB S CONTROL BYTE 0 S B7 CONVERSION RESULT 0 CONTROL BYTE 1 B0 S B7 CONVERSION RESULT 1 CONTROL BYTE 2 B0 S B7 CONVERSION RESULT 2 CONTROL BYTE 3 8 10 1 8 10 1 8 10 1 Figure 12a. Continuous Conversions, External Clock Mode, 10 Clocks/Conversion Timing CS SCLK DIN DOUT S CONTROL BYTE 0 B7 CONVERSION RESULT 0 S B0 CONTROL BYTE 1 B7 CONVERSION RESULT 1 Figure 12b. Continuous Conversions, External Clock Mode, 16 Clocks/Conversion Timing Data Framing The falling edge of CS does not start a conversion. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control byte. A conversion starts on the falling edge of SCLK, after the eighth bit of the control byte (the PD0 bit) is clocked into DIN. The start bit is defined as: The first high bit clocked into DIN with CS low any time the converter is idle; e.g., after VDD is applied. OR The first high bit clocked into DIN after the MSB of a conversion in progress is clocked onto the DOUT pin. If CS is toggled before the current conversion is complete, then the next high bit clocked into DIN is recognized as a start bit; the current conversion is terminated, and a new one is started. The fastest the MAX1110/MAX1111 can run is 10 clocks per conversion. Figure 12a shows the serialinterface timing necessary to perform a conversion every 10 SCLK cycles in external clock mode. Many microcontrollers require that conversions occur in multiples of eight SCLK clocks; 16 clocks per conversion is typically the fastest that a microcontroller can drive the MAX1110/MAX1111. Figure 12b shows the serial-interface timing necessary to perform a conversion every 16 SCLK cycles in external clock mode. 15 ______________________________________________________________________________________ +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs MAX1110/MAX1111 Applications Information Power-On Reset When power is first applied, and if SHDN is not pulled low, internal power-on reset circuitry activates the MAX1110/MAX1111 in internal clock mode. SSTRB is high on power-up and, if CS is low, the first logical 1 on DIN is interpreted as a start bit. Until a conversion takes place, DOUT shifts out zeros. No conversions should be performed until the reference voltage has stabilized (see Electrical Characteristics). Power-Down When operating at speeds below the maximum sampling rate, the MAX1110/MAX1111’s automatic powerdown mode can save considerable power by placing the converters in a low-current shutdown state between conversions. Figure 13 shows the average supply current as a function of the sampling rate. Select power-down with PD1 of the DIN control byte with S HDN high or high impedance (Table 3). Pull SHDN low at any time to shut down the converters completely. S HDN o verrides PD1 of the control byte. Figures 14a and 14b illustrate the various power-down sequences in both external and internal clock modes. Hard-Wired Power-Down Pulling SHDN low places the converters in hard-wired power-down. Unlike software power-down, the conversion is not completed; it stops coincidentally with SHDN being brought low. SHDN also controls the state of the internal reference (Table 5). Letting S HDN high impedance enables the internal 2.048V voltage reference. When returning to normal operation with SHDN high impedance, there is a tRC delay of approximately 1MΩ x CLOAD, where CLOAD is the capacitive loading on the SHDN pin. Pulling SHDN high disables the internal reference, which saves power when using an external reference. External Reference An external reference between 1V and VDD should be connected directly at the REFIN terminal. The DC input impedance at REFIN is extremely high, consisting of leakage current only (typically 10nA). During a conversion, the reference must be able to deliver up to 20µA average load current and have an output impedance of 1kΩ or less at the conversion clock frequency. If the reference has higher output impedance or is noisy, bypass it close to the REFIN pin with a 0.1µF capacitor. If an external reference is used with the MAX1110/ MAX1111, connect SHDN to VDD to disable the internal reference and decrease power consumption. SUPPLY CURRENT (μA) Software Power-Down Software power-down is activated using bit PD1 of the control byte. When software power-down is asserted, the ADCs continue to operate in the last specified clock mode until the conversion is complete. The ADCs then power down into a low quiescent-current state. In internal clock mode, the interface remains active, and conversion results can be clocked out after the MAX1110/ MAX1111 have entered a software power-down. The first logical 1 on DIN is interpreted as a start bit, which powers up the MAX1110/MAX1111. If the DIN byte contains PD1 = 1, then the chip remains powered up. If PD1 = 0, power-down resumes after one conversion. CLOAD = 60pF CODE = 10101010 100 CLOAD = 30pF CODE = 10101010 10 CLOAD = 30pF CODE = 11111111 VDD = VREFIN = 3V CLOAD AT DOUT AND SSTRB 1 0 10 20 30 40 Table 5. Hard-Wired Power-Down and Internal Reference State SHDN STATE 1 High Impedance 0 DEVICE MODE Enabled Enabled Power-Down INTERNAL REFERENCE Disabled Enabled Disabled 50 SAMPLING RATE (ksps) Figure 13. Average Supply Current vs. Sampling Rate 16 ______________________________________________________________________________________ MAX1110-fig13 1000 +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs MAX1110/MAX1111 CLOCK MODE SHDN INTERNAL EXTERNAL EXTERNAL SETS EXTERNAL CLOCK MODE DIN SXXXXX11 SXXXXX01 SETS POWERDOWN MODE SETS EXTERNAL CLOCK MODE SXX XXX1 1 DOUT DATA VALID DATA VALID DATA INVALID POWERDOWN POWERDOWN MODE POWERED UP POWERED UP POWERED UP Figure 14a. Power-Down Modes, External Clock Timing Diagram INTERNAL CLOCK MODE SETS INTERNAL CLOCK MODE DIN SXXXXX10 SXXXXX00 SETS POWER-DOWN MODE S DOUT SSTRB DATA VALID DATA VALID CONVERSION POWERED UP CONVERSION POWER-DOWN POWERED UP MODE Figure 14b. Power-Down Modes, Internal Clock Timing Diagram Internal Reference To use the MAX1110/MAX1111 with the internal reference, connect REFIN to REFOUT. The full-scale range of the MAX1110/MAX1111 with the internal reference is typically 2.048V with unipolar inputs, and ±1.024V with bipolar inputs. The internal reference should be bypassed to AGND with a 1µF capacitor placed as close to the REFIN pin as possible. Transfer Function Table 4 shows the full-scale voltage ranges for unipolar and bipolar modes. Figure 15 depicts the nominal, unipolar I/O transfer function, and Figure 16 shows the bipolar I/O transfer function when using a 2.048V reference. Code transitions occur at integer LSB values. Output coding is binary, with 1 LSB = 8mV (2.048V/256) for unipolar operation and 1 LSB = 8mV [(2.048V/2 - -2.048V/2)/256] for bipolar operation. ______________________________________________________________________________________ 17 +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs MAX1110/MAX1111 OUTPUT CODE 11111111 11111110 11111101 FULL-SCALE TRANSITION SUPPLIES +3V GND FS = VREFIN + COM 1LSB = VREFIN 256 00000011 00000010 00000001 00000000 0 (COM) 1 2 3 INPUT VOLTAGE (LSB) FS FS - 1LSB R* = 10Ω VDD AGND DGND +3V DGND MAX1110 MAX1111 * OPTIONAL DIGITAL CIRCUITRY Figure 15. Unipolar Transfer Function Figure 17. Power-Supply Grounding Connections Layout, Grounding, and Bypassing OUTPUT CODE 01111111 01111110 V +FS = REFIN + COM 2 VREFIN COM = 2 -V -FS = REFIN + COM 2 VREFIN 1LSB = 256 00000010 00000001 00000000 11111111 11111110 11111101 10000001 10000000 -FS COM INPUT VOLTAGE (LSB) 1 +FS - 2 LSB For best performance, use printed circuit boards. Wirewrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. Figure 17 shows the recommended system ground connections. A single-point analog ground (star ground point) should be established at AGND, separate from the logic ground. Connect all other analog grounds and DGND to the star ground. No other digital system ground should be connected to this ground. The ground return to the power supply for the star ground should be low impedance and as short as possible for noise-free operation. High-frequency noise in the VDD power supply can affect the comparator in the ADC. Bypass the supply to the star ground with 0.1µF and 1µF capacitors close to the V DD pin of the MAX1110/MAX1111. Minimize capacitor lead lengths for best supply-noise rejection. If the +3V power supply is very noisy, a 10Ω resistor can be connected to form a lowpass filter. Figure 16. Bipolar Transfer Function 18 ______________________________________________________________________________________ +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs Pin Configurations TOP VIEW CH0 1 CH1 2 CH2 3 CH3 4 CH4 5 CH5 6 CH6 7 CH7 8 COM 9 SHDN 10 MAX1110/MAX1111 + 20 VDD 19 SCLK 18 CS 17 DIN CH0 1 CH1 2 CH2 3 CH3 4 COM 5 SHDN 6 REFIN 7 REFOUT 8 + 16 VDD 15 SCLK 14 CS MAX1110 16 SSTRB 15 DOUT 14 DGND 13 AGND 12 REFOUT 11 REFIN MAX1111 13 DIN 12 SSTRB 11 DOUT 10 DGND 9 AGND QSOP SSOP Ordering Information PART MAX1110CAP+ MAX1110C/D MAX1110EAP+ MAX1111CEE+ MAX1111EEE+ MAX1111EEE/V+ TEMP RANGE 0°C to +70°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C -40°C to +85°C PIN-PACKAGE 20 SSOP Dice* 20 SSOP 16 QSOP 16 QSOP 16 QSOP Chip Information PROCESS: CMOS SUBSTRATE CONNECTED TO DGND Package Information For the latest package outline information and land patterns (footnote), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 20 SSOP 16 QSOP PACKAGE CODE A20+1 E16+1 OUTLINE NO. 21-0056 21-0055 LAND PATTERN NO. 90-0094 90-0167 *Dice are specified at TA = +25°C, DC parameters only. +Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part. ______________________________________________________________________________________ 19 +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs MAX1110/MAX1111 Revision History REVISION NUMBER 3 4 REVISION DATE 2/10 4/11 DESCRIPTION Added automotive qualified part to data sheet Removed PDIP packages from data sheet. Revised Timing Characteristics table and included style updates throughout data sheet. PAGES CHANGED 19 1–7, 10, 13, 14, 16, 18, 19 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.