MAX1150

19-1169; Rev 0; 12/96 KIT ATION EVALU LE VAILAB A 8-Bit, 500Msps Flash ADC ____________________________Features o o o o o 1:2 Demuxed ECL-Compatible Outputs Wide Input Bandwidth: 900MHz Low Input Capacitance: 15pF Metastable Errors Reduced to 1LSB Single -5.2V Supply _______________General Description The MAX1150 is a parallel flash analog-to-digital converter (ADC) capable of digitizing full-scale (0V to -2V) inputs into 8-bit digital words at an update rate of 500Msps. The ECL-compatible outputs are demuxed into two separate output banks, each with differential data-ready outputs to ease the task of data capture. The MAX1150’s wide input bandwidth and low capacitance eliminate the need for external track/hold amplifiers for most applications. A proprietary decoding scheme reduces metastable errors to 1LSB. This device operates from a single -5.2V supply, with a nominal power dissipation of 5.5W. MAX1150 ________________________Applications Digital Oscilloscopes Data Acquisition Transient-Capture Applications Radar, EW, ECM Direct RF/IF Downconversion Pin Configuration appears on last page. ______________Ordering Information PART MAX1150AIZS MAX1150BIZS TEMP. RANGE -20°C to +85°C -20°C to +85°C PIN-PACKAGE 80 MQUAD 80 MQUAD _________________________________________________________Functional Diagram CLK NCLK CLOCK BUFFER ANALOG VRT INPUT PREAMP COMPARATOR 255 DEMUX CLOCK BUFFER MAX1150 254 D8 (OVR) D8B D7B • • D5B • • ECL OUTPUT BUFFERS AND LATCHES D2B D1B D0B D8A D7A • • • D5A NDRB (NOT DATA READY) DRB (DATA READY) D8B (OVR) D7B (MSB) D6B D5B D4B D3B D2B D1B D0B (LSB) NDRA (NOT DATA READY) DRA (DATA READY) D8A (OVR) D7A (MSB) D6A D5A D4A D3A D2A D1A D0A (LSB) BANK A BANK B 152 D7 (MSB) 256-BIT TO 8-BIT DECODER WITH METASTABLE ERROR CORRECTION D6 151 128 VRM 127 D5 D4 64 D3 63 1:2 DEMULTIPLEXER D2 • • • D2A 2 D1 D1A 1 D0 (LSB) D0A VFB ________________________________________________________________ Maxim Integrated Products 1 For the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 8-Bit, 500Msps Flash ADC MAX1150 ABSOLUTE MAXIMUM RATINGS Supply Voltages Negative Supply Voltage (VEE to GND) ............-7.0V to +0.5V Ground Voltage Differential ...............................-0.5V to +0.5V Input Voltages Analog Input Voltage............................................+0.5V to VEE Reference Input Voltage ......................................+0.5V to VEE Digital Input Voltage.............................................+0.5V to VEE Reference Current (VRT to VRB) ......................................35mA Digital Output Current ...........................................0mA to -28mA Operating Temperature Range ...........................-20°C to +85°C Case Temperature ...........................................................+125°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10sec) .............................+300°C Storage Temperature Range .............................-65°C to +150°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VEE = -5.2V, VRB = -2.00V, VRM = -1.00V, VRT = 0.00V, fCLK = 500MHz, duty cycle = 50%, typical thermal impedance (θJC) = 4°C/W, Tj = TC = TA = +25°C.) (Note 1) PARAMETER Resolution DC ACCURACY Integral Nonlinearity Differential Nonlinearity No Missing Codes ANALOG INPUT Input Voltage Range Input Bias Current Input Resistance Input Capacitance Input Bandwidth Offset Error VRT Offset Error VRB Input Slew Rate REFERENCE INPUT Ladder Resistance Reference Bandwidth TIMING CHARACTERISTICS Maximum Sample Rate Aperture Jitter Acquisition Time CLK to DATA READY Delay Clock to Data Delay I V V IV IV 0.9 1.25 500 2 250 1.4 1.75 1.9 2.25 0.9 1.25 500 2 250 1.4 1.75 1.9 2.25 MHz ps ps ns ns I V 60 80 30 60 80 30 Ω MHz Over full input range Small signal Large signal VIN = 0V I I V V V V IV IV V -30 -30 5 VRB 0.75 15 15 900 500 30 30 -30 -30 5 VRT 2.0 VRB 0.75 15 15 900 500 30 30 VRT 2.0 V mA kΩ pF MHz mV mV V/ns fCLK = 100kHz fCLK = 100kHz I I -1.0 -0.85 Guaranteed 1.0 0.95 -1.5 -0.95 Guaranteed 1.5 1.5 LSB LSB CONDITIONS TEST LEVEL MIN MAX1150A TYP MAX 8 MIN MAX1150B TYP MAX 8 UNITS Bits 2 _______________________________________________________________________________________ 8-Bit, 500Msps Flash ADC ELECTRICAL CHARACTERISTICS (continued) (VEE = -5.2V, VRB = -2.00V, VRM = -1.00V, VRT = 0.00V, fCLK = 500MHz, duty cycle = 50%, typical thermal impedance (θJC) = 4°C/W, Tj = TC = TA = +25°C.) (Note 1) PARAMETER DYNAMIC PERFORMANCE Signal-to-Noise Ratio (without harmonics) Total Harmonic Distortion Signal-to-Noise and Distortion Spurious-Free Dynamic Range DIGITAL INPUTS Input High Voltage (CLK, NCLK) Input Low Voltage (CLK, NCLK) Clock Pulse Width High (tPWH) Clock Pulse Width Low (tPWL) Clock Synchronous Input Currents DIGITAL OUTPUTS Logic "1" Voltage Logic "0" Voltage POWER-SUPPLY REQUIREMENTS Supply Voltage (VEE) Supply Current (IEE) Power Dissipation I I V IV I I -4.95 -1.1 -0.9 -1.8 2.4 -5.2 1.05 5.5 -5.45 1.2 6.25 -4.95 -1.5 -1.1 -0.9 -1.8 2.4 -5.2 1.05 5.5 -5.45 1.2 6.25 V A W -1.5 V V I I I I V 1.0 1.0 -1.1 -0.7 -1.8 0.67 0.67 2 -1.5 1.0 1.0 -1.1 -0.7 -1.8 0.67 0.67 2 -1.5 V V ns ns µA fIN = 50MHz fIN = 250MHz fIN = 50MHz fIN = 250MHz fIN = 50MHz fIN = 250MHz fIN = 50MHz fIN = 250MHz I I I I I I I I 47 44 -46 -38 43 37 49 41 45 42 -44 -36 41 35 44 36 dB dBc dB dB dB CONDITIONS TEST LEVEL MIN MAX1150A TYP MAX MIN MAX1150B TYP MAX UNITS MAX1150 Note 1: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device test actually performed during production and Quality Assurance inspection. Unless otherwise noted, all tests are pulsed tests; therefore, Tj = TC = TA. TEST LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25°C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25°C. Parameter is guaranteed over specified temperature range. _______________________________________________________________________________________ 3 8-Bit, 500Msps Flash ADC MAX1150 ______________________________________________________________Pin Description PIN 1, 2, 3 4, 5, 19, 20, 22, 23, 27, 28, 38, 39, 40, 46, 47, 49, 60, 67, 79 6 7, 9, 11, 54, 56, 58, 69, 71, 73, 75, 77 8 10 12 13, 14, 31, 34, 41, 63, 64 15–18, 25, 26, 29, 30, 36, 37, 44, 45, 51, 52 21 24 32, 33 35 42 43 48 50 53 55 57 59, 61, 62, 65, 66, 68 70 72 74 76 78 80 NAME D2B, D3B, D4B VEE D5B DGND D6B D7B D8B N.C. AGND VRBF VRBS VIN VRM VRTF VRTS NCLK CLK DRA NDRA D0A D1A–D6A D7A D8A NDRB DRB D0B D1B FUNCTION Data Output Bank, Bits 2, 3, and 4 Negative Supply, nominally -5.2V Data Output Bank B, Bit 5 Digital Ground Data Output Bank B, Bit 6 Data Output Bank B, Bit 7 (MSB) Data Output Bank B, Bit 8 (OVR) No Connection. Not internally connected. Analog Ground Reference-Voltage Force Bottom Reference-Voltage Sense Bottom Analog Input Voltage. Can be either voltage or sense. Reference-Voltage Middle, nominally -1V Reference-Voltage Force Top Reference-Voltage Sense Top Inverse Clock Input Clock Input Data Ready Bank A Not Data Ready Bank A Data Output Bank A, Bit 0 (LSB) Data Output Bank A, Bits 1–6 Data Output Bank A, Bit 7 (MSB) Data Output Bank A, Bit 8 (OVR) Not Data Ready Bank B Data Ready Bank B Data Output Bank B, Bit 0 (LSB) Data Output Bank B, Bit 1 _______________Detailed Description The MAX1150 is one of the fastest monolithic, 8-bit, parallel, flash analog-to-digital converters (ADCs) available today. The nominal conversion rate is 500Msps, and the analog bandwidth is in excess of 900MHz. A major advance over previous flash converters is the inclusion of 255 input preamplifiers between the reference ladder and input comparators (see Functional Diagram). This not only reduces clock transient kickback to the input and reference ladder, but also reduces the effect of the input signal’s dynamic state on the input comparators’ latching characteristics. The preamplifiers act as buffers to stabilize the input capacitance so that it remains constant over different input voltage and frequency ranges, making the part easier to drive than previous flash converters. The preamplifiers also add a gain of +2 to the input signal, so that each comparator has a wider overdrive or threshold range to trip into or out of the active state. This gain reduces metastable states that can cause errors at the output. 4 _______________________________________________________________________________________ 8-Bit, 500Msps Flash ADC The MAX1150 has true differential analog and digital data paths from the preamplifiers to the output buffers (current-mode logic) for reducing potential missing codes while rejecting common-mode noise. Signature errors are also reduced by careful layout of the analog circuitry. The device’s output drive capability can provide full ECL swings into 50Ω loads. Table 1. Output Coding VIN (V) 0 D8 1 D7 . . . D0 10000000 10000001 10000011 • • • 10100001 10100000 11100000 • • • 11000001 11000000 01000000 • • • 01100001 01100000 00100000 • • • 00000011 00000001 00000000 MAX1150 Typical Interface Circuit The circuit of Figure 1 shows a method of achieving the least error by correcting for integral linearity, inputinduced distortion, and power- supply/ground noise. This is achieved with the use of external reference-ladder tap connections, an input buffer, and supply decoupling. Contact the factory for the MAX1150/MAX1151 evaluation kit manual, which contains more details on interfacing the MAX1150. The function of each pin and external connections to other components are described in the following sections. -0.5 0 -1.0 0 -1.5 0 VEE, AGND, DGND VEE is the supply pin with AGND as ground for the device. The power-supply pins should be bypassed as close to the device as possible with at least a 0.01µF ceramic capacitor. A 1µF tantalum can also be used for low-frequency suppression. DGND is the ground for the ECL outputs, and should be referenced to the output pulldown voltage and appropriately bypassed, as shown in Figure 1. VIN (Analog Input) There are two analog input pins that are tied to the same point internally. Either one may be used as an analog input sense, while the other is used for input force. This is convenient for testing the source signal to see if there is sufficient drive capability. The pins can also be tied together and driven by the same source. The MAX1150 is superior to similar devices due to a preamplifier stage before the comparators. This makes the device easier to drive because it has constant capacitance and induces less slew-rate distortion. CLK, NCLK (Clock Inputs) The clock inputs are designed to be driven differentially with ECL levels. The duty cycle of the clock should be kept at 50%, to avoid causing larger second harmonics. If this is not important to the intended application, duty cycles other than 50% may be used. D0 to D8, DR, NDR (A and B) The digital outputs can drive 50Ω to ECL levels when pulled down to -2V. When pulled down to -5.2V, the outputs can drive 130Ω to 1kΩ loads. All digital outputs are gray code, with the coding as shown in Table 1. -2.0 0 VRBF, VRBS, VRTF, VRTS, VRM (Reference Inputs) There are two reference inputs and one external reference voltage tap. These are -2V (VRB force and sense), mid-tap (VRM), and AGND (VRT force and sense). The reference pins and tap can be driven by op amps (as shown in Figure 1), or VRM can be bypassed for limited temperature operation. These voltage inputs can be bypassed to AGND for further noise suppression, if desired. The typical thermal impedance has ( θ CA ) for the MQUAD package been measured at θCA = 17°C/W, in still air with no heatsink. To ensure rated performance, we highly recommend using this device with a heatsink that can provide adequate air flow. We have found that a Thermalloy 17846 heatsink with a minimum air flow of 1 meter/second (200 linear feet per minute) provides adequate thermal performance under laboratory tests. Application-specific conditions should be taken into account to ensure that the device is properly heat sinked. Thermal Management _______________________________________________________________________________________ 5 8-Bit, 500Msps Flash ADC MAX1150 VIN VIN NDRB (NOT DATA READY) DRB (DATA READY) D8B (OVR) VIN BANK B BANK A D7B (MSB) D6B D5B VRTF D4B D3B D2B VRTS 22Ω U1 ** VRM D1B D0B (LSB) 50Ω R MAX1150 NDRA (NOT DATA READY) DRA (DATA READY) D8A (OVR) D7A (MSB) D6A D5A R VRBS 22Ω U1 1N2907 VRBF ** -5.2V * CLK CLOCK IN U2 NCLK 50Ω 50Ω VEE -2V PULL-DOWN (ANALOG) AGND DGND 0.1µF * * * * * * * * * * * * * * * * * * * * * D4A D3A D2A D1A D0A (LSB) -2.0V REFERENCE -2.0V PULL-DOWN (DIGITAL) L = Ferrite bead, DIGIKEY P98208BK or equivalent L * = 50Ω resistor * * = 10µF tantalum capacitor and 0.1µF chip capacitor U1 = OP220 or equivalent with low offset/noise -5.2V R = 1kΩ; 0.1% matched = AGND = DGND U2 = Motorola ECLinPS Lite, MC10EL16, differential receiver with 250ps (typ) propagation delay ** Figure 1. Typical Interface Circuit 6 _______________________________________________________________________________________ 8-Bit, 500Msps Flash ADC Operation The MAX1150 has 255 preamplifier/comparator pairs; each is supplied with the voltage from VRT to VRB, divided equally by the resistive ladder as shown in the Functional Diagram. This voltage is applied to the positive input of each preamplifier/comparator pair. An analog input voltage applied at VIN is connected to the negative inputs of each preamplifier/comparator pair. The comparators are then clocked through each one’s individual clock buffer. When the CLK pin is in the low state, the master or input stage of the comparators compares the analog input voltage to the respective reference voltage. When CLK changes from low to high, the comparators are latched to the state prior to the clock transition and output logic codes in sequence from the top comparators, closest to VRT (0V), down to the point where the magnitude of the input signal changes sign (thermometer code). The output of each comparator is then registered into four 64-to-6 bit decoders when CLK is changed from high to low. At the output of the decoders is a set of four 7-bit latches that are enabled (track) when the clock changes from high to low. From here, the output of the latches is coded into six LSBs from four columns, and four columns are coded into two MSBs. Finally, eight ECL output latches and buffers are used to drive the external loads. The conversion takes one clock cycle from the input to the data outputs. N N+1 N+4 VIN 2.0ns CLK NCLK DRA NDRA 1.4ns TYP N+2 N+3 N+5 N+6 MAX1150 DATA BANK A N-2 1.75ns TYP N N+2 N+4 DRB NDRB 1.4ns TYP N-1 1.75ns TYP N+1 N+3 DATA BANK B Figure 2. Timing Diagram INPUT CIRCUIT AGND OUTPUT CIRCUIT CLOCK INPUT AGND AGND VIN VR DGND CLK NCLK DATA OUT VEE VEE Figure 3. Subcircuit Schematics _______________________________________________________________________________________ 7 8-Bit, 500Msps Flash ADC MAX1150 ____________________________________________________________Pin Configuration 77 DGND 75 DGND 73 DGND 71 DGND 69 DGND 76 DRB 74 NDRB 80 D1B 78 D0B 68 D6A 72 D8A 70 D7A 67 VEE 66 D5A 79 VEE 65 D4A 64 63 62 61 60 59 58 57 56 55 54 53 TOP VIEW D2B D3B D4B VEE VEE D5B DGND D6B DGND 1 2 3 4 5 6 7 8 9 N.C. N.C. D3A D2A VEE D1A DGND D0A DGND NDRA DGND DRA AGND AGND CLK VEE CLK VEE VEE AGND AGND VRTS VRTF N.C. D7B 10 DGND 11 D8B 12 N.C. 13 N.C. 14 AGND 15 AGND 16 AGND 17 AGND 18 VEE 19 VEE 20 VRBF 21 VEE 22 VEE 23 VRBS 24 VIN 32 AGND 36 AGND 30 AGND 29 AGND 25 VRM 35 N.C. 31 N.C. 34 VIN 33 VEE 38 VEE 39 AGND 26 VEE 27 VEE 28 AGND 37 VEE 40 MAX1150 52 51 50 49 48 47 46 45 44 43 42 41 MQUAD Maxim Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 ___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.