MAX1200BCMH

19-1413; Rev 0; 12/98 KIT ATION EVALU E AILABL AV +5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC General Description Features o Monolithic 16-Bit, 1Msps A/D Converter o Single +5V Supply o ±VREF Differential Input Voltage Range o 87dB SNR for fIN = 100kHz o 91dB SFDR for fIN = 100kHz o 273mW Low-Power Dissipation o ±0.5LSB Differential Nonlinearity Error o Three-State, Two’s Complement Output Data o On-Demand Self-Calibration o Pin-Compatible 14-Bit Versions Available (1Msps MAX1205, 2.2Msps MAX1201) MAX1200 The MAX1200 16-bit, monolithic, analog-to-digital converter (ADC) is capable of conversion rates up to 1Msps. This CMOS integrated circuit uses a fully differential, pipelined architecture with digital error correction and a short self-calibration to ensure 16-bit linearity at full sample rates. An on-chip track/hold (T/H) maintains superb dynamic performance up to the Nyquist frequency. The MAX1200 operates from a single +5V supply. The fully differential inputs allow an input swing of ±VREF. The reference is also differential with the positive reference (RFPF) typically connected to +4.096V and the negative reference (RFNF) connected to analog ground. Additional sensing pins (RFPS, RFNS) are provided to compensate for any resistive divider action that may occur. A single-ended input is also possible using two operational amplifiers. Power dissipation is typically only 273mW at +5V, at a sampling rate of 1Msps. The device employs a CMOScompatible, 16-bit parallel, two’s complement output data format. For a higher sampling speed (up to 2.2Msps) but lower resolution (14-bit), select the MAX1201, a pin-compatible version of the MAX1200. The MAX1200 is available in an MQFP package and operates over the commercial (0°C to +70°C) and extended-industrial (-40°C to +85°C) temperature ranges. Ordering Information PART MAX1200ACMH MAX1200BCMH MAX1200AEMH MAX1200BEMH TEMP. RANGE 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C PIN-PACKAGE 44 MQFP 44 MQFP 44 MQFP 44 MQFP DNL (LSB) ±0.5 — ±0.5 — Pin Configuration TOP VIEW TEST0 34 INP RFNS RFNF 40 39 38 High-Resolution Imaging Communications Scanners Data Acquisition Instrumentation ST_CAL AGND AVDD AGND AGND AVDD DOR D15 D14 D13 D12 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 37 36 35 RFPS RFPF CM INN N.C. N.C. Applications END_CAL 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 MAX1200 OE DAV CLK DVDD DGND DGND DVDD TEST1 D0 D1 D2 D11 D10 D9 D8 DRVDD DGND D7 D6 D5 D4 MQFP ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. D3 +5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC MAX1200 ABSOLUTE MAXIMUM RATINGS AVDD to AGND, DGND ..........................................................+7V DVDD to DGND, AGND..........................................................+7V DRVDD to DGND, AGND .......................................................+7V INP, INN, RFPF, RFPS, RFNF, RFNS, CLK, CM..........(AGND - 0.3V) to (AVDD + 0.3V) Digital Inputs to DGND ............................-0.3V to (DVDD + 0.3V) Digital Output (DAV) to DGND ..............-0.3V to (DRVDD + 0.3V) Other Digital Outputs to DGND .............-0.3V to (DRVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 44-Pin MQFP (derate 11.11mW/°C above +70°C).......889mW Operating Temperature Ranges (TA) MAX1200_CMH ..................................................0°C to +70°C MAX1200_EMH................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, VCM = +2.048V, VIN = -0.5dBFS, fCLK = 2.048MHz; digital output load ≤ 20pF; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER ANALOG INPUT Input Voltage Range (Note 2) Input Resistance (Note 3) Input Capacitance EXTERNAL REFERENCE Reference Voltage (Note 4) Reference Input Resistance TRANSFER CHARACTERISTICS Resolution (No missing codes; Note 5) Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Input-Referred Noise DYNAMIC SPECIFICATIONS (Note 6) Maximum Sampling Rate Conversion Time (Pipeline Delay/Latency) Acquisition Time Overvoltage Recovery Time Aperture Delay Aperture Jitter Full-Power Bandwidth Small-Signal Bandwidth 2 tACQ tOVR tAD tAJ To full-scale step (0.006%) fSAMPLE fSAMPLE = fCLK / 2 1.024 4 125 450 3 5 3.3 78 Msps fSAMPLE Cycles ns ns ns psRMS MHz MHz RES INL DNL MAX1200A MAX1200B -0.2 -5 -1 After calibration, guaranteed for MAX1200A only 16 ±3.5 ±0.5 ±0.6 ±0.003 -3 75 +0.2 5 +1 Bits LSB LSB %FSR %FSR µVRMS VREF RREF 700 4.096 1000 4.5 V Ω VIN RI CI Per side in track mode Single-ended Differential 4.096 ±4.096 55 21 V kΩ pF SYMBOL CONDITIONS MIN TYP MAX UNITS _______________________________________________________________________________________ +5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC ELECTRICAL CHARACTERISTICS (continued) (AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, VCM = +2.048V, VIN = -0.5dBFS, fCLK = 2.048MHz; digital output load ≤ 20pF; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS VRFPS = 4.096V, VRFNS = AGND Signal-to-Noise Ratio (Note 5) SNR VRFPS = 3.5V, VRFNS = 1.5V fIN = 99.5kHz fIN = 300.5kHz fIN = 504.5kHz fIN = 99.5kHz fIN = 300.5kHz fIN = 504.5kHz fIN = 99.5kHz fIN = 300.5kHz fIN = 504.5kHz fIN = 99.5kHz fIN = 300.5kHz fIN = 504.5kHz fIN = 99.5kHz fIN = 300.5kHz fIN = 504.5kHz fIN = 99.5kHz fIN = 300.5kHz fIN = 504.5kHz fIN = 99.5kHz fIN = 300.5kHz fIN = 504.5kHz fIN = 99.5kHz fIN = 300.5kHz fIN = 504.5kHz 4.75 3 0.4 3 10pF loads on D0–D15 and DAV 0.1 273 0.1 PSRR Offset Gain 55 55 77 80 85 84 78 MIN 83 TYP 87 84 83 83 81 80 91 89 88 92 91 90 -87 -86 -85 -90 -89 -88 84 82 81 82 80.5 79.5 5 51 5.25 70 5.25 1.2 DVDD 0.6 377 V mA V mA V mA mW sec dB dB -84 dB -82 dB dB MAX UNITS MAX1200 VRFPS = 4.096V, VRFNS = AGND Spurious-Free Dynamic Range (Note 5) SFDR VRFPS = 3.5V, VRFNS = 1.5V VRFPS = 4.096V, VRFNS = AGND Total Harmonic Distortion (Note 5) THD VRFPS = 3.5V, VRFNS = 1.5V VRFPS = 4.096V, VRFNS = AGND Signal-to-Noise Ratio plus Distortion (Note 5) SINAD VRFPS = 3.5V, VRFNS = 1.5V POWER REQUIREMENTS Analog Supply Voltage Analog Supply Current Digital Supply Voltage Digital Supply Current Output Drive Supply Voltage Output Drive Supply Current Power Dissipation Warm-Up Time Power-Supply Rejection Ratio AVDD I(AVDD) DVDD I(DVDD) DRVDD I(DRVDD) PDSS _______________________________________________________________________________________ 3 +5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC MAX1200 TIMING CHARACTERISTICS (Figures 7, 8, 9) (AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, fCLK = 2.048MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Conversion Time Clock Period Clock HIGH Time Clock LOW Time Acquisition Time Output Delay DAV Pulse Width CLK-to-DAV Rising Edge Data Access Time Bus Relinquish Time Calibration Time SYMBOL tCONV tCLK tCH tCL tACQ tOD tDAV tS tAC tREL tCAL ST_CAL = DVDD CL = 20pF 187 187 CONDITIONS MIN TYP 4 / fSAMPLE 488 244 244 tCLK / 2 70 1 / fCLK 65 16 16 17,400 145 75 75 150 301 301 MAX UNITS ns ns ns ns ns ns ns ns ns ns fCLK Cycles DIGITAL INPUT AND OUTPUT CHARACTERISTICS (AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Input LOW Voltage Input HIGH Voltage Input Capacitance CLK Input LOW Voltage CLK Input HIGH Voltage CLK Input Current CLK Input Capacitance Digital Input Current Output Low Voltage Output High Voltage Three-State Leakage Current Three-State Output Capacitance VCLK VCLK ICLK CCLK IIN VOL VOH ILEAKAGE COUT VIN = 0 or DVDD ISINK = 1.6mA ISOURCE = 200µA DVDD - 0.4 VIN = 0 or VDD AVDD - 0.8 ±1 9 ±0.1 70 DVDD - 0.03 ±0.1 3.5 ±10 ±10 400 ±10 SYMBOL VIL VIH DVDD - 0.8 4 0.8 CONDITIONS MIN TYP MAX 0.8 UNITS V V pF V V µA pF µA mV V µA pF Note 1: Reference inputs driven by operational amplifiers for Kelvin-sensed operation. Note 2: For unipolar mode, the analog input voltage, VINP, must be within 0 and VREF, VINN = VCM / 2; where VREF = VRFPS - VRFNS. For differential mode, the analog input voltages VINP and VINN must be within 0 and VREF; where VREF = VRFPS - VRFNS. The common-mode voltage of the inputs INP and INN is VCM = (VRFPS + VRFNS) / 2. Note 3: RI varies inversely with sample rate. Note 4: Minimum and maximum parameters are not tested. Guaranteed by design. Note 5: Calibration remains valid for temperature changes within ±20°C and power-supply variations ±5%. Guaranteed by design. Note 6: All AC specifications are shown for the differential mode. 4 _______________________________________________________________________________________ +5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC __________________________________________Typical Operating Characteristics (AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND; VCM = +2.048V, differential input, fCLK = 2.048MHz, calibrated, TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY vs. TWO’S COMPLEMENT OUTPUT CODE MAX1200 toc01 MAX1200 DIFFERENTIAL NONLINEARITY vs. TWO’S COMPLEMENT OUTPUT CODE MAX1200toc02 SINGLE-TONE SPURIOUS-FREE DYNAMIC RANGE vs. INPUT AMPLITUDE (fIN = 99.5kHz) (dBFS) 110 100 90 SFDR (dB) 80 70 (dBc) 60 50 40 30 MAX1200toc03 5 4 3 2 1.0 0.75 0.50 DNL (LSB) 0.25 0 -0.25 -0.50 -0.75 120 INL (LSB) 1 0 -1 -2 -3 -4 -5 -32768 -16384 0 16384 32768 -1.0 -32,768 -16,384 0 16,384 32,768 -80 -70 -60 -50 -40 -30 -20 -10 0 TWO’S COMPLEMENT OUTPUT CODE TWO’S COMPLEMENT OUTPUT CODE INPUT AMPLITUDE (dBFS) SIGNAL-TO-NOISE RATIO PLUS DISTORTION vs. INPUT FREQUENCY MAX1200 toc04 TOTAL HARMONIC DISTORTION vs. INPUT FREQUENCY -76 AIN = -20dBFS -78 THD (dB) SNR (dB) -80 -82 -84 -86 AIN = -6dBFS MAX1200 toc05 SIGNAL-TO-NOISE RATIO vs. INPUT FREQUENCY AIN = -0.5dBFS 85 AIN = -6dBFS vsMAX1200 toc06 86 84 82 80 SINAD (dB) 78 76 74 72 70 68 1 10 100 AIN = -20dBFS AIN = -6dBFS AIN = -0.5dBFS -74 90 80 75 70 AIN = -0.5dBFS 65 1 10 100 1000 1 10 100 1000 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) AIN = -20dBFS -88 -90 1000 INPUT FREQUENCY (kHz) SIGNAL-TO-NOISE RATIO PLUS DISTORTION vs. SAMPLING RATE (fIN = 99.5kHz) MAX1200 toc07 TYPICAL FFT, fIN = 99.5kHz, 8192 VALUE RECORD MAX1200 toc08 TYPICAL FFT, fIN = 504.5MHz, 8192 VALUE RECORD -15 -30 AMPLITUDE (dBFS) -45 -60 -75 -90 -105 -120 -135 -150 MAX1200 toc09 85 0 -15 -30 AMPLITUDE (dBFS) -45 -60 -75 -90 -105 -120 -135 0 84 SINAD (dB) 83 82 81 80 0.1 1 SAMPLE RATE (Msps) 10 -150 0 200 400 600 FREQUENCY (kHz) 0 200 400 600 FREQUENCY (kHz) _______________________________________________________________________________________ 5 +5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC MAX1200 Typical Operating Characteristics (AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +3.5V, VRFNS = +1.5V; VCM = +2.5V, differential input, fCLK = 2.048MHz, calibrated, TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY vs. TWO’S COMPLEMENT OUTPUT CODE MAX1200 toc11 DIFFERENTIAL NONLINEARITY vs. TWO’S COMPLEMENT OUTPUT CODE MAX1200 toc12 2.0 1.5 1.0 0.8 0.6 0.4 DNL (LSB) 100 90 80 SFDR (dB) 70 60 50 40 30 20 10 0 (dBFS) INL (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -32,768 -16,384 0 16,384 32,768 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -32,768 -16,384 0 16,384 32,768 (dB) -90 -80 -70 -60 -50 -40 -30 -20 -10 INPUT AMPLITUDE (dBFS) 0 TWO’S COMPLEMENT OUTPUT CODE TWO’S COMPLEMENT OUTPUT CODE SIGNAL-TO-NOISE RATIO PLUS DISTORTION vs. INPUT FREQUENCY MAX1200 toc14 TOTAL HARMONIC DISTORTION vs. INPUT FREQUENCY MAX1200 TOC15 SIGNAL-TO-NOISE RATIO vs. INPUT FREQUENCY MAX1200 toc16 84 82 80 78 SINAD (dB) 76 74 72 70 68 66 64 62 1 AIN = -20dBFS 10 100 AIN = -0.5dBFS -77 -79 -81 AIN = -20dBFS 85 AIN = -0.5dBFS 80 AIN = -6dBFS THD (dB) -83 -85 -87 -89 AIN = -6dBFS SNR (dB) 75 AIN = -6dBFS 70 65 -91 -93 1000 1 10 100 1000 INPUT FREQUENCY (kHz) AIN = -0.5dBFS 60 1 AIN = -20dBFS 10 100 1000 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) SIGNAL-TO-NOISE RATIO PLUS DISTORTION vs. SAMPLING RATE (fIN = 99.5kHz) MAX1200 toc17 TYPICAL FFT, fIN = 99.5kHz, 8192 VALUE RECORD MAX1200 toc18 TYPICAL FFT, fIN = 504.5MHz, 8192 VALUE RECORD -15 -30 AMPLITUDE (dBFS) -45 -60 -75 -90 -105 -120 -135 -150 MAX1200 toc19 84 83 82 SINAD (dB) 81 80 79 78 0.1 1 SAMPLE RATE (Msps) 0 -15 -30 AMPLITUDE (dBFS) -45 -60 -75 -90 -105 -120 -135 -150 0 10 0 200 400 600 0 200 400 600 FREQUENCY (kHz) FREQUENCY (kHz) 6 _______________________________________________________________________________________ MAX1200 toc13 2.5 1.0 SINGLE-TONE SPURIOUS-FREE DYNAMIC RANGE vs. INPUT AMPLITUDE (fIN = 99.5kHz) 110 +5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC Pin Description PIN 1 2, 4, 5 3, 6 7 8 9 10 11 12 13 14 15 16 17, 28, 29 18 19 20 21 22 23 24 25 26 27, 30 31 32 33 34 35 36 37 38 39 40 41, 42 43 44 NAME ST_CAL AGND AVDD DOR D15 D14 D13 D12 D11 D10 D9 D8 DRVDD DGND D7 D6 D5 D4 D3 D2 D1 D0 TEST1 DVDD CLK DAV OE TEST0 CM RFPF RFPS RFNF RFNS INP N.C. INN END_CAL Digital Input to Start Calibration. ST_CAL = 0: Normal conversion mode. ST_CAL = 1: Start self-calibration. Analog Ground Analog Power Supply, +5V ±5% Data Out-of-Range Bit Bit 15 (MSB) Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Digital Power Supply for the Output Drivers. +3V to +5.25V, DRVDD ≤ DVDD Digital Ground Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Test Pin 1. Do not connect. Digital Power Supply, +3V to +5.25V Input Clock. Receives power from AVDD to reduce jitter. Data Valid Clock. This clock can be used to transfer the data to a memory or any other data acquisition system. Output Enable. OE = 0: D0–D15 and DOR are high impedance. OE = 1: All bits are active. Test Pin 0. Do not connect. Common-Mode Voltage. Analog Input. Drive midway between positive and negative reference voltages. Positive Reference Voltage, Force Input Positive Reference Voltage, Sense Input Negative Reference Voltage, Force Input Negative Reference Voltage, Sense Input Positive Input Voltage Not Connected. No internal connection. Negative Input Voltage Digital Output for End of Calibration. END_CAL = 0: Calibration in progress. END_CAL = 1: Normal conversion mode. 7 FUNCTION MAX1200 _______________________________________________________________________________________ +5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC MAX1200 Detailed Description Converter Operation The MAX1200 is a 16-bit, monolithic analog-to-digital converter (ADC) capable of conversion rates up to 1Msps. It uses a multistage, fully differential, pipelined architecture with digital error correction and self-calibration to provide typically 91dB spurious-free dynamic range at a 1Msps sampling rate. It also provides excellent SNR and THD performance up to the Nyquist frequency. This makes the device suitable for applications such as data acquisition, high-resolution imaging, scanners, digital communication, and instrumentation. Figure 1 shows the simplified, internal structure of the ADC. A switched-capacitor, pipelined architecture is used to digitize the signal at a high throughput rate. The first four stages of the pipeline use a low-resolution quantizer to approximate the input signal. The multiplying digital-to-analog converter (MDAC) stage is used to subtract the quantized analog signal from the input. The residue is then amplified with a fixed gain and passed on to the next stage. The accuracy of the converter is improved by a digital calibration algorithm which corrects for mismatches between the capacitors in the switched-capacitor MDAC. Note that the pipeline introduces latency of four sampling periods between the input being sampled and the output appearing at D15–D0. While the device can handle both single-ended or differential inputs (see the Requirements for Reference and Analog Signal Inputs section), the latter mode of operation will guarantee best THD and SFDR performance. The differential input provides the following advantages compared to a single-ended operation: • Twice as much signal input span • Common-mode noise immunity • Virtual elimination of the even-order harmonics • Less stringent requirements on the input signal processing amplifiers Requirements for Reference and Analog Signal Inputs Fully differential switched-capacitor circuits (SC) are used for both the reference and analog inputs (Figure 2). This allows either single-ended or differential signals to be used in the reference and/or analog signal paths. The signal voltage on these pins (INP, INN, RFP_, RFN_) should never exceed the analog supply rail, AVDD, nor fall below ground. RFP_ RFN_ CM AVDD AGND STAGE1 INP INN S/H ADC MDAC 8X STAGE2 STAGE3 STAGE4 ADC CLK DVDD ST_CAL DGND OE DRVDD CLOCK GENERATOR DAV CORRECTION AND CALIBRATION LOGIC END_CAL MAX1200 OUTPUT DRIVERS DOR D15–D0 Figure 1. Internal Functional Diagram 8 _______________________________________________________________________________________ +5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC MAX1200 CM RFPF INP RFNF INN RFPS RFPF RFNF RFPF CM RFNS Figure 2. Simplified MDAC Architecture Figure 3. Equivalent Input at the Reference Pins. The sense pins should not draw any DC current. Choice of Reference It is important to choose a low-noise reference such as the MAX6341, which can provide both excellent load regulation and low temperature drift. The equivalent input circuit for the reference pins is shown in Figure 3. Note that the reference pins drive approximately 1kΩ of resistance on-chip. They also drive a switched capacitor of 21pF. To meet the dynamic performance, the reference voltage is required to settle to 0.0015% within one clock cycle. Carefully choose an appropriate driving circuit (Figure 4). The capacitors at the reference pins (RFPF, RFNF) provide the dynamic charge required during each clock cycle, while the op amps ensure accuracy of the reference signals. These capacitors must have low dielectric-absorption characteristics, such as polystyrene or teflon capacitors. The reference pins can be connected to either singleended or differential voltages within the specified maximum levels. Typically the positive reference pin (RFPF) would be driven to +4.096V, and the negative reference pin (RFNF) connected to analog ground for best SNR performance. If THD performance is more important to the application than signal-to-noise ratio, choose a lower level, differential voltage such as V RFPS = +3.5V and VRFNS = +1.5V. There are sense pins, RFPS and RFNS, which can be used with external amplifiers to compensate for any resistive drop on these lines, internal or external to the chip. Ensure a correct reference voltage by using proper Kelvin connections at the sense pins. VRFP = +4.096V 5k CHIP BOUNDARY RFPF MAX410 5k RFPS VRFN = 0 RFNF MAX410 RFNS CM MAX410 Figure 4. Drive Circuit for Reference Pins and Common-Mode Pin Common-Mode Voltage The switched-capacitor input circuit at the analog input allows signals between AGND and the analog power supply. Since the common-mode voltage has a strong influence on the performance of the ADC, the best results are obtained by choosing V CM = (V RFPS + VRFNS) / 2. This can be achieved by using a resistive divider between the two reference potentials. Figure 4 shows a typical driving circuit for good dynamic performance. 9 _______________________________________________________________________________________ +5V Single-Supply, 1Msps, 16-Bit Self-Calibrating ADC MAX1200 Analog Signal Conditioning For single-ended inputs, the negative analog input pin (INN) is connected to the common-mode voltage pin (CM) and the positive analog input pin (INP) is connected to the input. To take full advantage of the ADC’s superior AC performance up to the Nyquist frequency, drive the chip with differential signals. In communication systems the signals may inherently be available in differential mode; however medical and/or other applications may only provide single-ended inputs. In this case, convert the single-ended signals into differential ones by using the circuit recommended in Figure 5. Use low-noise, wideband amplifiers, such as the MAX4108, to maintain the signal purity over the full-power bandwidth of the MAX1200 input. Lowpass or bandpass signals may be required to improve the signal-to-noise and distortion of the incoming signal. For low-frequency signals (