MAX1309ECV

19-3052; Rev 5; 3/11 KIT ATION EVALU BLE AVAILA 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges General Description The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312– MAX1314 12-bit, analog-to-digital converters (ADCs) offer eight, four, or two independent input channels. Independent track-and-hold (T/H) circuitry provides simultaneous sampling for each channel. The MAX1304/ MAX1305/MAX1306 provide a 0 to +5V input range with ±6V fault-tolerant inputs. The MAX1308/MAX1309/ MAX1310 provide a ±5V input range with ±16.5V fault-tolerant inputs. The MAX1312/MAX1313/MAX1314 have a ±10V input range with ±16.5V fault-tolerant inputs. These ADCs convert two channels in 0.9µs, and up to eight channels in 1.98µs, with an 8-channel throughput of 456ksps per channel. Other features include a 20MHz T/H input bandwidth, internal clock, internal (+2.5V) or external (+2.0V to +3.0V) reference, and power-saving modes. A 20MHz, 12-bit, bidirectional parallel data bus provides the conversion results and accepts digital inputs that activate each channel individually. All devices operate from a +4.75V to +5.25V analog supply and a +2.7V to +5.25V digital supply and consume 57mA total supply current when fully operational. Each device is available in a 48-pin 7mm x 7mm LQFP package and operates over the extended -40°C to +85°C temperature range. Features o Up to Eight Channels of Simultaneous Sampling 8ns Aperture Delay 100ps Channel-to-Channel T/H Match o Extended Input Ranges 0 to +5V (MAX1304/MAX1305/MAX1306) -5V to +5V (MAX1308/MAX1309/MAX1310) -10V to +10V (MAX1312/MAX1313/MAX1314) o Fast Conversion Time One Channel in 0.72µs Two Channels in 0.9µs Four Channels in 1.26µs Eight Channels in 1.98µs o High Throughput 1075ksps/Channel for One Channel 901ksps/Channel for Two Channels 680ksps/Channel for Four Channels 456ksps/Channel for Eight Channels o ±1 LSB INL, ±0.9 LSB DNL (max) o 84dBc SFDR, -86dBc THD, 71dB SINAD, fIN = 500kHz at 0.4dBFS o 12-Bit, 20MHz, Parallel Interface o Internal or External Clock o +2.5V Internal Reference or +2.0V to +3.0V External Reference o +5V Analog Supply, +3V to +5V Digital Supply 55mA Analog Supply Current 1.3mA Digital Supply Current Shutdown and Power-Saving Modes o 48-Pin LQFP Package (7mm x 7mm Footprint) MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 Applications SIN/COS Position Encoder Multiphase Motor Control Multiphase Power Monitoring Power-Grid Synchronization Power-Factor Monitoring Vibration and Waveform Analysis Ordering Information PART MAX1304ECM+ MAX1304ECM/V+ MAX1305ECM+ MAX1306ECM+ MAX1308ECM+ MAX1308ECM/V+ MAX1309ECM+ MAX1309ECM/V+ MAX1310ECM+ MAX1312ECM+ MAX1313ECM+ TEMP RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C PIN-PACKAGE 48 LQFP 48 LQFP 48 LQFP 48 LQFP 48 LQFP 48 LQFP 48 LQFP 48 LQFP 48 LQFP 48 LQFP 48 LQFP Selector Guide PART MAX1304ECM MAX1305ECM MAX1306ECM MAX1308ECM MAX1309ECM MAX1310ECM MAX1312ECM MAX1313ECM MAX1314ECM INPUT RANGE (V) 0 to +5 0 to +5 0 to +5 ±5 ±5 ±5 ±10 ±10 ±10 CHANNEL COUNT 8 4 2 8 4 2 8 4 2 MAX1314ECM+ -40°C to +85°C 48 LQFP +Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part. Pin Configurations appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 ABSOLUTE MAXIMUM RATINGS AVDD to AGND.........................................................-0.3V to +6V DVDD to DGND ........................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V CH0–CH7, I.C. to AGND (MAX1304/MAX1305/MAX1306)....±6V CH0–CH7, I.C. to AGND (MAX1308/MAX1309/MAX1310)..±16.5V CH0–CH7, I.C. to AGND (MAX1312/MAX1313/MAX1314)..±16.5V D0–D11 to DGND ...................................-0.3V to (VDVDD + 0.3V) EOC, EOLC, RD, WR, CS to DGND .......-0.3V to (VDVDD + 0.3V) CONVST, CLK, SHDN, CHSHDN to DGND -0.3V to (VDVDD + 0.3V) INTCLK/EXTCLK to AGND .....................-0.3V to (VAVDD + 0.3V) REFMS, REF, MSV to AGND ...................-0.3V to (VAVDD + 0.3V) REF+, COM, REF- to AGND ...................-0.3V to (VAVDD + 0.3V) Maximum Current into Any Pin Except AVDD, DVDD, AGND, DGND ...........................................................................±50mA Continuous Power Dissipation (TA = +70°C) LQFP (derate 22.7mW/°C above +70°C) ................1818.2mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Figures 3 and 4.) PARAMETER STATIC PERFORMANCE (Note 1) Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset-Error Matching Offset-Error Temperature Drift Gain Error Gain-Error Matching Gain-Error Temperature Drift DYNAMIC PERFORMANCE at fIN = 500kHz, AIN = -0.4dBFS (Note 2) Signal-to-Noise Ratio Signal-to-Noise Plus Distortion Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Isolation ANALOG INPUTS (CH0 through CH7) MAX1304/MAX1305/MAX1306 Input Voltage VCH MAX1308/MAX1309/MAX1310 MAX1312/MAX1313/MAX1314 0 -5 -10 +5 +5 +10 V SNR SINAD THD SFDR 80 68 68 71 71 -86 84 86 -80 dB dB dBc dBc dB Between all channels N INL DNL (Note 2) No missing codes (Note 2) Unipolar, 0x000 to 0x001 Bipolar, 0xFFF to 0x000 Unipolar, between all channels Bipolar, between all channels Unipolar, 0x000 to 0x001 Bipolar, 0xFFF to 0x000 12 ±0.5 ±0.3 ±3 ±3 ±9 ±9 7 7 ±2 ±3 4 ±16 ±14 ±1.0 ±0.9 ±16 ±16 ±20 ±20 Bits LSB LSB LSB LSB ppm/°C LSB LSB ppm/°C SYMBOL CONDITIONS MIN TYP MAX UNITS 2 _______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Figures 3 and 4.) PARAMETER Input Resistance (Note 3) SYMBOL RCH CONDITIONS MAX1304/MAX1305/MAX1306 MAX1308/MAX1309MAX1310 MAX1312/MAX1313/MAX1314 MAX1304/MAX1305/MAX1306 Input Current (Note 3) ICH MAX1308/MAX1309/MAX1310 MAX1312/MAX1313/MAX1314 Input Capacitance TRACK/HOLD One channel selected for conversion External-Clock Throughput Rate (Note 4) fTH Two channels selected for conversion Four channels selected for conversion Eight channels selected for conversion One channel selected for conversion Internal-Clock Throughput Rate (Note 4, Table 1) Small-Signal Bandwidth Full-Power Bandwidth Aperture Delay Aperture-Delay Matching Aperture Jitter INTERNAL REFERENCE REF Output Voltage Reference Output-Voltage Temperature Drift REFMS Output Voltage REF+ Output Voltage COM Output Voltage REF- Output Voltage Differential Reference Voltage VREFMS VREF+ VCOM VREFVREF+ VREF2.475 VREF 2.475 2.500 30 2.500 3.850 2.600 1.350 2.500 2.525 2.525 V ppm/°C V V V V V tAJ tAD fTH Two channels selected for conversion Four channels selected for conversion Eight channels selected for conversion 1075 901 680 456 983 821 618 413 20 20 8 100 50 MHz MHz ns ps psRMS ksps ksps CCH VCH = +5V VCH = 0V VCH = +5V VCH = -5V VCH = +10V VCH = -10V -1.13 -1.16 -0.157 MIN TYP 7.58 8.66 14.26 0.54 -0.12 0.29 -0.87 0.56 -0.85 15 pF 0.74 0.39 mA 0.72 kΩ MAX UNITS MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 _______________________________________________________________________________________ 3 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Figures 3 and 4.) PARAMETER REF Input Voltage Range REF Input Resistance REF Input Capacitance REFMS Input Voltage Range REFMS Input Resistance REFMS Input Capacitance REF+ Output Voltage COM Output Voltage REF- Output Voltage Differential Reference Voltage VREF+ VCOM VREFVREF+ VREFVIH VIL CIN IIN VIH VIL VOH VOL ISOURCE = 0.8mA, Figure 1 ISINK = 1.6mA, Figure 1 RD = high or CS = high RD = high or CS = high 0.06 15 VDVDD - 0.6 0.4 1 VIN = 0V or VDVDD VREF = +2.5V VREF = +2.5V VREF = +2.5V VREF = +2.5V VREFMS RREFMS (Note 6) 2.0 SYMBOL VREF RREF (Note 5) CONDITIONS MIN 2.0 TYP 2.5 5 15 2.5 5 15 3.850 2.600 1.350 2.500 3.0 MAX 3.0 UNITS V kΩ pF V kΩ pF V V V V EXTERNAL REFERENCE (REF and REFMS are externally driven) DIGITAL INPUTS (D0–D7, RD, WR, CS, CLK, SHDN, CHSHDN, CONVST) Input-Voltage High Input-Voltage Low Input Hysteresis Input Capacitance Input Current Input-Voltage High Input-Voltage Low Output-Voltage High Output-Voltage Low D0–D11 Tri-State Leakage Current D0–D11 Tri-State Output Capacitance POWER SUPPLIES Analog Supply Voltage Digital Supply Voltage AVDD DVDD MAX1304/MAX1305/MAX1306, all channels selected Analog Supply Current IAVDD MAX1308/MAX1309/MAX1310, all channels selected MAX1312/MAX1313/MAX1314, all channels selected 4.75 2.70 55 54 54 5.25 5.25 60 60 60 mA V V 0.7 x VDVDD 0.3 x VDVDD 20 15 0.02 0.7 x VAVDD 0.3 x VAVDD ±1 V V mV pF µA V V V V µA pF CLOCK-SELECT INPUT (INTCLK/EXTCLK) DIGITAL OUTPUTS (D0–D11, EOC, EOLC) 4 _______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Figures 3 and 4.) PARAMETER SYMBOL CONDITIONS MAX1304/MAX1305/MAX1306, all channels selected Digital Supply Current (CLOAD = 100pF) (Note 7) IDVDD MAX1308/MAX1309/MAX1310, all channels selected MAX1312/MAX1313/MAX1314, all channels selected Shutdown Current (Note 8) Power-Supply Rejection Ratio TIMING CHARACTERISTICS (Figure 1) Internal clock, Figure 7 Time to First Conversion Result tCONV External clock, Figure 8 Internal clock, Figure 7 Time to Subsequent Conversions CONVST Pulse-Width Low (Acquisition Time) CS Pulse Width RD Pulse-Width Low RD Pulse-Width High WR Pulse-Width Low CS to WR WR to CS CS to RD RD to CS Data Access Time (RD Low to Valid Data) Bus Relinquish Time (RD High) CLK Rise to EOC Delay CLK Rise to EOLC Fall Delay CONVST Fall to EOLC Rise Delay EOC Pulse Width tNEXT External clock, Figure 8 (Note 9) Figures 6–10 Figure 6 Figures 7, 8, 9 Figures 7, 8, 9 Figure 6 Figure 6 Figure 6 Figures 7, 8, 9 Figures 7, 8, 9 Figures 7, 8, 9 Figures 7, 8, 9 Figure 8 Figure 8 Internal clock, Figure 7 tEOC External clock, Figure 8 50 1 5 20 20 20 0.1 30 30 30 30 (Note 10) (Note 10) (Note 10) (Note 10) 30 30 800 12 200 3 1000.0 225 900 ns CLK Cycles ns CLK Cycles µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLK Cycle IAVDD IDVDD PSRR SHDN = DVDD, VCH = open SHDN = DVDD, RD = WR = high VAVDD = +4.75V to +5.25V MIN TYP 1.3 1.3 1.3 0.6 0.02 50 MAX 2.6 2.6 2.6 10 1 µA dB mA UNITS MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 tACQ tCS tRDL tRDH tWRL tCTW tWTC tCTR tRTC tACC tREQ tEOCD tEOLCD tCVEOLCD Figures 7, 8, 9 _______________________________________________________________________________________ 5 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Figures 3 and 4.) PARAMETER Input-Data Setup Time Input-Data Hold Time External CLK Period External CLK High Period External CLK Low Period External Clock Frequency Internal Clock Frequency CONVST High to CLK Edge SYMBOL tDTW tWTD tCLK tCLKH tCLKL fCLK fINT tCNTC Figures 8, 9 20 Figure 6 Figure 6 Figures 8, 9 Logic sensitive to rising edges, Figures 8, 9 Logic sensitive to rising edges, Figures 8, 9 (Note 11) CONDITIONS MIN 10 10 0.05 20 20 0.1 15 20 10.00 TYP MAX UNITS ns ns µs ns ns MHz MHz ns Note 1: For the MAX1304/MAX1305/MAX1306, VIN = 0 to +5V. For the MAX1308/MAX1309/MAX1310, VIN = -5V to +5V. For the MAX1312/MAX1313/MAX1314, VIN = -10V to +10V. Note 2: All channel performance is guaranteed by correlation to a single channel test. Note 3: The analog input resistance is terminated to an internal bias point (Figure 5). Calculate the analog input current using: I CH _ = VCH _ − VBIAS R CH _ for VCH_ within the input voltage range. Note 4: Throughput rate is given per channel. Throughput rate is a function of clock frequency (fCLK). The external clock throughput rate is specified with fCLK = 16.67MHz and the internal clock throughput rate is specified with fCLK = 15MHz. See the Data Throughput section for more information. Note 5: The REF input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REF input current using: I REF = VREF − 2 . 5V R REF for VREF within the input voltage range. Note 6: The REFMS input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REFMS input current using: IREFMS = VREFMS − 2 . 5V R REFMS for VREFMS within the input voltage range. Note 7: All analog inputs are driven with a -0.4dBFS 500kHz sine wave. Note 8: Shutdown current is measured with the analog input unconnected. The large amplitude of the maximum shutdown current specification is due to automated test equipment limitations. Note 9: CONVST must remain low for at least the acquisition period. The maximum acquisition time is limited by internal capacitor droop. Note 10: CS to WR and CS to RD are internally AND together. Setup and hold times do not apply. Note 11: Minimum CLK frequency is limited only by the internal T/H droop rate. Limit the time between the rising edge of CONVST and the falling edge of EOLC to a maximum of 1ms. 6 _______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Typical Operating Characteristics (VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS. TA = +25°C, unless otherwise noted.) (Figures 3 and 4) INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE MAX1304 toc01 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 MAX1304 toc02 1.0 0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1.0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE OFFSET ERROR vs. ANALOG SUPPLY VOLTAGE 0.8 0.6 OFFSET ERROR (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 4.7 4.8 4.9 5.0 VAVDD (V) 5.1 5.2 5.3 -12 -16 -40 -15 MAX1304 toc03 OFFSET ERROR vs. TEMPERATURE 12 8 OFFSET ERROR (LSB) 4 0 -4 -8 MAX1304 toc04 1.0 16 10 35 60 85 TEMPERATURE (°C) GAIN ERROR vs. ANALOG SUPPLY VOLTAGE MAX1304 toc05 GAIN ERROR vs. TEMPERATURE 12 8 MAX1304 toc06 1 0 GAIN ERROR (LSB) -1 -2 -3 -4 -5 4.7 4.8 4.9 5.0 VAVDD (V) 5.1 5.2 16 GAIN ERROR (LSB) 4 0 -4 -8 -12 -16 -40 -15 10 35 TEMPERATURE (°C) 60 85 5.3 _______________________________________________________________________________________ 7 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 Typical Operating Characteristics (continued) (VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS. TA = +25°C, unless otherwise noted.) (Figures 3 and 4) SMALL-SIGNAL BANDWIDTH vs. ANALOG INPUT FREQUENCY MAX1304 toc07 LARGE-SIGNAL BANDWIDTH vs. ANALOG INPUT FREQUENCY AIN = -0.5dBFS 0 -2 GAIN (dB) -4 -6 -8 -10 -12 MAX1304 toc08 MAX1304 toc10 2 AIN = -20dBFS 0 -2 GAIN (dB) -4 -6 -8 -10 -12 0.1 1 10 2 100 0.1 1 10 100 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) FFT PLOT (2048-POINT DATA RECORD) MAX1304 toc09 OUTPUT HISTOGRAM (DC INPUT) 6000 5497 5000 4000 COUNTS 3000 2000 1000 0 0 1084 0 2045 2046 2047 2048 0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 0 fTH = 1.04167Msps fIN = 500kHz AIN = -0.05dBFS SNR = 70.7dB SINAD = 70.6dB THD = -87.5dBc SFDR = 87.1dBc 1611 100 200 300 400 500 2044 FREQUENCY (kHz) DIGITAL OUTPUT CODE 8 _______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Typical Operating Characteristics (continued) (VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS. TA = +25°C, unless otherwise noted.) (Figures 3 and 4) SIGNAL-TO-NOISE RATIO vs. CLOCK FREQUENCY MAX1304 toc11 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 SIGNAL-TO-NOISE PLUS DISTORTION vs. CLOCK FREQUENCY 78 76 74 SINAD (dB) 72 70 68 66 64 62 60 MAX1304 toc12 80 78 76 74 SNR (dB) 72 70 68 66 64 62 60 0 5 10 15 20 80 25 0 5 10 15 20 25 fCLK (MHz) fCLK (MHz) TOTAL HARMONIC DISTORTION vs. CLOCK FREQUENCY MAX1304 toc13 SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK FREQUENCY 95 90 SFDR (dBc) 85 80 75 70 65 60 0 5 10 15 20 25 MAX1304 toc14 -60 -65 -70 THD (dBc) -75 -80 -85 -90 -95 -100 0 5 10 15 20 100 25 fCLK (MHz) fCLK (MHz) _______________________________________________________________________________________ 9 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 Typical Operating Characteristics (continued) (VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS. TA = +25°C, unless otherwise noted.) (Figures 3 and 4) SIGNAL-TO-NOISE RATIO vs. REFERENCE VOLTAGE MAX1304 toc15 SIGNAL-TO-NOISE PLUS DISTORTION vs. REFERENCE VOLTAGE 74 73 72 SINAD (dB) 71 70 69 68 67 66 65 MAX1304 toc16 75 74 73 72 SNR (dB) 71 70 69 68 67 66 65 2.0 2.2 2.4 2.6 2.8 75 3.0 2.0 2.2 2.4 2.6 2.8 3.0 VREF (V) VREF (V) TOTAL HARMONIC DISTORTION vs. REFERENCE VOLTAGE MAX1304 toc17 SPURIOUS-FREE DYNAMIC RANGE vs. REFERENCE VOLTAGE MAX1304 toc18 -70 -72 -74 -76 100 95 90 SFDR (dBc) 85 80 75 70 THD (dBc) -78 -80 -82 -84 -86 -88 -90 2.0 2.2 2.4 2.6 2.8 3.0 VREF (V) 2.0 2.2 2.4 2.6 2.8 3.0 VREF (V) 10 ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Typical Operating Characteristics (continued) (VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS. TA = +25°C, unless otherwise noted.) (Figures 3 and 4) ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE MAX1304 toc19 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE CLOAD = 50pF TA = +85°C TA = +25°C TA = -40°C MAX1304 toc20 57 56 55 IAVDD (mA) 54 53 52 51 4.7 4.8 4.9 5.0 VAVDD (V) 5.1 5.2 TA = -40°C TA = +85°C 2.0 1.8 1.6 IDVDD (mA) TA = +25°C 1.4 1.2 1.0 0.8 0.6 5.3 2.5 3.0 3.5 4.0 VDVDD (V) 4.5 5.0 5.5 ANALOG SHUTDOWN CURRENT vs. ANALOG SUPPLY VOLTAGE 680 660 640 IDVDD (nA) IAVDD (nA) 620 600 580 560 540 520 500 4.7 4.8 4.9 5.0 VAVDD (V) 5.1 5.2 5.3 10 2.5 MAX1304 toc21 DIGITAL SHUTDOWN CURRENT vs. DIGITAL SUPPLY VOLTAGE MAX1304 toc22 700 22 20 18 16 14 12 3.0 3.5 4.0 VDVDD (V) 4.5 5.0 5.5 ANALOG SUPPLY CURRENT vs. NUMBER OF CHANNELS SELECTED MAX1304 toc23 DIGITAL SUPPLY CURRENT vs. NUMBER OF CHANNELS SELECTED CHSHDN = 0 0.9 0.8 0.7 IDVDD (mA) 0.6 0.5 0.4 0.3 MAX1304 toc24 60 CHSHDN = 0 55 50 IAVDD (mA) 45 40 35 30 0 1 2 3 4 5 6 7 8 NUMBER OF CHANNELS SELECTED 1.0 0.2 0.1 0 1 2 3 4 5 6 7 8 NUMBER OF CHANNELS SELECTED ______________________________________________________________________________________ 11 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 Typical Operating Characteristics (continued) (VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ = CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS. TA = +25°C, unless otherwise noted.) (Figures 3 and 4) INTERNAL REFERENCE VOLTAGE INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE vs. ANALOG SUPPLY VOLTAGE MAX1304 toc25 2.5003 2.5002 VREF (V) 2.503 2.502 VREF (V) 2.501 2.500 2.499 2.498 2.497 2.496 -40 -15 10 35 60 2.5001 2.5000 2.4999 2.4998 2.4997 2.4996 4.7 4.8 4.9 5.0 VAVDD (V) 5.1 5.2 5.3 85 TEMPERATURE (°C) INTERNAL CLOCK CONVERSION TIME vs. ANALOG SUPPLY VOLTAGE MAX1304 toc27 INTERNAL CLOCK CONVERSION TIME vs. TEMPERATURE MAX1304 toc28 900 800 700 600 TIME (ns) 500 400 300 200 100 0 4.7 4.8 4.9 5.0 VAVDD (V) 5.1 5.2 tNEXT tCONV 820 800 tCONV 780 TIME (ns) tNEXT 200 180 160 5.3 -40 -15 10 35 60 85 TEMPERATURE (°C) ANALOG INPUT CHANNEL CURRENT vs. ANALOG INPUT CHANNEL VOLTAGE MAX1304 toc29 ANALOG INPUT CHANNEL CURRENT vs. ANALOG INPUT CHANNEL VOLTAGE 2.5 2.0 1.5 1.0 ICH_ (mA) 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 ICH_ (mA) MAX1308/MAX1309/MAX1310 MAX1304 toc30 ANALOG INPUT CHANNEL CURRENT vs. ANALOG INPUT CHANNEL VOLTAGE 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -20 -15 -10 -5 0 VCH_ (V) 5 10 15 20 MAX1312/MAX1313/MAX1314 MAX1304 toc31 2.0 MAX1304/MAX1305/MAX1306 1.5 1.0 ICH_ (mA) 0.5 0 -0.5 -1.0 -1.5 -2.0 -6 -4 -2 0 VCH_ (V) 2 4 6 3.0 2.0 -20 -15 -10 -5 0 VCH_ (V) 5 10 15 20 12 ______________________________________________________________________________________ MAX1304 toc26 2.5004 2.504 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Pin Description PIN MAX1304 MAX1308 MAX1312 1, 15, 17 2, 3, 14, 16, 23 4 5 MAX1305 MAX1309 MAX1313 1, 15, 17 2, 3, 14, 16, 23 4 5 MAX1306 MAX1310 MAX1314 1, 15, 17 2, 3, 14, 16, 23 4 5 NAME FUNCTION MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 AVDD Analog Power Input. AVDD is the power input for the analog section of the converter. Apply +5V to AVDD. Connect all AVDD pins together. See the Layout, Grounding, and Bypassing section for additional information. Analog Ground. AGND is the power return for AVDD. Connect all AGND pins together. Channel 0 Analog Input Channel 1 Analog Input Midscale Voltage Bypass. For the unipolar MAX1304/MAX1305/MAX1306, connect a 2.2µF and a 0.1µF capacitor from MSV to AGND. For the bipolar MAX1308/MAX1309/MAX1310/MAX1312/MAX1313/MAX1314, connect MSV to AGND. Channel 2 Analog Input Channel 3 Analog Input Channel 4 Analog Input Channel 5 Analog Input Channel 6 Analog Input Channel 7 Analog Input AGND CH0 CH1 6 6 6 MSV 7 8 9 10 11 12 13 7 8 — — — — 13 — — — — — — 13 CH2 CH3 CH4 CH5 CH6 CH7 Clock-Mode Select Input. Connect INTCLK/EXTCLK to AVDD to select the INTCLK/ internal clock. Connect INTCLK/EXTCLK to AGND to use an external clock EXTCLK connected to CLK. Midscale Reference Bypass or Input. REFMS connects through a 5k_ resistor to the internal +2.5V bandgap reference buffer. For the MAX1304/MAX1305/MAX1306 unipolar devices, VREFMS is the input to the unity-gain buffer that drives MSV. MSV sets the midpoint of the input voltage range. For internal reference operation, bypass REFMS with a ≥ 0.01µF capacitor to AGND. For external reference operation, drive REFMS with an external voltage from +2V to +3V. For the MAX1308/MAX1309/MAX1310/MAX1312/MAX1313/MAX1314 bipolar devices, connect REFMS to REF. For internal reference operation, bypass the REFMS/REF node with a ≥ 0.01µF capacitor to AGND. For external reference operation, drive the REFMS/REF node with an external voltage from +2V to +3V. ADC Reference Bypass or Input. REF connects through a 5k_ resistor to the internal +2.5V bandgap reference buffer. For internal reference operation, bypass REF with a ≥ 0.01µF capacitor. For external reference operation with the MAX1304/MAX1305/MAX1306 unipolar devices, drive REF with an external voltage from +2V to +3V. For external reference operation with the MAX1308/MAX1309/MAX1310/ MAX1312/MAX1313/MAX1314 bipolar devices, connect REFMS to REF and drive the REFMS/REF node with an external voltage from +2V to +3V. 18 18 18 REFMS 19 19 19 REF ______________________________________________________________________________________ 13 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 Pin Description (continued) PIN MAX1304 MAX1308 MAX1312 MAX1305 MAX1309 MAX1313 MAX1306 MAX1310 MAX1314 NAME FUNCTION 20 20 20 REF+ Positive Reference Bypass. Bypass REF+ with a 0.1µF capacitor to AGND. Also bypass REF+ to REF- with a 2.2µF and a 0.1µF capacitor. VREF+ = VCOM + VREF/2. Reference Common Bypass. Bypass COM to AGND with a 2.2µF and a 0.1µF capacitor. VCOM = 13/25 x AVDD. Negative Reference Bypass. Bypass REF- with a 0.1µF capacitor to AGND. Also bypass REF- to REF+ with a 2.2µF and a 0.1µF capacitor. VREF- = VCOM - VREF/2. Digital Ground. DGND is the power return for DVDD. Connect all DGND pins together. Digital Power Input. DVDD powers the digital section of the converter, including the parallel interface. Apply +2.7V to +5.25V to DVDD. Bypass DVDD to DGND with a 0.1µF capacitor. Connect all DVDD pins together. Digital I/O 0 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. Digital I/O 1 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. Digital I/O 2 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. Digital I/O 3 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. Digital I/O 4 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. Digital I/O 5 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. Digital I/O 6 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. Digital I/O 7 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. Digital Output 8 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. Digital Output 9 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. Digital Output 10 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. Digital Output 11 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1. End-of-Conversion Output. EOC goes low to indicate the end of a conversion. It returns high on the next rising CLK edge or the falling CONVST edge. End-of-Last-Conversion Output. EOLC goes low to indicate the end of the last conversion. It returns high when CONVST goes low for the next conversion sequence. Read Input. Pulling RD low initiates a read command of the parallel data bus. Write Input. Pulling WR low initiates a write command for configuring the device with D0–D7. 21 21 21 COM 22 22 22 REF- 24, 39 24, 39 24, 39 DGND 25, 38 26 27 28 29 30 31 32 33 34 35 36 37 40 25, 38 26 27 28 29 30 31 32 33 34 35 36 37 40 25, 38 26 27 28 29 30 31 32 33 34 35 36 37 40 DVDD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 EOC 41 42 43 41 42 43 41 42 43 EOLC RD WR 14 ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Pin Description (continued) PIN MAX1304 MAX1308 MAX1312 44 45 MAX1305 MAX1309 MAX1313 44 45 MAX1306 MAX1310 MAX1314 44 45 NAME FUNCTION MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 CS CONVST Chip-Select Input. Pulling CS low activates the digital interface. Forcing CS high places D0–D11 in high-impedance mode. Conversion Start Input. Driving CONVST high initiates the conversion process. The analog inputs are sampled on the rising edge of CONVST. External Clock Input. For external clock operation, connect INTCLK/EXTCLK to AGND and drive CLK with an external clock signal from 100kHz to 20MHz. For internal clock operation, connect INTCLK/EXTCLK to AVDD and connect CLK to DGND. Shutdown Input. Driving SHDN high initiates device shutdown. Connect SHDN to DGND for normal operation. 46 46 46 CLK 47 47 47 SHDN 48 48 48 Active-Low Analog-Input Channel-Shutdown Input. Drive CHSHDN low to power down analog inputs that are not selected for conversion in the configuration register. Drive CHSHDN high to power up all analog input CHSHDN channels regardless of whether they are selected for conversion in the configuration register. See the Channel Shutdown (CHSHDN) section for more information. I.C. Internally connected. Connect I.C. to AGND. — 9, 10, 11, 12 7, 8, 9, 10, 11, 12 Detailed Description VDD IOL = 1.6mA DEVICE PIN 1.6V 100pF IOH = 0.8mA The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312– MAX1314 are 12-bit ADCs. The devices offer 8, 4, or 2 independently selectable input channels, each with dedicated T/H circuitry. Simultaneous sampling of all active channels preserves relative phase information making these devices ideal for motor control and power monitoring. Three input ranges are available, 0 to +5V, ±5V and ±10V. The 0 to +5V devices provide ±6V faulttolerant inputs. The ±5V and ±10V devices provide ±16.5V fault-tolerant inputs. Two-channel conversion results are available in 0.9µs. Conversion results from all eight channels are available in 1.98µs. The 8-channel throughput is 456ksps per channel. Internal or external reference and clock capability offer great flexibility, and ease of use. A write-only configuration register can mask out unused channels and a shutdown feature reduces power. A 20MHz, 12-bit, parallel data bus outputs the conversion results. Figure 2 shows the functional diagram of these ADCs. Figure 1. Digital Load Test Circuit ______________________________________________________________________________________ 15 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 AVDD CH0 T/H 8x1 MUX CH7 T/H MAX1304–MAX1306 MAX1308–MAX1310 MAX1312–MAX1314 DVDD D11 D8 12-BIT ADC 8 x 12 SRAM OUTPUT DRIVERS D7 D0 MSV * REF+ COM REFCONFIGURATION REGISTER INTERFACE AND CONTROL 5kΩ REF 5kΩ REFMS 2.500V AGND WR CS RD CONVST SHDN INTCLK/EXTCLK CLK CHSHDN EOC EOLC DGND *SWITCH CLOSED ON UNIPOLAR DEVICES, OPEN ON BIPOLAR DEVICES Figure 2. Functional Diagram 16 ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 25, 38 0.1µF DGND 24, 39 GND +5V 0.1µF 0.1µF 0.1µF 1 AVDD DVDD +2.7V TO +5.25V 15 AVDD 17 AVDD CHSHDN SHDN CLK REFMS REF 48 47 46 45 44 43 42 41 40 DIGITAL INTERFACE AND CONTROL 6 BIPOLAR CONFIGURATION 0.01µF 18 19 0.1µF 2.2µF 0.1µF MSV MAX1308 MAX1312 CONVST CS WR 20 0.1µF 22 REF+ RD EOLC REF2.2µF EOC D11 0.1µF 21 COM 2, 3, 14, 16, 23 AGND 12 11 10 BIPOLAR ANALOG INPUTS 9 CH7 CH6 CH5 CH4 D10 D9 D8 D7 D6 D5 37 36 35 34 33 32 31 PARALLEL DIGITAL OUTPUT GND 8 CH3 7 CH2 5 CH1 4 CH0 13 INTCLK/EXTCLK D4 30 D3 D2 29 28 D1 27 D0 26 Figure 3. Typical Bipolar Operating Circuit ______________________________________________________________________________________ 17 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 +5V 0.1µF 0.1µF 0.1µF 2.2µF 0.1µF 0.01µF 0.01µF 1 15 17 AVDD AVDD AVDD DVDD 25, 38 0.1µF +2.7V TO +5.25V DGND 24, 39 GND 6 CHSHDN MSV SHDN CLK 48 47 46 45 44 43 42 41 40 DIGITAL INTERFACE AND CONTROL UNIPOLAR CONFIGURATION 18 19 REFMS CONVST MAX1304 REF CS WR 0.1µF 2.2µF 0.1µF 2.2µF 0.1µF GND 20 0.1µF 22 RD REF+ EOLC EOC REFD11 37 36 35 34 33 32 31 PARALLEL DIGITAL OUTPUT 21 COM 2, 3, 14, 16, 23 AGND 12 11 10 CH7 CH6 CH5 D10 D9 D8 D7 D6 D5 UNIPOLAR ANALOG INPUTS 9 CH4 8 CH3 7 CH2 5 CH1 4 CH0 13 INTCLK/EXTCLK D4 30 D3 D2 29 28 D1 27 D0 26 Figure 4. Typical Unipolar Operating Circuit 18 ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges acquisition time must be limited to 1ms. Accuracy with conversion times longer than 1ms cannot be guaranteed due to capacitor droop in the input circuitry. Due to the analog input resistive divider formed by R1 and R2 in Figure 5, any significant analog input source resistance (R SOURCE) results in gain error. Furthermore, R SOURCE causes distortion due to nonlinear analog input currents. Limit RSOURCE to a maximum of 100Ω. MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 AVDD MAX1304–MAX1306 MAX1308–MAX1310 MAX1312–MAX1314 OVERVOLTAGE PROTECTION CLAMP 2.5pF CSAMPLE R2 CHOLD *RSOURCE CH_ R1 Selecting an Input Buffer ANALOG SIGNAL SOURCE UNDERVOLTAGE PROTECTION CLAMP VBIAS *MINIMIZE RSOURCE TO AVOID GAIN ERROR AND DISTORTION. PART MAX1304 MAX1305 MAX1306 MAX1308 MAX1309 MAX1310 MAX1312 MAX1313 MAX1314 INPUT RANGE (V) R1 (kΩ) R2 (kΩ) VBIAS (V) 0 TO +5 3.33 5.00 0.90 ±5 6.67 2.86 2.50 ±10 13.33 2.35 2.06 R1 | | R2 = 2kΩ Figure 5. Single-Channel, Equivalent Analog Input T/H Circuit Analog Inputs Track and Hold (T/H) To preserve phase information across the multichannel MAX1304–MAX1306/MAX1308–MAX1310/MAX1312– MAX1314, all input channels have dedicated T/H amplifiers. Figure 5 shows the equivalent analog input T/H circuit for one channel. The input T/H circuit is controlled by the CONVST input. When CONVST is low, the T/H circuit tracks the analog input. When CONVST is high the T/H circuit holds the analog input. The rising edge of CONVST is the analog input sampling instant. There is an aperture delay (tAD) of 8ns and a 50psRMS aperture jitter (tAJ). The aperture delay of each dedicated T/H input is matched within 100ps of each other. To settle the charge on CSAMPLE to 12-bit accuracy, use a minimum acquisition time (t ACQ ) of 100ns. Therefore, CONVST must be low for at least 100ns. Although longer acquisition times allow the analog input to settle to its final value more accurately, the maximum To improve the input signal bandwidth under AC conditions, drive the input with a wideband buffer (>50MHz) that can drive the ADC’s input capacitance (15pF) and settle quickly. For example, the MAX4431 or the MAX4265 can be used for the 0 to +5V unipolar devices, or the MAX4350 can be used for ±5V bipolar inputs. Most applications require an input buffer to achieve 12-bit accuracy. Although slew rate and bandwidth are important, the most critical input buffer specification is settling time. The simultaneous sampling of multiple channels requires an acquisition time of 100ns. At the beginning of the acquisition, the ADC internal sampling capacitor array connects to the analog inputs, causing some disturbance. Ensure the amplifier is capable of settling to at least 12-bit accuracy during this interval. Use a low-noise, low-distortion, wideband amplifier that settles quickly and is stable with the ADC’s 15pF input capacitance. See the Maxim website at w ww.maxim-ic.com for application notes on how to choose the optimum buffer amplifier for your ADC application. Input Bandwidth The input-tracking circuitry has a 20MHz small-signal bandwidth, making it possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. Input Range and Protection The MAX1304/MAX1305/MAX1306 provide a 0 to +5V input voltage range with fault protection of ±6V. The MAX1308/MAX1309/MAX1310 provide a ±5V input voltage range with fault protection of ±16.5V. The MAX1312/MAX1313/MAX1314 provide a ±10V input voltage range with fault protection of ±16.5V. Figure 5 shows the single-channel equivalent input circuit. ______________________________________________________________________________________ 19 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 Data Throughput The data throughput (fTH) of the MAX1304–MAX1306/ MAX1308–MAX1310/MAX1312–MAX1314 is a function of the clock speed (fCLK). In internal clock mode, fCLK = 15MHz (typ). In external clock mode, 100kHz ≤ fCLK ≤ 20MHz. When reading during conversion (Figures 7 and 8), calculate fTH as follows: 1 fTH = 12 + 3 x ( N − 1) + 1 tACQ + tQUIET + fCLK where N is the number of active channels and tQUIET is the period of bus inactivity before the rising edge of CONVST. See the Starting a Conversion section for more information. Table 1 uses the above equation and shows the total throughput as a function of the number of channels selected for conversion. Clock Modes The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312– MAX1314 provide a 15MHz internal conversion clock. Alternatively, an external clock can be used. Internal Clock Internal clock mode frees the microprocessor from the burden of running the ADC conversion clock. For internal clock operation, connect INTCLK/EXTCLK to AVDD and connect CLK to DGND. Note that INTCLK/EXTCLK is referenced to AVDD, not DVDD. External Clock For external clock operation, connect INTCLK/EXTCLK to AGND and connect an external clock source to CLK. Note that INTCLK/EXTCLK is referenced to AVDD, not DVDD. The external clock frequency can be up to 20MHz. Linearity is not guaranteed with clock frequencies below 100kHz due to droop in the T/H circuits. Table 1. Throughput vs. Channels Sampled: fCLK = 15MHz, tACQ = 100ns, tQUIET = 50ns CHANNELS SAMPLED (N) 1 2 3 4 5 6 7 8 CLOCK CYCLES UNTIL LAST RESULT 12 15 18 21 24 27 30 33 CLOCK CYCLE FOR READING LAST CONVERSION 1 1 1 1 1 1 1 1 TOTAL CONVERSION TIME (ns) 800 1000 1200 1400 1600 1800 2000 2200 TOTAL THROUGHPUT (ksps) 983 1643 2117 2474 2752 2975 3157 3310 THROUGHPUT PER CHANNEL (fTH) 983 821 705 618 550 495 451 413 20 ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Applications Information Digital Interface The bidirectional parallel digital interface allows for setting the 8-bit configuration register (see the Configuration Register section) and reading the 12-bit conversion result. The interface includes the following control signals: chip select (CS), read (RD), write (WR), end of conversion (EOC), end of last conversion (EOLC), conversion start (CONVST), shutdown (SHDN), channel shutdown (CHSHDN), internal clock select (INTCLK/EXTCLK), and external clock input (CLK). Figures 6, 7, 8, 9, Table 2, and the Timing Characteristics show the operation of the interface. D0–D7 are bidirectional, and D8–D11 are output only. D0–D11 go high impedance when RD = 1 or CS = 1. However, the new configuration does not take effect until the next CONVST falling edge. At power-up all channels default active. Shutdown does not change the configuration register. The configuration register may be written to in shutdown. See the Channel Shutdown (CHSHDN) section for information about using the configuration register for power saving. MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 CONVST CONFIGURATION REGISTER UPDATES RD tCS Configuration Register Enable channels as active by writing to the configuration register through I/O lines D0–D7 (Table 2). The bits in the configuration register map directly to the channels, with D0 controlling channel zero, and D7 controlling channel seven. Setting any bit high activates the corresponding input channel, while resetting any bit low deactivates the corresponding channel. On the devices with less than eight channels, some of the bits have no function (Table 2). To write to the configuration register, pull CS and WR low, load bits D0 through D7 onto the parallel bus, and force WR high. The data are latched on the rising edge of WR (Figure 6). Write to the configuration register at any point during the conversion sequence. At powerup, write to the configuration register to select the active channels before beginning a conversion. CS tCTW WR tDTW D0–D7 tWRL tWTC DATA-IN tWTD Figure 6. Write Timing Table 2. Configuration Register PART NUMBER MAX1304 MAX1308 MAX1312 MAX1305 MAX1309 MAX1313 MAX1306 MAX1310 MAX1314 STATE ON OFF ON OFF ON OFF BIT/CHANNEL D0/CH0 1 0 1 0 1 0 D1/CH1 1 0 1 0 1 0 D2/CH2 1 0 1 0 X X D3/CH3 1 0 1 0 X X D4/CH4 1 0 X X X X D5/CH5 1 0 X X X X D6/CH6 1 0 X X X X D7/CH7 1 0 X X X X X = Don’t care (must be 1 or 0). ______________________________________________________________________________________ 21 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 SAMPLE INSTANT tACQ CONVST TRACK tCONV HOLD tNEXT TRACK EOC tEOC EOLC tQUIET ≥ 50ns CS* tCTR RD tACC D0–D11 tREQ *CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD. CH0 tRDL CH1 tRDH tRTC tCVEOLCD Figure 7. Read During Conversion—Channel 0 and Channel 1 Selected, Internal Clock Starting a Conversion To start a conversion using internal clock mode, pull CONVST low for the acquisition time (tACQ). The T/H acquires the signal while CONVST is low, and conversion begins on the rising edge of CONVST. The end-ofconversion signal ( EOC ) pulses low whenever a conversion result becomes available for read. The endof-last-conversion signal (EOLC) goes low when the last conversion result is available (Figure 7). To start a conversion using external clock mode, pull CONVST low for the acquisition time (tACQ). The T/H acquires the signal while CONVST is low. The rising edge of CONVST is the sampling instant. Apply an external clock to CLK to start the conversion. To avoid T/H droop degrading the sampled analog input signals, 22 the first CLK pulse must occur within 10µs from the rising edge of CONVST. Additionally, the external clock frequency must be greater than 100kHz to avoid T/H droop-degrading accuracy. The first conversion result is available for read when EOC goes low on the rising edge of the 13th clock cycle. Subsequent conversion results are available after every third clock cycle thereafter (Figures 8 and 9). In both internal and external clock modes, hold CONVST high until the last conversion result is read. If CONVST goes low in the middle of a conversion, the current conversion is aborted and a new conversion is initiated. Furthermore, there must be a period of bus inactivity (tQUIET) for 50ns or longer before the falling edge of CONVST for the specified ADC performance. ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 SAMPLE INSTANT tACQ CONVST TRACK tCNTC CLK 1 2 3 tCLK 12 tEOCD EOC tCONV EOLC tQUIET ≥ 50ns CS* tRTC tEOC tEOLCD tCVEOLCD 13 14 tNEXT HOLD tCLKH 15 16 tCLKL 17 tEOCD 18 19 1 TRACK tCTR RD tACC D0–D11 tREQ *CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD. CH3 tRDH tRDL CH7 Figure 8. Read During Conversion—Channel 3 and Channel 7 Selected, External Clock Reading a Conversion Result Reading During a Conversion Figures 7 and 8 show the interface signals to initiate a read operation during a conversion cycle. These figures show two channels selected for conversion. If more channels are selected, the results are available successively at every EOC falling edge. CS can be low at all times, low during the RD cycles, or the same as RD. After initiating a conversion by bringing CONVST high, wait for EOC to go low. In internal clock mode, EOC goes low within 900ns. In external clock mode, EOC goes low on the rising edge of the 13th CLK cycle. To read the conversion result, drive CS and RD low to latch data to the parallel digital output bus. Bring RD high to release the digital bus. In internal clock mode, the next EOC falling edge occurs within 225ns. In external clock mode, the next EOC falling edge occurs in three CLK cycles. When the last result is available EOLC goes low. Reading After Conversion Figure 9 shows the interface signals for a read operation after a conversion with all eight channels enabled. At the falling of EOLC, driving CS and RD low places the first conversion result onto the parallel bus. Successive low pulses of R D place the successive conversion results onto the bus. When the last conversion results in the sequence are read, additional read pulses wrap the pointer back to the first converted result. ______________________________________________________________________________________ 23 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 CONVST EOC ONLY LAST PULSE SHOWN tEOC tCVEOLCD EOLC CS* tRTC tCTR tRDL tRDH tQUIET = 50ns RD D0–D11 tACC CH0 tREQ CH1 CH2 CH3 CH4 CH5 CH6 CH7 * CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD. Figure 9. Read After Conversion—Eight Channels Selected, External Clock Power-Up Reset At power-up, all channels are selected for conversion (see the Configuration Register section). After applying power, allow the 1ms wake-up time to elapse and then initiate a dummy conversion and discard the results. After the dummy conversion is complete, accurate conversions can be obtained. Exiting shutdown (falling edge of SHDN) starts a conversion in the same way as the rising edge of CONVST. After coming out of shutdown, initiate a dummy conversion and discard the results. After the dummy conversion, allow the 1ms wake-up time to expire before initiating the first accurate conversion. Power-Saving Modes Shutdown Mode During shutdown the internal reference and analog circuits in the device shutdown and the analog supply current drops to 0.6µA (typ). Select shutdown mode using the SHDN input. Set SHDN high to enter shutdown mode. SHDN takes precedence over CHSHDN. Entering and exiting shutdown mode does not change the configuration byte. However, a new configuration byte can be written while in shutdown mode by following the standard write procedure shown in Figure 6. EOC and EOLC are high when the MAX1304–MAX1306/ MAX1308–MAX1310/MAX1312–MAX1314 are shut down. The state of the digital outputs D0–D11 is independent of the state of SHDN. If CS and RD are low, the digital outputs D0–D11 are active regardless of SHDN. The digital outputs only go high impedance when CS or RD is high. When the digital outputs are powered down, the digital supply current drops to 20nA. 24 Channel Shutdown (CHSHDN) The channel-shutdown feature allows analog input channels to be powered down when they are not selected for conversion. Powering down channels that are not selected for conversion reduces the analog supply current by 2.9mA per channel. To power down channels that are not selected for conversion, pull CHSHDN low. See the Configuration Register section for information on selecting and deselecting channels for conversion. The drawback of powering down analog inputs that are not selected for conversion is that it takes time to power them up. Figure 10 shows how a dummy conversion is used to power up an analog input in external clock mode. After selecting a new channel in the configuration register, initiate a dummy conversion and discard the results. After the dummy conversion, allow the 1ms wake-up time (tWAKE) to expire before initiating the first accurate conversion. ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 CS* tACQ CONVST CONFIGURATION REGISTER UPDATES WR CONFIGURATION REGISTER POWERS UP ONE OR MORE CHANNELS D0–D7 DATA IN tWAKE ≥ 1ms 1 CLK 2 3 4 5 12 13 1 DUMMY CONVERSION START FIRST ACCURATE CONVERSION START tACQ EOC EOLC *CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD. Figure 10. Powering Up an Analog Input Channel with a Dummy Conversion and Wake-Up Time (CHSHDN = 0, External-Clock Mode, One Channel Selected) CS* tACQ CONVST CONFIGURATION REGISTER UPDATES WR CONFIGURATION REGISTER POWERS UP ONE OR MORE CHANNELS D0–D7 DATA IN 1 CLK 2 3 4 5 12 13 FIRST ACCURATE CONVERSION START SECOND ACCURATE CONVERSION START tACQ 1 EOC EOLC *CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD. Figure 11. Powering Up an Analog Input Channel Directly (CHSHDN = 1, External-Clock Mode, One Channel Selected) ______________________________________________________________________________________ 25 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 To avoid the timing requirements associated with powering up an analog channel, force CHSHDN high. With CHSHDN high, each analog input is powered up regardless of whether it is selected for conversion in the configuration register. Note that shutdown mode takes precedence over the CHSHDN mode. erence voltage by driving REF with a +2.0V to +3.0V external reference. As shown in Figure 2, the REF input impedance is 5kΩ. For more information about using external references see the Transfer Functions section. Midscale Voltage (MSV) The voltage at MSV (VMSV) sets the midpoint of the ADC transfer functions. For the 0 to +5V input range (unipolar devices), the midpoint of the transfer function is +2.5V. For the ±5V and ±10V input range devices, the midpoint of the transfer function is zero. As shown in Figure 2, there is a unity-gain buffer between REFMS and MSV in the unipolar MAX1304/ MAX1305/MAX1306. This midscale buffer sets the midpoint of the unipolar transfer functions to either the internal +2.5V reference or an externally applied voltage at REFMS. VMSV follows VREFMS within ±3mV. The midscale buffer is not active for the bipolar devices. For these devices, MSV must be connected to AGND or externally driven. REFMS must be bypassed with a 0.01µF capacitor to AGND. See the Transfer Functions section for more information about MSV. Reference Internal Reference The internal reference circuits provide for analog input voltages of 0 to +5V for the unipolar MAX1304/ MAX1305/MAX1306, ±5V for the bipolar MAX1308/ MAX1309/MAX1310 or ±10V for the bipolar MAX1312/ MAX1313/MAX1314. Install external capacitors for reference stability, as indicated in Table 3 and shown in Figures 3 and 4. As illustrated in Figure 2, the internal reference voltage is 2.5V (VREF). This 2.5V is internally buffered to create the voltages at REF+ and REF-. Table 4 shows the voltages at COM, REF+, and REF-. External Reference External reference operation is achieved by overriding the internal reference voltage. Override the internal ref- Table 3. Reference Bypass Capacitors LOCATION MSV Bypass Capacitor to AGND REFMS Bypass Capacitor to AGND REF Bypass Capacitor to AGND REF+ Bypass Capacitor to AGND REF+ to REF- Capacitor REF- Bypass Capacitor to AGND COM Bypass Capacitor to AGND INPUT VOLTAGE RANGE UNIPOLAR (µF) 2.2 || 0.1 0.01 0.01 0.1 2.2 || 0.1 0.1 2.2 || 0.1 BIPOLAR (µF) N/A 0.01 0.01 0.1 2.2 || 0.1 0.1 2.2 || 0.1 N/A = Not applicable. Connect MSV directly to AGND. Table 4. Reference Voltages PARAMETER EQUATION CALCULATED VALUE (V) VREF = 2.000V, VAVDD = 5.0V ( ) CALCULATED VALUE (V) VREF = 2.500V, VAVDD = 5.0V ( ) CALCULATED VALUE (V) VREF = 3.000V, VAVDD = 5.0V ( ) VCOM VREF+ VREFVREF+ - VREF- VCOM = 13/25 x VAVDD VREF+ = VCOM + VREF/2 VREF- = VCOM - VREF/2 VREF+ - VREF- = VREF 2.600 3.600 1.600 2.000 2.600 3.850 1.350 2.500 2.600 4.100 1.100 3.000 26 ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Transfer Functions Unipolar 0 to +5V Devices Table 5 and Figure 12 show the offset binary transfer function for the MAX1304/MAX1305/MAX1306 with a 0 to +5V input range. The full-scale input range (FSR) is two times the voltage at REF. The internal +2.5V reference gives a +5V FSR, while an external +2V to +3V reference allows an FSR of +4V to +6V, respectively. Calculate the LSB size using: 1 LSB = 2 x VREF 212 The input range is centered about VMSV, internally set to +2.5V. For a custom midscale voltage, drive REFMS with an external voltage source and MSV will follow REFMS. Noise present on MSV or REFMS directly couples into the ADC result. Use a precision, low-drift voltage reference with adequate bypassing to prevent MSV from degrading ADC performance. For maximum FSR, do not violate the absolute maximum voltage ratings of the analog inputs when choosing MSV. Determine the input voltage as a function of V REF , VMSV, and the output code in decimal using: VCH_ = LSB x CODE10 + VMSV - 2.500V MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 which equals 1.22mV when using a 2.5V reference. Table 5. 0 to +5V Unipolar Code Table BINARY DIGITAL OUTPUT CODE DECIMAL EQUIVALENT DIGITAL OUTPUT CODE (CODE10) 4095 4094 2049 2048 2047 1 0 INPUT VOLTAGE (V) VREF = +2.5V VREFMS = +2.5V 2 x VREF 0xFFF 0xFFE 0xFFD 0xFFC ( ) BINARY OUTPUT CODE 1111 1111 1111 = 0xFFF 1111 1111 1110 = 0xFFE 1000 0000 0001 = 0x801 1000 0000 0000 = 0x800 0111 1111 1111 = 0x7FF 0000 0000 0001 = 0x001 0000 0000 0000 = 0x000 +4.9994 ± 0.5 LSB +4.9982 ± 0.5 LSB +2.5018 ± 0.5 LSB +2.5006 ± 0.5 LSB +2.4994 ± 0.5 LSB +0.0018 ± 0.5 LSB +0.0006 ± 0.5 LSB 0x801 0x800 0x7FF 0x0003 0x0002 0x0001 0x0000 0 123 2046 2048 2050 (MSV) 1 LSB = 2 x VREF 212 4095 4093 INPUT VOLTAGE (LSBs) Figure 12. 0 to +5V Unipolar Transfer Function ______________________________________________________________________________________ 27 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 Bipolar ±5V Devices Table 6 and Figure 13 show the two’s complement transfer function for the ±5V input range MAX1308/MAX1309/ MAX1310. The FSR is four times the voltage at REF. The internal +2.5V reference gives a +10V FSR, while an external +2V to +3V reference allows an FSR of +8V to +12V respectively. Calculate the LSB size using: 1 LSB = 4 x VREF 212 The input range is centered about V MSV. Normally, MSV = AGND, and the input is symmetrical about zero. For a custom midscale voltage, drive MSV with an external voltage source. Noise present on MSV directly couples into the ADC result. Use a precision, low-drift voltage reference with adequate bypassing to prevent MSV from degrading ADC performance. For maximum FSR, do not violate the absolute maximum voltage ratings of the analog inputs when choosing MSV. Determine the input voltage as a function of V REF , VMSV, and the output code in decimal using: VCH_ = LSB x CODE10 + VMSV which equals 2.44mV when using a 2.5V reference. Table 6. ±5V Bipolar Code Table TWO’s COMPLEMENT DIGITAL OUTPUT CODE 0111 1111 1111 = 0x7FF 0111 1111 1110 = 0x7FE 0000 0000 0001 = 0x001 0000 0000 0000 = 0x000 1111 1111 1111 = 0xFFF 1000 0000 0001 = 0x801 1000 0000 0000 = 0x800 DECIMAL EQUIVALENT DIGITAL OUTPUT CODE (CODE10) +2047 +2046 +1 0 -1 -2047 -2048 INPUT VOLTAGE (V) VREF = +2.5V VMSV = 0V 4 x VREF +4.9988 ±0.5 LSB +4.9963 ±0.5 LSB +0.0037 ±0.5 LSB +0.0012 ±0.5 LSB -0.0012 ±0.5 LSB -4.9963 ±0.5 LSB -4.9988 ±0.5 LSB TWO'S COMPLEMENT BINARY OUTPUT CODE ( ) 0x7FF 0x7FE 0x7FD 0x7FC 0x001 0x000 0xFFF 0x803 0x802 0x801 0x800 -2048 -2046 -1 0 +1 (MSV) 1 LSB = 4 x VREF 212 +2045 +2047 INPUT VOLTAGE (VCH_ - VMSV IN LSBs) Figure 13. ±5V Bipolar Transfer Function 28 ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Bipolar ±10V Devices Table 7 and Figure 14 show the two’s complement transfer function for the ±10V input range MAX1312/ MAX1313/MAX1314. The FSR is eight times the voltage at REF. The internal +2.5V reference gives a +20V FSR, while an external +2V to +3V reference allows an FSR of +16V to +24V, respectively. Calculate the LSB size using: 1 LSB = 8 x VREF 212 The input range is centered about V MSV. Normally, MSV = AGND, and the input is symmetrical about zero. For a custom midscale voltage, drive MSV with an external voltage source. Noise present on MSV directly couples into the ADC result. Use a precision, low-drift voltage reference with adequate bypassing to prevent MSV from degrading ADC performance. For maximum FSR, do not violate the absolute maximum voltage ratings of the analog inputs when choosing MSV. Determine the input voltage as a function of V REF , VMSV, and the output code in decimal using: VCH_ = LSB x CODE10 + VMSV MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 which equals 4.88mV with a +2.5V reference. Table 7. ±10V Bipolar Code Table TWO’s COMPLEMENT DIGITAL OUTPUT CODE 0111 1111 1111 = 0x7FF 0111 1111 1110 = 0x7FE 0000 0000 0001 = 0x001 0000 0000 0000 = 0x000 1111 1111 1111 = 0xFFF 1000 0000 0001 = 0x801 1000 0000 0000 = 0x800 DECIMAL EQUIVALENT DIGITAL OUTPUT CODE (CODE10) +2047 +2046 +1 0 -1 -2047 -2048 INPUT VOLTAGE (V) VREF = +2.5V VMSV = 0V 8 x VREF +9.9976 ±0.5 LSB +9.9927 ±0.5 LSB +0.0073 ±0.5 LSB 0.0024 ±0.5 LSB -0.0024 ±0.5 LSB -9.9927 ±0.5 LSB -9.9976 ±0.5 LSB TWO'S COMPLEMENT BINARY OUTPUT CODE ( ) 0x7FF 0x7FE 0x7FD 0x7FC 0x001 0x000 0xFFF 0x803 0x802 0x801 0x800 -2048 -2046 -1 0 +1 (MSV) 1 LSB = 8 x VREF 212 +2045 +2047 INPUT VOLTAGE (VCH_ - VMSV IN LSBs) Figure 14. ±10V Bipolar Transfer Function ______________________________________________________________________________________ 29 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 3-Phase Motor Controller The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312– MAX1314 are ideally suited for motor-control systems (Figure 15). The devices’ simultaneously sampled inputs eliminate the need for complicated DSP algorithms that realign sequentially sampled data into a simultaneous sample set. Additionally, the variety of input voltage ranges allows for flexibility when choosing current sensors and position encoders. MAX1308 DSP 12-BIT ADC T/H IGBT CURRENT DRIVERS CURRENT SENSOR IPHASE1 IPHASE3 IPHASE2 3-PHASE ELECTRIC MOTOR PHASE 1 PHASE 3 PHASE 2 POSITION ENCODER Figure 15. 3-Phase Motor Control 30 ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges 3-Phase Power-Monitoring System The 8-channel devices are well suited for use in 3-phase power monitoring (Figure 16). The simultaneously sampled eight channels eliminate the need for complicated DSP algorithms that realign sequentially sampled data into a simultaneous sample set. MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 MAX1312 T/H 12-BIT ADC MICROCONTROLLER BUFFERS AND INPUT PROTECTION VP3 VP1 VNEUTRAL VP2 IP3 IP2 IPn IP1 CURRENT TRANSFORMER PHASE 1 LOAD POWER GRID NEUTRAL CURRENT TRANSFORMER LOAD LOAD CURRENT TRANSFORMER PHASE 2 PHASE 3 CURRENT TRANSFORMER Figure 16. 3-Phase Power Monitoring ______________________________________________________________________________________ 31 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 Layout, Grounding, and Bypassing For best performance use PC boards. Board layout must ensure that digital and analog signal lines are separated from each other. Do not run analog and digital lines parallel to one another (especially clock lines), and do not run digital lines underneath the ADC package. Figure 17 shows the recommended system ground connections. Establish an analog ground point at AGND and a digital ground point at DGND. Connect all analog grounds to the analog ground point. Connect all digital grounds to the digital ground point. For lowest noise operation, make the power-supply ground returns as low impedance and as short as possible. Connect the analog ground point to the digital ground point at one location. High-frequency noise in the power supplies degrades the ADC’s performance. Bypass the analog power plane to the analog ground plane with a 2.2µF capacitor within one inch of the device. Bypass each AVDD to AGND pair of pins with a 0.1µF capacitor as close to the device as possible. AVDD to AGND pairs are pin 1 to pin 2, pin 14 to pin 15, and pin 16 to pin 17. Likewise, bypass the digital power plane to the digital ground plane with a 2.2µF capacitor within one inch of the device. Bypass each DVDD to DGND pair of pins with a 0.1µF capacitor as close to the device as possible. DVDD to DGND pairs are pin 24 to pin 25, and pin 38 to pin 39. If a supply is very noisy use a ferrite bead as a lowpass filter as shown in Figure 17. ANALOG SUPPLY +5V RETURN DIGITAL GROUND POINT DIGITAL SUPPLY RETURN +3V TO +5V OPTIONAL ANALOG GROUND FERRITE POINT BEAD AVDD AGND DGND DVDD DATA DGND DVDD MAX1304–MAX1306 MAX1308–MAX1310 MAX1312–MAX1314 DIGITAL CIRCUITRY Figure 17. Power-Supply Grounding and Bypassing Offset Error Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. Typically the point at which offset error is specified is either at or near the zeroscale point of the transfer function or at or near the midscale point of the transfer function. For the unipolar devices (MAX1304/MAX1305/ MAX1306), the ideal zero-scale transition from 0x000 to 0x001 occurs at 1 LSB above AGND (Figure 12, Table 5). Unipolar offset error is the amount of deviation between the measured zero-scale transition point and the ideal zero-scale transition point. For the bipolar devices (MAX1308/MAX1309/MAX1310/ MAX1312/MAX1313/MAX1314), the ideal midscale transition from 0xFFF to 0x000 occurs at MSV (Figures 14 and 13, Tables 7 and 6). The bipolar offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point. Definitions Integral Nonlinearity (INL) INL is the deviation of the values on an actual transfer function from a straight line. For these devices, this straight line is drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. Differential Nonlinearity (DNL) DNL is the difference between an actual step width and the ideal value of 1 LSB. For these devices, the DNL of each digital output code is measured and the worstcase value is reported in the Electrical Characteristics table. A DNL error specification of less than ±1 LSB guarantees no missing codes and a monotonic transfer function. 32 ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Gain Error Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. For the MAX1304– MAX1306/MAX1308–MAX1310/MAX1312–MAX1314, the gain error is the difference of the measured full-scale and zero-scale transition points minus the difference of the ideal full-scale and zero-scale transition points. For the unipolar devices (MAX1304/MAX1305/ MAX1306), the full-scale transition point is from 0xFFE to 0xFFF and the zero-scale transition point is from 0x000 to 0x001. For the bipolar devices (MAX1308/MAX1309/MAX1310/ MAX1312/MAX1313/MAX1314), the full-scale transition point is from 0x7FE to 0x7FF and the zero-scale transition point is from 0x800 to 0x801. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed as: ENOB = SINAD − 1.76 6.02 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first five harmonics to the fundamental itself. This is expressed as: ⎛ V 22 + V 32 + V 42 + V 52 + V 62 ⎞ THD = 20 x log ⎜ ⎟ ⎜ ⎟ V1 ⎝ ⎠ where V1 is the fundamental amplitude, and V2 through V 6 are the amplitudes of the 2nd- through 6thorder harmonics. Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNRdB[max] = 6.02dB × N + 1.76dB In reality, there are other noise sources such as thermal noise, reference noise, and clock jitter. For these devices, SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. SFDR is specified in decibels relative to the carrier (dBc). Channel-to-Channel Isolation Channel-to-channel isolation indicates how well each analog input is isolated from the others. The channel-tochannel isolation for these devices is measured by applying DC to channel 1 through channel 7 while an AC 500kHz, -0.4dBFS sine wave is applied to channel 0. An FFT is taken for channel 0 and channel 1 and the difference (in dB) of the 500kHz magnitudes is reported as the channel-to-channel isolation. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset. ⎛ ⎞ SIGNALRMS SINAD(dB) = 20 x log ⎜ (NOISE + DISTORTION)RMS ⎟ ⎝ ⎠ Aperature Delay Aperture delay (tAD) is the time delay from the CONVST rising edge to the instant when an actual sample is taken. ______________________________________________________________________________________ 33 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 Aperture Jitter Aperture Jitter (tAJ) is the sample-to-sample variation in aperture delay. Jitter is a concern when considering an ADC’s dynamic performance, e.g., SNR. To reconstruct an analog input from the ADC digital outputs, it is critical to know the time at which each sample was taken. Typical applications use an accurate sampling clock signal that has low jitter from sampling edge to sampling edge. For a system with a perfect sampling clock signal, with no clock jitter, the SNR performance of an ADC is limited by the ADC’s internal aperture jitter as follows: ⎛ ⎞ 1 SNR = 20 x log ⎜ ⎟ ⎝ 2 x π x fIN x tAJ ⎠ where fIN represents the analog input frequency and tAJ is the time of the aperture jitter. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC so that the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. Full-Power Bandwidth A large, -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as fullpower input bandwidth frequency. DC Power-Supply Rejection (PSRR) DC PSRR is defined as the change in the positive fullscale transfer function point caused by a ±5% variation in the analog power-supply voltage (AVDD). 34 ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Pin Configurations MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 TOP VIEW CHSHDN SHDN CLK CONVST CS WR RD EOLC EOC DGND DVDD D11 CHSHDN SHDN CLK CONVST CS WR RD EOLC EOC DGND DVDD D11 48 47 46 45 44 43 42 41 40 39 38 48 47 46 45 44 43 42 41 40 39 38 37 AVDD AGND AGND CH0 CH1 MSV CH2 CH3 CH4 CH5 CH6 CH7 1 2 3 4 5 6 7 8 9 10 11 12 + 36 35 34 33 32 31 30 29 28 27 26 25 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DVDD AVDD AGND AGND CH0 CH1 MSV CH2 CH3 I.C. I.C. I.C. I.C. 1 2 3 4 5 6 7 8 9 10 11 12 + 37 36 35 34 33 32 31 30 29 28 27 26 25 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DVDD MAX1304 MAX1308 MAX1312 MAX1305 MAX1309 MAX1313 13 14 15 16 17 18 19 20 21 22 23 24 13 14 15 16 17 18 19 20 21 22 23 INTCLK/EXTCLK AGND AVDD AGND AVDD REFMS REF REF+ COM REFAGND DGND 8-CHANNEL LQFP 48 47 46 45 44 43 42 41 40 39 38 AVDD AGND AGND CH0 CH1 MSV I.C. I.C. I.C. I.C. I.C. I.C. 1 2 3 4 5 6 7 8 9 10 11 12 + 37 CHSHDN SHDN CLK CONVST CS WR RD EOLC EOC DGND DVDD D11 MAX1306 MAX1310 MAX1314 13 14 15 16 17 18 19 20 21 22 23 ______________________________________________________________________________________ INTCLK/EXTCLK AGND AVDD AGND AVDD REFMS REF REF+ COM REFAGND DGND 2-CHANNEL LQFP 24 INTCLK/EXTCLK AGND AVDD AGND AVDD REFMS REF REF+ COM REFAGND DGND 4-CHANNEL LQFP 36 35 34 33 32 31 30 29 28 27 26 25 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DVDD 24 35 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 Chip Information PROCESS: 0.6µm BiCMOS Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 48 LQFP PACKAGE CODE C48+6 OUTLINE NO. 21-0054 LAND PATTERN NO. 90-0093 36 ______________________________________________________________________________________ 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges Revision History REVISION NUMBER 4 REVISION DATE 8/09 Added automotive part numbers Revised Ordering Information, Absolute Maximum Ratings, Electrical Characteristics, Typical Operating Characteristics, Pin Description, Tables 4, 6, and 7, Figures 2, 3, and 7, DC Power-Supply Rejection (PSRR) section, Pin Configurations, and Package Information. DESCRIPTION PAGES CHANGED 1 1–18, 20, 26, 28, 29, 32, 34–36 MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 5 4/11 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 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