MAX1462

19-1813; Rev 0; 10/00 KIT ATION EVALU E AILABL AV Low-Voltage, Low-Power, 16-Bit Smart ADC General Description Features o Low-Voltage Operation (2.4V to 3.6V) o Low-Noise, 310µA Single-Chip Sensor Signal Conditioning o High-Precision Front End Resolves 1MΩ. Rail-to-Rail® input range. Test/Program Mode Enable Input. When high, enables the MAX1462 programming/testing operations. Internally pulled to VSS with a 1MΩ (typ) resistor. Negative Sensor Input. Input impedance is typically >1MΩ. Rail-to-Rail input range. FUNCTION MAX1462 Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. Detailed Description The main functions of the MAX1462 include: • Analog front end: Includes PGA, CO-DAC, ADC, and temperature sensor. • Test system interface: Writes calibration coefficients to the DSP registers and EEPROM. • Test system interface: Observes the DSP operation. The sensor signal enters the MAX1462 and is adjusted for coarse gain and offset by the analog front end. Five bits in the configuration register set the CO-DAC and the coarse gain of the PGA (Tables 1 and 2). These bits must be properly configured for the optimum dynamic range of the ADC. The digitized sensor signal is stored in a read-only DSP register. The on-chip temperature sensor also has a 3-bit CODAC that places the temperature signal in the ADC operating range. Digitized temperature is also stored in a read-only DSP register. The DSP uses the digitized sensor, the temperature signals, and the correction coefficients to calculate the compensated and corrected output. The MAX1462 supports an automated production environment, where a test system communicates with a batch of MAX1462s and controls temperature and sensor excitation. The three-state digital outputs on the MAX1462 allow parallel connection of transducers, so that all five serial interface lines (XIN, TEST, RESET, SDIO, and SDO) can be shared. The test system selects an individual transducer using CS1 and CS2. The test system must vary the sensor’s input and temperature, calculate the correction coefficients for each unit, load the coefficients into the MAX1462 nonvolatile EEPROM, and test the resulting compensation. The MAX1462 DSP implements the following characteristic equation: D = Gain (1 + G1T + G2T 2 (Signal + Of ) × 2 0 + Of1T + Of2T )+D OFF _______________________________________________________________________________________ 5 Low-Voltage, Low-Power, 16-Bit Smart ADC where Gain corrects the sensor’s sensitivity, G1 and G2 correct for Gain-TC, T and Signal are the digitized outputs of the analog front end, Of0 corrects the sensor’s offset, Of1 and Of2 correct the Offset-TC, and DOFF is the output offset pedestal. The test system can write the calibration coefficients into the MAX1462 EEPROM or write to the DSP registers directly. The MAX1462 can begin a conversion using either the EEPROM contents or the register contents. When the test system issues commands, the MAX1462 is a serially controlled slave device. The test system observes the MAX1462 DSP operation in order to acquire the temperature and signal ADC results, to verify the calibration coefficients, and to get the output D. The MAX1462 places the contents of several important DSP registers on the serial interface after the tester issues a Start Conversion command. After calibration, compensation, and final test, the MAX1462 is adapted to its sensor and the pair can be removed from the test system. Use the resulting transducer by applying power and the START signal. Latch the 12-bit parallel digital output using the EOC pulse. The maximum conversion rate of the MAX1462 is 15Hz, using a 2MHz resonator. If an analog output is desired, build a simple lowpass filter using the OUT pin, the uncommitted op amp, and a few discrete components (Figure 8). MAX1462 Analog Front End, Including PGA, CO-DAC, ADC, and Temperature Sensor Before the sensor signal is digitized, it must be gained and CO corrected to maximize the ADC dynamic range. There are 2 bits (four possible settings) in the configuration register for the PGA gain, and 3 bits (eight possible settings) for the CO-DAC. The flowchart (Figure 1) shows a procedure for finding the optimum analog front-end settings when the sensor’s characteristics are unknown. Use the tabulated values (Tables 1 and 2) if the peak sensor excursions are known. See the Test System Interface section for details on writing these analog front-end bits. The PGA gain and the CO are very stable but are not accurate. Manufacturing variances on the gain and offset of the MAX1462 analog front-end superposition the residual sensor errors and are later removed during final calibration. For example, suppose the sensor’s sensitivity is +10mV/V with an offset of -12mV/V. Let the supply voltage be +3V. The full-scale (-FS) output of the sensor is then +3V(-12mV/V) = -36mV; +FS is then +3V (-12mV/V + 10mV/V) = -6mV. Following through the flowchart, the PGA gain setting is +3 (gain = +93V/V) and the CO correction setting is +1 (+15mV RTI) - (Referred-to-Input). The coarsely corrected -FS input to the ADC is (-36mV + 15mV)93 = -1.953V. The +FS input to the ADC is (-6mV + 15mV)93 = +0.837V. The input range of the ADC is ±VDD. Thus, the maximum and minimum digitized sensor signals become -1.953 / 3 = -0.651 and +0.837 / 3 = +0.279. Notice that the bridge multiplies the signal by VDD, and the ADC divides the signal by VDD. Thus, the system is ratiometric and not dependent on the DC value of VDD. The ADC output clips to ±1.0 when input values exceed ±VDD. The best signal-to-noise ratio (SNR) is achieved when the ADC input is within ±85% of VDD (Figure 2). Table 1. Nominal PGA Gain Settings PGA SETTING 0 1 2 3 PGA-1 0 0 1 1 PGA-0 0 1 0 1 NOMINAL GAIN (V/V) 46 61 77 93 Table 2. Typical Coarse Offset DAC Settings CO SETTING -3 -2 -1 -0 +0 +1 +2 +3 6 CO-S 1 1 1 1 0 0 0 0 CO-1 1 1 0 0 0 0 1 1 CO-0 1 0 1 0 0 1 0 1 % VDD (at ADC INPUT) -149 -96 -47 5 -5 47 96 149 PGA SETTING 0 (mV RTI) (VDD = 3V) -97 -62 -31 3 -3 31 62 97 PGA SETTING 1 (mV RTI) (VDD = 3V) -73 -47 -23 2 -2 23 47 73 PGA SETTING 2 (mV RTI) (VDD = 3V) -58 -37 -19 2 -2 19 37 58 PGA SETTING 3 (mV RTI) (VDD = 3V) -48 -31 -15 1 -1 15 31 48 _______________________________________________________________________________________ Low-Voltage, Low-Power, 16-Bit Smart ADC The MAX1462 includes an internal temperature-sensing bridge allowing the MAX1462 temperature to be used as a proxy for the sensor temperature. For this reason, the MAX1462 must be mounted in thermal proximity to the sensor. The output of the temperature-sensing bridge is also corrected by a 3-bit coarse-offset DAC and processed by the ADC. The selection of the temperature sensor offset (TSO) bits in the configuration register should be made so that the digitized temperature signal is as close to 0.0 as possible at midscale temperature. This is done to maximize the dynamic range of the thermal-calibration coefficients (Table 3). MAX1462 Test-System Interface: Writing Calibration Coefficients to the DSP Registers and EEPROM To make the MAX1462 respond to commands from the test system, raise the TEST pin and drive XIN with a –MAKE A TEST SYSTEM VARIABLE CALLED “NoMoreGain.” –SET THE TEMPERATURE TO WHERE THE SENSOR’S SENSITIVITY IS HIGHEST. THIS IS NORMALLY COLD FOR SILICON PRTs. –SET THE PGA GAIN SETTINGS TO MINIMUM. –CLEAR THE VARIABLE “NoMoreGain.” –APPLY MIDSCALE EXCITATION TO THE SENSOR. –FIND THE COARSE OFFSET DAC SETTING WHERE THE DIGITIZED SIGNAL REGISTER IS CLOSEST TO ZERO (MIDSCALE). –APPLY MAXIMUM SENSOR EXCITATION. –TEST FOR CLIPPING (DIGITIZED SIGNAL > 0.85). –APPLY MINIMUM SENSOR EXCITATION. –TEST FOR CLIPPING (DIGITIZED SIGNAL < -0.85). THE SENSOR SENSITIVITY VDD IS TOO LARGE. ADD A RESISTOR BETWEEN THE SERIES TOP OF THE BRIDGE RESISTOR AND VDD , THEN START OVER. YES DID ADC CLIP? IS THE PGA AT MINIMUM GAIN? YES SENSOR NO NO –REDUCE THE PGA GAIN ONE STEP. –SET THE VARIABLE “NoMoreGain.” IS THE PGA AT MAXIMUM GAIN? NO IS “NoMoreGain” SET? NO INCREASE THE PGA GAIN ONE STEP. YES YES RECORD THE PGA AND COARSE OFFSET SETTINGS. CAUTION: CLIPPING IS STILL POSSIBLE FOR LARGE SENSOR’S OFFSET TC AND LARGE TEMPERATURE RANGES. IF NECESSARY, GUARD BAND AGAINST CLIPPING BY REDUCING THE ±0.85 CLIPPING CONSTANTS ABOVE. Figure 1. Flowchart for Determining PGA and CO Settings _______________________________________________________________________________________ 7 Low-Voltage, Low-Power, 16-Bit Smart ADC MAX1462 0.010 0.008 NONLINEARITY ERROR (% FS) 0.006 0.004 0.002 0 -0.002 -0.004 -0.006 -0.008 -0.010 -100 -80 -60 -40 -20 0 20 40 60 80 100 SENSOR SIGNAL INPUT OR ADC INPUT/OUTPUT RANGE (%) ERROR (16-BIT LSBs) 2 1 0 -1 -2 -3 -4 -100 -80 -60 -40 -20 0 20 40 60 80 100 SENSOR SIGNAL INPUT OR ADC INPUT RANGE (%) 4 3 Figure 2a. Analog Front-End Integrated Nonlinearity (INL) (typ) Figure 2b. Analog Front-End Differential Nonlinearity (DNL) (typ) 4.0 NOISE STANDARD DEVIATION (16-BIT LSBs) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -100 -80 -60 -40 -20 0 20 40 60 80 100 SENSOR SIGNAL INPUT OR ADC INPUT/OUTPUT RANGE (%) two register fields, and command 2 hex requires an EEPROM address. The command word fields are: • Register Data Field: Holds the calibration coefficients to be written into the MAX1462 16-bit registers • EEPROM Address Field: Holds the hexadecimal address of the EEPROM bit to be set (from 00 hex to 7F hex) • Register Address Field: Contains the address of the register (0 to 7) where the calibration coefficient is to be written • Command Field: Instructs the MAX1462 to take a particular action (Table 4) Writing to the DSP Registers Command 1 hex writes calibration coefficients from the test system directly into the DSP registers. Tester commands 8 hex and C hex cause the MAX1462 to start a conversion using the calibration coefficients in the registers. This direct use of the registers speeds calibration and compensation because it does not require EEPROM write-access time. Bringing RESET low clears the DSP registers, so the test system should always write to the registers and start a conversion in a single command timing sequence. As shown in Table 5, seven registers hold the calibration coefficients of the characteristic equation: [DOUT = Gain (1 + G1T + G2T2) (Signal + Of0 + Of1T + Of2T2) + DOFF] implemented by the MAX1462 DSP. All of the registers are 16-bit, two’s complement coding format. When a register is interpreted as an integer, the decimal range is from -32768 (8000 hex) to +32767 (7FFF Figure 2c. Analog Front-End Noise Standard Deviation of the Samples (typ) 2MHz clock signal. It is not necessary to remove the resonator. R ESET must be low for at least 16 clock cycles to initialize the MAX1462. Then, a rising transition on RESET begins a 32-bit serial transfer of the testsystem command word through SDIO. The test system transitions SDIO on falling edges of the XIN clock; the MAX1462 latches data on the rising edge (Figure 3). The 32-bit command word generated by the test system is divided into four fields (Figure 3). The 4-bit command field is interpreted in Table 4. The other fields are usually ignored, except that command 1 hex uses the 8 _______________________________________________________________________________________ Low-Voltage, Low-Power, 16-Bit Smart ADC MAX1462 MIN 16 CLK CYCLES XIN 00 01 02 03 29 30 31 00 01 02 03 29 30 31 00 01 02 03 29 30 31 00 01 02 03 29 30 31 TEST RESET SDIO D0 D1 D2 D3 C3 NU NU D0 D1 D2 D3 C3 NU NU D0 D1 D2 D3 C3 NU NU D0 D1 D2 D3 C3 NU NU COMMAND 1 COMMAND 2 COMMAND 3 COMMAND n D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 E0 E1 LSB REGISTER DATA FIELD MSB LSB E2 E3 E4 E5 E6 R0 R1 R2 C0 C1 C2 C3 NU NU MSB LSB MSB LSB MSB REG. COMMAND ADD EEPROM ADDRESS FIELD NOTE: ALL TRANSITIONS MUST OCCUR WITHIN 100ns OF THE XIN CLOCK EDGE. Figure 3. Test-System Command Timing Diagram Table 3. TSO Settings TSO TSO-2 SETTING 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 TSO-1 0 0 1 1 0 0 1 1 TSO-0 0 1 0 1 0 1 0 1 TEMPERATURE BRIDGE OFFSET Maximum — — — — — — Minimum The Op Amp Power-Down bit enables the uncommitted op amp when set. The repeat-mode bit is tested by the last instruction of the DSP microcode, and, if set, immediately initiates another conversion cycle. The Maxim reserved bits should not be altered. Writing to the Internal EEPROM The test system writes to the EEPROM with commands 4 hex (Block-Erase the entire EEPROM), 2 hex (Write 1 to a single EEPROM bit), and 0 hex (NOOP). The minimum VDD required for all EEPROM write operations is 4.75V. During normal operation (when the TEST pin is low) or when the test system issues instructions A hex or E hex (Start Conversion from EEPROM values), the DSP reads the Calibration Coefficients from the EEPROM. In the normal production flow, determine the calibration coefficients using direct register access. Then load the calibration coefficients into the EEPROM with tester instruction 2 hex. Instruction 4 hex block-erases the EEPROM and is necessary only for a rework or reclaim operation. For each part, the Maxim reserved bits in the Configuration Register should be read before instruction 4 hex is issued, and restored afterwards. The MAX1462 is shipped with its internal EEPROM uninitialized, except for the reserved bits. h ex). Fractional coefficient values range from -1.0 (8000 hex) to +0.99997 (7FFF hex). The register at address 0 is called the Configuration Register. It holds the CO, PGA gain, Op Amp PowerDown, temperature-sensor offset, repeat mode, and reserved bits, as shown in Table 6. The functionality of the CO, PGA gain, and temperature-sensor bits is described in the Analog Front End, Including PGA, CODAC, ADC, and Temperature Sensor section. _______________________________________________________________________________________ 9 Low-Voltage, Low-Power, 16-Bit Smart ADC MAX1462 Table 4. Test System Commands COMMAND Write a calibration coefficient into a DSP register. Block-Erase the entire EEPROM (writes “0” to all 128 bits). Write 1 to a single EEPROM bit. NOOP (NO-OPeration). Start Conversion command. The registers are not updated with EEPROM values. SDIO and SDO are enabled as DSP outputs. Start Conversion command. The registers are updated with EEPROM values. SDIO and SDO are enabled as DSP outputs. Start Conversion command. The registers are not updated with EEPROM values. SDIO and SDO are disabled. Start Conversion command. The registers are updated with EEPROM values. SDIO and SDO are disabled. Reserved HEX CODE 1 hex 4 hex 2 hex 0 hex 8 hex A hex C hex E hex 3, 5, 6, 7, 9, B, D, F hex C3 0 0 0 0 1 1 1 1 C2 0 1 0 0 0 0 1 1 C1 0 0 1 0 0 1 0 1 C0 1 0 0 0 0 0 0 0 — — — — Table 5. DSP Calibration Coefficient Registers COEFFICIENT Gain G1 G2 Of0 Of1 Of2 DOFF REGISTER ADDRESS 1 2 3 4 5 6 7 FUNCTION Gain correction Linear TC gain Quadratic TC gain Offset correction Linear TC offset Quadratic TC offset Output midscale pedestal RANGE -32768 to +32767 -1.0 to +0.99997 -1.0 to +0.99997 -1.0 to +0.99997 -1.0 to +0.99997 -1.0 to +0.99997 -32768 to +32767 FORMAT Integer Fraction Fraction Fraction Fraction Fraction Integer The internal 128-bit EEPROM is arranged as eight 16bit words. These eight words are the configuration register and the seven calibration-coefficient values (Table 7). The MAX1462 EEPROM is bit addressable. The final calibration coefficients must be mapped into the EEPROM locations that are to be set. There is no bitclear instruction. Any EEPROM write operation is necessarily long because the internal charge pump must create and maintain voltages above 20V long enough to cause a reliably permanent change in the memory. Writing an EEPROM bit requires 6ms, so writing the EEPROM typically requires