MAX15023ETG

19-4219; Rev 2; 3/11 KIT ATION EVALU E AILABL AV Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller General Description Features o o o o o o o o o o o o 5.5V to 28V or 5V ±10% Input Supply Range 0.6V to (0.85 x VIN) Adjustable Outputs Adjustable 200kHz to 1MHz Switching Frequency Guaranteed Monotonic Startup into a Prebiased Load Lossless, Cycle-by-Cycle, Low-Side, Source Peak Current Limit with Adjustable, TemperatureCompensated Threshold Cycle-by-Cycle, Low-Side, Sink Peak CurrentLimit Protection Proprietary Adaptive Internal Digital Soft-Start ±1% Accurate Voltage Reference Internal Boost Diodes Adaptive Synchronous Rectification Eliminates External Freewheeling Schottky Diodes Hiccup-Mode Short-Circuit Protection and Thermal Shutdown Power-Good Outputs and Analog Enable Inputs for Power Sequencing MAX15023 The MAX15023 dual, synchronous step-down controller operates from a 5.5V to 28V or 5V ±10% input voltage range and generates two independent output voltages. Each output is adjustable from 85% of the input voltage down to 0.6V and supports loads of 12A or higher. Input voltage ripple and total RMS input ripple current are reduced by interleaved 180° out-of-phase operation. The MAX15023 offers the ability to adjust the switching frequency from 200kHz to 1MHz with an external resistor. The MAX15023’s adaptive synchronous rectification eliminates the need for external freewheeling Schottky diodes. The device also utilizes the external low-side MOSFET’s on-resistance as a current-sense element, eliminating the need for a current-sense resistor. This protects the DCDC components from damage during output overloaded conditions or output short-circuit faults without requiring a current-sense resistor. Hiccup-mode current limit reduces power dissipation during short-circuit conditions. The MAX15023 includes two independent power-good outputs and two independent enable inputs with precise turn-on/turn-off thresholds, which can be used for supply monitoring and for power sequencing. Additional protection features include cycle-by-cycle, low-side, sink peak current limit, and thermal shutdown. Cycle-by-cycle, low-side, sink peak current limit prevents reverse inductor current from reaching dangerous levels when the device is sinking current from the output. The MAX15023 also allows prebiased startup without discharging the output and features adaptive internal digital soft-start. This new proprietary feature enables monotonic charging of externally large output capacitors at startup, and achieves good control of the peak inductor current during hiccup-mode short-circuit protection. The MAX15023 is available in a space-saving and thermally enhanced 4mm x 4mm, 24-pin TQFN-EP package. The device operates over the -40°C to +85°C extended temperature range. Ordering Information PART MAX15023ETG+ TEMP RANGE -40°C to +85°C PIN-PACKAGE 24 TQFN-EP* -40°C to +85°C MAX15023ETG/V+ 24 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Pin Configuration COMP2 PGND2 13 12 11 10 LX2 BST2 DH2 DH1 BST1 LX1 9 *EP 8 7 1 FB1 2 EN1 3 EN2 4 PGOOD1 5 DL1 6 PGND1 TOP VIEW PGOOD2 15 18 RT 19 SGND 20 IN 21 LIM2 22 LIM1 23 COMP1 24 17 16 14 Applications Point-of-Load Regulators Set-Top Boxes LCD TV Secondary Supplies Switches/Routers Power Modules DSP Power Supplies MAX15023 + TQFN *EXPOSED PAD (CONNECT TO GROUND). ________________________________________________________________ Maxim Integrated Products DL2 VCC FB2 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller MAX15023 ABSOLUTE MAXIMUM RATINGS IN to SGND.............................................................-0.3V to +30V BST_ to VCC............................................................-0.3V to +30V LX_ to SGND .............................................................-1V to +30V EN_ to SGND............................................................-0.3V to +6V PGOOD_ to SGND .................................................-0.3V to +30V BST_ to LX_ ..............................................................-0.3V to +6V DH_ to LX_ ..........................................….-0.3V to (VBST_ + 0.3V) DL_ to PGND_ ............................................-0.3V to (VCC + 0.3V) SGND to PGND_ .................................................. -0.3V to +0.3V VCC to SGND................-0.3V to the lower of +6V or (VIN + 0.3V) All Other Pins to SGND...............................-0.3V to (VCC + 0.3V) VCC Short Circuit to SGND.........................................Continuous VCC Input Current (IN = VCC, internal LDO not used) ......600mA PGOOD_ Sink Current ........................................................20mA Continuous Power Dissipation (TA = +70°C)(Note 1) 24-Pin TQFN-EP (derate 27.8mW/°C above +70°C)......2222.2mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Note 1: These power limits are due to the thermal characteristics of the package, absolute maximum junction temperature (150°C), and the JEDEC 51-7 defined setup. Maximum power dissipation could be lower, limited by the thermal shutdown protection included in this IC. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 2) 24 TQFN-EP Junction-to-Ambient Thermal Resistance (θJA)...............+36°C/W Junction-to-Case Thermal Resistance (θJC)......................+8°C/W Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to http://www.maxim-ic.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS (VIN = 12V, RT = 33kΩ, CVCC = 4.7µF, CIN = 1µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) PARAMETER GENERAL Input Voltage Range Quiescent Supply Current Standby Supply Current VCC REGULATOR Output Voltage VCC Regulator Dropout VCC Short-Circuit Output Current VCC Undervoltage Lockout VCC Undervoltage Lockout Hysteresis ERROR AMPLIFIER (FB_, COMP_) FB_ Input Voltage Set-Point FB_ Input Bias Current VFB_ IFB_ VFB_ = 0.6V 594 -250 600 606 +250 mV nA VCC 6V < VIN < 28V, ILOAD = 5mA VIN = 6V, 1mA < ILOAD < 100mA ILOAD = 100mA VIN = 5V VCC_UVLO VCC falling 150 3.6 5.00 5.2 0.07 250 3.8 430 4 5.50 V V mA V mV VIN IIN IIN_SBY 5.5 VIN = VCC VFB1 = VFB2 = 0.9V, no switching VEN1 = VEN2 = VSGND 4.5 4.5 0.21 28 5.5 6 0.35 V mA mA SYMBOL CONDITIONS MIN TYP MAX UNITS 2 _______________________________________________________________________________________ Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller ELECTRICAL CHARACTERISTICS (continued) (VIN = 12V, RT = 33kΩ, CVCC = 4.7µF, CIN = 1µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) PARAMETER FB_ to COMP_ Transconductance Amplifier Open-Loop Gain Amplifier Unity-Gain Bandwidth COMP_ Swing (High) COMP_ Swing (Low) COMP_ Source/Sink Current ENABLE (EN_) EN_ Input High EN_ Input Hysteresis EN_ Input Leakage Current OSCILLATOR Switching Frequency Switching Frequency Adjustment Range PWM Ramp Peak-to-Peak Amplitude PWM Ramp Valley Phase Shift Between Channels Minimum Controllable On-Time Maximum Duty Cycle OUTPUT DRIVERS DH_ On-Resistance DL_ On-Resistance DH_ Peak Current DL_ Peak Current DH_, DL_ Break-Before-Make Time (Dead Time) SOFT-START Soft-Start Duration Reference Voltage Steps 2048 64 Switching cycles Steps Low, sinking 100mA, VBST_ - VLX_ = 5V High, sourcing 100mA, VBST_ - VLX_ = 5V Low, sinking 100mA, VCC = 5.2V High, sourcing 100mA, VCC = 5.2V CLOAD = 10nF CLOAD = 10nF Sinking Sourcing Sinking Sourcing 1 1.2 0.75 1.4 3 2 3 2 15 Ω Ω A A ns 86 VRAMP VVALLEY From DH1 to DH2 rising edges fSW Each converter (Note 4) 460 200 1.42 0.72 180 60 87.5 100 500 540 1000 kHz kHz V V Degrees ns % VEN_H VEN_HYS ILEAK_EN_ -250 EN_ rising 1.15 1.20 150 +250 1.25 V mV nA ICOMP_ No load at COMP_ | ICOMP_ |, VCOMP_ = 1.5V 45 SYMBOL gm CONDITIONS ICOMP = ±40µA No load MIN 650 TYP 1200 80 10 2.4 0.6 80 120 MAX 1900 UNITS µS dB MHz V V µA MAX15023 _______________________________________________________________________________________ 3 Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller MAX15023 ELECTRICAL CHARACTERISTICS (continued) (VIN = 12V, RT = 33kΩ, CVCC = 4.7µF, CIN = 1µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) PARAMETER CURRENT LIMIT/HICCUP Cycle-by-Cycle, Low-Side, Source Peak Current-Limit Threshold Adjustment Range LIM_ Reference Current LIM_ Reference Current TC Number of Consecutive CurrentLimit Events to Hiccup Hiccup Timeout Cycle-by-Cycle, Low-Side, Sink Peak Current-Limit Sense Voltage BOOST Boost Switch Resistance POWER-GOOD OUTPUTS PGOOD_ Threshold PGOOD_ Output Leakage PGOOD_ Output Low Voltage THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis Temperature falling +150 20 °C °C VFB_ rising VFB_ falling ILEAK_PGD VPGOOD_ = 28V, VEN_ = 5V, VFB_ = 0.8V VPGOOD_L IPGOOD_ = 2mA, EN_ = SGND 88.5 85.5 92.5 89.5 96.5 93.5 1 0.4 % VFB(NOMINAL) µA V VIN = VCC = 5.2V, IBST_ = 10mA 4.5 8 Ω Out of soft-start ILIM_ Source peak limit = VLIM_/10 VLIM_ = 0.3V to 3V, TA = +25°C VLIM_ = 0.3V 30 45 50 2400 7 7936 VLIM_/ 20 300 55 mV µA ppm/°C Events Switching cycles V SYMBOL CONDITIONS MIN TYP MAX UNITS Note 3: All Electrical Characteristics limits over temperature are 100% tested at room temperature and guaranteed by design over the specified temperature range. Note 4: Select RT as RT (kΩ) = 24806 (fSW (kHz)) 1.0663 (24806 has a 1 unit). farad 4 _______________________________________________________________________________________ Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller Typical Operating Characteristics (Supply = IN = 12V, unless otherwise noted. See Typical Application Circuit of Figure 6.) MAX15023 EFFICIENCY vs. LOAD CURRENT 95 90 85 80 75 70 65 60 55 50 45 40 35 30 0.1 VOUT1 = 3.3V 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 0.1 MAX15023 toc01 EFFICIENCY vs. LOAD CURRENT VOUT1 = 3.3V MAX15023 toc02 OUTPUT VOLTAGE CHANGE vs. LOAD CURRENT 100.8 OUTPUT VOLTAGE CHANGE (%) 100.6 100.4 100.2 100.0 99.8 99.6 99.4 99.2 99.0 0 2 4 6 8 10 12 LOAD CURRENT (A) OUT1 MAX15023 toc03 101.0 EFFICIENCY (%) EFFICIENCY (%) VOUT1 = 1.2V VOUT1 = 1.2V VIN = 12V 1 10 100 VIN = VCC = 5V 1 10 100 LOAD CURRENT (A) LOAD CURRENT (A) VCC VOLTAGE vs. LOAD CURRENT MAX15023 toc04 VCC VOLTAGE vs. IN VOLTAGE MAX15023 toc05 VCC VOLTAGE vs. TEMPERATURE 5.45 5.40 SUPPLY VOLTAGE (V) 5.35 5.30 5.25 5.20 5.15 5.10 5.05 5.00 ILOAD = 5mA MAX15023 toc06 5.40 5.35 SUPPLY VOLTAGE (V) 5.30 5.50 5.35 5.20 VCC VOLTAGE (V) 5.05 4.90 4.75 4.60 4.45 4.30 ILOAD = 50mA ILOAD = 5mA 5.50 5.25 5.20 5.15 5.10 5.05 5.00 0 15 30 45 60 75 90 105 120 135 150 LOAD CURRENT (mA) 4.15 4.00 4 8 12 16 20 24 28 IN VOLTAGE (V) -40 -15 10 35 30 85 TEMPERATURE (°C) SWITCHING FREQUENCY vs. RT 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 10 20 30 40 50 RT (kΩ) 60 70 80 90 800 750 700 650 600 550 500 450 400 350 300 250 200 -40 MAX15023 toc07 SWITCHING FREQUENCY vs. TEMPERATURE MAX15023 toc08 IIN CURRENT vs. SWITCHING FREQUENCY VIN = 12V 180 IIN CURRENT (mA) 150 120 90 60 CDL = CDH = 1nF CDL = CDH = 10nF CDL = CDH = 4.7nF MAX15023 toc09 210 RT = 22.1kΩ SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) RT = 33.2kΩ RT = 66.5kΩ 30 0 CDL = CDH = 0nF -15 10 35 60 85 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) TEMPERATURE (°C) _______________________________________________________________________________________ 5 Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller MAX15023 Typical Operating Characteristics (continued) (Supply = IN = 12V, unless otherwise noted. See Typical Application Circuit of Figure 6.) IIN + IVCC CURRENT vs. SWITCHING FREQUENCY MAX15023 toc10 EN_ TURN-ON AND TURN-OFF THRESHOLD vs. TEMPERATURE EN_ TURN-ON AND TURN-OFF THRESHOLDS MAX15023 toc11 LIM_ CURRENT vs. TEMPERATURE 58 56 LIM_ CURRENT (µA) 54 52 50 48 46 44 42 40 38 ILIM2 ILIM1 MAX15023 toc12 210 VIN = VCC = 5V 180 IIN + IVCC CURRENT (mA) 150 120 90 60 30 0 CDL_ = CDH_ = 1nF CDL = CDH = 0nF CDL_ = CDH_ = 10nF 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 -40 -15 10 35 60 EN_ FALLING EN_ RISING 60 CDL_ = CDH_ = 4.7nF 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) 85 -40 -15 10 35 60 85 TEMPERATURE (°C) TEMPERATURE (°C) SHUTDOWN CURRENT vs. TEMPERATURE MAX15023 toc13 CURRENT-LIMIT THRESHOLD vs. RLIM 270 CURRENT-LIMIT THRESHOLD (mV) 240 210 180 150 120 90 60 30 SINK CURRENT LIMIT SOURCE CURRENT LIMIT MAX15023 toc14 230 225 SHUTDOWN CURRENT (µA) 220 215 210 205 200 -40 -15 10 35 60 300 0 85 5 10 15 20 25 30 35 40 45 50 55 60 RLIM (kΩ) TEMPERATURE (°C) LOAD TRANSIENT ON OUT1 MAX15023 toc15 LOAD TRANSIENT ON OUT2 MAX15023 toc16 VOUT1 (AC-COUPLED) 100mV/div VOUT2 (AC-COUPLED) 200mV/div VOUT1 (AC-COUPLED) 100mV/div VOUT2 (AC-COUPLED) 50mV/div IOUT1 5A/div IOUT2 2A/div 10µs/div 10µs/div 6 _______________________________________________________________________________________ Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller Typical Operating Characteristics (continued) (Supply = IN = 12V, unless otherwise noted. See Typical Application Circuit of Figure 6.) MAX15023 LINE-TRANSIENT RESPONSE MAX15023 toc17 STARTUP AND DISABLE FROM EN MAX15023 toc18 IOUT1 = 1.2A VIN 5V/div VEN1 5V/div VIN 10V/div VOUT1 (AC-COUPLED) 50mV/div VOUT1 500mV/div VOUT2 (AC-COUPLED) 100mV/div 2ms/div 2ms/div VPGOOD1 5V/div STARTUP AND DISABLE FROM EN MAX15023 toc19 STARTUP AND TURN-OFF FROM IN MAX15023 toc20 IOUT2 = 500mA VEN2 5V/div VIN 10V/div EN1 = EN2 = VCC IOUT1 = 1.2A VIN 10V/div VOUT1 1V/div VOUT2 2V/div VPGOOD2 5V/div 2ms/div 4ms/div VPGOOD1 5V/div STARTUP AND TURN-OFF FROM IN MAX15023 toc21 STARTUP INTO PREBIASED OUTPUT (0.5V PREBIASED) MAX15023 toc22 IOUT2 = 500mA VIN 10V/div VOUT1 500mV/div VOUT2 2V/div 0V VPGOOD2 5V/div 4ms/div 2ms/div _______________________________________________________________________________________ 7 Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller MAX15023 Typical Operating Characteristics (continued) (Supply = IN = 12V, unless otherwise noted. See Typical Application Circuit of Figure 6.) STARTUP INTO PREBIASED OUTPUT (1V PREBIASED) MAX15023 toc23 STARTUP INTO PREBIASED OUTPUT (1.5V PREBIASED) MAX15023 toc24 VOUT1 500mV/div VOUT1 500mV/div 0V 0V 2ms/div 2ms/div DH_ AND DL_ DISOVERLAP MAX15023 toc25 DH_ AND DL_ DISOVERLAP MAX15023 toc26 IOUT1 = 5A VDH1 10V/div IOUT1 = 5A VDH1 10V/div VDL1 5V/div VDL1 5V/div VLX1 10V/div VLX1 10V/div 20ns/div 20ns/div OUT-OF-PHASE SWITCHING FORMS MAX15023 toc27 SINK CURRENT-LIMIT WAVEFORMS MAX15023 toc28 1.5V PREBIASED VLX1 10V/div ILX1 5A/div VLX2 10V/div ILX2 2A/div IOUT1 = 5A IOUT2 = 2.5A 1µs/div 100µs/div VOUT1 200mV/div VLX1 20V/div ILX1 2A/div 8 _______________________________________________________________________________________ Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller MAX15023 Pin Description PIN 1 NAME FB1 FUNCTION Feedback Input for Regulator 1. Connect FB1 to a resistive divider between Output 1 and SGND to adjust the output voltage between 0.6V and (0.85 x input voltage (V)). See the Setting the Output Voltage section. Active-High Enable Input for Regulator 1. When the voltage at EN1 exceeds 1.2V (typ), the controller begins regulating OUT1. When the voltage falls below 1.05V (typ), the regulator is turned off. The EN1 input can be used for power sequencing and as a secondary UVLO. Connect EN1 to VCC for always-on applications. Active-High Enable Input for Regulator 2. When the voltage at EN2 exceeds 1.2V (typ), the controller begins regulating OUT2. When the voltage falls below 1.05V (typ), the regulator is turned off. The EN2 input can be used for power sequencing and as a secondary UVLO. Connect EN2 to VCC for always-on applications. Power-Good Output (Open Drain) for Channel 1. To obtain a logic signal, pull up PGOOD1 with an external resistor connected to a positive voltage below 28V. Low-Side Gate-Driver Output for Regulator 1. DL1 swings from VCC to PGND1. DL1 is low before VCC reaches the UVLO rising threshold voltage. Low-Side Gate-Driver Supply Return (Regulator 1). Connect to the source of the low-side MOSFET of Regulator 1. External Inductor Connection for Regulator 1. Connect LX1 to the switched side of the inductor. LX1 serves as the lower supply rail for the DH1 high-side gate driver and as sensing input of the synchronous MOSFET’s VDS drop (drain terminal). Boost Flying-Capacitor Connection for Regulator 1. Connect a ceramic capacitor with a minimum value of 100nF between BST1 and LX1. High-Side Gate-Driver Output for Regulator 1. DH1 swings from LX1 to BST1. DH1 is low before VCC reaches the UVLO rising threshold voltage. High-Side Gate-Driver Output for Regulator 2. DH2 swings from LX2 to BST2. DH2 is low before VCC reaches the UVLO rising threshold voltage. Boost Flying-Capacitor Connection for Regulator 2. Connect a ceramic capacitor with a minimum value of 100nF between BST2 and LX2. External Inductor Connection for Regulator 2. Connect LX2 to the switched side of the inductor. LX2 serves as the lower supply rail for the DH2 high-side gate driver and as sensing input of the synchronous MOSFET’s VDS drop (drain terminal). 2 EN1 3 EN2 4 5 6 PGOOD1 DL1 PGND1 7 LX1 8 9 10 11 BST1 DH1 DH2 BST2 12 LX2 _______________________________________________________________________________________ 9 Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller MAX15023 Pin Description (continued) PIN 13 14 15 NAME PGND2 DL2 PGOOD2 FUNCTION Low-Side Gate-Driver Supply Return (Regulator 2). Connect to the source of the low-side MOSFET of Regulator 2. Low-Side Gate-Driver Output for Regulator 2. DL2 swings from VCC to PGND2. DL2 is low before VCC reaches the UVLO rising threshold voltage. Power-Good Output (Open Drain) for Channel 2. To obtain a logic signal, pull up PGOOD2 with an external resistor connected to a positive voltage below 28V. Internal 5.2V Linear Regulator Output and the Device’s Core Supply. When using the internal regulator, bypass VCC to SGND with a 4.7µF minimum low-ESR ceramic capacitor. If VCC is connected to IN for 5V operation, then a 2.2µF ceramic capacitor is adequate for decoupling (see the Typical Application Circuits). Feedback Input for Regulator 2. Connect FB2 to a resistive divider between output 2 and SGND to adjust the output voltage between 0.6V and (0.85 x input voltage (V)). See the Setting the Output Voltage section. Compensation Pin for Regulator 2. See the Compensation section. Oscillator-Timing Resistor Input. Connect a resistor from RT to SGND to set the oscillator frequency from 200kHz to 1MHz (see the Setting the Switching Frequency section). Signal Ground. Connect SGND to the SGND plane. SGND also serves as sensing input of the synchronous MOSFET’s VDS drop (source terminals) for both channels. Internal VCC Regulator Input. Bypass IN to SGND with a 1µF minimum ceramic capacitor when the internal linear regulator (VCC) is used. When operating in the 5V ±10% range, connect IN to VCC. Current-Limit Adjustment for Regulator 2. Connect a resistor (RLIM2) from LIM2 to SGND to adjust the current-limit threshold (VITH2) from 30mV (RLIM2 = 6kΩ) to 300mV (RLIM2 = 60kΩ). See the Setting the Cycle-by-Cycle Low-Side Source Peak Current Limit section. Current-Limit Adjustment for Regulator 1. Connect a resistor (RLIM1) from LIM1 to SGND to adjust the current-limit threshold (VITH1) from 30mV (RLIM1 = 6kΩ) to 300mV (RLIM1 = 60kΩ). See the Setting the Cycle-by-Cycle Low-Side Source Peak Current Limit section. Compensation Pin for Regulator 1. See the Compensation section. Exposed Paddle. Connect EP to a large copper plane at SGND potential to improve thermal dissipation. Do not use as the main IC’s SGND ground connection. 16 VCC 17 18 19 20 21 FB2 COMP2 RT SGND IN 22 LIM2 23 24 — LIM1 COMP1 EP 10 ______________________________________________________________________________________ MAX15023 RT CK2 ENABLE1 FB1 VREF ENABLE1 HICCUP TIMEOUT CK2 PWM ENABLE2 RAMP BOOST DRIVER LIM2 ENABLE LOGIC HICCUP TIMEOUT DC-DC CONVERTER 2 PWM HICCUP CONTROL LOGIC VCC DL1 LIM1/20 LOW-SIDE DRIVER PGND1 FB1 ENABLE1 PGOOD1 SGND LIM1 0.925 x VREF LIM1/10 SOURCE CURRENT-LIMIT COMPARATOR PGOOD COMPARATOR VREF CK1 VREF CK1 RAMP GENERATOR PWM COMPARATOR BST1 GATEP ENABLE2 HICCUP SOFT-START/ STOP LOGIC AND HICCUP LOGIC DAC_VREF gM COMP1 OSCILLATOR CK1 COMP2 BST2 DH2 PGND2 DC-DC CONVERTER 1 VREF EN1 ENABLE1 COMPARATOR VREF EN2 ENABLE2 COMPARATOR VREF THERMAL SHUTDOWN SGND STARTUP BIAS DH1 HIGHSIDE DRIVER IN IN UVLO LX1 VREF INTERNAL VOLTAGE REGULATOR VCC VCC UVLO SINK CURRENT-LIMIT COMPARATOR VREF = 0.6V BANDGAP REFERENCE LIM2 LIM1 LIM CURRENT GENERATOR MAX15023 GEN PGOOD2 FB2 DL2 LX2 MAX15023 ______________________________________________________________________________________ Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller Functional Diagram 11 Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller MAX15023 Detailed Description The MAX15023 dual, synchronous, step-down controller operates from a 5.5V to 28V or 5V ±10% input voltage range and generates two independent output voltages. As long as the controller’s input bias voltage is within the specified range, the input power bus can also be lower than 4.5V and step-down conversion from a 3.3V rail is also possible. Both output voltages can be set from 0.6V to 85% of regulator’s input voltage. Each output can support loads of 12A or higher. The switching sequence of the regulators is interleaved with 180° out-of-phase operation, so that input voltage ripple and total RMS input ripple current are reduced. Enable inputs with precise turn-on/off threshold (±4.2%) allow accurate external UVLO settings. Powergood (PGOOD) open-drain outputs can be used for supply sequencing. The MAX15023’s capability to provide low output voltages (down to 0.6V) and high output current (in excess of 12A) makes it ideal for applications where a 5V or 12V bus is postregulated to deliver low voltages and high currents, such as in set-top boxes. The switching frequency is adjustable from 200kHz to 1MHz using an external resistor. The MAX15023’s adaptive synchronous rectification eliminates the need for external freewheeling Schottky diodes. The MAX15023 utilizes voltage-mode control and external compensation. The device also utilizes cycle-bycycle low-side source peak current limit for overcurrent protection, where the external low-side MOSFET’s onresistance is used as a current-sense element during the inductor freewheeling time, eliminating the need for a current-sense resistor. The current-limit threshold voltage is resistor adjustable independently on each regulator from 30mV to 300mV and is temperature compensated, so that the effects of the MOSFET’s R DS(ON) v ariation over temperature are reduced. Hiccup-mode current limit reduces average current and power dissipation during a prolonged short-circuit condition. The MAX15023 also features a proprietary adaptive internal digital soft-start and allows prebias startup without discharging the output. Adaptive digital softstart, by acting on the loop voltage reference, automatically prolongs the soft-start time, if the current-limit threshold is reached during the soft-start sequence. This increases the ability to smoothly bring up a large, unknown amount of output capacitance. Also, since soft-start is invoked during hiccup-mode short-circuit protection, the same voltage reference rollback algorithm achieves good control of the peak inductor current during steady short-circuit or overload conditions. An additional protection feature (cycle-by-cycle lowside sink peak current limit) prevents the regulators from sinking excessive amount of current if the prebias voltage exceeds the programmed steady-state regulation level, or if another voltage source is trying to force the output above that. This way, the synchronous rectifier MOSFET and the body diode of the high-side MOSFET do not experience dangerous levels of current stress while the regulator is sinking current from the output. Thermal shutdown protects the MAX15023 from excessive power dissipation. DC-DC PWM Controller The MAX15023 step-down controller uses a PWM voltage-mode control scheme (see the F unctional Diagram) for each channel. Control loop compensation is external for providing maximum flexibility in choosing the operating frequency and output LC filter components. An internal transconductance error amplifier produces an integrated error voltage at COMP_ that helps provide higher DC accuracy. The voltage at COMP_ sets the duty cycle using a PWM comparator and a ramp generator. On the rising edge of its internal clock, the high-side n-channel MOSFET of each regulator turns on and remains on until either the appropriate duty cycle or the maximum duty cycle is reached. During the high-side MOSFET’s on-time, the inductor current ramps up. During the second-half of the switching cycle, the high-side MOSFET turns off and the lowside n-channel MOSFET turns on. Now the inductor releases the stored energy as its current ramps down, providing current to the output. Under overload conditions, when the inductor current exceeds the selected cycle-by-cycle low-side source peak current-limit threshold (see the Current-Limit Circuit (LIM_) section), the high-side MOSFET does not turn on at the subsequent clock rising edge and the low-side MOSFET remains on to let the inductor current ramp down. Interleaved Out-of-Phase Operation The two independent regulators in the MAX15023 operate 180° out-of-phase to reduce input filtering requirements, reduce electromagnetic interference (EMI), and improve efficiency. This effectively lowers component cost and saves board space, making the MAX15023 ideal for cost-sensitive applications. 12 ______________________________________________________________________________________ Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller The internal oscillator frequency is divided down to obtain separated clock signals for each regulator. The phase difference of the two clock signals is 180°, so that the high-side MOSFETs turn on out-of-phase. The instantaneous input current peaks of both regulators no longer overlap, resulting in reduced RMS ripple current and input voltage ripple. As a result, this allows an input capacitor with a lower ripple-current rating to be used or allows the use of fewer or less expensive capacitors, as well as reduces EMI filtering and shielding requirements. on only when the DL_ gate driver has been turned off. Similarly, it prevents the low-side (DL_) from turning on until the DH_ gate driver has been turned off. The adaptive driver dead time allows operation without shoot-through with a wide range of MOSFETs, minimizing delays, and maintaining efficiency. There must be a lowresistance, low-inductance path from the DL_ and DH_ drivers to the MOSFET gates for the adaptive dead-time circuits to work properly. Otherwise, because of the stray impedance in the gate discharge path, the sense circuitry could interpret the MOSFET gates as off while the VGS of the MOSFET is still high. To minimize stray impedance, use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver). Synchronous rectification reduces conduction losses in the rectifier by replacing the normal low-side Schottky catch diode with a low-resistance MOSFET switch. The internal pulldown transistor that drives DL_ low is robust, with a 0.75Ω (typ) on-resistance. This low onresistance helps prevent DL_ from being pulled up during the fast rise time of the LX_ node, due to capacitive coupling from the drain to the gate of the low-side synchronous rectifier MOSFET. MAX15023 Internal 5.2V Linear Regulator The MAX15023’s internal functions and MOSFET drivers are designed to operate from a 5V ±10% supply voltage. If the available supply voltage exceeds 5.5V, a 5.2V internal low-dropout linear regulator is used to power internal functions and the MOSFET drivers at VCC. If an external 5V ±10% supply voltage is available, then IN and VCC can be tied to the 5V supply. The maximum regulator input voltage (VIN) is 28V. The regulator’s input (IN) must be bypassed to SGND with a 1µF ceramic capacitor when the regulator is used. Bypass the regulator’s output (V CC ) with a 4.7µF ceramic capacitor to SGND. The VCC dropout voltage is typically 70mV, so when VIN is greater than 5.5V, VCC is typically 5.2V. The MAX15023 also employs a UVLO circuit that disables both regulators when VCC falls below 3.8V (typ). The 430mV UVLO hysteresis prevents chattering on power-up/power-down. The internal V CC linear regulator can source up to 100mA to supply the IC, power the low-side gate drivers, recharge the external boost capacitors, and supply small external loads. The current available for external loads depends on the current consumed for the MOSFET gate drive. For example, when switched at 600kHz, a single MOSFET with 18nC total gate charge (at VGS = 5V) requires 18nC x 600kHz ≅ 11mA. Since four MOSFETs are driven and 6mA (max) is used by the internal control functions, the current available for external loads is: (100 – (4 x 11) – 6)mA ≅ 50mA High-Side Gate-Drive Supply (BST_) and Internal Boost Switches The high-side MOSFET is turned on by closing an internal switch between BST_ and DH_. This provides the necessary gate-to-source voltage to turn on the high-side MOSFET, an action that boosts the gate drive signal above VIN. The boost capacitor connected between BST_ and LX_ holds up the voltage across the gate driver during the high-side MOSFET on-time. The charge lost by the boost capacitor for delivering the gate charge is refreshed when the high-side MOSFET is turned off and LX_ node swings down to ground. When the corresponding LX_ node is low, an internal high-voltage switch connected between VCC and BST_ recharges the boost capacitor to the VCC voltage. The need for external boost diodes is negated. See the Boost FlyingCapacitor Selection section in the Design Procedure section to choose the right size of the boost capacitor. MOSFET Gate Drivers (DH_, DL_) The DH_ and DL_ drivers are optimized for driving large size n-channel power MOSFETs. Under normal operating conditions and after startup, the DL_ low-side drive waveform is always the complement of the DH_ high-side drive waveform (with controlled dead time to prevent cross-conduction or shoot-through). On each channel, an adaptive dead-time circuit monitors the DH and DL outputs and prevents the opposite-side MOSFET from turning on until the other MOSFET is fully off. Thus, the circuit allows the high-side driver to turn Enable Inputs (EN_), Adaptive Soft-Start and Soft-Stop The MAX15023 can be used to regulate two independent outputs. Each of the two outputs can be turned on and off independently of one another by controlling the enable input of each phase (EN1 and EN2). A logic-high on each enable pin turns on the corresponding channel. Then, the soft-start sequence is initiated by step-wise increasing the reference voltage of 13 ______________________________________________________________________________________ Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller the error amplifier. The duration of the soft-start ramp is 2048 switching cycles and the resolution is 1/64 of the steady-state regulation voltage. This allows a smooth increase of the output voltage. A logic-low on each EN_ initiates a soft-stop sequence by stepping down the reference voltage of the error amplifier. After the soft-stop sequence is completed, the MOSFET drivers are both turned off. See Figure 1 for more detail. Connect EN1 and EN2 to VCC for always-on operation. Owing to their accurate turn-on and turn–off thresholds, EN1 and EN2 can be used as a UVLO adjustment input and for power sequencing together with the PGOOD_ outputs. (See the Setting the Enable Input (EN_) section). The adaptive action in the soft-start becomes visible if the cycle-by-cycle, low-side, source peak current limit is reached during the soft-start ramping sequence. In this case, the rate-of-rise of the internal reference is decreased, so that the PWM controller tries to regulate to the inductor current around its limit value, rather than UVLO VCC A B C D E MAX15023 the output voltage. The soft-start time can be prolonged up to 4096 clock cycles (twice the normal soft-start duration). This implementation allows the soft-start time to be automatically adapted to the time necessary to keep the LX current below the limit while charging the output capacitor. Since soft-start is invoked by the hiccup-mode shortcircuit protection, also see the H iccup Mode Overcurrent Protection section for additional details. Power-Good Outputs (PGOOD_) The MAX15023 includes two power-good comparators to monitor the regulators’ output voltages and detect the power-good threshold, fixed at 92.5% of the nominal FB voltage. The PGOOD_ outputs are open-drain and should be pulled up with an external resistor to the supply voltage of the logic input they drive. This voltage should not exceed 28V. They can sink up to 2mA of current while low. F G H I EN_ VOUT_ 2048 CLK CYCLES DAC_VREF_ 2048 CLK CYCLES DH_ DL_ SYMBOL UVLO VCC EN_ VOUT_ DAC_VREF_ DH_ DL_ A DEFINITION Undervoltage threshold value is provided in the Electrical Characteristics table. Internal 5.2V linear regulator output. Active-high enable input. Regulator output voltage. Regulator internal soft-start and soft-stop signal. Regulator high-side gate-driver output. Regulator low-side gate-driver output. VCC rising while below the UVLO threshold. EN_ is low. SYMBOL B C D E F G H I DEFINITION VCC is higher than the UVLO threshold. EN_ is low. EN is pulled high. DH_ and DL_ start switching. Normal operation. VCC drops below UVLO. VCC goes above UVLO threshold. DH_ and DL_ start switching. Normal operation. EN_ is pulled low. VOUT_ enters soft-stop. EN_ is pulled high. DH_ and DL_ start switching. Normal operation. VCC drops below UVLO. Figure 1. MAX15023 Detailed Power-On/-Off Sequencing 14 ______________________________________________________________________________________ Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller Each PGOOD_ goes high (high impedance) when the corresponding regulator output increases above 92.5% of its nominal regulated voltage. Each PGOOD_ goes low when the corresponding regulator output voltage drops typically below 89.5% of its nominal regulated voltage. PGOOD_ can be used as power-on-reset or power sequencing for the two regulators. PGOOD_ asserts low during the hiccup timeout period. threshold during the low-side MOSFET on-time, the controller does not initiate a new PWM cycle and lets the inductor current decay in the next cycle. Since cycle-by-cycle, low-side, source peak current sensing is employed, the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are functions of the low-side MOSFET’s on-resistance, currentlimit threshold, inductor value, and input voltage. Cycle-by-cycle, low-side, sink peak current limit is also implemented by monitoring the voltage drop across the low-side MOSFET, but with opposite polarity (drain more positive than source). If this drop exceeds 1/20 the voltage at the corresponding LIM_ pin at any time during the low-side MOSFET on-time, the low-side MOSFET is turned off and the inductor current flows from the output through the high-side MOSFET back. If the cycle-by-cycle, low-side, sink peak current limit is activated, the DH_ and DL_ switching sequence is no longer complementary. MAX15023 Startup into a Prebiased Output When the controller starts into a prebiased output, the DH_/DL_ complementary switching sequence is inhibited until the PWM comparator commands its first PWM pulse. Until then, DH_ and DL_ are kept off so that the converter does not sink current from the output. The first PWM pulse occurs when the ramping reference voltage increases above the FB_ voltage or the internal soft-start time is over. Current-Limit Circuit (LIM_) The current-limit circuit employs a cycle-by-cycle lowside source peak and sink current-sensing algorithm that uses the on-resistance of the low-side MOSFET as a current-sensing element, so that costly sense resistors are not required. The current-limit circuit is also temperature compensated to track the MOSFET’s onresistance variation over temperature. The current limit is adjustable on each channel with an external resistor at LIM_ (see the T ypical Application Circuits ), and accommodates MOSFETs with a wide range of onresistance characteristics (see the Design Procedure section). The adjustment range is from 30mV to 300mV for the cycle-by-cycle, low-side, source peak current limit, corresponding to resistor values of 6kΩ to 60kΩ. The cycle-by-cycle, low-side, source peak current-limit threshold across the low-side MOSFET is precisely 1/10 the voltage seen at LIM_, while the cycle-by-cycle, lowside, sink peak current-limit threshold is 1/20 the voltage seen at LIM_. The MAX15023 uses SGND to sense the voltage of the source terminals of the low-side MOSFETs for both channels, and LX_ to sense the drain voltage of each low-side MOSFET. Carefully observe the PCB Layout Guidelines section to ensure that noise and systematic errors do not corrupt the current-sense signals seen by LX_ and SGND on each channel. Cycle-by-cycle, low-side, source peak current limit acts when the inductor current flows in the normal direction, and the drain (LX_) is more negative than source (sensed by SGND) during the low-side MOSFET ontime. If the magnitude of current-sense signal exceeds the cycle-by-cycle, low-side, source peak current-limit Hiccup Mode Overcurrent Protection Hiccup mode overcurrent protection reduces power dissipation during prolonged short-circuit or deep overload conditions. After the soft-start sequence has been completed, on each switching cycle where the cycle-by-cycle, low-side, source peak current-limit threshold is reached, a 3-bit counter is incremented. The counter is decremented on each switching cycle where the threshold is not reached, and stopped at zero (000). If the cycle-by-cycle, low-side, source peak currentlimit condition persists, the counter fills up reaching 111 (= 7 events). Then, the controller stops both DL_ and DH_ drivers and waits for 7936 switching cycles (hiccup timeout delay). After this delay, the controller initiates a new soft-start sequence. If cycle-by-cycle, low-side, source peak current-limit events occur during the soft-start time, turn-on cycles are still skipped to control the inductor current, but the fill-up of the 3-bit counter does not terminate the soft-start sequence. Rather, the soft-start ramp is slowed down or rolled back based on the cycle-by-cycle, low-side, source peak current-limit events occurrences, so that the PWM controller tries to regulate the inductor current around its limit value, rather than the output voltage. This proprietary technique prevents the duty cycle from saturating, and limits the on-time and thus, the peak inductor current is reached every time the high-side MOSFET is turned on. ______________________________________________________________________________________ 15 Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller MAX15023 In case of a nonideal short circuit applied at the output, the output voltage equals the output impedance times the limited inductor current during this phase. After reaching the maximum allowable limit of the soft-start duration (twice the normal soft-start time), the controller remains off for 7936 clock cycles before trying to soft-start again. The maximum voltage conversion ratio is limited by the maximum duty cycle (Dmax): VOUT × VDROP2 + (1 − Dmax ) × VDROP1 D < Dmax − max VIN VIN where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PCB resistances. VDROP2 is the sum of the resistances in the charging path, including high-side switch, inductor, and PCB resistances. In practice, the above condition should be met with adequate margin for good load-transient response. Undervoltage Lockout The MAX15023 has an internal undervoltage lockout (UVLO) circuit to monitor the voltage on V CC . The UVLO circuit prevents the MAX15023 from operating if the voltages for the MOSFET drivers or for the internal control functions are too low. The VCC falling threshold is 3.8V (typ), with 430mV hysteresis to prevent chattering on the rising/falling edge of the supply voltage. Before VCC reaches UVLO rising threshold voltage, DL_ and DH_ stay low to inhibit switching. Setting the Enable Input (EN_) Each controller has an enable input referenced to an analog voltage (1.2V). When the voltage exceeds 1.2V, the regulator is enabled. To set a specific turn-on threshold that can act as a secondary UVLO, a resistive divider circuit can be used (see Figure 2) Select R2 (EN_ to SGND resistor) to a value lower than 200kΩ. Calculate R1 (VMON to EN_ resistor) with the following equation: ⎡⎛ V ⎞⎤ R1 = R2 ⎢⎜ MON ⎟ − 1⎥ ⎢⎝ VEN _ H _ ⎠ ⎥ ⎣ ⎦ where VEN_H_ = 1.2V (typical). Thermal-Overload Protection Thermal-overload protection limits total power dissipation in the MAX15023. When the device’s die-junction temperature exceeds TJ = +150°C, an on-chip thermal sensor shuts down the device, forcing DL_ and DH_ low, allowing the IC to cool. The thermal sensor turns the device on again after the junction temperature cools by 20°C. During thermal shutdown, the regulators shut down, and soft-start is reset. Thermal-overload protection can be triggered by power dissipation in the LDO regulator, by excessive driving losses, or by both. Therefore, carefully evaluate the total power dissipation (see the Power Dissipation section) to avoid unwanted triggering of the thermal-overload protection in normal operation. Design Procedure Effective Input Voltage Range Although the MAX15023 controllers can operate from input supplies up to 28V and regulate down to 0.6V, the minimum voltage conversion ratio (VOUT/VIN) might be limited by the minimum controllable on-time. For proper fixed-frequency PWM operation, the voltage conversion ratio should obey the following condition: VOUT > tON(MIN) × fSW VIN where tON(MIN) is 100ns (max) and fSW is the switching frequency in Hertz. If the desired voltage conversion does not meet the above condition, then pulse skipping occurs to decrease the effective duty cycle. To avoid this, decrease the switching frequency or lower the input voltage VIN. MA15023 VMON R1 EN_ R2 Figure 2. Adjustable Enable Voltage 16 ______________________________________________________________________________________ Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller Setting the Output Voltage Set the MAX15023 output voltage on each channel by connecting a resistive divider from the output to FB_ to SGND (Figure 3). Select R2 (FB_ to SGND resistor) less than or equal to 16kΩ. Calculate R1 (OUT_ to FB_ resistor) with the following equation: ⎡⎛ VOUT _ ⎞ ⎤ R1 = R2 ⎢⎜ ⎟ − 1⎥ ⎢⎝ VFB _ ⎠ ⎥ ⎣ ⎦ where VFB_ = 0.6V (typ) (see the Electrical Characteristics table) and VOUT_ can range from 0.6V to (0.85 x VIN). Resistor R1 also plays a role in the design of the Type III compensation network. If a Type III compensation network is used, make sure to review the values of R1 and R 2 according to the T ype III Compensation Network (See Figure 5) section. Inductor Selection Three key inductor parameters must be specified for operation with the MAX15023: inductance value (L), inductor saturation current (ISAT), and DC resistance (RDC). To select inductance value, the ratio of inductor peak-to-peak AC current to DC average current (LIR) must be selected first. A good compromise between size and loss is a 30% peak-to-peak ripple current to average-current ratio (LIR = 0.3). The switching frequency, input voltage, output voltage, and selected LIR then determine the inductor value as follows: (V − V ) V L = OUT IN OUT VINfSWIOUTLIR where VIN, VOUT, and IOUT are typical values (so that efficiency is optimum for typical conditions). The switching frequency is set by RT (see the Setting the Switching Frequency section). The exact inductor value is not critical and can be adjusted in order to make trade-offs among size, cost, efficiency, and transient response requirements. Lower inductor values minimize size and cost, but also improve transient response and reduce efficiency due to higher peak currents. On the other hand, higher inductance increases efficiency by reducing the RMS current, but requires more output capacitance to meet load-transient specifications. Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. The inductor’s saturation rating (ISAT) must be high enough to ensure that saturation can occur only above the maximum current-limit value, given the tolerance of the lowside MOSFET’s on-resistance and of the LIM_ reference current (I LIM ). On the other hand, these tolerances should not prevent the converter from delivering the rated load current (ILOAD(MAX)). Combining these conditions, the inductor saturation current (ISAT) should be such that: ISAT > RDS(ON,MAX) ⎛ LIR ⎞ × 1+ ⎟ × ILOAD(MAX) RDS(ON,TYP) ⎜ ⎝ 2⎠ MAX15023 Setting the Switching Frequency The switching frequency, fSW, for each channel is set by a resistor (RT) connected from RT to SGND. The relationship between fSW and RT is: RT = 24806 (fSW )1.0663 where f SW is in kHz, R T i s in k Ω , and 24806 is in 1/farad. For example, a 600kHz switching frequency is set with R T = 27.05k Ω . Higher frequencies allow designs with lower inductor values and less output capacitance. Consequently, peak currents and I 2R losses are lower at higher switching frequencies, but core losses, gate-charge currents, and switching losses increase. OUT_ R1 FB_ R2 MA15023 Figure 3. Adjustable Output Voltage where RDS(ON,MAX) and RDS(ON,TYP) are the maximum and typical on-resistance of the low-side MOSFET. For a given inductor type and value, choose the LIR corresponding to the worst-case inductor tolerance. For LIR = 0.4, and a +25% on the low-side MOSFET’s RDS(ON,MAX), the inductor saturation current should be about 50% greater than the converter’s maximum load current. A variety of inductors from different manufacturers can be chosen to meet this requirement (for example, Coilcraft MSS1278 series). 17 ______________________________________________________________________________________ Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller MAX15023 Setting the Cycle-by-Cycle, Low-Side, Source Peak Current Limit The minimum current-limit threshold must be high enough to support the maximum expected load current with the worst-case low-side MOSFET on-resistance value since the low-side MOSFET’s on-resistance is used as the current-sense element. The inductor’s cycle-by-cycle, low-side, source peak current occurs at ILOAD(MAX) minus half the ripple current. The ripple current is maximum when the inductor value is at the lower limit of its specified tolerance. The minimum value of the current-limit threshold voltage (V ITH ) should be greater than the voltage on the low-side MOSFET during the ripple-current valley: ⎛ LIR ⎞ VITH > RDS(ON,MAX) × ILOAD(MAX) × ⎜1 − ⎟ ⎝ 2⎠ where R DS(ON) i s the on-resistance of the low-side MOSFET in ohms. Use the maximum value for RDS(ON) from the low-side MOSFET’s data sheet. To adjust the current-limit threshold, connect a resistor (RLIM_) from LIM_ to SGND. The relationship between the current-limit threshold (VITH_) and RLIM_ is: RLIM _ = 10 × VITH _ 50µA where: V D = OUT VIN All equations listed above are valid under the assumption that the input ports of both converters can be merged in the physical layout, so that only one input capacitor truly serves both converters. If this is not the case, additional low-ESR, low-ESL ceramic capacitors should be locally placed on each converter’s input port, connected between the drain of the high-side MOSFET and the source of the low-side MOSFET. where: ∆IL = and: I × D(1 − D) CIN = OUT ∆VQ × fSW (VIN − VOUT ) × VOUT VIN × fSW × L I RMS has a maximum value when the input voltage equals twice the output voltage (V IN = 2V OUT ), so IRMS(MAX) = ILOAD(MAX)/2. Choose an input capacitor that exhibits less than +10°C temperature rise at the RMS input current for optimal long-term reliability. The input voltage ripple is composed of ∆VQ (caused by the capacitor discharge) and ∆VESR (caused by the ESR of the capacitor). Use low-ESR ceramic capacitors with high ripple current capability at the input. Assume the contribution from the ESR and capacitor discharge are equal to 50%. Calculate the input capacitance and ESR required for a specified input voltage ripple using the following equations: ESRIN = ∆VESR ∆I IOUT + L 2 where RLIM_ is in kΩ and VITH_ is in mV. An RLIM_ resistance range of 6kΩ to 60kΩ corresponds to a current-limit threshold of 30mV to 300mV. When adjusting the current limit, use 1% tolerance resistors to minimize errors in the current-limit threshold setting. Input Capacitor The input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit’s switching. The two converters of the MAX15023 run 180° out-ofphase, thereby, effectively doubling the switching frequency at the input and lowering the input RMS current. The input ripple waveform would be unsymmetrical due to the difference in load current and duty cycle between converter 1 and converter 2. In fact, the worst-case input RMS current occurs when only one controller is operating. The converter delivering the highest output power (VOUT x IOUT) must be used in the formulas below: The input capacitor RMS current requirement (IRMS) is defined by the following equation: IRMS = ILOAD(MAX) 18 Output Capacitor The key selection parameters for the output capacitor are capacitance value, ESR, and voltage rating. These parameters affect the overall stability, output ripple voltage, and transient response. The output ripple has two components: variations in the charge stored in the output capacitor, and the voltage drop across the capacitor’s ESR caused by the current flowing into and out of the capacitor: ∆VRIPPLE ≅ ∆VESR + ∆VQ VOUT (VIN − VOUT ) VIN ______________________________________________________________________________________ Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller The output voltage ripple as a consequence of the ESR and the output capacitance is: ∆VESR = ∆IL × ESR ∆IL 8 × COUT × fSW (V − V ) × VOUT ∆IL = IN OUT VIN × fSW × L ∆VQ = where ∆IL is the peak-to-peak inductor current ripple (see the Inductor Selection section). These equations are suitable for initial capacitor selection, but final values should be verified by testing in a prototype or evaluation circuit. As a general rule, a smaller inductor ripple current results in less output ripple voltage. The output capacitor must be also checked against load-transient response requirements. The allowable deviation of the output voltage during fast load transients also determines the output capacitance, its ESR, and its equivalent series inductance (ESL). The output capacitor supplies the load current during a load step until the controller responds with a greater duty cycle. The response time (tRESPONSE) depends on the closedloop bandwidth of the converter (see the Compensation section). The resistive drop across the output capacitor’s ESR, the drop across the capacitor’s ESL (∆VESL), and the capacitor discharge causes a voltage droop during the load step. Use a combination of low-ESR tantalum/aluminum electrolytic or polymer and ceramic capacitors for better transient load and voltage ripple performance. Nonleaded capacitors and capacitors in parallel help reduce the ESL. Keep the maximum output voltage deviation below the tolerable limits of the load. Use the following equations to calculate the required ESR, ESL, and capacitance value during a load step: ESR = ∆VESR ISTEP ×t I COUT = STEP RESPONSE ∆VQ ∆VESL × t STEP ISTEP 1 tRESPONSE ≅ 3 × fO Compensation Each channel of the MAX15023 provides an internal transconductance amplifier with its inverting input and its output available to the user for external frequency compensation. The flexibility of external compensation for each converter offers wide selection of output filtering components, especially the output capacitor. For cost-sensitive applications, use low-ESR aluminum electrolytic capacitors; for component-size sensitive applications, use low-ESR tantalum, polymer, or ceramic capacitors at the output. The high switching frequency of the MAX15023 allows use of ceramic capacitors at the output. Choose the small-signal components for the error amplifier to achieve the desired closed-loop bandwidth and phase margin. To choose the appropriate compensation network type, the power-supply poles and zeros, the zero crossover frequency, and the type of the output capacitor must be determined. In a buck converter, the LC filter in the output stage introduces a pair of complex poles at the following frequency: fPO = 1 2π × L OUT × COUT MAX15023 The output capacitor and its ESR also introduce a zero at: fZO = 1 2π × ESR × COUT The loop-gain crossover frequency (fO, where the loop gain equals 1 (0dB)) should be set below 1/10 the switching frequency: f fO ≤ SW 10 Choosing a lower crossover frequency might also help in reducing the effects of noise pickup into the feedback loop, such as jittery duty cycle. In order to maintain a stable system, two stability criteria must be met: 1) The phase shift at the crossover frequency fO, must be less than 180°. In other words, the phase margin of the loop must be greater than zero. 2) The gain at the frequency where the phase shift is -180° (gain margin) must be less than 1. ESL = where ISTEP is the load step, tSTEP is the rise time of the load step, tRESPONSE is the response time of the controller, and fO is the closed-loop crossover frequency. ______________________________________________________________________________________ 19 Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller MAX15023 It is recommended to have a phase margin around +50° to +60° to maintain a robust loop stability and well-behaved transient response. If an electrolytic or large-ESR tantalum output capacitor is used, the capacitor ESR zero fZO typically occurs between the LC poles and the crossover frequency fO (fPO < fZO < fO). In this case, use a Type II (PI or proportional-integral) compensation network. If a ceramic or low-ESR tantalum output capacitor is used, the capacitor ESR zero typically occurs above the desired crossover frequency fO, that is fPO < fO < fZO. In this situation, choose a Type III (PID or proportional-integral-derivative) compensation network. The total loop gain as the product of the modulator gain and the error amplifier gain at fO should equal 1. So: GainMOD × GainEA = 1 Therefore: VIN ESR V × × FB × gm × RF = 1 VOSC (2π × fO × L OUT ) VOUT Solving for RF: RF = VOSC × (2π × fO × L OUT ) × VOUT VFB × VIN × gm × ESR Type II Compensation Network (See Figure 4) If fZO is lower than fO and close to fPO, the phase lead of the capacitor ESR zero almost cancels the phase loss of one of the complex poles of the LC filter around the crossover frequency. Therefore, a Type II compensation network with a midband zero and a high-frequency pole can be used to stabilize the loop. In Figure 4, RF and CF introduce a midband zero (fZ1). RF and CCF in the Type II compensation network also provide a high-frequency pole (fP1), which mitigates the effects of the output high-frequency ripple. To calculate the component values for Type II compensation network in Figure 4, follow the instruction below: 1) Calculate the gain of the modulator (GainMOD)— composed of the regulator’s pulse-width modulator, LC filter, feedback divider, and associated circuitry at crossover frequency: GainMOD = VIN ESR V × × FB VOSC (2π × fO × L OUT ) VOUT 2) Set a midband zero (fZ1) at 0.75 x fPO (to cancel one of the LC poles): fZ1 = Solving for CF: CF = 1 2π × RF × fPO × 0.75 1 = 0.75 × fPO 2π × RF × CF 3) Place a high-frequency pole at fP1 = 0.5 x fSW (to attenuate the ripple at the switching frequency, fSW) and calculate CCF using the following equation: 1 CCF = 1 π × RF × fSW − CF VOUT R1 where VIN is the regulator’s input voltage, VOSC is the amplitude of the ramp in the pulse-width modulator, VFB is the FB_ input voltage set-point (0.6V typically, see Electrical Characteristics table), and VOUT is the desired output voltage. The gain of the error amplifier (GainEA) in midband frequencies is: GainEA = gm × RF where gm is the transconductance of the error amplifier. R2 VREF gm RF CF COMP CCF Figure 4. Type II Compensation Network 20 ______________________________________________________________________________________ Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller Type III Compensation Network (See Figure 5) If the output capacitor used is a low-ESR tantalum or ceramic type, the ESR-induced zero frequency is usually above the targeted zero crossover frequency (fO). In this case, Type III compensation is recommended. Type III compensation provides three poles and two zeros at the following frequencies: 1 2π × RF × CF 1 fZ2 = 2π × CI × (R1 + RI) fZ1 = Two midband zeros (fZ1 and fZ2) cancel the pair of complex poles introduced by the LC filter: fP1 = 0 fP1 introduces a pole at zero frequency (integrator) for nulling DC output voltage errors: fP2 = 1 2π × RI × CI 2) The gain of the modulator (GainMOD)—composed of the regulator’s pulse-width modulator, LC filter, feedback divider, and associated circuitry at crossover frequency is: GainMOD = VIN 1 × VOSC (2π × fO )2 × L OUT × COUT MAX15023 The gain of the error amplifier (GainEA) in midband frequencies is: GainEA = 2π × fO × CI × RF The total loop gain as the product of the modulator gain and the error amplifier gain at fO should be equal to 1. So: GainMOD × GainEA = 1 Therefore: VIN 1 × × 2π × fO × CI × RF = 1 VOSC (2π × fO )2 × COUT × L OUT Depending on the location of the ESR zero (fZO), fP2 can be used to cancel it, or to provide additional attenuation of the high-frequency output ripple: 1 fP3 = C × CCF 2π × RF × F CF + CCF fP3 attenuates the high-frequency output ripple. The locations of the zeros and poles should be such that the phase margin peaks around fO. Ensure that RF>>2/gm (1/gm(MIN) = 1/600µS = 1.67kΩ) and the parallel resistance of R1, R2, and RI is greater than 1/gm. Otherwise, a 180° phase shift is introduced to the response and will make it unstable. The following procedure is recommended: 1) With RF ≥ 10kΩ, place the first zero (fZ1) at 0.5 x fPO: fZ1 = so: CF = 1 2π × RF × 0.5 × fPO 1 = 0.5 × fPO 2π × RF × CF Solving for CI: CI = VOSC × (2π × fO × L OUT × COUT ) VIN × RF 3) If f PO < f O < f ZO < f SW /2, the second pole (f P2 ) should be used to cancel fZO. This way, the Bode plot of the loop gain plot does not flatten out soon after the 0dB crossover, and maintains its -20dB/decade slope up to 1/2 the switching frequency. This is likely to occur if the output capacitor is a low-ESR tantalum or polymer. Then set: fP2 = fZO If a ceramic capacitor is used, then the capacitor ESR zero, fZO, is likely to be located even above 1/2 the switching frequency, that is, fPO < fO< fSW/2 < fZO. In this case, the frequency of the second pole (fP2) should be placed high enough in order not to significantly erode the phase margin at the crossover frequency. For example, it can be set at 5 x fO, so that its contribution to phase loss at the crossover frequency, fO, is only about 11°: fP2 = 5 x fO Once fP2 is known, calculate RI: RI = 1 2π × fP2 × CI 21 ______________________________________________________________________________________ Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller MAX15023 4) Place the second zero (fZ2) at 0.2 x fO or at fPO, whichever is lower and calculate R1 using the following equation: R1 = 1 − RI 2π × fZ2 × CI All four n-channel MOSFETs must be a logic-level type with guaranteed on-resistance specifications at VGS = 4.5V. For maximum efficiency, choose a high-side MOSFET (NH_) that has conduction losses equal to the switching losses at the typical input voltage. Ensure that the conduction losses at minimum input voltage do not exceed MOSFET package thermal limits, or violate the overall thermal budget. Also, ensure that the conduction losses plus switching losses at the maximum input voltage do not exceed package ratings or violate the overall thermal budget. Ensure that the MAX15023 DL_ gate drivers can drive a low-side MOSFET (NL_). In particular, check that the dV/dt caused by NH_ turning on does not pull up the NL_ gate through NL_’s drain-to-gate capacitance. This is the most frequent cause of cross-conduction problems. Gate-charge losses are dissipated by the driver and do not heat the MOSFET. Therefore, if the drive current is taken from the internal LDO regulator, the power dissipation due to drive losses must be checked. All MOSFETs must be selected so that their total gate charge is low enough; therefore, VCC can power all four drivers without overheating the IC: PDRIVE = VIN × QG _ TOTAL × fSW where QG_TOTAL is the sum of the gate charges of all four MOSFETs. 5) Place the third pole (fP3) at half the switching frequency and calculate CCF: CCF = (2π × 0.5 × fSW × RF × CF ) − 1 VFB × R1 VOUT − VFB CF 6) Calculate R2 as: R2 = MOSFET Selection The MAX15023’s step-down controller drives two external logic-level n-channel MOSFETs as the circuit switch elements. The key selection parameters to choose these MOSFETs include: • On-resistance (RDS(ON) ) • Maximum drain-to-source voltage (VDS(MAX) ) • Minimum threshold voltage (VTH(MIN) ) • Total gate charge (Qg) • Reverse transfer capacitance (CRSS) • Power dissipation Power Dissipation Device’s maximum power dissipation depends on the thermal resistance from the die to the ambient environment and the ambient temperature. The thermal resistance depends on the device package, PCB copper area, other thermal mass, and airflow. The power dissipated into the package (PT) depends on the supply configuration (see the Typical Application Circuits). It can be calculated using the following equation: PT = VIN x IIN For the circuits of Figures 7 and 8: PT = VCC x (IIN + IVCC) where VIN and VCC are the voltages at the respective pins, IIN is the current at the input of the internal LDO (IIN is practically zero for the circuits of Figures 7 and 8), IVCC is the current consumed by the internal core and drivers when the internal regulator is unused for 5V supply operation (IN = VCC). See the corresponding Typical Operating Characteristics for the typical curves of IIN and IVCC current consumption vs. operating frequency at various load capacitance values. VOUT CCF RF RI R1 CF CI gm R2 VREF COMP Figure 5. Type III Compensation Network 22 ______________________________________________________________________________________ Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller To estimate the temperature rise of the die, use the following equation: TJ = TA + (PT x θJA) where θJA is the junction-to-ambient thermal resistance of the package, PT is power dissipated in the device, and TA is the ambient temperature. The θJA is 36°C/W for the 24-pin TQFN package on multilayer boards, with the conditions specified by the respective JEDEC standards (JESD51-5, JESD51-7). If actual operating conditions significantly deviate from those described in the JEDEC standards, then an accurate estimation of the junction temperature requires a direct measurement of the case temperature (TC). Then, the junction temperature can be calculated using the following equation: TJ = TC + (PT x θJC) Use 3°C/W as θJC thermal resistance for the 24-pin TQFN package. The case-to-ambient thermal resistance (θCA) is dependent on how well the heat is transferred from the PCB to the ambient. Therefore, solder the exposed pad of the TQFN package to a large copper area to spread heat through the board surface, minimizing the case-to-ambient thermal resistance. Use large copper areas to keep the PCB temperature low. Applications Information PCB Layout Guidelines Make the controller ground connections as follows: create a small analog ground plane near the IC or use a dedicated internal plane. Connect this plane to SGND and use this plane for the ground connection for the IN bypass capacitor, compensation components, feedback dividers, RT resistor, and LIM_ resistors. If possible, place all power components on the top side of the board, and run the power stage currents (especially the one having large high-frequency components) using traces or copper fills on the top side only, without adding vias. On the top side, lay out a large PGND copper area for the output of channels 1 and 2, and connect the bottom terminals of the high-frequency input capacitors, output capacitors, and the source terminals of the low-side MOSFETs to that area. Then, make a star connection of the SGND plane to the top copper PGND area with few vias in the vicinity of the source terminal sensing. Do not connect PGND and SGND anywhere else. Refer to the MAX15023 Evaluation Kit data sheet for guidance. Keep the power traces and load connections short, especially at the ground terminals. This practice is essential for high efficiency and jitter-free operation. Use thick copper PCBs (2oz vs. 1oz) to enhance efficiency. Place the controller IC adjacent to the synchronous rectifier MOSFETs (NL_) and keep the connections for LX_, PGND_, DH_, and DL_ short and wide. Use multiple small vias to route these signals from the top to the bottom side. The gate current traces must be short and wide, measuring 50 mils to 100 mils wide if the low-side MOSFET is 1in from the controller IC. Connect each PGND trace from the IC close to the source terminal of the respective low-side MOSFET. Route high-speed switching nodes (BST_, LX_, DH_, and DL_) away from the sensitive analog areas (RT, COMP_, LIM_, and FB_). Group all SGND-referred and feedback components close to the IC. Keep the FB_ and compensation network nets as small as possible to prevent noise pickup. MAX15023 Boost Flying-Capacitor Selection The MAX15023 uses a bootstrap circuit to generate the necessary gate-to-source voltage to turn on the highside MOSFET. The selected n-channel high-side MOSFET determines the appropriate boost capacitance values (CBST_in Typical Application Circuits) according to the following equation: CBST _ = Qg ∆VBST _ where Qg is the total gate charge of the high-side MOSFET and ∆VBST_ is the voltage variation allowed on the high-side MOSFET driver after turn-on. Choose ∆VBST_ such that the available gate drive voltage is not significantly degraded (e.g., ∆ V BST_ = 100mV to 300mV) when determining C BST_. The boost flyingcapacitor should be a low-ESR ceramic capacitor. A minimum value of 100nF is recommended. ______________________________________________________________________________________ 23 Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller MAX15023 Typical Application Circuits VOUT1 12.1kΩ 16.2kΩ 3300pF 12.1kΩ 22pF 30.1kΩ VIN 9V TO 16V 1µF 1.62kΩ 390pF 19 RT 33kΩ 18 3300pF 20kΩ 33pF 10kΩ 22.1kΩ VOUT2 22 LIM2 45.3kΩ 1 24 23 21 IN FB1 COMP1 LIM1 20 SGND EN1 200kΩ 2 EN1 RT VCC 47kΩ MAX15023 15 3 PGOOD2 COMP2 EN2 FB2 17 PGOOD2 EN2 200kΩ VCC PGOOD1 VIN 10µF 25V 10µF 25V 47kΩ 4 PGOOD1 VCC 16 4.7µF VIN VCC Q1 FDS8880 CBST1 0.22µF 9 8 DH1 BST1 DL1 PGND1 PGND2 DL2 LX1 DH2 BST2 LX2 10 11 CBST2 0.22µF Q4 FDS6982AS-Q1 10µF 25V VOUT1 22µF 6.3V 1500µF 2.5V 0.8µH 2200pF 1.5Ω 3.3µH 2200pF 1.5Ω 22µF 6.3V 22µF 6.3V VOUT2 22µF 6.3V 7 Q3 FDS8880 Q2 FDS8880 56 13 14 12 Q5 FDS6982AS-Q2 DL1 Figure 6. Application Diagram (Operation from a Single-Supply Rail, VIN = 9V to 16V) 24 ______________________________________________________________________________________ Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller MAX15023 Typical Application Circuits (continued) VIN 4.5V TO 5.5V R8 C8 R5 C5 C6 R6 R10 R9 RT 22 LIM2 21 IN 20 SGND 19 RT C5 R4 COMP2 18 FB2 17 C2 VCC 16 R1 C4 C3 R2 R3 COMP1 1 EN1 RPU1 EN2 PGOOD1 VIN CIN1 3 4 5 6 2 FB1 EN1 EN2 LIM1 R7 24 23 PGOOD1 DL1 PGND1 BST1 MAX15023 RPU2 PGOOD2 15 DL2 14 VIN PGND2 13 BST2 PGOOD2 DH1 DH2 LX1 7 L1 VOUT1 COUT1 Q2 Q1 8 9 10 11 12 Q3 L2 VOUT2 Q4 COUT2 CBST1 CBST2 Figure 7. Application Diagram (Operation with VIN = VCC = 5V ±10%) ______________________________________________________________________________________ LX2 CIN2 25 Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller MAX15023 Typical Application Circuits (continued) VIN 3.3V R8 C8 VAUX 4.5V TO 5.5V R5 C5 C6 R6 R10 R9 RT 22 LIM2 21 IN 20 SGND 19 RT C5 R4 COMP2 18 FB2 17 C2 VCC 16 R1 C4 C3 R2 R3 1 EN1 RPU1 EN2 PGOOD1 CIN1 3 4 5 6 2 FB1 EN1 EN2 COMP1 LIM1 R7 24 23 PGOOD1 DL1 PGND1 BST1 MAX15023 RPU2 PGOOD2 15 DL2 14 PGND2 13 BST2 VIN 3.3V CIN2 PGOOD2 DH1 DH2 LX1 7 L1 VOUT1 COUT1 Q2 Q1 8 9 10 11 12 Q3 L2 VOUT2 Q4 COUT2 CBST1 CBST2 Figure 8. Application Diagram (Operation with Auxiliary 5V Supply and 3.3V Bus) 26 ______________________________________________________________________________________ LX2 Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller Chip Information PROCESS: BiCMOS MAX15023 Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 24 TQFN-EP PACKAGE CODE T2444+4 OUTLINE NO. 21-0139 LAND PATTERN NO. 90-0022 ______________________________________________________________________________________ 27 Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller MAX15023 Revision History REVISION NUMBER 0 1 2 REVISION DATE 7/08 2/09 3/11 Initial release Updated Electrical Characteristics, Current-Limit Circuit (LIM_), and Setting the Enable Input (EN_) sections. Added automatic part MAX5023ETG/V+ DESCRIPTION PAGES CHANGED — 4, 15, 16 1, 2, 13, 27 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.