MAX16021

19-4145; Rev 2; 10/08 Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating General Description The MAX16016/MAX16020/MAX16021 supervisory circuits monitor power supplies, provide battery-backup control, and chip-enable (CE) gating to write protect memory in microprocessor (µP)-based systems. These low-power devices improve system reliability by providing several supervisory functions in a small, single integrated solution. The MAX16016/MAX16020/MAX16021 perform four basic system functions: 1) Provide a µP reset output during VCC supply powerup, power-down, and brownout conditions. 2) Control VCC to battery-backup switching internally to maintain data or low-power operation for memories, real-time clocks (RTCs), and other digital logic when the main power is removed. 3) Provide memory write protection through internal chip-enable gating during brownout. 4) Provide a combination of additional supervisory functions listed in the Features section. The MAX16016/MAX16020/MAX16021 operate from a 1.53V to 5.5V supply voltage and offer fixed reset thresholds for monitoring 5V, 3.3V, 3V, 2.5V, and 1.8V systems. Each device is available with either a pushpull or open-drain reset output. The MAX16016/MAX16020/MAX16021 are available in small TDFN/TQFN packages and are fully specified for an operating temperature range of -40°C to +85°C. Features o System Monitoring for 5V, 3.3V, 3V, 2.5V, or 1.8V Power-Supply Voltages o 1.53V to 5.5V Operating Voltage Range o Low 1.2µA Supply Current (0.25µA in BatteryBackup Mode) o 145ms (min) Reset Timeout Period o Battery Freshness Seal o On-Board Gating of CE Signals, 1.5ns Propagation Delay (MAX16020/MAX16021) o Debounced Manual Reset Input o Watchdog Timer, 1.2s (typ) Timeout o Power-Fail Comparator and Low-Line Indicator for Monitoring Voltages Down to 0.6V o Battery-On, Battery-OK, and Battery Test Indicators o Small 10-Pin TDFN or 16-Pin TQFN Packages o UL®-Certified to Conform to IEC60950-1 MAX16016/MAX16020/MAX16021 Ordering Information PART MAX16016_TB_+T TEMP RANGE -40°C to +85°C PIN-PACKAGE 10 TDFN-EP* The first placeholder “_” designates all output options. Letter “L” indicates push-pull outputs and letter “P” indicates opendrain outputs. The last placeholder “_” designates the reset threshold (see Table 1). T = Tape and reel. +Denotes a lead-free/RoHS-compliant package. *EP = Exposed pad. Ordering Information continued at end of data sheet. Selector Guide located at end of data sheet. Applications Main/Backup Power for RTCs, CMOS Memories Industrial Control GPS Systems Set-Top Boxes Point-of-Sale Equipment Portable/Battery Equipment Pin Configurations CEOUT 14 TOP VIEW CEIN VCC 16 BATT MR PFI WDI 1 2 15 13 12 11 RESET GND PFO WDO + MAX16020 3 4 5 LL 6 BATT_TEST 7 BATTOK *EP 8 BATTON 10 9 *EP = EXPOSED PAD. TQFN UL is a registered trademark of Underwriters Laboratories, Inc. Pin Configurations continued at end of data sheet. 1 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. OUT Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating MAX16016/MAX16020/MAX16021 ABSOLUTE MAXIMUM RATINGS VCC, BATT, OUT, BATT_TEST to GND.....................-0.3V to +6V RESET, RESET, PFO, BATTOK, WDO, BATTON, BATT_TEST, LL, (all open-drain) to GND .....................-0.3V to +6V RESET, RESET, BATTOK, WDO, BATTON, LL (all push-pull) to GND......................-0.3V to (VOUT + 0.3V) WDI, PFI to GND.......................................-0.3V to (VOUT + 0.3V) CEIN, CEOUT to GND ..............................-0.3V to (VOUT + 0.3V) MR to GND .................................................-0.3V to (VCC + 0.3V) Input Current VCC Peak Current.................................................................1A VCC Continuous Current ...............................................250mA BATT Peak Current .......................................................500mA BATT Continuous Current ...............................................70mA Output Current OUT Short Circuit to GND Duration ....................................10s RESET, RESET, BATTON ....................................................20mA Continuous Power Dissipation (TA = +70°C) 10-Pin TDFN (derate 24.4mW/°C above +70°C) .......1951mW 16-Pin TQFN (derate 25mW/°C above +70°C) ..........2000mW Thermal Resistance (Note 1) For 10-Pin TDFN θJA ................................................................................41°C/W For 16-Pin TQFN θJA ................................................................................40°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = 1.53V to 5.5V, VBATT = 3V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER Operating Voltage Range (Note 3) SYMBOL VCC, VBATT CONDITIONS VCC or VBATT > VTH VCC = 1.62V Supply Current ICC VCC > VTH VCC = 2.8V VCC = 3.6V VCC = 5.5V Supply Current in Battery-Backup Mode VCC Switchover Threshold Voltage BATT Switchover Threshold Voltage BATT Standby Current BATT Freshness Leakage Current IBATT VCC = 0V VCC rising, VCC - VBATT VCC falling, VCC < VTH, VCC - VBATT VCC > VBATT + 0.2V VBATT = 5.5V VCC = 4.75V, IOUT = 150mA VCC to OUT On-Resistance RON VCC = 3.15V, IOUT = 65mA VCC = 2.35V, IOUT = 25mA VCC = 1.91V, IOUT = 10mA Output Voltage in Battery-Backup Mode VBATT = 4.5V, IOUT = 20mA VOUT VBATT = 2.5V, IOUT = 20mA VBATT - 0.1 V VBATT - 0.15 1.4 1.7 2.1 2.6 -10 MIN 0 1.2 1.9 2.3 3.4 0.25 0.1 x VCC 0 +10 20 4.5 4.5 5.0 5.5 Ω TYP MAX 5.5 2 3 3.5 5 0.5 µA V mV nA nA µA UNITS V 2 _______________________________________________________________________________________ Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating ELECTRICAL CHARACTERISTICS (continued) (VCC = 1.53V to 5.5V, VBATT = 3V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER Reset Threshold VCC Falling to Reset Delay Reset Timeout Period RESET Output Low Voltage RESET Output High Voltage (Push-Pull Output) RESET Output Leakage Current (Open-Drain Output) SYMBOL VTH tRD tRP VCC ≥ 3.3V, ISINK = 3.2mA, RESET asserted VOL VCC ≥ 1.6V, ISINK = 1mA, RESET asserted VCC ≥ 1.2V, ISINK = 100µA, RESET asserted VOH VCC = 1.1 x VTH, ISOURCE = 100µA, RESET deasserted VRESET = 5.5V, RESET deasserted VCC ≥ 3.3V, ISINK = 3.2mA, RESET deasserted RESET Output Low Voltage VOL VCC ≥ 1.8V, ISINK = 1.0mA, RESET deasserted VCC = 0.9 x VTH, ISOURCE = 100µA, RESET asserted VRESET = 5.5V, RESET asserted VOUT - 0.3 1 VOUT - 0.3 1 0.3 V 0.3 V µA VCC falling at 10V/ms 145 CONDITIONS MIN TYP (see Table 1) 20 215 285 0.3 0.3 0.3 V µA V MAX UNITS V µs ms RESET OUTPUT (RESET, RESET) MAX16016/MAX16020/MAX16021 RESET Output High Voltage (Push-Pull Output) RESET Output Leakage Current (Open-Drain Output) POWER-FAIL COMPARATOR PFI, Input Threshold PFI, Hysteresis PFI Input Current PFO Output Low Voltage PFO Output Voltage High (Push-Pull Output) PFO, Leakage Current (Open-Drain Output) PFO, Delay Time MANUAL RESET (MR) Input Low Voltage Input High Voltage Pullup Resistance Glitch Immunity MR to Reset Delay VOH VPFT VPFI-HYS VIN falling, 1.6V ≤ VCC ≤ 5.5V VCC = 5.5V VCC ≥ 1.6V, ISINK = 1mA, output asserted 0.572 -1 0.590 30 0.611 +1 0.3 0.3 V mV µA V VOL VCC ≥ 1.2V, ISINK = 100µA, output asserted VCC = 1.1 x VTH, ISOURCE = 100µA, output asserted VPFO = 5.5V, output deasserted VPFI + 100mV to VPFI - 100mV 20 VOUT - 0.3 VOH V 1 µA µs VIL VIH VCC = 3.3V 0.7 x VCC 20 30 100 120 0.3 x VCC V V kΩ ns ns _______________________________________________________________________________________ 3 Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating MAX16016/MAX16020/MAX16021 ELECTRICAL CHARACTERISTICS (continued) (VCC = 1.53V to 5.5V, VBATT = 3V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER WATCHDOG TIMER (WDI, WDO) Watchdog Timeout Period Minimum WDI Input Pulse Width WDI Input Low Voltage WDI Input High Voltage WDI Input Current (Note 7) WDO Output Low Voltage WDO Output High Voltage (Push-Pull Output) WDO Leakage Current (Open-Drain Output) BATTERY-ON INDICATOR (BATTON) Output Low Voltage BATTON Leakage Current BATTON Output High Voltage Output Short-Circuit Current (Note 4) CE GATING (CEIN, CEOUT) CEIN Leakage Current CEIN to CEOUT Resistance CEOUT Short-Circuit Current CEIN to CEOUT Propagation Delay Reset asserted, VCC = 0.9 x VTH or 0V Reset not asserted (Note 5) Reset asserted, CEOUT = 0, VCC = 0.9 x VTH 50Ω source, CLOAD = 50pF, VCC = 4.75V VCC = 5V, VCC ≥ VBATT, ISOURCE = 100µA Output High Voltage VCC = 0V, VBATT ≥ 2.2V ISOURCE = 1µA Reset to CEOUT Delay 0.8 x VCC VBATT 0.1 12 µs -1 8 0.75 1.5 +1 50 2 7 µA Ω mA ns VOH VOL ISINK = 3.2mA, VBATT = 2.1V VBATTON = 5.5V VCC = 0.9 x VTH, ISOURCE = 100µA, BATTON asserted Sink current, VCC = 5V VOUT - 0.3 60 0.3 1 V µA V mA VOL VOH tWD tWDI VIL VIH (Note 6) (Note 6) VWDI = 0 or 5.5V, time average VCC = 1.1 x VTH, ISINK = 1mA, WDO asserted VCC = 1.1 x VTH, ISOURCE = 100µA, WDO deasserted VWDO = 5.5V, WDO deasserted VOUT - 0.3 1 0.7 x VCC -1 +1 0.3 0.83 320 0.3 x VCC 1.235 1.64 s ns V V µA V V µA SYMBOL CONDITIONS MIN TYP MAX UNITS V 4 _______________________________________________________________________________________ Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating ELECTRICAL CHARACTERISTICS (continued) (VCC = 1.53V to 5.5V, VBATT = 3V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER LOW LINE (LL) Low Line to Reset Threshold Voltage VCC Falling to LL Delay LL Output Low Voltage LL Output High Voltage (PushPull Output) Output Leakage Current BATTOK Threshold BATTOK Output Voltage Low BATTOK Output High Voltage BATTOK Output Leakage Current BATT_TEST Output Low Voltage VOL VOH VOL VOH VCC falling VCC falling at 10V/ms VCC ≥ 1.6V, ISINK = 1mA, LL asserted VCC ≥ 1.2V, ISINK = 100µA, LL asserted VCC = 0.9 x VTH_LL, ISOURCE = 100µA, LL deasserted VLL = 5.5V, LL deasserted Inferred internally from BATT VCC = 1.1 x VTH, ISINK = 1mA, reset asserted VCC = 1.1 x VTH, ISOURCE = 100µA, BATTOK asserted VBATTOK = 5.5V, deasserted VCC = 1.1 x VTH, ISINK = 1mA VOUT 0.3 1 0.3 2.508 2.6 VOUT 0.3 1 2.673 0.3 (see Table 2) 20 0.3 0.3 mV µs V V µA V V V µA V SYMBOL CONDITIONS MIN TYP MAX UNITS MAX16016/MAX16020/MAX16021 BATTERY-OK INDICATOR (BATTOK, BATT_TEST) Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: All devices are 100% production tested at TA = +25°C and TA = +85°C. Limits to -40°C are guaranteed by design. VBATT can be 0V anytime, or VCC can go down to 0V if VBATT is active (except at startup). Use external current-limit resistor to limit current to 20mA (max). CEIN/CEOUT resistance is tested with VCC = 5V and VCEIN = 0V or 5V. WDI is internally serviced within the watchdog period if WDI is left unconnected. The WDI input current is specified as the average input current when the WDI input is driven high or low. The WDI input is designed for a three-stated output device with a 10µA maximum leakage current and capable of driving a maximum capacitive load of 200pF. The three-state device must be able to source and sink at least 200µA when active. Table 1a. Reset Threshold Ranges (MAX16016) SUFFIX L M T S R Z Y W V RESET THRESHOLD RANGES (V) MIN 4.508 4.264 2.991 2.845 2.549 2.243 2.117 1.603 1.514 TYP 4.63 4.38 3.08 2.93 2.63 2.32 2.19 1.67 1.575 MAX 4.906 4.635 3.239 3.080 2.755 2.425 2.288 1.733 1.639 Table 1b. Reset Threshold Ranges (MAX16020/MAX16021) SUFFIX L M T S R Z Y W V RESET THRESHOLD RANGES (V) MIN 4.520 4.275 3.010 2.862 2.568 2.260 2.133 1.616 1.528 TYP 4.684 4.428 3.100 2.946 2.640 2.323 2.192 1.661 1.571 MAX 4.852 4.585 3.190 3.034 2.716 2.390 2.255 1.710 1.618 _______________________________________________________________________________________ 5 Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating MAX16016/MAX16020/MAX16021 Table 2. Low-Line Threshold Ranges SUFFIX MIN L M T S R Z Y W V 4.627 4.378 3.075 2.922 2.620 2.309 2.180 1.653 1.563 LOW-LINE THRESHOLD RANGES (V) TYP 4.806 4.543 3.181 3.023 2.409 2.383 2.246 1.704 1.612 MAX 4.955 4.683 3.274 3.111 2.787 2.450 2.311 1.752 1.657 Typical Operating Characteristics (VCC = 5V, VBATT = 0V, TA = +25°C, unless otherwise noted.) VCC SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX16016 toc01 VCC SUPPLY CURRENT vs. TEMPERATURE (IOUT = 0) MAX16016 toc02 BATT SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX16020PTEZ+ VBATT = 2.5V MAX16016 toc03 5 MAX16020PTEZ+ 4 6 MAX16020PTEZ+ 5 4 0.7 0.6 0.5 IBATT (µA) ICC (µA) ICC (µA) 3 0.4 0.3 0.2 0.1 0 3 2 2 1 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40 -15 10 35 60 85 SUPPLY VOLTAGE (V) TEMPERATURE (°C) 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) BATTERY SUPPLY CURRENT vs. TEMPERATURE (VCC = 0V) MAX16016 toc04 BATT STANDBY CURRENT vs. TEMPERATURE MAX16016 toc05 VCC TO OUT ON-RESISTANCE vs. SUPPLY VOLTAGE MAX16020PTEZ+ VCC TO OUT ON-RESISTANCE (Ω) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 IOUT = 10mA IOUT = 25mA MAX16016 toc06 0.5 VBATT = +3.0V 0.4 5 4 BATT STANDBY CURRENT (nA) 3 2 1 0 -1 -2 -3 -4 VCC = 3.2V VBATT = 3.0V 4.0 IBATT (µA) 0.3 0.2 0.1 0 -40 -15 10 35 60 85 TEMPERATURE (°C) -5 -40 -15 10 35 60 85 TEMPERATURE (°C) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) 6 _______________________________________________________________________________________ Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating Typical Operating Characteristics (continued) (VCC = 5V, VBATT = 0V, TA = +25°C, unless otherwise noted.) VCC TO OUT ON-RESISTANCE vs. TEMPERATURE MAX16016 toc07 MAX16016/MAX16020/MAX16021 BATT TO OUT ON-RESISTANCE vs. TEMPERATURE (VCC = 0V, IOUT = 20mA) VBATT = 2.5V BATT TO OUT ON-RESISTANCE (Ω) 4 VBATT = 3V MAX16016 toc08 RESET OUTPUT VOLTAGE LOW vs. SINK CURRENT MAX16016 toc09 5 VCC = +3.15V, IOUT = 65mA VCC TO OUT ON-RESISTANCE (Ω) 4 5 0.5 RESET OUTPUT VOLTAGE LOW (V) 0.4 3 3 0.3 VCC = 3.3V 0.2 VCC = 5V 0.1 2 2 1 1 VBATT = 4.5V 0 -40 -15 10 35 60 85 TEMPERATURE (°C) 0 -40 -15 10 35 60 85 TEMPERATURE (°C) 0 0 2 4 6 8 10 12 14 16 18 20 SINK CURRENT (mA) NORMALIZED RESET THRESHOLD vs. TEMPERATURE MAX16016 toc10 MAXIMUM TRANSIENT DURATION vs. RESET THRESHOLD OVERDRIVE MAXIMUM TRANSIENT DURATION (µs) 450 400 350 300 250 200 150 100 50 0 0 50 100 150 200 250 300 350 400 RESET OCCURS ABOVE THE CURVE MAX16020PTEZ+ MAX16016 toc11 RESET TIMEOUT PERIOD vs. TEMPERATURE 208 RESET TIMEOUT PERIOD (ms) 206 204 202 200 198 196 194 192 190 -40 -15 10 35 60 85 MAX16020PTEZ+ MAX16016 toc12 1.005 1.004 NORMALIZED RESET THRESHOLD 1.003 1.002 1.001 1.000 0.999 0.998 0.997 0.996 0.996 -40 -15 10 35 60 500 210 85 TEMPERATURE (°C) RESET THRESHOLD OVERDRIVE (mV) TEMPERATURE (°C) WATCHDOG TIMEOUT PERIOD vs. TEMPERATURE MAX16016 toc13 PFI THRESHOLD vs. TEMPERATURE 0.64 0.63 PFI THRESHOLD (V) 0.62 0.61 0.60 0.59 0.58 0.57 0.56 0.55 VPFIVPFI+ MAX16016 toc14 NORMALIZED LL THRESHOLD vs. TEMPERATURE 1.004 NORMALIZED LL THRESHOLD 1.003 1.002 1.001 1.000 0.999 0.998 0.997 0.996 0.995 MAX16016 toc15 1.5 1.4 WATCHDOG TIMEOUT PERIOD (s) 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 -40 -15 10 35 60 0.65 1.005 85 -40 -15 10 35 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) _______________________________________________________________________________________ 7 Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating MAX16016/MAX16020/MAX16021 Typical Operating Characteristics (continued) (VCC = 5V, VBATT = 0V, TA = +25°C, unless otherwise noted.) WDO OUTPUT VOLTAGE LOW vs. SINK CURRENT MAX16016 toc16 VCC SUPPLY CURRENT vs. WDI FREQUENCY MAX16016 toc17 BATTON OUTPUT VOLTAGE LOW vs. SINK CURRENT MAX16016 toc18 0.5 WDO OUTPUT VOLTAGE LOW (V) 70 60 50 ICC (µA) 0.5 BATTON OUTPUT VOLTAGE LOW (V) 0.4 0.4 0.3 VCC = 3.3V 0.2 VCC = 5V 40 30 20 0.3 VCC = 3.3V 0.2 VCC = 5V 0.1 0.1 10 0 0 2 4 6 8 10 12 14 16 18 20 SINK CURRENT (mA) 0 0 10 100 1000 WDI FREQUENCY (kHz) 0 0 2 4 6 8 10 12 14 16 18 20 SINK CURRENT (mA) BATTOK OUTPUT VOLTAGE LOW vs. SINK CURRENT MAX16016 toc19 MR FALLING TO RESET DELAY MAX16016 toc20 0.5 BATTOK OUTPUT VOLTAGE LOW (V) 0.4 VCC = 3.3V 0.3 MR 5V/div 0.2 VCC = 5V RESET 5V/div 0.1 0 0 2 4 6 8 10 12 14 16 18 20 200ns/div SINK CURRENT (mA) RESET PROPAGATION DELAY vs. THRESHOLD OVERDRIVE MAX16020PTEZ+ 60 PROPAGATION DELAY (µs) 50 40 30 20 10 0 0 50 100 150 200 250 300 350 400 THRESHOLD OVERDRIVE (mV) MAX16016 toc21 CHIP-ENABLE GATING LOCKING OUT SIGNAL DURING RESET CONDITION MAX16016 toc22 70 RESET 5V/div CEIN 5V/div CEOUT 5V/div 10µs/div 8 _______________________________________________________________________________________ Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating Pin Description—MAX16016 PIN 1 2 NAME VCC BATT FUNCTION Supply Voltage Input. Bypass VCC to GND with a 0.1µF capacitor. Backup Battery Input. If VCC falls below its reset threshold, and if VBATT > VCC, OUT connects to BATT. If VCC rises above 1.01 x VBATT, OUT connects to VCC. Bypass BATT to GND with a 0.1µF capacitor. Active-Low Manual Reset Input. RESET asserts when MR is pulled low. RESET remains low for the duration of reset timeout period after MR transitions from low to high. Connect MR to OUT or leave unconnected if not used. MR is internally connected to OUT through a 30kΩ pullup resistor. Power-Fail Comparator Input. Connect PFI to a resistive divider to set the desired PFI threshold. The PFI input is referenced to an internal VPFT threshold. A VPFT-HYS internal hysteresis provides noise immunity. The power-fail comparator is powered from OUT. Watchdog Timer Input. If WDI remains high or low for longer than the watchdog timeout period (tWD), the internal watchdog timer runs out and a reset pulse is triggered for the reset timeout period or WDO goes low. The internal watchdog clears when reset asserts or whenever WDI sees a rising or falling edge. To disable the watchdog feature, leave WDI unconnected or three-state the driver connected to WDI. Active-High Battery-On Output. BATTON goes high when in battery-backup mode. Active-Low Power-Fail Comparator Output. PFO goes low when VPFI falls below the internal VPFT threshold and goes high when VPFI rises above VPFT + VPFT-HYS hysteresis. Ground Active-Low Reset Output. RESET asserts when VCC falls below the reset threshold or MR is pulled low. RESET remains low for the duration of the reset timeout period after VCC rises above the reset threshold and MR goes high. RESET also asserts low when the internal watchdog timer runs out. Switched Output. OUT is connected to VCC when the reset output is not asserted or when VCC is greater than VBATT. OUT connects to BATT when RESET is asserted and VBATT is greater than VCC. Bypass OUT to GND with a 0.1µF (min) capacitor. MAX16016/MAX16020/MAX16021 3 MR 4 PFI 5 WDI 6 7 8 9 BATTON PFO GND RESET 10 OUT _______________________________________________________________________________________ 9 Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating MAX16016/MAX16020/MAX16021 Pin Description—MAX16020/MAX16021 PIN MAX16020 MAX16021 1 1 NAME FUNCTION Backup Battery Input. If VCC falls below its reset threshold, and if VBATT > VCC, OUT connects to BATT. If VCC rises above 1.01 x VBATT, OUT connects to VCC. Bypass BATT to GND with a 0.1µF capacitor. Active-Low Manual Reset Input. RESET asserts when MR is pulled low. RESET remains low for the duration of reset timeout period after MR transitions from low to high. Connect MR to OUT or leave unconnected if not used. MR is internally connected to OUT through a 30kΩ pullup resistor. Power-Fail Comparator Input. Connect PFI to a resistive divider to set the desired PFI threshold. The PFI input is referenced to an internal VPFT threshold. VPFT-HYS internal hysteresis provides noise immunity. The power-fail comparator is powered from OUT. Watchdog Timer Input. If WDI remains high or low for longer than the watchdog timeout period (tWD), the internal watchdog timer runs out and asserts WDO. The internal watchdog clears when reset asserts or whenever WDI sees a rising or falling edge. To disable the watchdog feature, leave WDI unconnected or three-state the driver connected to WDI. Active-Low Low-Line Output. LL goes low when VCC falls to 2.5% above the reset threshold (Table 3). LL provides an early warning of VCC failure before reset asserts. Use this output to generate a nonmaskable interrupt (NMI) to initiate an orderly shutdown routine when VCC is falling. BATT 2 2 MR 3 3 PFI 4 4 WDI 5 5 LL 6 — Open-Drain Battery-Test Output. Pulses low for 1.3s every 24 hours during the battery BATT_TEST voltage test. If VBATT < 2.6V, BATTOK deasserts low. See Figure 6 for providing additional load during the battery test. Active-High Reset Output. RESET asserts when VCC falls below the reset threshold or when MR asserts and stays asserted for the reset timeout period after VCC rises above the reset threshold and MR deasserts. Battery-OK Output. BATTOK goes low when the battery voltage falls below the BATTOK threshold (BATTOK is low when in battery-backup mode). Active-High Battery-On Output. BATTON goes high when in battery-backup mode. — 6 RESET 7 8 7 8 BATTOK BATTON 10 ______________________________________________________________________________________ Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating Pin Description—MAX16020/MAX16021 (continued) PIN MAX16020 MAX16021 9 9 NAME FUNCTION Active-Low Watchdog Output. WDO asserts when WDI remains high or low longer than the watchdog timeout period. WDO returns high on the next WDI transition or when a reset is asserted. Active-Low Power-Fail Comparator Output. PFO goes low when VPFI falls below the internal 0.6V threshold and goes high when VPFT rises above VPFT + VPFT-HYS hysteresis. Ground Active-Low Reset Output. RESET asserts when VCC falls below the reset threshold or MR is pulled low. RESET remains low for the duration of the reset timeout period after VCC rises above the reset threshold and MR goes high. Switched Output. OUT is connected to VCC when the reset output is not asserted or when VCC is greater than VBATT. OUT connects to BATT when RESET is asserted and VBATT is greater than VCC. Bypass OUT to GND with a 0.1µF (min) capacitor. Active-Low Chip-Enable Output. CEOUT goes low only when CEIN is low and reset is not asserted. If CEIN is low when reset is asserted, CEOUT stays low for 12µs (typ) or until CEIN goes high, whichever occurs first. Chip-Enable Input. The input to CE gating circuitry. Connect to GND or OUT if not used. Supply Voltage Input. Bypass VCC to GND with a 0.1µF capacitor. Exposed Pad. Internally connected to GND. Connect EP to a large ground plane to aid heat dissipation. Do not use EP as the only ground connection for the device. MAX16016/MAX16020/MAX16021 WDO 10 11 12 10 11 12 PFO GND RESET 13 13 OUT 14 15 16 — 14 15 16 — CEOUT CEIN VCC EP ______________________________________________________________________________________ 11 Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating MAX16016/MAX16020/MAX16021 Functional Diagrams BATT BATTERY FRESHNESS SEAL OUT VCC BATTON MR RESET DELAY RESET OUT REF PFO PFI CLEAR WDI 100nA WATCHDOG TRANSITION DETECTOR WATCHDOG TIMER MAX16016 25kΩ GND 12 ______________________________________________________________________________________ Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating Functional Diagrams (continued) BATT MAX16016/MAX16020/MAX16021 BATTERY FRESHNESS SEAL BATTERY TEST CIRCUIT DISABLE BATT_TEST (MAX16020 ONLY) OUT VCC LATCH BATTOK MR RESET DELAY BATTON RESET (RESET) (MAX16021 ONLY) OUT REF PF1 OUT LL PFO CE OUTPUT CONTROL WDO WDI WATCHDOG TRANSITION DETECTOR CLEAR WATCHDOG TIMER 25kΩ CEIN 100nA CEOUT MAX16020 MAX16021 GND ______________________________________________________________________________________ 13 Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating MAX16016/MAX16020/MAX16021 Detailed Description The Typical Application Circuit shows a typical connection using the MAX16020. OUT powers the static random-access memory (SRAM). If VCC is greater than the reset threshold (VTH), or if VCC is lower than VTH, but higher than VBATT, VCC connects to OUT. If VCC is lower than VTH and VCC is less than VBATT, BATT connects to OUT (see the Functional Diagrams). In battery-backup mode, an internal MOSFET connects the backup battery to OUT. The on-resistance of the MOSFET is a function of backup-battery voltage and temperature. brownout. During normal operation, the CE gate is enabled and passes all CE transitions. When the reset output asserts, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. CEOUT is pulled up to OUT through an internal current source. The 1.5ns propagation delay from C E IN to CEOUT allows the devices to be used with most µPs and high-speed DSPs. During normal operation (reset not asserted), CEIN is connected to C E OUT through a low on-resistance transmission gate. If CEIN is high when a reset asserts, CEOUT remains high regardless of any subsequent transition on CEIN during the reset event. If CEIN is low when reset asserts, CEOUT is held low for 12µs to allow completion of the read/write operation. After the 12µs delay expires, CEOUT goes high and stays high regardless of any subsequent transitions on CEIN during the reset event. When CEOUT is disconnected from CEIN, CEOUT is actively pulled up to OUT. The propagation delay through the CE circuitry depends on both the source impedance of the drive to CEIN and the capacitive loading at CEOUT. Minimize the capacitive load at CEOUT to minimize the propagation delay, and use a low output-impedance driver. Backup-Battery Switchover In a brownout or power failure, it may be necessary to preserve the contents of the RAM. With a backup battery installed at BATT, the MAX16016/MAX16020/MAX16021 automatically switch the RAM to the backup power when VCC falls. The MAX16016/MAX16020/MAX16021 have a BATTON output that goes high when in battery-backup mode. These devices require two conditions before switching to battery-backup mode: 1) VCC must be below the reset threshold. 2) VCC must be below VBATT. Table 3 lists the status of the inputs and outputs in battery-backup mode. The device does not power up if the only voltage source is on BATT. OUT only powers up from VCC at startup. Low-Line Output (LL) The low-line comparator monitors VCC with a threshold voltage typically 2.5% higher than the reset threshold (see Table 2). LL asserts prior to a reset condition during a brownout condition. On power-up, LL deasserts after the reset output. LL can be used to provide a nonmaskable interrupt (NMI) to the µP when the voltage begins to fall to initiate an orderly software shutdown routine. CE Signal Gating The MAX16020/MAX16021 provide internal gating of CE signals to prevent erroneous data from being written to CMOS RAM in the event of a power failure or Table 3. Input and Output Status in Battery-Backup Mode PIN VCC OUT BATT RESET/RESET BATTON BATTOK CEIN CEOUT REF STATUS Disconnected from OUT Connected to BATT Connected to OUT. Current drawn from the battery is less than 0.55µA (at VBATT = 3V, excluding IOUT) when VCC = 0V. Asserted High state (push-pull), high impedance (open-drain) Low state Disconnected from CEOUT Pulled up to VOUT Not affected Manual Reset Input Many µP-based products require manual reset capability, allowing the operator, a test technician, or external logic circuitry to initiate a reset. For the MAX16016/MAX16020/ MAX16021, a logic-low on MR asserts RESET/RESET. RESET/RESET remains asserted while MR is low. When MR goes high RESET/RESET deasserts after a minimum of 145ms (tRP). MR has an internal 30kΩ pullup resistor to VCC. MR can be driven with TTL/CMOS logic levels or with open-drain/collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from a long cable or the device is used in a noisy environment, connect a 0.1µF capacitor from MR to GND to provide additional noise immunity. 14 ______________________________________________________________________________________ Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating Watchdog Timer Watchdog Input The watchdog monitors µP activity through the input WDI. If the µP becomes inactive, either the reset output is asserted in pulses (MAX16016) or the watchdog output goes low (MAX16020/MAX16021). To use the watchdog function, connect WDI to a bus line or µP I/O line. If WDI remains high or low for longer than the watchdog timeout period, the internal watchdog timer runs out and RESET asserts for the reset timeout period (MAX16016) or WDO goes low (MAX16020/MAX16021). The internal watchdog timer clears whenever the reset output asserts or the WDI sees a rising or falling edge within the watchdog timeout period. The WDI input is designed for a threestated output device with a 10µA maximum leakage current and the capability of driving a maximum capacitive load of 200pF. The three-state device must be able to source and sink at least 200µA when active. Disable the watchdog timer by leaving WDI unconnected or by three-stating the driver connected to WDI. The watchdog timer periodically attempts to pulse WDI to the opposite logic-level through a 25kΩ resistor for 40µs to determine whether WDI is either unconnected or latched to a logic state. The watchdog function is also disabled when in battery-backup mode. Watchdog Output WDO remains high if there is a transition or pulse at WDI during the watchdog-timeout period. WDO goes low if no transition occurs at WDI during the watchdog timeout period and remains low until the next transition at WDI or when a reset is asserted. Connect WDO to MR to generate a system reset on every watchdog fault. When a watchdog fault occurs in this mode, WDO goes low, which pulls MR low, causing a reset pulse to be issued. As soon as the reset output is asserted, the watchdog timer clears and WDO returns high. With WDO connected to M R , a continuous high or low on WDI causes 145ms (min) reset pulses to be issued every 1.235s. MAX16016/MAX16020/MAX16021 Battery Testing Function/BATTOK Indicator (MAX16020/MAX16021) The MAX16020/MAX16021 feature a battery testing function that works in conjunction with the BATTOK output. The battery voltage is tested for 1.235s after VCC is applied and once every 24 hours thereafter. During this test, an internal 100kΩ resistor is connected from BATT to ground and the battery is monitored to ensure that the battery voltage is above 2.6V. If the battery voltage is below 2.6V, the BATTOK output deasserts low to indicate a weak battery condition. The MAX16020 has a BATT_TEST output that pulses high during the battery voltage test. Connect a resistor and FET as shown in Figure 6 to provide an additional load during the battery test. In battery-backup mode, the battery testing function is disabled and BATTOK goes low. Battery Freshness Seal Mode The MAX16016/MAX16020/MAX16021 battery freshness seal disconnects the backup battery from internal circuitry and OUT until VCC is applied. This ensures the backup battery connected to BATT is fresh when the final product is used for the first time. The internal freshness seal latch prevents BATT from powering OUT until VCC has come up for the first time, setting the latch. When VCC subsequently turns off, BATT begins to power OUT. tWD tWD tWD WDI WDO Figure 1. Watchdog Timing (MAX16016/MAX16020) ______________________________________________________________________________________ 15 Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating MAX16016/MAX16020/MAX16021 To reenable the freshness seal: 1) Connect a battery to BATT. 2) Bring VCC to 0V. 3) Drive MR higher than VBATT + 1.2V for at least 3µs. 4) Pull OUT to 0V. Power-Fail Comparator The MAX16016/MAX16020/MAX16021 offer an undervoltage comparator that the output PFO goes low when the voltage at PFI falls below its VPFT threshold. Common uses for the power-fail comparator include monitoring the power supply (such as a battery) before any voltage regulation to provide an early power-fail warning, so software can conduct an orderly system shutdown. The power-fail comparators have a typical input hysteresis of VPFT_HYS and are powered from OUT, making them independent of the reset circuit. Connect unused PFI inputs to GND if not used. Reset Output A µP’s reset input starts the µP in a known state. The µP supervisory circuits assert a reset to prevent codeexecution errors during power-up, power-down, and brownout conditions. Reset output is guaranteed to be a logic-low or logic-high depending on the device chosen. RESET or RESET asserts when VCC is below the reset threshold and remains asserted for at least 145ms (tRP) after VCC rises above the reset threshold. RESET or RESET also asserts when MR is low. The MAX16016 watchdog function causes RESET to assert in pulses following a watchdog timeout. The reset output is available in both push-pull and open-drain configurations. Applications Information Monitoring an Additional Supply The MAX16016/MAX16020/MAX16021 µP supervisors can monitor either positive or negative supplies using a resistive voltage-divider to PFI. PFO can be used to generate an interrupt to the µP or to trigger a reset (Figures 2 and 3). To monitor a negative supply, connect the top of the resistive divider to VCC. Connect the bottom of the resistive divider to the negative voltage to be monitored. 5V V1 0.1µF R1 VCC PFI RESET PFI R2 RESET µP R2 PFO 0.1µF V2 R1 VCC MAX16016L MAX16020L MAX16021L MAX16016 MAX16020 MAX16021 V- PFO MR GND GND ADDITIONAL SUPPLY RESET VOLTAGE R1+R2 V2(RESET) = VPFT x R2 R2 — (5 - VPFT) R1 VTRIP = VPFT - VTRIP IS NEGATIVE +5V PFO 0 VTRIP 0V V- (—) Figure 2. Monitoring an Additional Supply by Connecting PFO to MR 16 Figure 3. Monitoring a Negative Supply ______________________________________________________________________________________ Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating Adding Hysteresis to PFI The power-fail comparators have a typical input hysteresis of VPFT-HYS. This is sufficient for most applications where a power-supply line is being monitored through an external voltage-divider (see the Monitoring an Additional Supply section). Figure 4 shows how to add hysteresis to the power-fail comparator. Select the ratio of R1 and R2 so that PFI sees VPFT when VIN falls to the desired trip point (VTRIP). Resistor R3 adds hysteresis. R3 is typically an order of magnitude greater than R1 or R2. R3 should be larger than 50kΩ to prevent it from loading down P FO . Capacitor C1 adds additional noise rejection. Battery-On Indicator (Push-Pull Version) BATTON goes high when in battery-backup mode. Use BATTON to indicate battery-switchover status or to supply base drive to an external pass transistor for higher current applications (Figure 5). MAX16016/MAX16020/MAX16021 Operation Without a Backup Power Source The MAX16016/MAX16020/MAX16021 provide a battery-backup function. If a backup power source is not used, connect BATT to GND and OUT to VCC. +5V VIN 0.1µF 0.1µF R1 PFI R2 VCC VCC 1µF VCC BATT C1* R3 PFO TO µP BATTON OUT CEOUT CE CMOS RAM MAX16016L MAX16020L MAX16021L MR MAX16020L CEIN ADDRESS DECODE A0–A15 µP GND *OPTIONAL RESET VTRIP = VPFT x PFT_HYS PFT RESET (R1+R2 —) R2 R1 R1 ) x (– + – + 1) V = (V + V R2 R3 V -V V V = R1 x (— + —) + V R2 R3 H PFT CC PFT L GND Figure 5. BATTON Driving an External Pass Transistor PFT WHERE VPFT IS THE POWER-FAIL THRESHOLD VOLTAGE +5V PFO 0 VL VTRIP VH VIN Figure 4. Adding Hysteresis to the Power-Fail Comparator ______________________________________________________________________________________ 17 Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating MAX16016/MAX16020/MAX16021 Replacing the Backup Battery When VCC is above VTH, the backup power source can be removed without danger of triggering a reset pulse. The device does not enter battery-backup mode when VCC stays above the reset threshold voltage. BATT VCC RLOAD Negative-Going VCC Transients The MAX16016/MAX16020/MAX16021 are relatively immune to short duration, negative going VCC transients. Resetting the µP when VCC experiences only small glitches is usually not desirable. A 0.1µF bypass capacitor mounted close to VCC provides additional transient immunity. MAX16020L BATT_TEST Figure 6. Adjustable BATT_TEST Load 18 ______________________________________________________________________________________ Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating Pin Configurations (continued) BATTON OUT VCC MAX16016/MAX16020/MAX16021 TOP VIEW RESET GND OUT PFO 16 BATT MR 1 2 + 15 14 CEOUT CEIN 13 12 11 RESET GND PFO WDO 10 9 8 7 6 MAX16016 *EP + 1 VCC 2 BATT 3 MR 4 PFI 5 WDI MAX16021 PFI WDI 3 4 5 LL 6 RESET 7 BATTOK *EP 8 BATTON 0.1µF RTC 10 9 TDFN TQFN Typical Application Circuit 3.3V SECONDARY DC VOLTAGE 0.1µF R1 PFI R2 VCC VCC RESET LL WDI WDO RST NMI I/O I/O A0–A15 µP MAX16020L OUT 0.1µF (MIN) PFO MR CEOUT RAM CE ADDRESS DECODE BATT GND 0.1µF CEIN ______________________________________________________________________________________ 19 Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating MAX16016/MAX16020/MAX16021 Selector Guide PART MAX16016LTB_ MAX16016PTB_ MAX16020LTE_ MAX16020PTE_ MAX16021LTE_ MAX16021PTE_ ALL LOGIC OUTPUTS (EXCEPT BATT_TEST) Push-pull Open-drain Push-pull Open-drain Push-pull Open-drain MR √ √ √ √ √ √ POWER-FAIL COMPARATOR √ √ √ √ √ √ WATCHDOG BATTON TIMER WDI WDI WDI/WDO WDI/WDO WDI/WDO WDI/WDO √ √ √ √ √ √ LOWBATTOK/ LINE BATT_TEST/ OUTPUT RESET — — √ √ √ √ — — BATTOK/ BATT_TEST BATTOK/ BATT_TEST BATTOK/ RESET BATTOK/ RESET CHIPENABLE — — √ √ √ √ Ordering Information (continued) PART MAX16020_TE_+T MAX16021_TE_+T TEMP RANGE -40°C to +85°C -40°C to +85°C PIN-PACKAGE 16 TQFN-EP* 16 TQFN-EP* Chip Information PROCESS: BiCMOS The first placeholder “_” designates all output options. Letter “L” indicates push-pull outputs and letter “P” indicates opendrain outputs. The last placeholder “_” designates the reset threshold (see Table 1). T = Tape and reel. +Denotes a lead-free/RoHS-compliant package. *EP = Exposed pad. Package Information For the latest package outline information, go to www.maxim-ic.com/packages. PACKAGE TYPE 10 TDFN 16 TQFN PACKAGE CODE T1033-1 T1644-4 DOCUMENT NO. 21-0137 21-0139 20 ______________________________________________________________________________________ Low-Power µP Supervisory Circuits with Battery-Backup Circuit and Chip-Enable Gating Revision History REVISION NUMBER 0 1 2 REVISION DATE 5/08 7/08 9/08 Initial release Released the MAX16016. Updated Ordering Information, Electrical Characteristics, Tables 1 and 2, Pin Description, and Detailed Description. Released the MAX16021. DESCRIPTION PAGES CHANGED — 1, 3, 4, 5, 9, 10, 12, 13, 15, 16, 19, 20 20 MAX16016/MAX16020/MAX16021 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.