MAX16026TE

19-0525; Rev 3; 1/07 KIT ATION EVALU LE B AVAILA Dual-/Triple-/Quad-Voltage, CapacitorAdjustable, Sequencing/Supervisory Circuits General Description The MAX16025–MAX16030 are dual-/triple-/quad-voltage monitors and sequencers that are offered in a small TQFN package. These devices offer enormous design flexibility as they allow fixed and adjustable thresholds to be selected through logic inputs and provide sequence timing through small external capacitors. These versatile devices are ideal for use in a wide variety of multivoltage applications. As the voltage at each monitored input exceeds its respective threshold, its corresponding output goes high after a propagation delay or a capacitor-set time delay. When a voltage falls below its threshold, its respective output goes low after a propagation delay. Each detector circuit also includes its own enable input, allowing the power-good outputs to be shut off independently. The independent output for each detector is available with push-pull or open-drain configuration with the open-drain version capable of supporting voltages up to 28V, thereby allowing them to interface to shutdown and enable inputs of various DC-DC regulators. Each detector can operate independently as four separate supervisory circuits or can be daisy-chained to provide controlled power-supply sequencing. The MAX16025–MAX16030 also include a reset function that deasserts only after all of the independently monitored voltages exceed their threshold. The reset timeout is internally fixed or can be adjusted externally. These devices are offered in a 4mm x 4mm TQFN package and are fully specified from -40°C to +125°C. Features o 2.2V to 28V Operating Voltage Range o Fixed Thresholds for 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V Systems o 1.5% Accurate Adjustable Threshold Monitors Voltages Down to 0.5V o 2.7% Accurate Fixed Thresholds Over Temperature o Fixed (140ms min)/Capacitor-Adjustable Delay Timing o Independent Open-Drain/Push-Pull Outputs o Enable Inputs for Each Monitored Voltage o 9 Logic-Selectable Threshold Options o Manual Reset and Tolerance Select (5%/10%) Inputs o Small, 4mm x 4mm TQFN Package o Fully Specified from -40°C to +125°C MAX16025–MAX16030 Ordering Information PART* MAX16025TE+ MAX16026TE+ MAX16027TP+ MAX16028TP+ MAX16029TG+ TEMP RANGE -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C PINPACKAGE 16 TQFN 16 TQFN 20 TQFN 20 TQFN 24 TQFN PKG CODE T1644-4 T1644-4 T2044-3 T2044-3 T2444-4 Applications Multivoltage Systems DC-DC Supplies Servers/Workstations Storage Systems Networking/Telecommunication Equipment MAX16030TG+ -40°C to +125°C 24 TQFN T2444-4 +Denotes lead-free package. *For tape and reel, add a “T” after the “+.” All tape and reel orders are available in 2.5k increments. Pin Configurations RESET OUT1 OUT3 18 MR 19 CRESET 20 17 16 15 14 13 12 11 10 TH1 EN4 EN3 EN2 EN1 GND TH0 9 8 7 1 VCC 2 IN1 3 IN2 4 IN3 5 IN4 6 TOL TOP VIEW Selector Guide PART MAX16025 MAX16026 MAX16027 MAX16028 MAX16029 MAX16030 MONITORED VOLTAGES 2 2 3 3 4 4 INDEPENDENT OUTPUTS 2 (Open-drain) 2 (Push-pull) 3 (Open-drain) 3 (Push-pull) 4 (Open-drain) 4 (Push-pull) RESET OUTPUT Open-drain Push-pull Open-drain Push-pull Open-drain Push-pull CDLY4 21 CDLY3 22 CDLY2 23 CDLY1 24 MAX16029 MAX16030 + THIN QFN (4mm x 4mm) Pin Configurations continued at end of data sheet. 1 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. OUT2 OUT4 Dual-/Triple-/Quad-Voltage, CapacitorAdjustable, Sequencing/Supervisory Circuits MAX16025–MAX16030 ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND.) VCC .........................................................................-0.3V to +30V EN1–EN4 ....................................................-0.3V to (VCC + 0.3V) OUT1–OUT4 (push-pull).............................-0.3V to (VCC + 0.3V) OUT1–OUT4 (open-drain) ......................................-0.3V to +30V RESET (push-pull) ......................................-0.3V to (VCC + 0.3V) RESET (open-drain) ..................................................-0.3V to 30V IN1–IN4.......................................................-0.3V to (VCC + 0.3V) MR, TOL, TH1, TH0 ....................................-0.3V to (VCC + 0.3V) CDLY1–CDLY4 .........................................................-0.3V to +6V CRESET ......................................................-0.3V to (VCC + 0.3V) Input/Output Current (all pins)..........................................±20mA Continuous Power Dissipation (TA = +70°C) 16-Pin TQFN (derate 25mW/°C above +70°C) ...........2000mW 20-Pin TQFN (derate 25.6mW/°C above +70°C) ........2051mW 24-Pin TQFN (derate 27.8mW/°C above +70°C) ........2222mW Operating Temperature Range .........................-40°C to +125°C Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = 2.2V to 28V, TA = -40°C to +125°C, unless otherwise specified. Typical values are at VCC = 3.3V and TA = +25°C.) (Note 1) PARAMETER SUPPLY Operating Voltage Range Undervoltage Lockout Undervoltage-Lockout Hysteresis VCC UVLO (Note 2) (Note 2) 2.2 1.8 1.9 50 VCC = 3.3V VCC = 12V VCC = 28V 2.970 2.805 2.250 2.125 1.620 1.530 1.350 1.275 1.080 1.020 0.492 0.463 500 -100 40 47 52 3.052 2.888 2.313 2.187 1.665 1.575 1.387 1.312 1.110 1.050 0.5 0.472 0.5 Fixed threshold IL Adjustable threshold only (VIN_ = 1V) 918 +100 75 75 80 3.135 2.970 2.375 2.250 1.710 1.620 1.425 1.350 1.140 1.080 0.508 0.481 V % kΩ nA V µA 28.0 2.0 V V mV SYMBOL CONDITIONS MIN TYP MAX UNITS UVLOHYST VCC falling All OUT_ and RESET at logic-high (IN_ current excluded) VCC Supply Current INPUTS (IN_) ICC 3.3V threshold, TOL = GND 3.3V threshold, TOL = VCC 2.5V threshold, TOL = GND 2.5V threshold, TOL = VCC IN_ Thresholds (IN_ Falling) VTH 1.8V threshold, TOL = GND 1.8V threshold, TOL = VCC 1.5V threshold, TOL = GND 1.5V threshold, TOL = VCC 1.2V threshold, TOL = GND 1.2V threshold, TOL = VCC Adjustable Threshold (IN_ Falling) IN_ Hysteresis (IN_ Rising) IN_ Input Resistance IN_ Input Current VTH VHYST TOL = GND TOL = VCC 2 _______________________________________________________________________________________ Dual-/Triple-/Quad-Voltage, CapacitorAdjustable, Sequencing/Supervisory Circuits ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.2V to 28V, TA = -40°C to +125°C, unless otherwise specified. Typical values are at VCC = 3.3V and TA = +25°C.) (Note 1) PARAMETER CRESET AND CDLY_ CRESET Threshold CRESET Charge Current CDLY_ Threshold CDLY_ Charge Current Input Low Voltage Input High Voltage TH1, TH0 Logic-Input Floating TOL, TH1, TH0 Logic-Input Current EN_ Input Leakage Current MR Internal Pullup Current OUTPUTS (OUT_, RESET) Output Low Voltage (Open-Drain or Push-Pull) Output High Voltage (Push-Pull) Output Leakage Current (OpenDrain) Reset Timeout Period TIMING IN_ to OUT_ Propagation Delay IN_ to RESET Propagation Delay MR Minimum Input Pulse Width EN_ or MR Glitch Rejection tOFF EN_ to OUT_ Delay MR to RESET Delay tON From device enabled to device disabled From device disabled to device enabled (CDLY_ open) MR falling tDELAY+ tDELAYIN_ rising, CDLY_ open IN_ falling, CDLY_ open 35 20 35 2 280 3 30 3 µs µs µs µs µs ns VCC ≥ 1.2V, ISINK = 90µA VOL VCC ≥ 2.25V, ISINK = 0.5mA VCC ≥ 4.5V, ISINK = 1mA VOH ILKG tRP VCC ≥ 3V, ISOURCE = 500µA VCC ≥ 4.5V, ISOURCE = 800µA Output not asserted low, VOUT = 28V CRESET = VCC, VCC = 3.3V CRESET open 140 190 0.030 0.8 x VCC 0.8 x VCC 1 260 0.3 0.3 0.35 V µA ms V VTOL, VTH1, VTH0 = GND or VCC VEN_ = VCC or GND VCC = 3.3V -1 -100 250 535 VTH-RESET ICH-RESET VTH-CDLY ICH-CDLY VIL VIH 1.4 0.6 +1 +100 820 CRESET rising, VCC = 3.3V VCC = 3.3V CDLY_ rising, VCC = 3.3V VCC = 3.3V 0.465 380 0.95 200 0.5 500 1 250 0.535 620 1.05 300 0.4 V nA V nA V V V µA nA nA SYMBOL CONDITIONS MIN TYP MAX UNITS MAX16025–MAX16030 DIGITAL LOGIC INPUTS (EN_, MR, TOL, TH1, TH0) tRST-DELAY IN_ falling (Note 3) Note 1: Devices are production tested at TA = +25°C. Limits over temperature are guaranteed by design. Note 2: Operating below the UVLO causes all outputs to go low. The outputs are guaranteed to be in the correct state for VCC down to 1.2V. Note 3: In order to guarantee an assertion, the minimum input pulse width must be greater than 2µs. _______________________________________________________________________________________ 3 Dual-/Triple-/Quad-Voltage, CapacitorAdjustable, Sequencing/Supervisory Circuits MAX16025–MAX16030 Typical Operating Characteristics (VCC = 3.3V, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX16025 toc01 SUPPLY CURRENT vs. TEMPERATURE VCC = 28V 55 SUPPLY CURRENT (μA) 50 45 VCC = 12V 40 35 30 VCC = 3.3V MAX16026 MAX16025 toc02 NORMALIZED ADJUSTABLE THRESHOLD vs. TEMPERATURE 1.003 1.002 1.001 1.000 0.999 0.998 0.997 0.996 0.995 0.994 0.993 0.992 0.991 0.990 TOL = VCC MAX16025 toc03 60 MAX16026 55 SUPPLY CURRENT (μA) 50 45 40 35 30 2 6 10 14 18 22 26 60 NORMALIZED THRESHOLD TOL = GND ADJUSTABLE THRESHOLD -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 30 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) SUPPLY VOLTAGE (V) NORMALIZED ADJUSTABLE THRESHOLD vs. TEMPERATURE 1.003 1.002 1.001 1.000 0.999 0.998 0.997 0.996 0.995 0.994 0.993 0.992 0.991 0.990 TOL = VCC MAX16025 toc04 OUT_ DELAY vs. CCDLY_ 4500 4000 OUT_ DELAY (ms) 3500 3000 2500 2000 1500 1000 MAX16025 toc05 RESET TIMEOUT PERIOD vs. CCRESET MAX16025 toc06 5000 RESET TIMEOUT PERIOD (ms) 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 NORMALIZED THRESHOLD TOL = GND 3.3V THRESHOLD -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 500 0 0 100 200 300 400 500 600 700 800 900 1000 CCDLY_ (nF) 0 100 200 300 400 500 600 700 800 900 1000 CCRESET (nF) FIXED RESET TIMEOUT PERIOD vs. TEMPERATURE 194 193 192 CRESET = VCC MAX16025 toc07 OUT_ LOW VOLTAGE vs. SINK CURRENT MAX16025 toc08 OUT_ HIGH VOLTAGE vs. SOURCE CURRENT MAX16025 toc09 195 FIXED RESET TIMEOUT PERIOD (ms) 1.0 3.5 3.0 2.5 0.8 VOUT_ (V) 191 190 189 188 187 186 185 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) VOUT_ (V) 0.6 2.0 1.5 1.0 0.4 0.2 0.5 PUSH-PULL VERSIONS 0 0 1 2 3 4 5 SINK CURRENT (mA) 6 7 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 SOURCE CURRENT (mA) 4 _______________________________________________________________________________________ Dual-/Triple-/Quad-Voltage, CapacitorAdjustable, Sequencing/Supervisory Circuits Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25°C, unless otherwise noted.) MAX16025–MAX16030 RESET OUTPUT LOW VOLTAGE vs. SINK CURRENT MAX16025 toc10 RESET OUTPUT HIGH VOLTAGE vs. SOURCE CURRENT MAX16025 toc11 ENABLE TURN-OFF MAX16025 toc12 1.0 0.9 RESET OUTPUT LOW VOLTAGE (V) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 SINK CURRENT (mA) 3.5 RESET OUTPUT HIGH VOLTAGE (V) 3.0 2.5 2.0 1.5 1.0 0.5 PUSH-PULL VERSIONS 0 0 CRESET = VCC CDLY_ = OPEN EN_ OUT_ RESET 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 SOURCE CURRENT (mA) 4μs/div ENABLE TURN-ON MAX16025 toc13 RESET TIMEOUT DELAY MAX16025 toc14 MR FALLING vs. RESET MAX16025 toc15 CRESET = VCC CDLY_ = OPEN EN_ CRESET = VCC CDLY_ = OPEN IN_ CRESET = VCC CDLY_ = OPEN MR OUT_ OUT_ RESET RESET RESET 40ms/div 100ms/div 4μs/div MR RISING vs. RESET MAX16025 toc16 MAXIMUM TRANSIENT DURATION vs. THRESHOLD OVERDRIVE MAXIMUM TRANSIENT DURATION (μs) 90 80 70 60 50 40 30 20 10 0 1 10 100 1000 OUTPUT ASSERTED ABOVE THIS LINE MAX16025 toc17 100 CRESET = VCC CDLY_ = OPEN MR RESET 40ms/div THRESHOLD OVERDRIVE (mV) _______________________________________________________________________________________ 5 Dual-/Triple-/Quad-Voltage, CapacitorAdjustable, Sequencing/Supervisory Circuits MAX16025–MAX16030 Pin Description PIN MAX16025/ MAX16026 1 MAX16027/ MAX16029/ MAX16028 MAX16030 1 1 NAME FUNCTION Supply Voltage Input. Connect a 2.2V to 28V supply voltage to power the device. All outputs are low when VCC is below the UVLO. For noisy systems, bypass VCC to GND with a 0.1µF capacitor. Monitored Input 1. When the voltage at IN1 exceeds its threshold, OUT1 goes high after the capacitor-adjustable delay period. When the voltage at IN1 falls below its threshold, OUT1 goes low after a propagation delay. Monitored Input 2. When the voltage at IN2 exceeds its threshold, OUT2 goes high after the capacitor-adjustable delay period. When the voltage at IN2 falls below its threshold, OUT2 goes low after a propagation delay. Monitored Input 3. When the voltage at IN3 exceeds its threshold, OUT3 goes high after the capacitor-adjustable delay period. When the voltage at IN3 falls below its threshold, OUT3 goes low after a propagation delay. Monitored Input 4. When the voltage at IN4 exceeds its threshold, OUT4 goes high after the capacitor-adjustable delay period. When the voltage at IN4 falls below its threshold, OUT4 goes low after a propagation delay. Threshold Tolerance Input. Connect TOL to GND to select thresholds 5% below nominal. Connect TOL to VCC to select thresholds 10% below nominal. Ground Active-High Logic-Enable Input 1. Driving EN1 low causes OUT1 to go low regardless of the input voltage. Drive EN1 high to enable the monitoring comparator. Active-High Logic-Enable Input 2. Driving EN2 low causes OUT2 to go low regardless of the input voltage. Drive EN2 high to enable the monitoring comparator. Active-High Logic-Enable Input 3. Driving EN3 low causes OUT3 to go low regardless of the input voltage. Drive EN3 high to enable the monitoring comparator. Active-High Logic-Enable Input 4. Driving EN4 low causes OUT4 to go low regardless of the input voltage. Drive EN4 high to enable the monitoring comparator. Threshold Select Input 1. Connect TH1 to VCC or GND, or leave it open to select the input-voltage threshold option in conjunction with TH0 (see Table 2). Threshold Select Input 0. Connect TH0 to VCC or GND, or leave it open to select the input-voltage threshold option in conjunction with TH1 (see Table 2). Output 4. When the voltage at IN4 is below its threshold or EN4 goes low, OUT4 goes low. Output 3. When the voltage at IN3 is below its threshold or EN3 goes low, OUT3 goes low. Output 2. When the voltage at IN2 is below its threshold or EN2 goes low, OUT2 goes low. VCC 2 2 2 IN1 3 3 3 IN2 — 4 4 IN3 — — 5 IN4 4 5 6 5 6 7 6 7 8 TOL GND EN1 7 8 9 EN2 — 9 10 EN3 — — 11 EN4 8 9 — — 10 10 11 — 12 13 12 13 14 15 16 TH1 TH0 OUT4 OUT3 OUT2 6 _______________________________________________________________________________________ Dual-/Triple-/Quad-Voltage, CapacitorAdjustable, Sequencing/Supervisory Circuits Pin Description (continued) PIN MAX16025/ MAX16026 11 MAX16027/ MAX16029/ MAX16028 MAX16030 14 17 NAME FUNCTION Output 1. When the voltage at IN1 is below its threshold or EN1 goes low, OUT1 goes low. Active-Low Reset Output. RESET asserts low when any of the monitored voltages (IN_) falls below its respective threshold, any EN_ goes low, or MR is asserted. RESET remains asserted for the reset timeout period after all of the monitored voltages exceed their respective threshold, all EN_ are high, all OUT_ are high, and MR is deasserted. MAX16025–MAX16030 OUT1 12 15 18 RESET 13 16 19 14 17 20 — — 21 — 18 22 Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset timeout period after MR is deasserted (as long as all OUT_ are high). Capacitor-Adjustable Reset Delay Input. Connect an external capacitor from CRESET to GND to set the reset timeout period or connect to VCC for the CRESET default 140ms minimum reset timeout period. Leave CRESET open for internal propagation delay. Capacitor-Adjustable Delay Input 4. Connect an external capacitor from CDLY4 CDLY4 to GND to set the IN4 to OUT4 (and EN4 to OUT4) delay period. Leave CDLY4 open for internal propagation delay. Capacitor-Adjustable Delay Input 3. Connect an external capacitor from CDLY3 CDLY3 to GND to set the IN3 to OUT3 (and EN3 to OUT3) delay period. Leave CDLY3 open for internal propagation delay. MR CDLY2 Capacitor-Adjustable Delay Input 2. Connect an external capacitor from CDLY2 to GND to set the IN2 to OUT2 (and EN2 to OUT2) delay period. Leave CDLY2 open for internal propagation delay. Capacitor-Adjustable Delay Input 1. Connect an external capacitor from CDLY1 to GND to set the IN1 to OUT1 (and EN1 to OUT1) delay period. Leave CDLY1 open for internal propagation delay. Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane. 15 19 23 16 20 24 CDLY1 — — — EP Table 1. Output State* EN_ Low High Low IN_ VIN_ < VTH VIN_ < VTH VIN_ > VTH Low Low Low OUT_ = high (MAX16026/MAX16028/ MAX16030) High VIN_ > VTH OUT_ = high impedance (MAX16025/MAX16027/ MAX16029) OUT_ Table 2. Input-Voltage Threshold Selector TH1/TH0 LOGIC Low/Low Low/High Low/Open High/Low High/High High/Open Open/Low Open/High Open/Open IN3 IN4 IN1 (ALL IN2 (ALL (MAX16027/ (MAX16029/ VERSIONS) VERSIONS) MAX16028) MAX16030) (V) (V) (V) (V) 3.3 3.3 3.3 3.3 2.5 3.3 3.3 2.5 Adj 2.5 1.8 1.5 1.2 1.8 Adj Adj Adj Adj 1.8 Adj Adj 1.8 Adj 2.5 Adj Adj Adj 1.5 Adj Adj 2.5 Adj Adj Adj Adj Adj *When VCC falls below the UVLO, all outputs go low regardless of the state of EN_ and VIN_. The outputs are guaranteed to be in the correct state for VCC down to 1.2V. _______________________________________________________________________________________ 7 Dual-/Triple-/Quad-Voltage, CapacitorAdjustable, Sequencing/Supervisory Circuits MAX16025–MAX16030 TH0 TH1 EN4 EN3 EN2 EN1 DELAY IN1 THRESHOLD SELECT LOGIC 250nA LOGIC DRIVER OUT1 1V IN2 MAX16029 MAX16030 DELAY DRIVER OUT2 IN3 DELAY DRIVER OUT3 IN4 DELAY DRIVER OUT4 GND RESET DELAY LOGIC TOL REFERENCE DRIVER RESET VCC CDLY1 CDLY2 CDLY3 CDLY4 CRESET MR Figure 1. MAX16029/MAX16030 Simplified Functional Diagram 8 _______________________________________________________________________________________ Dual-/Triple-/Quad-Voltage, CapacitorAdjustable, Sequencing/Supervisory Circuits MAX16025–MAX16030 VCC VUVLO IN_ VTH VTH t < tON EN_ OUT_ tDELAYtON tDELAY+ tRST_DELAY tRP RESET tRP tOFF tON tRP Figure 2. Timing Diagram (CDLY_ Open) Detailed Description The MAX16025–MAX16030 are low-voltage, accurate, dual-/triple-/quad-voltage microprocessor (µP) supervisors in a small TQFN package. These devices provide supervisory and sequencing functions for complex multivoltage systems. The MAX16025/MAX16026 monitor two voltages, the MAX16027/MAX16028 monitor three voltages, and the MAX16029/MAX16030 monitor four voltages. The MAX16025–MAX16030 offer independent outputs and enable functions for each monitored voltage. This configuration allows the device to operate as four separate supervisory circuits or be daisy-chained together to allow controlled sequencing of power supplies during power-up initialization. When all of the monitored voltages exceed their respective thresholds, an independent reset output deasserts to allow the system processor to operate. These devices offer enormous flexibility as there are nine threshold options that are selected through two threshold-select logic inputs. Each monitor circuit also offers an independent enable input to allow both digital and analog control of each monitor output. A tolerance select input allows these devices to be used in systems requiring 5% or 10% power-supply tolerances. In addition, the time delays and reset timeout can be adjusted using small capacitors. There is also a fixed 140ms minimum reset timeout feature. _______________________________________________________________________________________ 9 Dual-/Triple-/Quad-Voltage, CapacitorAdjustable, Sequencing/Supervisory Circuits MAX16025–MAX16030 Applications Information Tolerance The MAX16025–MAX16030 feature a pin-selectable threshold tolerance. Connect TOL to GND to select the thresholds 5% below the nominal value. Connect TOL to VCC to select the threshold tolerance 10% below the nominal voltage. Do not leave TOL unconnected. The following equation is provided to help estimate the value of the resistors based on the amount of acceptable error: e × VINTH R1 = A IL where eA is the fraction of the maximum acceptable absolute resistive divider error attributable to the input leakage current (use 0.01 for ±1%), VINTH is the voltage at which the output (OUT_) should assert, and IL is the worst-case IN_ leakage current (see the Electrical Characteristics). Calculate R2 as follows: R2 = VTH × R1 VINTH − VTH Adjustable Input These devices offer several monitoring options with both fixed and/or adjustable reset thresholds (see Table 2). For the adjustable threshold inputs, the threshold voltage (VTH) at each adjustable IN_ input is typically 0.5V (TOL = GND) or 0.472V (TOL = VCC). To monitor a voltage VINTH, connect a resistive divider network to the circuit as shown in Figure 3 and use the following equation to calculate the threshold voltage: R1 ⎞ ⎛ VINTH = VTH × ⎜1 + ⎟ ⎝ R2 ⎠ Choosing the proper external resistors is a balance between accuracy and power use. The input to the voltage monitor is a high-impedance input with a small 100nA leakage current. This leakage current contributes to the overall error of the threshold voltage where the output is asserted. This induced error is proportional to the value of the resistors used to set the threshold. With lower value resistors, this error is reduced, but the amount of power consumed in the resistors increases. VINTH R1 IN_ Unused Inputs Connect any unused IN_ and EN_ inputs to VCC. OUT_ Output An OUT_ goes low when its respective IN_ input voltage drops below its specified threshold or when its EN_ goes low (see Table 1). OUT_ goes high when EN_ is high and V IN_ is above its threshold after a time delay. The MAX16025/MAX16027/MAX16029 feature open-drain, outputs while the MAX16026/MAX16028/MAX16030 have push-pull outputs. Open-drain outputs require an external pullup resistor to any voltage from 0 to 28V. RESET Output RESET asserts low when any of the monitored voltages (IN_) falls below its respective threshold, any EN_ goes low, or MR is asserted. RESET remains asserted for the reset timeout period after all of the monitored voltages exceed their respective threshold, all EN_ are high, all OUT_ are high, and MR is deasserted. The MAX16025/ MAX16027/MAX16029 have an open-drain, active-low reset output, while the MAX16026/MAX16028/ MAX16030 have a push-pull, active-low reset output. Open-drain RESET requires an external pullup resistor to any voltage from 0 to 28V. MAX16025– MAX16030 R2 VTH Adjustable Reset Timeout Period (CRESET) R1 = R2 x ( VVINTH -1) TH All of these parts offer an internally fixed reset timeout (140ms min) by connecting CRESET to VCC. The reset timeout can also be adjusted by connecting a capacitor from CRESET to GND. When the voltage at CRESET reaches 0.5V, RESET goes high. When RESET goes high, CRESET is immediately held low. Figure 3. Setting the Adjustable Input 10 ______________________________________________________________________________________ Dual-/Triple-/Quad-Voltage, CapacitorAdjustable, Sequencing/Supervisory Circuits Calculate the reset timeout period as follows: debounce circuitry is not required. If MR is driven from long cables or if the device is used in a noisy environment, connect a 0.1µF capacitor from MR to GND to provide additional noise immunity. MAX16025–MAX16030 V t RP = TH−RESET × CCRESET + 35 × 10 −6 ICH−RESET where VTH-RESET is 0.5V, ICH-RESET is 0.5µA, tRP is in seconds, and CCRESET is in Farads. To ensure timing accuracy and proper operation, minimize leakage at CCRESET. Pullup Resistor Values The exact value of the pullup resistors for the opendrain outputs is not critical, but some consideration should be made to ensure the proper logic levels when the device is sinking current. For example, if VCC = 2.25V and the pullup voltage is 28V, keep the sink current less than 0.5mA as shown in the Electrical Characteristics table. As a result, the pullup resistor should be greater than 56kΩ. For a 12V pullup, the resistor should be larger than 24kΩ. Note that the ability to sink current is dependent on the VCC supply voltage. Adjustable Delay (CDLY_) When VIN rises above VTH with EN_ high, the internal 250nA current source begins charging an external capacitor connected from CDLY_ to GND. When the voltage at CDLY_ reaches 1V, OUT_ goes high. When OUT_ goes high, CDLY_ is immediately held low. Adjust the delay (tDELAY) from when VIN rises above VTH (with EN_ high) to OUT_ going high according to the equation: V tDELAY = TH− CDLY × CCDLY + 35 × 10 −6 ICH− CDLY where VTH-CDLY is 1V, ICH-CDLY is 0.25µA, CCDLY is in Farads, tDELAY is in seconds, and tDELAY+ is the internal propagation delay of the device. To ensure timing accuracy and proper operation, minimize leakage at CDLY. Power-Supply Bypassing The device operates with a VCC supply voltage from 2.2V to 28V. When VCC falls below the UVLO threshold, all the outputs go low and stay low until VCC falls below 1.2V. For noisy systems or fast rising transients on VCC, connect a 0.1µF ceramic capacitor from VCC to GND as close to the device as possible to provide better noise and transient immunity. Ensuring Valid Output with VCC Down to 0V (MAX16026/MAX16028/MAX16030 Only) When VCC falls below 1.2V, the ability for the output to sink current decreases. In order to ensure a valid output as VCC falls to 0V, connect a 100kΩ resistor from OUT/RESET to GND. Manual-Reset Input (MR) Many µP-based products require manual-reset capability, allowing the operator, a test technician, or external logic circuitry to initiate a reset. A logic-low on M R asserts RESET low. RESET remains asserted while MR is low and during the reset timeout period (140ms fixed or capacitor adjustable) after MR returns high. The MR input has a 500nA internal pullup, so it can be left unconnected, if not used. MR can be driven with TTL or CMOS logic levels, or with open-drain/collector outputs. Connect a normally open momentary switch from MR to GND to create a manual-reset function. External Typical Application Circuits Figures 4 and 5 show typical applications for the MAX16025–MAX16030. In high-power applications, using an n-channel device reduces the loss across the MOSFETs as it offers a lower drain-to-source on-resistance. However, an n-channel MOSFET requires a sufficient VGS voltage to fully enhance it for a low RDS_ON. The application in Figure 4 shows the MAX16027 configured in a multiple-output sequencing application. Figure 5 shows the MAX16029 in a power-supply sequencing application using n-channel MOSFETs. ______________________________________________________________________________________ 11 Dual-/Triple-/Quad-Voltage, CapacitorAdjustable, Sequencing/Supervisory Circuits MAX16025–MAX16030 +12V BUS +3.3V IN DC-DC EN OUT IN DC-DC EN OUT +2.5V IN DC-DC EN OUT +1.8V EN1 VCC IN1 OUT1 EN2 IN2 OUT2 EN3 IN3 OUT3 +3.3V MAX16027 MR RESET CDLY1 CDLY2 CDLY3 CRESET GND TOL TH0 TH1 SYSTEM RESET Figure 4. Sequencing Multiple-Voltage System 12V BUS 1.5V 1.8V TO LOADS 2.5V 3.3V IN1 OUT1 IN2 OUT2 IN3 OUT3 IN4 OUT4 +3.3V VCC EN1 EN2 EN3 EN4 MAX16029 RESET CDLY1 CDLY2 CDLY3 CDLY4 CRESET GND TOL TH0 TH1 MR SYSTEM RESET Figure 5. Multiple-Voltage Sequencing Using n-Channel FETs 12 ______________________________________________________________________________________ Dual-/Triple-/Quad-Voltage, CapacitorAdjustable, Sequencing/Supervisory Circuits Pin Configurations (continued) TOP VIEW RESET RESET OUT1 OUT2 OUT1 OUT2 OUT3 TH0 TH0 MAX16025–MAX16030 12 11 10 9 15 MR 16 CRESET 17 CDLY3 18 6 5 EN1 CDLY2 19 GND CDLY1 20 14 13 12 11 10 9 TH1 EN3 EN2 EN1 GND MR 13 CRESET 14 CDLY2 15 CDLY1 16 8 7 TH1 EN2 MAX16025 MAX16026 MAX16027 MAX16028 8 7 6 + 1 VCC 2 IN1 3 IN2 4 TOL + 1 VCC 2 IN1 3 IN2 4 IN3 5 TOL THIN QFN (4mm x 4mm) THIN QFN (4mm x 4mm) Chip Information PROCESS: BICMOS TRANSISTOR COUNT: 3642 ______________________________________________________________________________________ 13 Dual-/Triple-/Quad-Voltage, CapacitorAdjustable, Sequencing/Supervisory Circuits MAX16025–MAX16030 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 24L QFN THIN.EPS PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm 21-0139 E 1 2 14 ______________________________________________________________________________________ Dual-/Triple-/Quad-Voltage, CapacitorAdjustable, Sequencing/Supervisory Circuits Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX16025–MAX16030 PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm 21-0139 E 2 2 Revision History Pages changed at Rev 1: 1, 3, 15 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.