MAX9879

19-4436; Rev 0; 2/09 KIT ATION EVALU ABLE AVAIL Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier Features ♦ Better than 9dB Margin Under EN 55022 Class B Limits with No Filter Components ♦ Low RF Susceptibility Design Rejects TDMA Noise from GSM Radios ♦ Input Mixer with User Defined Input Mode ♦ Stereo 715mW Speaker Output (RL = 8Ω, VDD = 3.7V) ♦ Stereo 58mW Headphone Output (16Ω, VDD = 3.7V) ♦ Low 0.04% THD+N at 1kHz (Class D Power Amplifier) ♦ Low 0.018% THD+N at 1kHz (Headphone Amplifier) ♦ 88% Efficiency (RL = 8Ω, POUT = 750mW) ♦ 1.6Ω Analog Switch for Speaker Amplifier Bypass ♦ High Speaker Amplifier PSRR (72dB at 217Hz) ♦ High Headphone Amplifier PSRR (84dB at 217Hz) ♦ I2C Control ♦ Hardware and Software Shutdown Mode ♦ Ultra-Low Click and Pop ♦ Robust Design with Current and Thermal Protection ♦ Available in Space-Saving Package 5x6 UCSP (2.5mm x 3mm) General Description The MAX9879 combines a high-efficiency stereo Class D audio power amplifier with a stereo capacitor-less DirectDrive® headphone amplifier. Maxim’s filterless class D amplifiers with active emissions limiting technology provide Class AB performance with Class D efficiency. The Class D power amplifier delivers up to 715mW from a 3.7V supply into an 8Ω load with 88% efficiency to extend battery life. The filterless modulation scheme combined with active emission limiting circuitry and spread-spectrum modulation greatly reduces EMI while eliminating the need for output filtering used in traditional Class D devices. The headphone amplifier delivers up to 58mW from a 3.7V supply into a 16 Ω load. Maxim’s patented DirectDrive architecture produces a ground-referenced output from a single supply, eliminating the need for large DC-blocking capacitors, saving cost, space and component height. The device utilizes a user-defined input architecture, three preamplifier gain settings, an input mixer, volume control, comprehensive click-and-pop suppression, and I2C control. A bypass mode feature disables the integrated Class D amplifier and utilizes an internal DPST switch to allow an external amplifier to drive the speaker that is connected at the outputs of the MAX9879. The MAX9879 is available in a thermally efficient, space-saving 30-bump UCSP™ package. MAX9879 Ordering Information PART MAX9879ERV+ TEMP RANGE -40°C to +85°C PIN-PACKAGE 30 UCSP (5x6) Applications Cell Phones Portable Multimedia Players DirectDrive is a registered trademark of Maxim Integrated Products, Inc. UCSP is a trademark of Maxim Integrated Products, Inc. +Denotes a lead(Pb)-free/RoHS-compliant package. Simplified Block Diagram SINGLE SUPPLY 2.7V TO 5.5V Pin Configuration TOP VIEW (BUMP SIDE DOWN) 1 2 3 4 5 6 PREAMPLIFIER VOLUME CONTROL A C1P B C1N RXINPGNDL RXIN+ PGNDR PVDDR OUTLPVDDL OUTL+ PGNDR OUTR- MIXER I2 C INTERFACE VOLUME CONTROL C VSS D HPL BIAS INB1 INA1 SCL SDA GND GND GND GND OUTR+ BYPASS E HPR VDD INB2 INA2 SHDN VCCIO MAX9879 ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier MAX9879 ABSOLUTE MAXIMUM RATINGS VDD, PVDDL, PVDDR to GND ..................................-0.3V to +6V VDD, PVDDL to PVDDR .........................................-0.3V to +0.3V VDD to PVDDL .......................................................-0.3V to +0.3V VCCIO to GND...........................................................-0.3V to +4V PGNDL, PGNDR, to GND......................................-0.3V to +0.3V PGNDL to PGNDR.................................................-0.3V to +0.3V VSS to GND...............................................................-6V to +0.3V C1N to GND ................................................(VSS - 0.3V) to +0.3V C1P to GND ...........................................-0.3V to (PVDD_ + 0.3V) HPL, HPR to VSS (Note 1).............................-0.3V to the lower of (VDD - VSS + 0.3V) or +9V HPL, HPR to VDD (Note 2) .........................+0.3V to the higher of (VSS - PVDD_ - 0.3V) or -9V INA1, INA2, INB1, INB2, BIAS..................................-0.3V to +4V SDA, SCL, SHDN......................................................-0.3V to +4V All Other Pins to GND ............................-0.3V to (PVDD_ + 0.3V) Continuous Current In/Out of PVDD_, PGND_, OUT_ ....±800mA Continuous Current In/Out of HPR and HPL .....................140mA Continuous Current In/Out of RXIN+ and RXIN- ...............150mA Continuous Input Current VSS ...........................................100mA Continuous Input Current (All Other Pins) ........................±20mA Duration of OUT_ Short Circuit to PGND_ or PVDD_...............................................Continuous Duration of Short Circuit Between OUT_+ and OUT_- ..................................Continuous Duration of HP_ Short Circuit to GND or PVDDL........Continuous Continuous Power Dissipation (TA = +70°C) 5x6 UCSP Multilayer Board (derate 16.5mW/°C above +70°C) .............................1250mW Junction Temperature ......................................................+150°C Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Note 1: HPR and HPL should be limited to no more than 9V above VSS, or above PVDD + 0.3V, whichever limits first. Note 2: HPR and HPL should be limited to no more than 9V below PVDD, or below VSS - 0.3V, whichever limits first. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = VPVDDL = VPVDDR = 3.7V, VCCIO = 1.8V, VGND = VPGNDL = VPGNDR = 0. Single-ended inputs, preamp = 0, volume controls = 0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL or HPR to GND. RSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 3, 4) PARAMETER Analog Supply Voltage Range Digital Supply Voltage Range SYMBOL VDD, PVDDR PVDDL VCCIO CONDITIONS Guaranteed by PSRR Test MIN 2.7 1.7 HP mode, RHP = ∞ Quiescent Current IDD Stereo SPK mode, RSPK = ∞ Mono SPK mode, RSPK = ∞ Stereo SPK + HP mode, RHP= RSPK = ∞ ISHDN = IDD + IPVDDR + IPVDDL + ICC; TA = +25°C Software shutdown Hardware shutdown 5.6 9.8 6.6 13.2 5 0.1 10 11 3 21 5.5 2.3 1.2 0.230 VP-P 31 8 TYP MAX 5.5 3.6 9.0 18 10 24 10 µA 1 ms kΩ mA UNITS V V Shutdown Current ISHDN Turn-On Time Input Resistance tON RIN Time from shutdown or power-on to full operation TA = +25°C, preamp = 0dB or +5.5dB TA = +25°C, preamp = +20dB Preamp = 0 Preamp = +5.5dB Preamp = +20dB Maximum Input Signal Swing 2 _______________________________________________________________________________________ Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier MAX9879 ELECTRICAL CHARACTERISTICS (continued) (VDD = VPVDDL = VPVDDR = 3.7V, VCCIO = 1.8V, VGND = VPGNDL = VPGNDR = 0. Single-ended inputs, preamp = 0, volume controls = 0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL or HPR to GND. RSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 3, 4) PARAMETER Common-Mode Rejection Ratio Input DC Voltage Bias Voltage SPEAKER AMPLIFIER TA = +25°C (volume at mute) Output Offset Voltage VOS TA = +25°C (volume at 0dB, ENA = 1 and ENB = 0 or ENB = 1 and ENA = 0, ΔIN_ = 0) Peak voltage, TA = +25°C A-weighted, 32 samples per second, volume at mute (Note 5) Into shutdown Out of shutdown PVDD_ = VDD = 2.7V to 5.5V f = 217Hz, 100mVP-P ripple f = 1kHz, 100mVP-P ripple f = 20kHz, 100mVP-P ripple Output Power POUT THD+N ≤ 1%, RSPK = 8Ω VDD = 3.7V VDD = 3.3V VDD = 3.0V 50 ±0.5 ±4.5 -70 dBV -70 76 72 dB 68 55 715 565 470 0.04 92 94 dB 88 92 700 ±40 kHz 0.2 % mW ±4 mV mV VBIAS SYMBOL CMRR CONDITIONS Preamp = 0 fIN = 1kHz (differential input mode) IN__ inputs Preamp = 5.5dB Preamp = 20dB 1.22 1.13 MIN TYP 58 55 43 1.3 1.2 1.38 1.272 V V dB MAX UNITS Click-and-Pop Level KCP Power-Supply Rejection Ratio (Note 5) PSRR TA = +25°C Total Harmonic Distortion + Noise THD+N f = 1kHz, POUT = 350mW, TA = +25°C, RSPK = 8Ω A-weighted, ENA = 1 and ENB = 0 or ENB = 1 and ENA = 0 ΔIN_ = 0 (single-ended) ΔIN_ = 1 (differential) ΔIN_ = 0 (single-ended) ΔIN_ = 1 (differential) Signal-to-Noise Ratio SNR A-weighted ENA = ENB = 1 Output Frequency _______________________________________________________________________________________ 3 Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier MAX9879 ELECTRICAL CHARACTERISTICS (continued) (VDD = VPVDDL = VPVDDR = 3.7V, VCCIO = 1.8V, VGND = VPGNDL = VPGNDR = 0. Single-ended inputs, preamp = 0, volume controls = 0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL or HPR to GND. RSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 3, 4) PARAMETER Current Limit Efficiency Speaker Gain Output Noise Crosstalk HEADPHONE AMPLIFIERS TA = +25°C (volume at mute) Output Offset Voltage VOS TA = +25°C (Volume at 0dB, ENA = 1 and ENB = 0 or ENA = 0 and ENB = 1, ΔIN_ = 0) Peak voltage, TA = 25°C A-weighted, 32 samples per second, volume at mute (Note 5) Into shutdown Out of shutdown PVDD_ = VDD = 2.7V to 5.5V f = 217Hz, VRIPPLE = 100mVP-P f = 1kHz, VRIPPLE = 100mVP-P f = 20kHz, VRIPPLE = 100mVP-P RHP = 16Ω RHP = 32Ω 2.6 TA = +25°C, HPL to HPR, volume at 0dB, ENA=1 and ENB = 0 or ENA = 1 and ENB = 0, ΔIN_ = 0 RHP = 32Ω (POUT = 10mW, f = 1kHz) RHP = 16Ω (POUT = 10mW, f = 1kHz) 70 ±0.22 ±1.5 -75 dBV -75 85 84 dB 80 ±0.85 mV mV η AV A-weighted, (ENA = 1 and ENB = 0 or ENA = 0 and ENB = 1), ΔIN_ = 0 OUTL to OUTR, OUTR to OUTL, f = 20Hz to 20kHz POUT = 600mW, f = 1kHz 17.4 SYMBOL CONDITIONS MIN TYP 1.5 88 18 63 75 18.4 MAX UNITS A % dB µVRMS dB Click-and-Pop Level KCP Power-Supply Rejection Ratio (Note 5) PSRR TA = +25°C 62 58 54 3 ±0.3 3.4 ±2.5 Output Power Headphone Gain Channel-to-Channel Gain Tracking POUT AV THD+N = 1% mW dB % 0.018 % 0.037 0.08 Total Harmonic Distortion + Noise THD+N 4 _______________________________________________________________________________________ Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier ELECTRICAL CHARACTERISTICS (continued) (VDD = VPVDDL = VPVDDR = 3.7V, VCCIO = 1.8V, VGND = VPGNDL = VPGNDR = 0. Single-ended inputs, preamp = 0, volume controls = 0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL or HPR to GND. RSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 3, 4) PARAMETER SYMBOL CONDITIONS ENA = 1 and ENB = 0 or ENA = 1 and ENB = 0 ENA = 1 and ENB = 1 Slew Rate Capacitive Drive Crosstalk Charge-Pump Frequency VOLUME CONTROL Minimum Setting Maximum Setting Input Gain _VOL = 1 _VOL = 31 PGAIN_ = 00 Input A or B PGAIN_ = 01 PGAIN_ = 10 Mute Attenuation Zero-Crossing Detection Time Out ANALOG SWITCH On-Resistance RON IRXIN__ = 20mA, RXIN_ = 0 and VDD, BYPASS = 1 TA = +25°C TA = TMIN to TMAX 0.3 0.3 88 dB 2.4 4 5.2 0.25 % Ω f = 1kHz, _VOL = 0 ZCD = 1 Speaker Headphone -75 0 0 5.5 20 100 110 60 dB ms dB dB dB SR CL HPL to HPR, HPR to HPL, f = 20Hz to 20kHz ΔIN_ = 0 ΔIN_ = 1 ΔIN_ = 0 ΔIN_ = 1 MIN TYP 98 98 96 96 0.35 100 67 350 ±20 V/µs pF dB kHz dB MAX UNITS MAX9879 Signal-to-Noise Ratio SNR A-weighted, RHP = 16Ω Total Harmonic Distortion + Noise Series resistance is VDIFRXIN = 2VP-P, 10Ω per switch VCMRXIN = VDD/2, f = 1kHz, BYPASS = 1 No series resistors BYPASS = 0, RXIN+ and RXIN- to GND = 50Ω, RSPK = 8Ω, f = 10kHz, referred to speaker output signal Off-Isolation DIGITAL INPUTS (SDA, SCL, SHDN) Input Voltage High (SDA, SCL) Input Voltage Low (SDA, SCL) Input Hysteresis (SDA, SCL) VIH VIL VHYS 0.7 x VCCIO 0.3 x VCCIO 200 V V mV _______________________________________________________________________________________ 5 Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier MAX9879 ELECTRICAL CHARACTERISTICS (continued) (VDD = VPVDDL = VPVDDR = 3.7V, VCCIO = 1.8V, VGND = VPGNDL = VPGNDR = 0. Single-ended inputs, preamp = 0, volume controls = 0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL or HPR to GND. RSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 3, 4) PARAMETER Input Voltage High (SHDN) Input Voltage Low (SHDN) Input Hysteresis (SHDN) SDA, SCL, SHDN Input Capacitance Input Leakage Current Input Leakage Current DIGITAL OUTPUTS (SDA open drain) Output Low-Voltage SDA Output High-Voltage SDA Output Fall Time SDA 2-WIRE INTERFACE TIMING External Pullup Voltage Range (SDA and SCL) Serial-Clock Frequency Bus Free Time Between STOP and START Conditions START Condition Hold START Condition Setup Time Clock Low Period Clock High Period Data Setup Time Data Hold Time SCL/SDA Receiving Rise Time SCL/SDA Receiving Fall Time 1.7 fSCL tBUF tHD:STA tSU:STA tLOW tHIGH tSU:DAT tHD:DAT tR tF VCCIO =1.8V (Note 6) SDA Transmitting Fall Time tF VCCIO = 3.6V (Note 6) (Note 6) DC 1.3 0.6 0.6 1.3 0.6 100 0 20 + 0.1 x CB 20 + 0.1 x CB 20 + 0.1 x CB 20 + 0.05 x CB 900 300 300 250 ns 250 3.6 400 V kHz µs µs µs µs µs ns ns ns ns VOL VOH tOF ISINK = 3mA ISINK = 3mA VH(MIN) to VL(MAX) bus capacitance = 10pF to 400pF, ISINK = 3mA VCCIO 0.4 250 0.4 V V ns SYMBOL VIH VIL VHYS CIN IIN IIN SDA, SCL, SHDN, TA = +25°C VCCIO = 0, TA = +25°C 100 10 ±1.0 ±1.0 CONDITIONS MIN 1.4 0.4 TYP MAX UNITS V V mV pF µA µA 6 _______________________________________________________________________________________ Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier ELECTRICAL CHARACTERISTICS (continued) (VDD = VPVDDL = VPVDDR = 3.7V, VCCIO = 1.8V, VGND = VPGNDL = VPGNDR = 0. Single-ended inputs, preamp = 0dB, volume controls = 0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL or HPR to GND. RSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 3, 4) PARAMETER Set-Up Time for STOP Condition Pulse Width of Spike Suppressed Capacitive Load for Each Bus Line SYMBOL tSU:STO tSP CB CONDITIONS MIN 0.6 0 50 400 TYP MAX UNITS µs ns pF MAX9879 Note 3: All devices are 100% production tested at TA = +25°C. All temperature limits are guaranteed by design. Note 4: Class D amplifier testing performed with a resistive load in series with an inductor to simulate an actual speaker load. For RSPKR = 8Ω, L = 68mH. Note 5: Amplifier inputs are AC-coupled to GND. Note 6: CB is in pF. _______________________________________________________________________________________ 7 Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier MAX9879 Typical Operating Characteristics (VDD = VPVDDL = VPVDDR = 3.7V, VCCIO = 1.8V, VGND = VPGNDL = VPGNDR = 0. Single-ended inputs, preamp = 0dB, volume controls = 0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL or HPR to GND. RSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) GENERAL SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX9879 toc01 SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX9879 toc02 SUPPLY CURRENT vs. SUPPLY VOLTAGE HEADPHONE + STEREO-SPEAKER MODE 18 SUPPLY CURRENT (mA) 16 14 12 10 8 6 4 MAX9879 toc03 10 HEADPHONE MODE 8 SUPPLY CURRENT (mA) 16 STEREO-SPEAKER MODE 14 SUPPLY CURRENT (mA) 12 10 8 6 4 2 20 6 4 2 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 SUPPLY VOLTAGE (V) 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 SUPPLY VOLTAGE (V) 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 SUPPLY VOLTAGE (V) SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX9879 toc04 SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX9879 toc05 VOLUME LEVEL vs. VOLUME STEP 90 80 ATTENUATION (dB) 70 60 50 40 30 fIN = 1kHz MAX9879 toc06 16 SOFTWARE-SHUTDOWN MODE 14 SUPPLY CURRENT (µA) 12 10 8 6 4 2 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 50 HARDWARE-SHUTDOWN MODE 40 SUPPLY CURRENT (nA) 100 30 20 10 20 10 0 5.5 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) 0 0 4 8 12 16 20 24 28 32 VOLUME STEP 8 _______________________________________________________________________________________ Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier Typical Operating Characteristics (continued) (VDD = VPVDDL = VPVDDR = 3.7V, VCCIO = 1.8V, VGND = VPGNDL = VPGNDR = 0. Single-ended inputs, preamp = 0dB, volume controls = 0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL or HPR to GND. RSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) MAX9879 SPEAKER AMPLIFIERS (Headphone Disabled) THD+N vs. FREQUENCY SPEAKER MAX9879 toc07 THD+N vs. FREQUENCY SPEAKER MAX9879 toc08 THD+N vs. OUTPUT POWER PVDD_ = 3.7V RL = 8Ω 1 THD+N (%) MAX9879 toc09 10 PVDD_= 3.7V RL = 8Ω 1 THD+N (%) 10 PVDD_= 3.0V RL = 8Ω 1 THD+N (%) 10 OUTPUT POWER = 200mW OUTPUT POWER = 100mW fIN = 6kHz 0.1 0.1 0.1 OUTPUT POWER = 600mW 0.01 0.01 0.1 1 FREQUENCY (kHz) 10 100 0.01 0.01 OUTPUT POWER = 400mW 0.01 0.1 1 FREQUENCY (kHz) 10 100 0 fIN = 20Hz 200 400 600 fIN = 1kHz 800 1000 OUTPUT POWER (mW) THD+N vs. OUTPUT POWER MAX9879 toc10 THD+N vs. OUTPUT POWER PVDD_ = 3.7V RL = 8Ω LEFT SPEAKER ONLY 1 THD+N (%) fIN = 6kHz MAX9879 toc11 10 PVDD_ = 3.0V RL = 8Ω 1 THD+N (%) 10 fIN = 6kHz 0.1 fIN = 20Hz 0.01 0 100 200 300 400 500 600 700 OUTPUT POWER (mW) 0.1 fIN = 1kHz fIN = 20Hz 0.01 0 200 400 600 fIN = 1kHz 800 1000 OUTPUT POWER (mW) EFFICIENCY vs. OUTPUT POWER MAX9879 toc12 OUTPUT POWER vs. SUPPLY VOLTAGE 1800 1600 OUPUT POWER (mW) 1400 1200 1000 800 600 400 THD+N = 1% RL = 8Ω fIN = 1kHz MAX9879 toc13 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 fIN = 1kHz, RL = 8Ω 2000 THD+N = 10% 200 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 100 200 300 400 500 600 700 800 900 OUTPUT POWER (mW) SUPPLY VOTAGE (V) _______________________________________________________________________________________ 9 Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier MAX9879 Typical Operating Characteristics (continued) (VDD = VPVDDL = VPVDDR = 3.7V, VCCIO = 1.8V, VGND = VPGNDL = VPGNDR = 0. Single-ended inputs, preamp = 0dB, volume controls = 0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL or HPR to GND. RSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) SPEAKER AMPLIFIERS (Headphone Disabled) OUTPUT POWER vs. LOAD MAX9879 toc14 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (SPEAKER MODE) MAX9879 toc15 CROSSTALK vs. FREQUENCY RL = 8Ω VIN = 1VP-P MAX9879 toc16 1000 f = 1kHz 800 OUPUT POWER (mW) THD+N = 10% 0 -10 -20 -30 PSRR (dB) -40 -50 -60 -70 LEFT RL = 8Ω VRIPPLE = 100mVP-P INPUTS AC GROUNDED RIGHT 0 -20 CROSSTALK (dB) -40 -60 600 400 THD+N = 1% RIGHT TO LEFT -80 -100 LEFT TO RIGHT -120 200 -80 -90 0 1 10 LOAD (Ω) 100 -100 0.01 0.1 1 FREQUENCY (kHz) 10 100 0.01 0.1 1 FREQUENCY (kHz) 10 100 OUTPUT FREQUENCY SPECTRUM SPEAKER MODE MAX9879 toc17 WIDEBAND FREQUENCY SPECTRUM (SPEAKER MODE) -10 OUTPUT MAGNITUDE (dBV) -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 RBW = 1kHz INPUT AC GROUNDED MAX9879 toc18 0 -20 OUTPUT MAGNITUDE (dBV) -40 -60 -80 -100 -120 -140 0 5 10 FREQUENCY (kHz) MAX9879 toc19 0 VOUT = -60dBV f = 1kHz RL = 8Ω UNWEIGHTED 15 20 0 1 10 100 FREQUENCY (MHz) MAX9879 toc20 SHDN 1V/div SDA 2V/div SCL 2V/div OUT+ - OUT1V/div 400μs/div 2ms/div 10 ______________________________________________________________________________________ Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier Typical Operating Characteristics (continued) (VDD = VPVDDL = VPVDDR = 3.7V, VCCIO = 1.8V, VGND = VPGNDL = VPGNDR = 0. Single-ended inputs, preamp = 0dB, volume controls = 0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL or HPR to GND. RSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) MAX9879 HEADPHONE AMPLIFIERS (Speaker Disabled) TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (HEADPHONE MODE) MAX9879 toc21 MAX9879 toc22 TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (HEADPHONE NOISE) VDD = 3.7V RL = 16Ω 1 THD+N (%) OUTPUT POWER = 10mW 0.1 MAX9879 toc23 10 SDA 2V/div 1 THD+N (%) SCL 2V/div VDD = 3.7V RL = 32Ω 10 0.1 OUTPUT POWER = 20mW OUT+ - OUT0.01 1V/div OUTPUT POWER = 45mW 0.001 2ms/div 0.01 0.1 1 FREQUENCY (kHz) 10 100 0.01 OUTPUT POWER = 40mW 0.001 0.01 0.1 1 FREQUENCY (kHz) 10 100 TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (HEADPHONE MODE) MAX9879 toc24 TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (HEADPHONE MODE) MAX9879 toc25 TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (HEADPHONE MODE) VDD = 3.7V RL = 32Ω 1 MAX9879 toc26 10 VDD = 3.0V RL = 32Ω 1 THD+N (%) 10 VDD = 3.0V RL = 16Ω 1 THD+N (%) OUTPUT POWER = 7mW 0.1 10 THD+N (%) 0.1 OUTPUT POWER = 30mW 0.1 fIN = 1kHz 0.01 OUTPUT POWER = 10mW 0.001 0.01 0.1 1 FREQUENCY (kHz) 10 100 0.01 OUTPUT POWER = 22mW 0.01 fIN = 6kHz fIN = 100Hz 0.001 0.01 0.1 1 FREQUENCY (kHz) 10 100 0.001 0.01 0.1 1 FREQUENCY (kHz) 10 100 TOTAL HARMONIC DISTORTION + NOISE vs. OUTPUT POWER (HEADPHONE MODE) MAX9879 toc27 TOTAL HARMONIC DISTORTION + NOISE vs. OUTPUT POWER (HEADPHONE MODE) MAX9879 toc28 TOTAL HARMONIC DISTORTION + NOISE vs. OUTPUT POWER (HEADPHONE MODE) VDD = 3.0V RL = 16Ω 10 THD+N (%) fIN = 100Hz 0.1 MAX9879 toc29 10 VDD = 3.7V RL = 16Ω 1 THD+N (%) fIN = 100Hz 0.1 100 VDD = 3.0V RL = 32Ω 10 THD+N (%) 100 0.1 fIN = 100Hz 0.01 fIN = 1kHz 0.001 0 20 40 60 80 100 OUTPUT POWER (mW) fIN = 6kHz 0.01 fIN = 1kHz 0.001 0 10 20 30 40 50 60 70 OUTPUT POWER (mW) fIN = 6kHz 0.01 fIN = 1kHz fIN = 6kHz 0.001 0 10 20 30 40 50 60 OUTPUT POWER (mW) ______________________________________________________________________________________ 11 Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier MAX9879 Typical Operating Characteristics (continued) (VDD = VPVDDL = VPVDDR = 3.7V, VCCIO = 1.8V, VGND = VPGNDL = VPGNDR = 0. Single-ended inputs, preamp = 0dB, volume controls = 0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL or HPR to GND. RSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) HEADPHONE AMPLIFIERS (Speaker Disabled) TOTAL HARMONIC DISTORTION + NOISE vs. OUTPUT POWER (HEADPHONE MODE) MAX9879 toc30 POWER DISSIPATION vs. OUTPUT POWER (HEADPHONE MODE) MAX9879 toc31 OUTPUT POWER vs. SUPPLY VOLTAGE 75 OUTPUT POWER (mW) 60 50 40 30 20 10 0 RL = 32Ω fIN = 1kHz 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 THD+N = 10% THD+N = 10% MAX9879 toc32 100 VDD = 3.7V 10 THD+N (%) 250 225 POWER DISSIPATION (mW) 200 175 150 125 100 75 50 25 0 RL = 32Ω RL = 16Ω VDD = 3.0V 80 0.1 RL = 16Ω 0.01 RL = 32Ω 0.001 0.1 1 10 100 OUTPUT POWER (mW) 0 1 10 100 TOTAL OUTPUT POWER (mW) SUPPLY VOLTAGE (V) OUTPUT POWER vs. SUPPLY VOLTAGE MAX9879 toc33 OUTPUT POWER vs. LOAD RESISTANCE (HEADPHONE MODE) MAX9879 toc34 OUTPUT POWER vs. LOAD RESISTANCE (HEADPHONE MODE) 90 OUTPUT POWER (mW) 80 70 50 30 20 10 0 C1 = C2 = 0.47μF C1 = C2 = 1μF C1 = C2 = 2.2μF f = 1kHz THD+N = 1% MAX9879 toc35 160 140 OUPUT POWER (mW) 120 100 80 60 40 20 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 RL = 16Ω fIN = 1kHz THD+N = 1% THD+N = 10% 100 90 80 OUPUT POWER (mW) 70 60 50 40 30 20 10 0 THD+N = 1% THD+N = 10% VDD = 3.3V f = 1kHz 100 5.5 10 LOAD RESISTANCE (Ω) 100 10 LOAD RESISTANCE (Ω) 100 SUPPLY VOTAGE (V) POWER SUPPLY REJECTION RATIO vs. FREQUENCY (HEADPHONE MODE) MAX9879 toc36 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (HEADPHONE MODE) MAX9879 toc37 CROSSTALK vs. FREQUENCY (HEADPHONE MODE) -10 -20 CROSSTALK (dB) -30 -40 -50 -60 -70 -80 LEFT TO RIGHT RIGHT TO LEFT RL = 16Ω f = 1kHz VIN = 1VP-P MAX9879 toc38 0 -10 -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 -100 0.01 0.1 1 FREQUENCY (kHz) 10 RIGHT LEFT VRIPPLE = 100mVP-P INPUTS AC GROUNDED 0 OUTPUT FREQUENCY SPECTRUM (dB) -20 -40 -60 -80 -100 -120 -140 VOUT = -60dB f =1kHz RL = 32Ω 0 100 0 5 10 FREQUENCY (kHz) 15 20 0.01 0.1 1 FREQUENCY (Hz) 10 100 12 ______________________________________________________________________________________ Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier Typical Operating Characteristics (continued) (VDD = VPVDDL = VPVDDR = 3.7V, VCCIO = 1.8V, VGND = VPGNDL = VPGNDR = 0. Single-ended inputs, preamp = 0dB, volume controls = 0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL or HPR to GND. RSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) MAX9879 HEADPHONE AMPLIFIERS (Speaker Disabled) COMMON-MODE REJECTION RATIO vs. FREQUENCY (HEADPHONE MODE) -10 -20 GAIN (dB) -30 -40 -50 -60 -70 -80 0.01 0.1 1 FREQUENCY (kHz) 10 100 20μs/div AV = 0dB AV = +5.5dB HP_ 1V/div AV = +20dB SHDN 1V/div MAX9879 toc39 0 MAX9879 toc40 ______________________________________________________________________________________ 13 Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier MAX9879 Typical Operating Characteristics (continued) (VDD = VPVDDL = VPVDDR = 3.7V, VCCIO = 1.8V, VGND = VPGNDL = VPGNDR = 0. Single-ended inputs, preamp = 0dB, volume controls = 0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL or HPR to GND. RSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) ANALOG SWITCH MAX9879 toc41 MAX9879 toc42 SDA 2V/div SCL 2V/div SDA 2V/div SCL 2V/div HP_ 1V/div HP_ 1V/div 2ms/div 2ms/div THD+N vs. OUTPUT POWER BYPASS SWITCH MAX9879 toc43 THD+N vs. OUTPUT POWER BYPASS SWITCH PVDD_ = 3.7V RL = 8Ω NO SERIES RESISTORS 1 THD+N (%) fIN = 100Hz fIN = 1kHz MAX9879 toc44 100 PVDD_ = 3.7V RL = 8Ω NO SERIES RESISTORS fIN = 100Hz fIN = 1kHz 10 10 THD+N (%) 1 0.1 0.1 fIN = 6kHz 0.01 0 200 400 600 800 1000 OUTPUT POWER (mW) 0.01 0 30 60 90 120 150 OUTPUT POWER (mW) fIN = 6kHz 14 ______________________________________________________________________________________ Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier Pin Description BUMP A1 A2 A3 A4 A5, B5 A6 B1 B2 B3 B4 B6 C1 C2, C3, C4, C5 C6 D1 D2 D3 D4 D5 D6 E1 E2 E3 E4 E5 E6 NAME C1P OUTLPVDDL OUTL+ PGNDR OUTRC1N RXINPGNDL RXIN+ PVDDR VSS GND OUTR+ HPL BIAS INB1 INA1 SCL SDA HPR VDD INB2 INA2 SHDN VCCIO Left-Speaker Negative Output Left-Channel Class D Power Supply. Bypass with a 1µF capacitor to PGNDL. Left-Speaker Positive Output Right-Channel Class D Power Ground Right-Speaker Negative Output Charge-Pump Flying Capacitor Negative Terminal. Connect a 1µF capacitor between C1P and C1N. Receiver Bypass Negative Input Left-Channel Class D Power Ground Receiver Bypass Positive Input Right-Channel Class D Power Supply. Bypass with a 1µF capacitor to PGNDL. Headphone Amplifier Negative Power Supply. Bypass with a 1µF capacitor to PGND. Analog Ground Right-Speaker Positive Output Headphone Amplifier Right Output Common-Mode Bias. Bypass to GND with a 1µF capacitor. Input B1. Left input or negative input. Input A1. Left input or negative input. Serial-Clock Input. Connect a pullup resistor from SDA to VCCIO. Serial-Data Input/Output. Connect a pullup resistor from SDA to VCCIO. Headphone Amplifier Left Output Analog Supply. Connect to PVDDL and PVDDR. Bypass with a 1µF capacitor to GND. Input B2. Right input or positive input. Input A2. Right input or positive input. Active-Low Shutdown Input Signal I2C Power Supply FUNCTION Charge-Pump Flying Capacitor Positive Terminal. Connect a 1µF capacitor between C1P and C1N. MAX9879 Detailed Description Signal Path The MAX9879 signal path consists of flexible inputs, signal mixing, volume control, and output amplifiers (Figures 1a, 1b, 1c). The inputs can be configured for single-ended or differential signals (Figure 2). The internal preamplifiers feature three programmable gain settings of 0dB, +5.5dB, and +20dB. Following preamplification, the input signals are mixed, volume adjusted, and routed to the headphone and speaker amplifiers based on the output mode configuration (see Table 6). The volume control stages provide up to 75dB attenuation. The headphone amplifiers provide +3dB of gain while the speaker amplifier provides +18dB of additional gain. When an input is configured as mono differential, it can be routed to both speakers or to both headphones. When an input is stereo, it is routed to either the stereo headphones or the stereo speakers. Simultaneous operation is also possible. If the right speaker amplifier is disabled then the left and right audio signals are summed into the left speaker amplifier and vice-versa. When the application does not require the use of both INA_ and INB_, the SNR of the MAX9879 is improved by deselecting the unused input through the I2C output mode register and AC-coupling the unused inputs to ground with a 330pF capacitor. The 330pF capacitor and the input resistance to the MAX9879 form a highpass filter preventing audible noise from coupling into the outputs. ______________________________________________________________________________________ 15 Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier MAX9879 STEREO MODE 1μF INA1 1μF L INPUT A INA2 R R L + CLASS AB HPR L CLASS AB HPL R + 1μF 1μF INB1 INB2 CLASS D L INPUT B R R CLASS D OUTRNOTE: STEREO SPEAKER OUTPUTS MAY BE SUMMED FOR MONO OUTPUT. L + OUTR+ OUTLOUTL+ Figure 1a. Stereo-Mode Signal Path MONO MODE 1μF INA1 1μF + INPUT A INA2 CLASS AB + HPR CLASS AB HPL OUTL+ 1μF 1μF INB1 INB2 CLASS D + INPUT B CLASS D OUTROUTR+ OUTL- Figure 1b. Mono-Mode Signal Path 16 ______________________________________________________________________________________ Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier MAX9879 MONO IN, STEREO IN, OUTPUT IN STEREO MODE 1μF INA1 1μF L INPUT A INA2 R R L + CLASS AB HPR L CLASS AB HPL R + 1μF 1μF INB1 INB2 CLASS D + INPUT B CLASS D OUTRNOTE: STEREO SPEAKER OUTPUTS MAY BE SUMMED FOR MONO OUTPUT. + OUTR+ OUTLOUTL+ Figure 1c. Mono INB, Stereo INA, Output in Stereo-Mode Signal Path ______________________________________________________________________________________ 17 Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier MAX9879 STEREO SINGLE-ENDED IN_2 (R) R TO MIXER IN_1 (L) L DIFFERENTIAL IN_2 (+) IN_1 (-) TO MIXER Figure 2. Differential and Stereo Single-Ended Input Configurations 18 ______________________________________________________________________________________ Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier Volume Control and Mute The MAX9879 features three Volume Control registers (see Table 4), allowing independent volume control of speaker and headphone amplifier outputs. There is one Speaker Volume Control register that evenly controls both speaker outputs. Two Headphone Volume Control registers provide independent control of each headphone output. Each volume control register provides 31 attenuation steps providing 0dB to -75dB (typ) of total attenuation and a mute function. interference (EMI) regulation standards. Limiting the dV/dt normally results in decreased efficiency. Maxim’s active emissions limiting circuitry actively limits the dV/dt of the rising and falling edge transitions, providing reduced EMI emissions, while maintaining up to 88% efficiency. In addition to active emission limiting, the MAX9879 features a patented spread-spectrum modulation mode that flattens the wideband spectral components. Proprietary techniques ensure that the cycle-to-cycle variation of the switching period does not degrade audio reproduction or efficiency (see the Typical Operating Characteristics). With spread-spectrum modulation, the switching frequency varies randomly by ±40kHz around the center frequency (700kHz). The effect is to reduce the peak energy at harmonics of the switching frequency. Above 10MHz, the wideband spectrum looks like white noise for EMI purposes (see Figure 4). MAX9879 Class D Speaker Amplifier The MAX9879 integrates a filterless Class D amplifier that offers much higher efficiency than Class AB without the typical disadvantages. The high efficiency of a Class D amplifier is due to the switching operation of the output stage transistors. In a Class D amplifier, the output transistors act as currentsteering switches and consume negligible additional power. Any power loss associated with the Class D output stage is mostly due to the I2R loss of the MOSFET on-resistance, and quiescent current overhead. The theoretical best efficiency of a linear amplifier is 78%, however, that efficiency is only exhibited at peak output power. Under normal operating levels (typical music reproduction levels), efficiency falls below 30%, whereas the MAX9879 still exhibits 88% efficiency under the same conditions (Figure 3). Speaker Current Limit Most applications do not enter current limit unless the output is short circuited or connected incorrectly. When the output current of the speaker amplifier exceeds the current limit (1.5A, typ) the MAX9879 disables the outputs for approximately 250µs. At the end of 250µs, the outputs are re-enabled, and if the fault condition still exists, the MAX9879 continues to disable and reenable the outputs until the fault condition is removed. Ultra-Low EMI Filterless Output Stage In traditional Class D amplifiers, the high dV/dt of the rising and falling edge transitions results in increased EMI emissions, which requires the use of external LC filters or shielding to meet EN55022 electromagneticMAX9877 EFFICIENCY vs. IDEAL CLASS EFFICIENCY 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 0.25 0.50 0.75 1.00 OUTPUT POWER (W) VDD = PVDD_ = 3.7V (MAX9879) VSUPPLY = 3.7V (IDEAL CLASS AB) IDEAL CLASS AB MAX9879 MAX9877 fig03 Bypass Mode The integrated DPST analog audio switch allows the MAX9879’s Class D amplifier to be bypassed. In bypass mode, the Class D amplifier is automatically disabled allowing an external amplifier to drive the speaker connected between OUTL+ and OUTL- through RXIN+ and RXIN- (see the Typical Application Circuit ). The bypass switch is enabled at startup. The switch can be opened or closed even when the MAX9879 is in software shutdown (see the I2C Register Description section). Unlike discrete solutions, the switch design reduces coupling of Class D switching noise to the RXIN_ inputs. This eliminates the need for a costly T-switch. The bypass switch is typically used with two 10Ω resistors connected to each input. These resistors, in combination with the switch on-resistance and an 8Ω load, approximate the 32Ω load expected by the external amplifier. Although not required, using the resistors optimizes THD+N. Drive RXIN+ and RXIN- with a low-impedance source to minimize noise on the pins. In applications that do not require the bypass mode, leave RXIN+ and RXINunconnected. 19 100 Figure 3. MAX9879 Efficiency vs. Class AB Efficiency ______________________________________________________________________________________ Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier MAX9879 40 TEST LIMIT 35 AMPLITUDE (dBμV/m) 30 25 20 MAX9879 OUTPUT 15 10 5 30 60 80 100 120 140 160 180 200 220 240 260 280 300 FREQUENCY (MHz) TEST LIMIT 40 AMPLITUDE (dBμV/m) 35 25 MAX9879 OUTPUT 20 15 10 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 FREQUENCY (MHz) Figure 4. EMI with 152mm of Speaker Cable DirectDrive Headphone Amplifier Traditional single-supply headphone amplifiers have outputs biased at a nominal DC voltage (typically half the supply). Large coupling capacitors are needed to block this DC bias from the headphone. Without these capacitors, a significant amount of DC current flows to the headphone, resulting in unnecessary power dissipation and possible damage to both the headphone and headphone amplifier. Maxim’s patented DirectDrive ® architecture uses a charge pump to create an internal negative supply voltage. This allows the headphone outputs of the MAX9879 to be biased at GND while operating from a single supply (Figure 5). Without a DC component, there is no need for the large DC-blocking capacitors. Instead of two large (220µF, typ) capacitors, the MAX9879 charge pump requires two small ceramic capacitors, DirectDrive is a registered trademark of Maxim Integrated Products, Inc. 20 conserving board space, reducing cost, and improving the frequency response of the headphone amplifier. See the Output Power vs. Load Resistance graph in the Typical Operating Characteristics for details of the possible capacitor sizes. There is a low DC voltage on the amplifier outputs due to amplifier offset. However, the offset of the MAX9879 is typically ±1.5mV, which, when combined with a 32Ω load, results in less than 47µA of DC current flow to the headphones. In addition to the cost and size disadvantages of the DC-blocking capacitors required by conventional headphone amplifiers, these capacitors limit the amplifier’s low-frequency response and can distort the audio signal. Previous attempts at eliminating the output-coupling capacitors involved biasing the headphone return (sleeve) to the DC bias voltage of the headphone amplifiers. This method raises some issues: ______________________________________________________________________________________ Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier 1) The sleeve is typically grounded to the chassis. Using the midrail biasing approach, the sleeve must be isolated from system ground, complicating product design. 2) During an ESD strike, the amplifier’s ESD structures are the only path to system ground. Thus, the amplifier must be able to withstand the full energy from an ESD strike. 3) When using the headphone jack as a line out to other equipment, the bias voltage on the sleeve may conflict with the ground potential from other equipment, resulting in possible damage to the amplifiers. The MAX9879 features a low-noise charge pump. The switching frequency of the charge pump is 1/2 of the Class D switching frequency, regardless of the operating mode. Since the Class D amplifiers are operated in spread-spectrum mode, the charge pump also switches with a spread-spectrum pattern. The nominal switching frequency is well beyond the audio range, and thus does not interfere with audio signals. The switch drivers feature a controlled switching speed that minimizes noise generated by turn-on and turn-off transients. By limiting the switching speed of the charge pump, the di/dt noise caused by the parasitic trace inductance is minimized. Although not typically required, additional high-frequency noise attenuation can be achieved by increasing the size of C2 (see the Typical Application Circuit ). The charge pump is active only in headphone modes. MAX9879 Headphone Current Limit The headphone amplifier current is limited to 140mA (typ). The current limit clamps the output current, which appears as clipping when the maximum current is exceeded. Shutdown Mode The MAX9879 features two ways of entering low-power shutdown: • The device can be placed in shutdown mode by writing to the SHDN bit in the Output Control Register. • The device can be placed in an ultra-low power shutdown mode by setting the SHDN pin to 0V. This completely disables the MAX9879 including the I 2 C interface. Click-and-Pop Suppression The MAX9879 features click-and-pop suppression that eliminates audible transients from occurring at startup and shutdown. Use the following procedure to start up the MAX9879: 1) Configure the desired output mode and preamplifier gain. 2) Set the SHDN bit to 1 to start up the amplifier. 3) Wait 10ms for the startup time to pass. 4) Increase the output volume to the desired level. To disable the device simply set SHDN to 0. During the startup period, the MAX9879 precharges the input capacitors to prevent clicks and pops. If the output amplifiers have been programmed to be active they are held in shutdown until the precharge period is complete. When power is initially applied to the MAX9879, the power-on-reset state of all three volume control registers is mute. For most applications, the volume can be set to the desired level once the device is active. If the clickand-pop is too high, step through intermediate volume settings with zero-crossing detection disabled. Stepping through higher volume settings has a greater impact on click-and-pop than lower volume settings. For the lowest possible click and pop, start up the device at minimum volume and then step through each volume setting until the desired setting is reached. Disable zerocrossing detection if no input signal is expected. VDD VOUT VDD/2 GND CONVENTIONAL DRIVER BIASING SCHEME +VDD VOUT GND -VDD DirectDrive BIASING SCHEME Figure 5. Traditional Amplifier Output vs. MAX9879 DirectDrive Output ______________________________________________________________________________________ 21 Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier MAX9879 I2C Interface I2C Address The slave address of the MAX9879 is 1001101R/(W) (write: 0x9A, read: 0x9B). Table 1. Register Map REGISTER Input Mode Control Speaker Volume Control Left Headphone Volume Control Right Headphone Volume Control Output Mode Control REGISTER ADDRESS 0x00 POR STATE 0x40 B7 0 B6 ZCD B5 ΔINA B4 ΔINB B3 B2 B1 B0 PGAINA PGAINB 0x01 0x00 0 0 0 SPKVOL 0x02 0x00 0 0 0 HPLVOL 0x03 0x00 0 0 0 HPRVOL 0x04 0x49 SHDN BYPASS 0 ENB ENA LSPK EN RSPK EN HPEN Table 2. Input Mode Control Register REGISTER 0x00 B7 0 B6 ZCD B5 ΔINA B4 ΔINB B3 PGAINA B2 B1 PGAINB B0 I2C Register Description Zero-Crossing Detection (ZCD) Zero-crossing detection limits distortion in the output signal during volume transitions by delaying the transition until the mixer output crosses the internal bias voltage. A timeout period (typically 60ms) forces the volume transition if the mixer output signal does not cross the bias voltage. 1 = Zero-crossing detection is enabled. 0 = Zero-crossing detection is disabled. 1 = IN_ is configured as a mono differential input with IN_2 as the positive and IN_1 as the negative input. 0 = IN_ is configured as a stereo single-ended input with IN_2 as the right and IN_1 as the left input. Differential Input Configuration (ΔIN_) The inputs INA_ and INB_ can be configured for mono differential or stereo single-ended operation. Preamplifier Gain (PGAIN_) The preamplifier gain of INA_ and INB_ can be programmed by writing to PGAIN_. 00 = 0dB 01 = +5.5dB 10 = +20dB 11 = Reserved 22 ______________________________________________________________________________________ Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier MAX9879 Table 3. Speaker/Left Headphone/Right Headphone Volume Control REGISTER 0x01 0x02 0x03 B7 0 0 0 B6 0 0 0 B5 0 0 0 B4 B3 B2 B1 B0 SVOL (Table 4) HPLVOL (Table 4) HPRVOL (Table 4) Volume Control The device has a separate volume control for left headphone, right headphone, and speaker amplifiers. The total system gain is a combination of the input gain, the volume control, and the output amplifier gain. Table 4 shows the volume settings for each volume control. Table 4. Volume Control Settings CODE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 _VOL B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 GAIN (dB) MUTE -75 -71 -67 -63 -59 -55 -51 -47 -44 -41 -38 -35 -32 -29 -26 CODE 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 _VOL B4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 GAIN (dB) -23 -21 -19 -17 -15 -13 -11 -9 -7 -6 -5 -4 -3 -2 -1 0 Table 5. Output Mode Control REGISTER 0x04 B7 SHDN B6 BYPASS B5 0 B4 ENB B3 ENA B2 LSPK EN B1 RSPK EN B0 HPEN Shutdown (SHDN) 1 = MAX9879 operational. 0 = MAX9879 in low-power shutdown mode. SHDN is an active-low shutdown bit that overrides all settings and places the entire device in low-power shutdown mode. The I2C interface is fully active in this shutdown mode and bypass mode remains operational. ______________________________________________________________________________________ 23 Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier MAX9879 Bypass Mode (BYPASS) 1 = MAX9879 bypass switches are closed and the Class D amplifier is disabled. 0 = Bypass mode disabled. This mode does not control headphone operation. proper slave address followed by the register address and then the data word. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted to the MAX9879 is 8 bits long and is followed by an acknowledge clock pulse. A master reading data from the MAX9879 transmits the proper slave address followed by a series of nine SCL pulses. The MAX9879 transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START (S) or REPEATED START (Sr) condition, a not acknowledge, and a STOP (P) condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500 Ω, is required on SDA. SCL operates only as an input. A pullup resistor, typically greater than 500Ω, is required on SCL if there are multiple masters on the bus, or if the single master has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX9879 from high voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Output Mode Control Register Speaker/Headphone Output Mode (_SPKEN/HPEN) The MAX9879 features independent enables and input selection for each speaker amplifier and the headphone amplifier. See Table 6 for a detailed description of the available modes. If the right speaker amplifier is disabled, the stereo signals are automatically summed to mono for the left output and vice-versa. Table 6. Speaker/Headphone Modes BIT LSPKEN RSPKEN HPEN ENA ENB DESCRIPTION Enable bit for left speaker Enable bit for right speaker Enable bit for headphone amplifier Enable bit for input A Enable bit for input B I2C Interface Specification The MAX9879 features an I2C/SMBus™-compatible, 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the MAX9879 and the master at clock rates up to 400kHz. Figure 6 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. The master device writes data to the MAX9879 by transmitting the Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the S TART and STOP Conditions section). START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START (S) condition is a high-to-low transition on SDA with SCL high. A STOP (P) condition is a low-tohigh transition on SDA while SCL is high (Figure 7). SDA tSU:DAT tLOW SCL tHD:STA tR START CONDITION tHIGH tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD:DAT tSU:STA tBUF tSU:STA tSU:STO Figure 6. 2-Wire Interface Timing Diagram SMBus is a trademark of Intel Corp. 24 ______________________________________________________________________________________ Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier A START (S) condition from the master signals the beginning of a transmission to the MAX9879. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START (Sr) condition is generated instead of a STOP condition. Early STOP Conditions The MAX9879 recognizes a STOP (P) condition at any point during data transmission except if the STOP (P) condition occurs in the same high pulse as a START (S) condition. For proper operation, do not send a STOP (P) condition during the same SCL high pulse as the START (S) condition. Slave Address The MAX9879 is preprogrammed with a slave address of 1001101R/(W). The address is defined as the seven most significant bits (MSBs) followed by the Read/Write bit. Setting the Read/Write bit to 1 configures the MAX9879 for read mode. Setting the Read/Write bit to 0 configures the MAX9879 for write mode. The address is the first byte of information sent to the MAX9879 after the START (S) condition. Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the MAX9879 uses to handshake receipt each byte of data when in write mode (see Figure 8). The MAX9879 pulls down SDA during the entire master-generated 9th clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master may retry communication. The master pulls down SDA during the ninth clock cycle to acknowledge receipt of data when the MAX9879 is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not acknowledge is sent when the master reads the final byte of data from the MAX9879, followed by a STOP (P) condition. Write Data Format A write to the MAX9879 includes transmission of a START (S) condition, the slave address with the R/W bit set to 0, one byte of data to configure the internal register address pointer, one or more bytes of data, and a STOP (P) condition. Figure 9 illustrates the proper frame format for writing one byte of data to the MAX9879 S Sr P SCL SDA Figure 7. START (S), STOP (P), and REPEATED START (Sr) Conditions CLOCK PULSE FOR ACKNOWLEDGMENT START CONDITION SCL 1 2 8 NOT ACKNOWLEDGE 9 SDA ACKNOWLEDGE Figure 8. Acknowledge ______________________________________________________________________________________ 25 Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier MAX9879 MAX9879. Figure 10 illustrates the frame format for writing n bytes of data to the MAX9879. The slave address with the R/W bit set to 0 indicates that the master intends to write data to the MAX9879. The MAX9879 acknowledges receipt of the address byte during the master-generated 9th SCL pulse. The second byte transmitted from the master configures the MAX9879’s internal register address pointer. The pointer tells the MAX9879 where to write the next byte of data. An acknowledge pulse is sent by the MAX9879 upon receipt of the address pointer data. The third byte sent to the MAX9879 contains the data that is written to the chosen register. An acknowledge pulse from the MAX9879 signals receipt of the data byte. The address pointer autoincrements to the next register address after each received data byte. This autoincrement feature allows a master to write to sequential registers within one continuous frame. Figure 10 illustrates how to write to multiple registers with one frame. The master signals the end of transmission by issuing a STOP (P) condition. Register addresses greater than 0x04 are reserved. Do not write to these addresses. ACKNOWLEDGE FROM MAX9879 B7 ACKNOWLEDGE FROM MAX9877 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9877 REGISTER ADDRESS A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P B6 B5 B4 B3 B2 B1 B0 Figure 9. Writing One Byte of Data to the MAX9879 ACKNOWLEDGE FROM MAX9879 ACKNOWLEDGE FROM MAX9879 S SLAVE ADDRESS R/W 0 ACKNOWLEDGE FROM MAX9879 A REGISTER ADDRESS A B7 B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX9879 B7 B6 B5 B4 B3 B2 B1 B0 DATA BYTE 1 1 BYTE A DATA BYTE n 1 BYTE A P AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 10. Writing n Bytes of Data to the MAX9879 NOT ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MAX9879 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9879 REGISTER ADDRESS A ACKNOWLEDGE FROM MAX9879 Sr SLAVE ADDRESS R/W 1 A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P REPEATED START Figure 11. Reading One Indexed Byte of Data from the MAX9879 26 ______________________________________________________________________________________ Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier MAX9879 ACKNOWLEDGE FROM MAX9879 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9879 REGISTER ADDRESS A ACKNOWLEDGE FROM MAX9879 Sr SLAVE ADDRESS R/W 1 A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P REPEATED START Figure 12. Reading n Bytes of Indexed Data from the MAX9879 Read Data Format Send the slave address with the R/W bit set to 1 to initiate a read operation. The MAX9879 acknowledges receipt of its slave address by pulling SDA low during the 9th SCL clock pulse. A START (S) command followed by a read command resets the address pointer to register 0x00. The first byte transmitted from the MAX9879 is the contents of register 0x00. Transmitted data is valid on the rising edge of SCL. The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP (P) condition can be issued after any number of read data bytes. If a STOP (P) condition is issued followed by another read operation, the first data byte to be read will be from register 0x00. The address pointer can be preset to a specific register before a read command is issued. The master presets the address pointer by first sending the MAX9879‘s slave address with the R/W bit set to 0 followed by the register address. A REPEATED START (Sr) condition is then sent followed by the slave address with the R/W bit set to 1. The MAX9879 then transmits the contents of the specified register. The address pointer autoincrements after transmitting the first byte. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP (P) condition. Figure 11 illustrates the frame format for reading one byte from the MAX9879. Figure 12 illustrates the frame format for reading multiple bytes from the MAX9879. OUT+ MAX9879 OUT- Figure 13. Optional Ferrite Bead Filter filters add cost, increase the solution size of the amplifier, and can decrease efficiency and THD+N performance. The traditional PWM scheme uses large differential output swings (2 x VDD(P-P)) and causes large ripple currents. Any parasitic resistance in the filter components results in a loss of power, lowering the efficiency. The MAX9879 does not require an output filter. The device relies on the inherent inductance of the speaker coil and the natural filtering of both the speaker and the human ear to recover the audio component of the square-wave output. Eliminating the output filter results in a smaller, less costly, more efficient solution. Because the frequency of the MAX9879 output is well beyond the bandwidth of most speakers, voice coil movement due to the square-wave frequency is very small. Although this movement is small, a speaker not designed to handle the additional power can be damaged. For optimum results, use a speaker with a series inductance > 10µH. Typical 8Ω speakers exhibit series inductances in the 20µH to 100µH range. Component Selection Optional Ferrite Bead Filter In applications where speaker leads exceed 20mm, additional EMI suppression can be achieved by using a filter constructed from a ferrite bead and a capacitor to ground. A ferrite bead with low DC resistance, highfrequency (> 1.176MHz) impedance of 100Ω to 600Ω, and rated for at least 1A should be used. The capacitor value varies based on the ferrite bead chosen and the Applications Information Filterless Class D Operation Traditional Class D amplifiers require an output filter to recover the audio signal from the amplifier’s output. The ______________________________________________________________________________________ 27 Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier MAX9879 actual speaker lead length. Select a capacitor less than 1nF based on EMI performance. RF SUSCEPTIBILITY EFFICIENCY (dBμ) Input Capacitor An input capacitor, CIN, in conjunction with the input impedance of the MAX9879 forms a highpass filter that removes the DC bias from an incoming signal. The ACcoupling capacitor allows the amplifier to automatically bias the signal to an optimum DC level. Assuming zero source impedance, the -3dB point of the highpass filter is given by: f−3dB = 1 2πRINCIN -10 -30 -50 -70 -90 -110 -130 -150 10 100 1k FREQUENCY (Hz) 10k NOISE FLOOR MAX9879 THRESHOLD OF HEARING Choose CIN so that f-3dB is well below the lowest frequency of interest. Use capacitors whose dielectrics have low-voltage coefficients, such as tantalum or aluminum electrolytic. Capacitors with high-voltage coefficients, such as ceramics, may result in increased distortion at low frequencies. 100k Figure 14. MAX9879 Susceptibility to a GSM Cell Phone Radio BIAS Capacitor BIAS is the output of the internally generated DC bias voltage. The BIAS bypass capacitor, CBIAS, reduces power supply and other noise sources at the common-mode bias node. Bypass BIAS with a 1µF capacitor to GND. Charge-Pump Capacitor Selection Use capacitors with an ESR less than 100mΩ for optimum performance. Low-ESR ceramic capacitors minimize the output resistance of the charge pump. Most surfacemount ceramic capacitors satisfy the ESR requirement. For best performance over the extended temperature range, select capacitors with an X7R dielectric. Flying Capacitor (C1) The value of the flying capacitor (C1) affects the output resistance of the charge pump. A C1 value that is too small degrades the device’s ability to provide sufficient current drive, which leads to a loss of output voltage. Increasing the value of C1 reduces the charge-pump output resistance to an extent. Above 1µF, the on-resistance of the switches and the ESR of C1 and C2 dominate. Output Holding Capacitor (C2) The output capacitor value and ESR directly affect the ripple at VSS. Increasing the value of C2 reduces output ripple. Likewise, decreasing the ESR of C2 reduces both ripple and output resistance. Lower capacitance values can be used in systems with low maximum output power levels. See the Output Power vs. Load Resistance graph in the Typical Operating Characteristics. PVDD Bulk Capacitor (C3) In addition to the recommended PVDD bypass capacitance, bulk capacitance equal to C3 should be used. Place the bulk capacitor as close as possible to the device. Supply Bypassing, Layout, and Grounding Proper layout and grounding are essential for optimum performance. Use wide traces for the power-supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. Wide traces also aid in moving heat away from the package. Proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any switching noise from coupling into the audio signal. Connect PGND and GND together at a single point on the PCB. Route all traces that carry switching transients away from GND and the traces/components in the audio signal path. Connect the PVDD_ pins to a 2.7V to 5.5V source. Bypass PVDD_ to PGND pin with a 1µF ceramic capacitor. Additional bulk capacitance should be used to prevent power supply pumping. Bypass PVDD_ to the PGND pin with a 1µF ceramic capacitor. Additional bulk capacitance should be used to prevent powersupply pumping. Place the bypass capacitors as close as possible to the MAX9879. Connect VDD to PVDD_. Bypass VDD to GND with a 1µF capacitor. Place the bypass capacitors as close as possible to the MAX9879. 28 ______________________________________________________________________________________ MAX9877 fig14 Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier RF Susceptibility GSM radios transmit using time-division multiple access (TDMA) with 217Hz intervals. The result is an RF signal with strong amplitude modulation at 217Hz that is easily demodulated by audio amplifiers. Figure 14 shows the susceptibility of the MAX9879 to a transmitting GSM radio placed in close proximity. Although there is measurable noise at 217Hz and its harmonics, the noise is well below the threshold of hearing using typical headphones. In RF applications, improvements to both layout and component selection decreases the MAX9879’s susceptibility to RF noise and prevent RF signals from being demodulated into audible noise. Trace lengths should be kept below 1/4 the wavelength of the RF frequency of interest. Minimizing the trace lengths prevents them from functioning as antennas and coupling RF signals into the MAX9879. The wavelength λ in meters is given by: λ = c/f where c = 3 x 108 m/s, and f = the RF frequency of interest. Route audio signals on middle layers of the PCB to allow ground planes above and below shield them from RF interference. Ideally the top and bottom layers of the PCB should primarily be ground planes to create effective shielding. Additional RF immunity can also be obtained from relying on the self-resonant frequency of capacitors as it exhibits the frequency response similar to a notch filter. Depending on the manufacturer, 10pF to 20pF capacitors typically exhibit self resonance at RF frequencies. These capacitors, when placed at the input pins, can effectively shunt the RF noise at the inputs of the MAX9879. For these capacitors to be effective, they must have a low-impedance, low-inductance path to the ground plane. Do not use microvias to connect to the ground plane as these vias do not conduct well at RF frequencies. MAX9879 45±5μm 250μm Figure 15. PCB Footprint Recommendation Diagram UCSP Applications Information For the latest application details on UCSP construction, dimensions, tape carrier information, PCB techniques, bump-pad layout, and recommended reflow temperature profile, as well as the latest information on reliability testing results, refer to the Application Note 1891: Understanding the Basics of the Wafer-Level ChipScale Package (WL-CSP) on Maxim’s website at www.maxim-ic.com/ucsp. See Figure 15 for the recommended PCB footprint for the MAX9879. ______________________________________________________________________________________ 29 Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier MAX9879 Typical Application Circuit 2.7V TO 5.5V 1.7V TO 3.6V C2 1μF VSS C1 C1N B1 C1 1μF C1P A1 1μF CHARGE PUMP VCCIO E6 0.1μF 1μF C3 1μF PVDDL A3 B6 PVDDR C3 1μF VDD E2 MAX9879 -75dB TO 0dB 3dB E1 HPR INA2 E4 INPUT A 0dB/+5.5dB/+20dB 3dB -75dB TO 0dB INB2 E3 INPUT B 0dB/+5.5dB/+20dB CLASS D MODULATOR +18dB -75dB TO 0dB E5 D2 D6 D5 CLASS D MODULATOR +18dB I2C CONTROL BYPASS -75dB TO 0dB A4 OUTL+ A2 OUTLC6 OUTR+ A6 OUTRD1 HPL 1μF 1μF INA1 D4 CONNECT TO VCCIO FOR 1μF NORMAL OPERATION INB1 D3 SHDN BIAS 1μF SDA SCL 10Ω RXIN+ B4 BASEBAND RECEIVER AMPLIFIER 10Ω RXIN- B2 C2, C3, C4, C5 A5, B5 B3 GND PGNDR PGNDL Chip Information PROCESS: BiCMOS 30 ______________________________________________________________________________________ Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 30 NCSP PACKAGE CODE R302A3+1 DOCUMENT NO. 21-0432 MAX9879 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. bpitchcontrol UCSP.EPS