MAXQ61CX

19-5231; Rev 0; 4/10 16-Bit Microcontroller with Infrared Module General Description The MAXQ61C is a low-power, 16-bit MAXQ® microcontroller designed for low-power applications including universal remote controls, consumer electronics, and white goods. The device combines a powerful 16-bit RISC microcontroller and integrated peripherals including two universal synchronous/asynchronous receivertransmitters (USARTs) and an SPI™ master/slave communications port, along with an IR module with carrier frequency generation and flexible port I/O capable of multiplexed keypad control. The device includes 80KB of ROM memory and 2KB of data SRAM. For the ultimate in low-power battery-operated performance, the device includes an ultra-low-power stop mode (0.2µA typ). In this mode, the minimum amount of circuitry is powered. Wake-up sources include external interrupts, the power-fail interrupt, and a timer interrupt. The microcontroller runs from a wide 1.70V to 3.6V operating voltage. S 1.70V to 3.6V Operating Voltage S 33 Total Instructions for Simplified Programming S Three Independent Data Pointers Accelerate Data S S S S Features S High-Performance, Low-Power, 16-Bit RISC Core S DC to 12MHz Operation Across Entire Operating Range MAXQ61C S Applications Remote Controls Battery-Powered Portable Equipment Consumer Electronics Home Appliances White Goods S Movement with Automatic Increment/Decrement Dedicated Pointer for Direct Read from Code Space 16-Bit Instruction Word, 16-Bit Data Bus 16 x 16-Bit General-Purpose Working Registers Memory Features 80KB Application ROM 2KB Data SRAM Additional Peripherals Power-Fail Warning Power-On Reset (POR)/Brownout Reset Automatic IR Carrier Frequency Generation and Modulation Two 16-Bit Programmable Timers/Counters with Prescaler and Capture/Compare One SPI Port and Two USART Ports Programmable Watchdog Timer 8kHz Nanopower Ring Oscillator Wake-Up Timer Up to 32 General-Purpose I/Os (J, K, and X Versions Only) Low Power Consumption 0.2µA (typ), 2.0µA (max) in Stop Mode, TA = +25NC, Power-Fail Monitor Disabled 2.0mA (typ) at 12MHz in Active Mode Ordering Information/Selector Guide PART MAXQ61CA-xxxx+ MAXQ61CE-xxxx+ MAXQ61CJ-xxxx+ MAXQ61CK-xxxx+ MAXQ61CX-xxxx+ TEMP RANGE 0NC to +70NC 0NC to +70NC 0NC to +70NC 0NC to +70NC 0NC to +70NC OPERATING VOLTAGE (V) 1.7 to 3.6 1.7 to 3.6 1.7 to 3.6 1.7 to 3.6 1.7 to 3.6 PROGRAM MEMORY (KB) 80 ROM 80 ROM 80 ROM 80 ROM 80 ROM DATA MEMORY (KB) 2 2 2 2 2 GPIO 20 20 32 32 32 PIN-PACKAGE 32 TQFN-EP* 32 LQFP 44 TQFN-EP* 44 TQFP Bare die Note: Contact the factory for information about masked ROM devices. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. MAXQ is a registered trademark of Maxim Integrated Products, Inc. SPI is a trademark of Motorola, Inc. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. _______________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 16-Bit Microcontroller with Infrared Module MAXQ61C TABLE OF CONTENTS Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SPI Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Stack Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Utility ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 IR Carrier Generation and Modulation Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Carrier Generation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 IR Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 IR Transmit—Independent External Carrier and Modulator Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 IR Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Carrier Burst-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 16-Bit Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power-Fail Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Grounds and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Deviations from the MAXQ610 User’s Guide for the MAXQ61C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Development and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2 ______________________________________________________________________________________ 16-Bit Microcontroller with Infrared Module MAXQ61C LIST OF FIGURES Figure 1. IR Transmit Frequency Shifting Example (IRCFME = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 2. IR Transmit Carrier Generation and Carrier Modulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 3. IR Transmission Waveform (IRCFME = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 4. External IRTXM (Modulator) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 5. IR Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 6. Receive Burst-Count Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7. SPI Master Communication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. SPI Slave Communication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9. On-Chip Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 10. Power-Fail Detection During Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 11. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 12. Stop Mode Power-Fail Detection with Power-Fail Monitor Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 LIST OF TABLES Table 1. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 2. USART Mode Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 3. Power-Fail Detection States During Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 4. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 5. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . 24 _______________________________________________________________________________________ 3 16-Bit Microcontroller with Infrared Module MAXQ61C ABSOLUTE MAXIMUM RATINGS Voltage Range on VDD with Respect to GND ..... -0.3V to +3.6V Voltage Range on Any Lead with Respect to GND Except VDD ............... -0.3V to (VDD + 0.5V) Continuous Power Dissipation (TA = +70NC) 32-Pin TQFN (single-layer board) (derate 21.3mW/NC above +70NC).......................... 1702.1mW 32-Pin TQFN (multilayer board) (derate 34.5mW/NC above +70NC).......................... 2758.6mW 32-Pin LQFP (multilayer board) (derate 20.7mW/NC above +70NC).......................... 1652.9mW 44-Pin TQFN (single-layer board) (derate 27mW/NC above +70NC)............................. 2162.2mW 44-Pin TQFN (multilayer board) (derate 37mW/NC above +70NC)................................ 2963mW Operating Temperature Range ............................. 0NC to +70NC Storage Temperature Range............................ -65NC to +150NC Lead Temperature (excluding dice; soldering, 10s) ......+300NC Soldering Temperature (reflow) ......................................+260NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (VDD = VRST to 3.6V, TA = 0NC to +70NC, unless otherwise noted.) (Note 1) PARAMETER Supply Voltage 1.8V Internal Regulator Power-Fail Warning Voltage for Supply Power-Fail Reset Voltage POR Voltage RAM Data-Retention Voltage Active Current SYMBOL VDD VREG18 VPFW VRST VPOR VDRV IDD_1 IS1 Stop-Mode Current IS2 Current Consumption During Power-Fail Power Consumption During POR Stop-Mode Resume Time Power-Fail Monitor Startup Time Power-Fail Warning Detection Time Input Low Voltage for IRTX, IRRX, RESET, and All Port Pins Input High Voltage for IRTX, IRRX, RESET, and All Port Pins Input Hysteresis (Schmitt) Input Low Voltage for HFXIN Input High Voltage for HFXIN 4 Power-Fail On Monitors VDD Monitors VDD (Note 2) Monitors VDD (Note 3) Sysclk = 12MHz (Note 4) Power-Fail Off TA = +25NC TA = 0°C +70NC TA = +25NC TA = 0°C to +70NC CONDITIONS MIN VRST 1.62 1.75 1.64 1.0 1.0 2.5 0.15 0.15 22 27.6 [(3 x IS2) + ((PCI - 3) x (IS1 + INANO))]/PCI 100 375 + (8192 x tHFXIN) (Note 3) (Notes 3, 7) 10 VGND 0.7 x VDD VDD = 3.3V, TA = +25NC VGND 0.7 x VDD 300 0.3 x VDD VDD 0.3 x VDD VDD 150 3.75 2.0 8 31 38 FA FA 1.8 1.8 1.67 TYP MAX 3.6 1.98 1.85 1.70 1.42 UNITS V V V V V V mA IPFR (Note 5) IPOR tON tPFM_ON tPFW VIL VIH VIHYS VIL_HFXIN VIH_HFXIN (Note 6) nA Fs Fs Fs V V mV V V ______________________________________________________________________________________ 16-Bit Microcontroller with Infrared Module RECOMMENDED OPERATING CONDITIONS (continued) (VDD = VRST to 3.6V, TA = 0NC to +70NC, unless otherwise noted.) (Note 1) PARAMETER IRRX Input Filter Pulse-Width Reject IRRX Input Filter Pulse-Width Accept Output Low Voltage for IRTX SYMBOL tIRRX_R tIRRX_A VDD = 3.6V, IOL = 25mA (Note 3) VOL_IRTX VDD = 2.35V, IOL = 10mA (Note 3) VDD = 1.85V, IOL = 4.5mA Output Low Voltage for RESET and All Port Pins (Note 8) Output High Voltage for IRTX and All Port Pins Input/Output Pin Capacitance for All Port Pins Input Leakage Current Input Pullup Resistor for RESET, IRTX, IRRX, P0, P1, P2 Crystal/Resonator Crystal/Resonator Period Crystal/Resonator Warmup Time Oscillator Feedback Resistor EXTERNAL CLOCK INPUT External Clock Frequency External Clock Period External Clock Duty Cycle System Clock Frequency System Clock Period NANOPOWER RING TA = +25NC Nanopower Ring Frequency Nanopower Ring Duty Cycle Nanopower Ring Current WAKE-UP TIMER Wake-Up Timer Interval IR Carrier Frequency fIR (Note 3) fCK/2 Hz 5 tWAKEUP 1/fNANO 65,535/ fNANO s fNANO tNANO INANO TA = +25NC, VDD = POR voltage (Note 3) (Note 3) Typical at VDD = 1.64V, TA = +25°C (Note 3) 3.0 1.7 40 40 8.0 2.4 60 400 20.0 kHz % nA fXCLK tXCLK tXCLK_DUTY (Note 3) fCK tCK HFXOUT = GND 45 fHFXIN fXCLK 1/fCK DC 1/fXCLK 55 12 MHz ns % MHz ns VDD = 3.6V, IOL = 11mA (Note 3) VOL VDD = 2.35V, IOL = 8mA (Note 3) VDD = 1.85V, IOL = 4.5mA VOH CIO IL RPU IOH = -2mA (Note 3) Internal pullup disabled VDD = 3.0V, VOL = 0.4V (Note 3) VDD = 2.0V, VOL = 0.4V -100 16 17 DC 1/fHFXIN From initial oscillation (Note 3) 0.5 8192 x tHFXIN 1.0 1.5 28 30 VDD - 0.5 0.4 0.4 0.4 300 1.0 1.0 1.0 0.5 0.5 0.5 VDD 15 +100 39 41 12 V pF nA kW MHz ns ms MW V V CONDITIONS MIN TYP MAX 50 UNITS ns ns MAXQ61C EXTERNAL CRYSTAL/RESONATOR fHFXIN tHFXIN tXTAL_RDY ROSCF _______________________________________________________________________________________ 16-Bit Microcontroller with Infrared Module MAXQ61C SPI ELECTRICAL CHARACTERISTICS (VDD = VRST to 3.6V, TA = 0NC to +70NC, unless otherwise noted.) (Note 9) PARAMETER SPI Master Operating Frequency SPI Slave Operating Frequency SPI I/O Rise/Fall Time SCLK Output Pulse-Width High/ Low MOSI Output Hold Time After SCLK Sample Edge MOSI Output Valid to Sample Edge MISO Input Valid to SCLK Sample Edge Rise/Fall Setup MISO Input to SCLK Sample Edge Rise/Fall Hold SCLK Inactive to MOSI Inactive SCLK Input Pulse-Width High/Low SSEL Active to First Shift Edge MOSI Input to SCLK Sample Edge Rise/Fall Setup MOSI Input from SCLK Sample Edge Transition Hold MISO Output Valid After SCLK Shift Edge Transition SSEL Inactive SCLK Inactive to SSEL Rising MISO Output Disabled After SSEL Edge Rise SYMBOL 1/tMCK 1/tSCK tSPI_RF tMCH, tMCL tMOH tMOV tMIS tMIH tMLH tSCH, tSCL tSSE tSIS tSIH tSOV tSSH tSD tSLH tCK + tSPI_RF tSPI_RF 2tCK + 2tSPI_RF tSPI_RF tSPI_RF tSPI_RF 2tSPI_RF CL = 15pF, pullup = 560W 8.3 tMCK/2 tSPI_RF tMCK/2 tSPI_RF tMCK/2 tSPI_RF 25 0 tMCK/2 tSPI_RF tSCK/2 CONDITIONS MIN TYP MAX fCK/2 fCK/4 23.6 UNITS MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1: Specifications to 0NC are guaranteed by design and are not production tested. Typical = +25NC, VDD = +3.3V, unless otherwise noted. Note 2: The power-fail reset and POR detectors are designed to operate in tandem to ensure that one or both of these signals is active at all times when VDD < VRST, ensuring the device maintains the reset state until minimum operating voltage is achieved. Note 3: Guaranteed by design and not production tested. Note 4: Measured on the VDD pin and the device not in reset. All inputs are connected to GND or VDD. Outputs do not source/ sink any current. The device is executing code from ROM memory. Note 5: The power-check interval (PCI) can be set to always on, or to 1024, 2048, or 4096 nanopower ring clock cycles. Note 6: Current consumption during POR when powering up while VDD is less than the POR release voltage. Note 7: The minimum amount of time that VDD must be below VPFW before a power-fail event is detected; refer to the MAXQ610 User’s Guide for details. Note 8: The maximum total current, IOH(MAX) and IOL(MAX), for all listed outputs combined should not exceed 32mA to satisfy the maximum specified voltage drop. This does not include the IRTX output. Note 9: AC electrical specifications are guaranteed by design and are not production tested. 6 ______________________________________________________________________________________ 16-Bit Microcontroller with Infrared Module Pin Configurations P1.2/INT2 P1.1/INT1 P1.0/INT0 P2.6/TMS P2.7/TDO P2.4/TCK P2.5/TDI MAXQ61C P1.2/INT2 P1.1/INT1 P1.0/INT0 P2.6/TMS P2.7/TDO P2.4/TCK P2.5/TDI TOP VIEW GND TOP VIEW 24 23 22 21 20 19 18 24 P1.3/INT3 25 P1.4/INT4 26 P1.5/INT5 27 P1.6/INT6 28 P1.7/INT7 29 GND 30 IRTX 31 IRRX 32 1 P0.0/IRTXM 23 22 21 20 19 18 17 16 15 14 N.C. N.C. HFXOUT HFXIN GND REGOUT VDD RESET P1.3/INT3 25 P1.4/INT4 26 P1.5/INT5 27 P1.6/INT6 28 P1.7/INT7 29 GND 30 IRTX 31 IRRX 32 GND 17 16 15 14 N.C. N.C. HFXOUT HFXIN GND REGOUT VDD RESET MAXQ61C 13 12 11 MAXQ61C 13 12 11 10 9 + 2 P0.1/RX0 3 P0.2/TX0 4 P0.3/RX1 5 P0.4/TX1 6 P0.5/TBA0/TBA1 EP 10 9 7 P0.6/TBB0 8 P0.7/TBB1 + 1 P0.0/IRTXM 2 P0.1/RX0 3 P0.2/TX0 4 P0.3/RX1 5 P0.4/TX1 6 P0.5/TBA0/TBA1 7 P0.6/TBB0 8 P0.7/TBB1 TQFN (5mm × 5mm) P3.7/INT15 P3.6/INT14 P1.0/INT0 P2.6/TMS P2.7/TDO P2.4/TCK P2.5/TDI GND N.C. 33 32 31 30 29 28 27 26 N.C. TOP VIEW 25 24 23 P3.5/INT13 LQFP (7mm × 7mm) P1.1/INT1 P1.2/INT2 P1.3/INT3 P1.4/INT4 P1.5/INT5 P1.6/INT6 P1.7/INT7 GND IRTX IRRX P0.0/IRTXM 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 P3.4/INT12 P3.3/INT11 P3.2/INT10 P3.1/INT9 P3.0/INT8 HFXOUT HFXIN GND REGOUT VDD RESET MAXQ61C + 1 2 3 4 5 6 7 8 9 EP 13 12 10 P2.0/MOSI P2.1/MISO P0.5/TBA0/TBA1 TQFN (7mm × 7mm) _______________________________________________________________________________________ P2.2/SCLK P0.6/TBB0 P0.7/TBB1 P2.3/SSEL P0.1/RX0 P0.2/TX0 P0.3/RX1 P0.4/TX1 11 7 16-Bit Microcontroller with Infrared Module MAXQ61C Pin Configurations (continued) P3.7/INT15 P3.6/INT14 24 P3.5/INT13 23 22 21 20 19 18 P3.4/INT12 P3.3/INT11 P3.2/INT10 P3.1/INT9 P3.0/INT8 HFXOUT HFXIN GND REGOUT VDD RESET 17 16 15 14 13 12 1 P0.1/RX0 2 P0.2/TX0 3 P0.3/RX1 4 P0.4/TX1 5 P0.5/TBA0/TBA1 6 P0.6/TBB0 7 P0.7/TBB1 8 P2.0/MOSI 9 P2.1/MISO 10 P2.2/SCLK 11 P2.3/SSEL P1.0/INT0 P2.6/TMS P2.7/TDO P2.4/TCK P2.5/TDI GND N.C. 27 TOP VIEW 33 P1.1/INT1 34 P1.2/INT2 35 P1.3/INT3 36 P1.4/INT4 37 P1.5/INT5 38 P1.6/INT6 39 P1.7/INT7 40 GND 41 IRTX 42 IRRX 43 P0.0/IRTXM 44 32 31 30 29 28 N.C. 26 25 MAXQ61C + TQFP (10mm × 10mm) NOTE: CONTACT FACTORY FOR BARE DIE PAD CONFIGURATION. 8 ______________________________________________________________________________________ 16-Bit Microcontroller with Infrared Module Pin Description PIN BARE DIE 32 TQFNEP/LQFP 10 12 17, 30 44 TQFNEP/TQFP 13 15 28, 41 NAME POWER PINS 14 16 27, 40 VDD GND GND Supply Voltage Ground. Connect directly to the ground plane. Ground. For low-current applications (< 10mA of GPIO current, exclusive of IRTX sink current), these pins can be left unconnected. If used, they should be connected directly to the ground plane. 1.8V Regulator Output. This pin must be connected to ground through a 1.0FF (ESR: 2–10W) external ceramic-chip capacitor. The capacitor must be placed as close to this pin as possible. No devices other than the capacitor should be connected to this pin. Exposed Pad (TQFN Only). For low-current applications (< 10mA of GPIO current, exclusive of IRTX sink current), these pins can be left unconnected. If used, they should be connected directly to the ground plane. RESET PINS Digital, Active-Low Reset Input/Output. The device remains in reset as long as this pin is low and begins executing from the utility ROM at address 8000h when this pin returns to a high state. The pin includes pullup current source; if this pin is driven by an external device, it should be driven by an open-drain source capable of sinking in excess of 4mA. This pin can be left unconnected if there is no need to place the device in a reset state using an external signal. This pin is driven low as an output when an internal reset condition occurs. CLOCK PINS 17 18 13 14 16 17 HFXIN HFXOUT High-Frequency Crystal Input. Connect an external crystal or resonator between HFXIN and HFXOUT for use as the high-frequency system clock. Alternatively, HFXIN is the input for an external, high-frequency clock source when HFXOUT is connected to ground. IR FUNCTION PINS IR Transmit Output. IR transmission pin capable of sinking 25mA. This pin defaults to a high-impedance input with the weak pullup disabled during all forms of reset. Software must configure this pin after release from reset to remove the high-impedance input condition. IR Receive Input. This pin defaults to a high-impedance input with the weak pullup disabled during all forms of reset. Software must configure this pin after release from reset to remove the high-impedance input condition. FUNCTION MAXQ61C 15 11 14 REGOUT — — — EP 13 9 12 RESET 41 31 42 IRTX 42 32 43 IRRX _______________________________________________________________________________________ 9 16-Bit Microcontroller with Infrared Module MAXQ61C Pin Description (continued) PIN BARE DIE 32 TQFNEP/LQFP 44 TQFNEP/TQFP NAME FUNCTION GENERAL-PURPOSE I/O AND SPECIAL FUNCTION PINS Port 0 General-Purpose, Digital I/O Pins. These port pins function as general-purpose I/O pins with their input and output states controlled by the PD0, PO0, and PI0 registers. All port pins default to high-impedance mode after a reset. Software must configure these pins after release from reset to remove the high-impedance condition. All special functions must be enabled from software before they can be used. GPIO PORT PIN 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 44 1 2 3 4 5 6 7 P0.0/IRTXM P0.1/RX0 P0.2/TX0 P0.3/RX1 P0.4/TX1 P0.5/TBA0/ TBA1 P0.6/TBB0 P0.7/TBB1 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 SPECIAL FUNCTION IR Modulator Output USART 0 Receive USART 0 Transmit USART 1 Receive USART 1 Transmit Type B Timer 0 Pin A or Type B Timer 1 Pin A Type B Timer 0 Pin B Type B Timer 1 Pin B Port 1 General-Purpose, Digital I/O Pins with Interrupt Capability. These port pins function as general-purpose I/O pins with their input and output states controlled by the PD1, PO1, and PI1 registers. All port pins default to high-impedance mode after a reset. Software must configure these pins after release from reset to remove the high-impedance condition. All external interrupts must be enabled from software before they can be used. GPIO PORT PIN 32 33 34 35 36 37 38 39 22 23 24 25 26 27 28 29 33 34 35 36 37 38 39 40 P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT3 P1.4/INT4 P1.5/INT5 P1.6/INT6 P1.7/INT7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 EXTERNAL INTERRUPT INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 10 _____________________________________________________________________________________ 16-Bit Microcontroller with Infrared Module Pin Description (continued) PIN BARE DIE 32 TQFNEP/LQFP 44 TQFNEP/TQFP NAME FUNCTION Port 2 General-Purpose, Digital I/O Pins. These port pins function as general-purpose I/O pins with their input and output states controlled by the PD2, PO2, and PI2 registers. All port pins default to high-impedance mode after a reset. Software must configure these pins after release from reset to remove the high-impedance condition. All special functions must be enabled from software before they can be used. GPIO PORT PIN 9 10 11 12 28 29 30 31 — — — — 18 19 20 21 8 9 10 11 29 30 31 32 P2.0/MOSI P2.1/MISO P2.2/SCLK P2.3/SSEL P2.4/TCK P2.5/TDI P2.6/TMS P2.7/TDO P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 SPECIAL FUNCTION SPI: Master Out-Slave In SPI: Master In-Slave Out SPI: Slave Clock SPI: Active-Low Slave Select JTAG: Test Clock JTAG: Test Data In JTAG: Test Mode Select JTAG: Test Data Out MAXQ61C Port 3 General-Purpose, Digital I/O Pins with Interrupt Capability. These port pins function as general-purpose I/O pins with their input and output states controlled by the PD3, PO3, and PI3 registers. All port pins default to high-impedance mode after a reset. Software must configure these pins after release from reset to remove the high-impedance condition. All external interrupts must be enabled from software before they can be used. GPIO PORT PIN 19 20 21 22 23 24 25 26 — — — — — — — — — 15, 16 18 19 20 21 22 23 24 25 26, 27 P3.0/INT8 P3.1/INT9 P3.2/INT10 P3.3/INT11 P3.4/INT12 P3.5/INT13 P3.6/INT14 P3.7/INT15 N.C. P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 No Connection. Not internally connected. EXTERNAL INTERRUPT INT8 INT9 INT10 INT11 INT12 INT13 INT14 INT15 NO CONNECTION PINS ______________________________________________________________________________________ 11 16-Bit Microcontroller with Infrared Module MAXQ61C Block Diagram over competing microcontrollers. An integrated POR circuit with brownout support resets the device to a known condition following a power-up cycle or brownout condition. Additionally, a power-fail warning flag is set, and a power-fail interrupt can be generated when the system voltage falls below the power-fail warning voltage, VPFW. The power-fail warning feature allows the application to notify the user that the system supply is low and appropriate action should be taken. MAXQ61C REGULATOR VOLTAGE MONITOR GPIO 2x 16-BIT TIMER 16-BIT MAXQ RISC CPU CLOCK WATCHDOG 8kHz NANO RING 80KB USER ROM 1.5KB UTILITY ROM 2KB DATA SRAM IR DRIVER IR TIMER SPI Microprocessor The device is based on Maxim’s low-power, 16-bit MAXQ family of RISC cores. The core supports the Harvard memory architecture with separate 16-bit program and data address buses. A fixed 16-bit instruction word is standard, but data can be arranged in 8 or 16 bits. The MAXQ core in the device is implemented as a pipelined processor with performance approaching 1MIPS per MHz. The 16-bit data path is implemented around register modules, and each register module contributes specific functions to the core. The accumulator module consists of sixteen 16-bit registers and is tightly coupled with the arithmetic logic unit (ALU). A configurable soft stack supports program flow. Execution of instructions is triggered by data transfer between functional register modules or between a functional register module and memory. Because data movement involves only source and destination modules, circuit switching activities are limited to active modules only. For power-conscious applications, this approach localizes power dissipation and minimizes switching noise. The modular architecture also provides a maximum of flexibility and reusability that are important for a microprocessor used in embedded applications. The MAXQ instruction set is highly orthogonal. All arithmetical and logical operations can use any register in conjunction with the accumulator. Data movement is supported from any register to any other register. Memory is accessed through specific data-pointer registers with autoincrement/decrement support. USART X2 Detailed Description The MAXQ61C provides integrated, low-cost solutions that simplify the design of IR communications equipment such as universal remote controls. Standard features include the highly optimized, single-cycle, MAXQ, 16-bit RISC core; 80KB of user ROM memory; 2KB data RAM; soft stack; 16 general-purpose registers; and three data pointers. The MAXQ core has the industry’s best MIPS/mA rating, allowing developers to achieve the same performance as competing microcontrollers at substantially lower clock rates. Lower active-mode current combined with the even lower MAXQ61C stopmode current (0.2FA typ) results in increased battery life. Application-specific peripherals include flexible timers for generating IR carrier frequencies and modulation. A high-current IR drive pin capable of sinking up to 25mA current and output pins capable of sinking up to 5mA are ideal for IR applications. It also includes general-purpose I/O pins ideal for keypad matrix input, and a power-fail-detection circuit to notify the application when the supply voltage is nearing the microcontroller’s minimum operating voltage. At the heart of the device is the MAXQ 16-bit, RISC core. Operating from DC to 12MHz, almost all instructions execute in a single clock cycle (83.3ns at 12MHz), enabling nearly 12MIPS true-code operation. When active device operation is not required, an ultra-low-power stop mode can be invoked from software, resulting in quiescent current consumption of less than 0.2FA (typ) and 2.0FA (max). The combination of high-performance instructions and ultra-low stop-mode current increases battery life Memory The microcontroller incorporates several memory types: • 80KB user ROM • 2KB SRAM data memory • 1.5KB utility ROM • Soft stack 12 _____________________________________________________________________________________ 16-Bit Microcontroller with Infrared Module The device provides a soft stack that can be used to store program return addresses (for subroutine calls and interrupt handling) and other general-purpose data. This soft stack is located in the 2KB SRAM data memory, which means that the SRAM data memory must be shared between the soft stack and general-purpose application data storage. However, the location and size of the soft stack is determined by the user, providing maximum flexibility when allocating resources for a particular application. The stack is used automatically by the processor when the CALL, RET, and RETI instructions are executed and when an interrupt is serviced. An application can also store and retrieve values explicitly using the stack by means of the PUSH, POP, and POPI instructions. The SP pointer indicates the current top of the stack, which initializes by default to the top of the SRAM data memory. As values are pushed onto the stack, the SP pointer decrements, which means that the stack grows downward towards the bottom (lowest address) of the data memory. Popping values off the stack causes the SP pointer value to increase. Refer to the MAXQ610 User’s Guide for more details. The utility ROM is a 1.5KB block of internal ROM memory located in program space beginning at address 8000h. This ROM includes the following routines: Stack Memory always automatically jumps to location 0000h, which is the beginning of user application code. MAXQ61C Watchdog Timer The internal watchdog timer greatly increases system reliability. The timer resets the device if software execution is disturbed. The watchdog timer is a free-running counter designed to be periodically reset by the application software. If software is operating correctly, the counter is periodically reset and never reaches its maximum count. However, if software operation is interrupted, the timer does not reset, triggering a system reset and optionally a watchdog timer interrupt. This protects the system against electrical noise or electrostatic discharge (ESD) upsets that could cause uncontrolled processor operation. The internal watchdog timer is an upgrade to older designs with external watchdog devices, reducing system cost and simultaneously increasing reliability. The watchdog timer functions as the source of both the watchdog timer timeout and the watchdog timer reset. The timeout period can be programmed in a range of 215 to 224 system clock cycles. An interrupt is generated when the timeout period expires if the interrupt is enabled. All watchdog timer resets follow the programmed interrupt timeouts by 512 system clock cycles. If the watchdog timer is not restarted for another full interval in this time period, a system reset occurs when the reset timeout expires. See Table 1. Utility ROM • Production test routines (internal memory tests, memory loader, etc.), which are used for internal testing only, and are generally of no use to the endapplication developer • User-callable routines for buffer copying and fast table lookup (more information on these routines can be found in the MAXQ610 User’s Guide) Following any reset, execution begins in the utility ROM at address 8000h. At this point, unless test mode has been invoked (which requires special programming through the JTAG interface), the utility ROM in the device IR Carrier Generation and Modulation Timer The dedicated IR timer/counter module simplifies lowspeed infrared (IR) communication. The IR timer implements two pins (IRTX and IRRX) for supporting IR transmit and receive, respectively. The IRTX pin has no corresponding port pin designation, so the standard PD, PO, and PI port control status bits are not present. However, the IRTX pin output can be manipulated high or low using the PWCN.IRTXOUT and PWCN.IRTXOE bits when the IR timer is not enabled (i.e., IREN = 0). Table 1. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00) WD[1:0] 00 01 10 11 WATCHDOG CLOCK Sysclk/215 Sysclk/218 Sysclk/221 Sysclk/224 WATCHDOG INTERRUPT TIMEOUT 2.7ms 21.9ms 174.7ms 1.4s WATCHDOG RESET AFTER WATCHDOG INTERRUPT (µs) 42.7 42.7 42.7 42.7 13 ______________________________________________________________________________________ 16-Bit Microcontroller with Infrared Module MAXQ61C The IR timer is composed of a carrier generator and a carrier modulator. The carrier generation module uses the 16-bit IR carrier register (IRCA) to define the high and low time of the carrier through the IR carrier high byte (IRCAH) and IR carrier low byte (IRCAL). The carrier modulator uses the IR data bit (IRDATA) and IR modulator time register (IRMT) to determine whether the carrier or the idle condition is present on IRTX. The IR timer is enabled when the IR enable bit (IREN) is set to 1. The IR Value register (IRV) defines the beginning value for the carrier modulator. During transmission, the IRV register is initially loaded with the IRMT value and begins down counting towards 0000h, whereas in receive mode it counts upward from the initial IRV register value. During the receive operation, the IRV register can be configured to reload with 0000h when capture occurs on detection of selected edges or can be allowed to continue free-running throughout the receive operation. An overflow occurs when the IR timer value rolls over from 0FFFFh to 0000h. The IR overflow flag (IROV) is set to 1 and an interrupt is generated if enabled (IRIE = 1). The IRCAH byte defines the carrier high time in terms of the number of IR input clocks, whereas the IRCAL byte defines the carrier low time. • IR Input Clock (fIRCLK) = fSYS/2IRDIV[1:0] • Carrier Frequency (fCARRIER) = fIRCLK/(IRCAH + IRCAL + 2) • Carrier High Time = IRCAH + 1 • Carrier Low Time = IRCAL + 1 • Carrier Duty Cycle = (IRCAH + 1)/(IRCAH + IRCAL + 2) During transmission, the IRCA register is latched for each IRV down-count interval, and is sampled along with the IRTXPOL and IRDATA bits at the beginning of each new IRV down-count interval so that duty-cycle variation and frequency shifting is possible from one interval to the next, which is illustrated in Figure 1. Figure 2 illustrates the basic carrier generation and its path to the IRTX output pin. The IR transmit polarity bit (IRTXPOL) defines the starting/idle state and the carrier polarity of the IRTX pin when the IR timer is enabled. During IR transmission (IRMODE = 1), the carrier generator creates the appropriate carrier waveform, while the carrier modulator performs the modulation. The carrier modulation can be performed as a function of carrier cycles or IRCLK cycles dependent on the setting of the IRCFME bit. When IRCFME = 0, the IRV down counter is clocked by the carrier frequency and thus the modulation is a function of carrier cycles. When IRCFME = 1, the IRV down counter is clocked by IRCLK, allowing carrier modulation timing with IRCLK resolution. The IRTXPOL bit defines the starting/idle state as well as the carrier polarity for the IRTX pin. If IRTXPOL = 1, the IRTX pin is set to a logic-high when the IR timer module is enabled. If IRTXPOL = 0, the IRTX pin is set to a logic-low when the IR timer is enabled. A separate register bit, IR data (IRDATA), is used to determine whether the carrier generator output is output to the IRTX pin for the next IRMT carrier cycles. When IRDATA = 1, the carrier waveform (or inversion of this waveform if IRTXPOL = 1) is output on the IRTX pin during the next IRMT cycles. When IRDATA = 0, the idle condition, as defined by IRTXPOL, is output on the IRTX pin during the next IRMT cycles. The IR timer acts as a down counter in transmit mode. An IR transmission starts when the IREN bit is set to 1 when IRMODE = 1; when the IRMODE bit is set to 1 when IREN = 1; or when IREN and IRMODE are both set to 1 in the same instruction. The IRMT and IRCA registers, along with the IRDATA and IRTXPOL bits, are sampled at the beginning of the transmit process and every time the IR timer value reload its value. When the IRV reaches 0000h value, on the next carrier clock, it does the following: 1) Reloads IRV with IRMT. 2) Samples IRCA, IRDATA, and IRTXPOL. 3) Generates IRTX accordingly. 4) Sets IRIF to 1. 5) Generates an interrupt to the CPU if enabled (IRIE = 1). To terminate the current transmission, the user can switch to receive mode (IRMODE = 0) or clear IREN to 0. Carrier Modulation Time = IRMT + 1 carrier cycles IR Transmission Carrier Generation Module 14 _____________________________________________________________________________________ 16-Bit Microcontroller with Infrared Module MAXQ61C IRCA IRCA = 0202h IRCA = 0002h IRMT IRMT = 3 IRMT = 5 IRCA, IRMT, IRDATA SAMPLED AT END OF IRV DOWN-COUNT INTERVAL 3 2 1 0 5 4 3 2 1 0 CARRIER OUTPUT (IRV) IRDATA 0 1 0 IR INTERRUPT IRTX IRTXPOL = 1 IRTX IRTXPOL = 0 Figure 1. IR Transmit Frequency Shifting Example (IRCFME = 0) IRTXPOL CARRIER GENERATION 0 IRTX PIN 1 IRCLK IRCAH + 1 IRCAL + 1 CARRIER IRCFME 0 1 IRDATA IRMT SAMPLE IRDATA ON IRV = 0000h CARRIER MODULATION IR INTERRUPT Figure 2. IR Transmit Carrier Generation and Carrier Modulator Control ______________________________________________________________________________________ 15 16-Bit Microcontroller with Infrared Module MAXQ61C The normal transmit mode modulates the carrier based upon the IRDATA bit. However, the user has the option to input the modulator (envelope) on an external pin if desired. If the IRENV[1:0] bits are configured to 01b or 10b, the modulator/envelope is output to the IRTXM pin. The IRDATA bit is output directly to the IRTXM pin (if IR Transmit—Independent External Carrier and Modulator Outputs IRTXPOL = 0) on each IRV down-count interval boundary just as if it were being used to internally modulate the carrier frequency. If IRTXPOL = 1, the inverse of the IRDATA bit is output to the IRTXM pin on the IRV interval down-count boundaries. See Figure 4. When the envelope mode is enabled, it is possible to output either the modulated (IRENV[1:0] = 01b) or unmodulated (INENV[1:0] = 10b) carrier to the IRTX pin. IRMT = 3 CARRIER OUTPUT (IRV) 3 2 1 0 3 2 1 0 IRDATA 0 1 0 IR INTERRUPT IRTX IRTXPOL = 1 IRTX IRTXPOL = 0 Figure 3. IR Transmission Waveform (IRCFME = 0) IRTXM IRTXPOL = 1 IRTXM IRTXPOL = 0 IRDATA 1 0 1 0 1 0 1 0 IR INTERRUPT IRV INTERVAL IRMT IRMT IRMT IRMT Figure 4. External IRTXM (Modulator) Output 16 _____________________________________________________________________________________ 16-Bit Microcontroller with Infrared Module MAXQ61C CARRIER GENERATION IRCLK IRCAH + 1 IRCAL + 1 CARRIER MODULATION 0 1 IRCFME 0000h IRV IR INTERRUPT COPY IRV TO IRMT ON EDGE DETECT IRXRL IR TIMER OVERFLOW INTERRUPT TO CPU IRRX PIN RESET IRV TO 0000h EDGE DETECT IRDATA Figure 5. IR Capture When configured in receive mode (IRMODE = 0), the IR hardware supports the IRRX capture function. The IRRXSEL[1:0] bits define which edge(s) of the IRRX pin should trigger the IR timer capture function. The IR module starts operating in the receive mode when IRMODE = 0 and IREN = 1. Once started, the IR timer (IRV) starts up counting from 0000h when a qualified capture event as defined by IRRXSEL happens. The IRV register is, by default, counting carrier cycles as defined by the IRCA register. However, the IR carrier frequency detect (IRCFME) bit can be set to 1 to allow clocking of the IRV register directly with the IRCLK for finer resolution. When IRCFME = 0, the IRCA defined carrier is counted by IRV. When IRCFME = 1, the IRCLK clocks the IRV register. On the next qualified event, the IR module does the following: 1) Captures the IRRX pin state and transfers its value to IRDATA. If a falling edge occurs, IRDATA = 0. If a rising edge occurs, IRDATA = 1. 2) Transfers its current IRV value to the IRMT. 3) Resets IRV content to 0000h (if IRXRL = 1). 4) Continues counting again until the next qualified event. If the IR timer value rolls over from 0FFFFh to 0000h before a qualified event happens, the IR timer overflow (IROV) flag is set to 1 and an interrupt is generated, if enabled. The IR module continues to operate in receive mode until it is stopped by switching into transmit mode (IRMODE = 1) or clearing IREN = 0. IR Receive A special mode reduces the CPU processing burden when performing IR learning functions. Typically, when operating in an IR learning capacity, some number of carrier cycles are examined for frequency determination. Once the frequency has been determined, the IR receive function can be reduced to counting the number of carrier pulses in the burst and the duration of the combined mark-space time within the burst. To simplify this process, the receive burst-count mode (as enabled by the RXBCNT bit) can be used. When RXBCNT = 0, the standard IR receive capture functionality is in place. When RXBCNT = 1, the IRV capture operation is disabled and the interrupt flag associated with the capture no longer denotes a capture. In the carrier burst-count mode, the IRMT register only counts qualified edges. The IRIF interrupt flag (normally used to signal a capture when RXBCNT = 0) now becomes set if two IRCA cycles elapse without getting a qualified edge. The IRIF interrupt flag thus denotes absence of the carrier and the beginning of a space in the receive signal. When the RXBCNT bit is changed from 0 to 1, the IRMT register is set to 0001h. The IRCFME bit is still used to define whether the IRV register is counting system IRCLK clocks or IRCA-defined carrier cycles. The IRXRL bit defines whether the IRV register is reloaded with 0000h on detection of a qualified edge (per the IRXSEL[1:0] bits). Figure 6 and the descriptive sequence embedded in the figure illustrate the expected usage of the receive burst-count mode. Carrier Burst-Count Mode ______________________________________________________________________________________ 17 16-Bit Microcontroller with Infrared Module MAXQ61C CARRIER FREQUENCY CALCULATION IRMT = PULSE COUNTING IRV = CARRIER CYCLE COUNTING IRMT = PULSE COUNTING IRRX IRV IRMT 1 2 3 4 5 6 7 8 9 1 TO 4 CAPTURE INTERRUPT (IRIF = 1). IRV ≥ IRMT. IRV = 0 (IF IRXRL = 1). SOFTWARE SETS IRCA = CARRIER FREQUENCY. SOFTWARE SETS RXBCNT = 1 (WHICH CLEARS IRMT = 0001 IN HARDWARE). SOFTWARE CLEARS IRCFME = 0 SO THAT IRV COUNTS CARRIER CYCLES. IRV IS RESET TO 0 ON QUALIFIED EDGE DETECTION IF IRXRL = 1. SOFTWARE ADDS TO IRMT THE NUMBER OF PULSES USED FOR CARRIER MEASUREMENT. IRCA x 2x COUNTER FOR SPACE CAN BEGIN IMMEDIATELY (QUALIFIED EDGE RESETS). QUALIFIED EDGE DETECTED: IRMT++ IRV RESET TO 0 IF IRXRL = 1. IRCA x 2 PERIOD ELAPSES: IRIF = 1; CARRIER ABSENCE = SPACE. BURST MARK = IRMT PULSES. SOFTWARE CLEARS RXBCNT = 0 SO THAT WE CAPTURE ON THE NEXT QUALIFIED EDGE. QUALIFIED EDGE DETECTED: IRIF = 1, CAPTURE IRV IRMT AS THE BURST SPACE (PLUS UP TO ONE CARRIER CYCLE). SOFTWARE SET RXBCNT = 1 AS IN (5). CONTINUE (5) TO (8) UNTIL LEARNING SPACE EXCEEDS SOME DURATION. IRV ROLLOVERS CAN BE USED. 5 6 7 8 9 Figure 6. Receive Burst-Count Example 16-Bit Timers/Counters The microcontroller provides two timers/counters that support the following functions: • 16-bit timer/counter • 16-bit up/down autoreload • Counter function of external pulse • 16-bit timer with capture • 16-bit timer with compare • Input/output enhancements for pulse-width modulation • Set/reset/toggle output state on comparator match • Prescaler with 2n divider (for n = 0, 2, 4, 6, 8, 10) 18 _____________________________________________________________________________________ 16-Bit Microcontroller with Infrared Module USART The device provides two USART peripherals with the following features: • 2-wire interface • Full-duplex operation for asynchronous data transfers • Half-duplex operation for synchronous data transfers • Programmable interrupt when transmit or receive data operation completes • Independent programmable baud-rate generator • Optional 9th bit parity support • Start/stop bit support Serial Peripheral Interface (SPI) The integrated SPI provides an independent serial communication channel that communicates synchronously with peripheral devices in a multiple master or multiple slave system. The interface allows access to a 4-wire, full-duplex serial bus, and can be operated in either master mode or slave mode. Collision detection is provided when two or more masters attempt a data transfer at the same time. The maximum SPI master transfer rate is Sysclk/2. When operating as an SPI slave, the device can support up to Sysclk/4 SPI transfer rate. Data is transferred as an 8-bit or 16-bit value, MSB first. In addition, the SPI module supports configuration of an active SSEL state (active low or active high) through the slave active select. MAXQ61C Table 2. USART Mode Details MODE Mode 0 Mode 1 Mode 2 Mode 3 TYPE Synchronous Asynchronous Asynchronous Asynchronous START BITS N/A 1 1 1 DATA BITS 8 8 8+1 8+1 STOP BITS N/A 1 1 1 SHIFT SSEL SAMPLE SHIFT SAMPLE SCLK CKPOL/CKPHA 0/1 OR 1/0 tMCK tMCH SCLK CKPOL/CKPHA 0/0 OR 1/1 tMOH tMCL tMOV MOSI MSB MSB-1 tRF LSB tMLH tMIS MISO MSB MSB-1 tMIH LSB Figure 7. SPI Master Communication Timing ______________________________________________________________________________________ 19 16-Bit Microcontroller with Infrared Module MAXQ61C SHIFT SSEL SAMPLE SHIFT SAMPLE tSSH tSD tSSE tSCK SCLK CKPOL/CKPHA 0/1 OR 1/0 tSCH tSCL SCLK CKPOL/CKPHA 0/0 OR 1/1 tSIS MOSI MSB tSIH MSB-1 LSB tSOV MISO MSB MSB-1 tRF LSB tSLH Figure 8. SPI Slave Communication Timing General-Purpose I/O The microcontroller provides port pins for general-purpose I/O that have the following features: • CMOS output drivers • Schmitt trigger inputs • Optional weak pullup to VDD when operating in input mode While the microcontroller is in a reset state, all port pins become high impedance with both weak pullups and input buffers disabled, unless otherwise noted. From a software perspective, each port appears as a group of peripheral registers with unique addresses. Special function pins can also be used as general-purpose I/O pins when the special functions are disabled. For a detailed description of the special functions available for each pin, refer to the MAXQ610 User’s Guide. HFXOUT C1 C2 RF = 1MI Q50% C1 = C2 = 12pF RF VDD HFXIN CLOCK CIRCUIT STOP Figure 9. On-Chip Oscillator On-Chip Oscillator An external quartz crystal or a ceramic resonator can be connected between HFXIN and HFXOUT, as illustrated in Figure 9. Noise at HFXIN and HFXOUT can adversely affect onchip clock timing. It is good design practice to place the crystal and capacitors near the oscillator circuitry and connect HFXIN and HFXOUT to ground with a direct short trace. The typical values of external capacitors vary with the type of crystal to be used and should be initially selected based on load capacitance as suggested by the manufacturer. 20 _____________________________________________________________________________________ 16-Bit Microcontroller with Infrared Module Operating Modes The lowest power mode of operation is stop mode. In this mode, CPU state and memories are preserved, but the CPU is not actively running. Wake-up sources include external I/O interrupts, the power-fail warning interrupt, wake-up timer, or a power-fail reset. Any time the microcontroller is in a state where code does not need to be executed, the user software can put the device into stop mode. The nanopower ring oscillator is an internal ultralow-power (400nA) 8kHz ring oscillator that can be used to drive a wake-up timer that exits stop mode. The wakeup timer is programmable by software in steps of 125Fs up to approximately 8s. The power-fail monitor is always on during normal operation. However, it can be selectively disabled during stop mode to minimize power consumption. This feature is enabled using the power-fail monitor disable (PFD) bit in the PWCN register. The reset default state for the PFD bit is 1, which disables the power-fail monitor function during stop mode. If power-fail monitoring is disabled (PFD = 1) during stop mode, the circuitry responsible for generating a power-fail warning or reset is shut down and neither condition is detected. Thus, the VDD < VRST condition does not invoke a reset state. Figures 10, 11, and 12 show the power-fail detection and response during normal and stop-mode operation. If a reset is caused by a power-fail, the power-fail monitor can be set to one of the following intervals: • Always on—continuous monitoring • 211 nanopower ring oscillator clocks (~256ms) • 212 nanopower ring oscillator clocks (~512ms) • 213 nanopower ring oscillator clocks (~1.024s) In the case where the power-fail circuitry is periodically turned on, the power-fail detection is turned on for two nanopower ring-oscillator cycles. If VDD > VRST during detection, VDD is monitored for an additional nanopower ring-oscillator period. If VDD remains above VRST for the third nanopower ring period, the CPU exits the reset state and resumes normal operation from utility ROM at 8000h after satisfying the crystal warmup period. If a reset is generated by any other event, such as the RESET pin being driven low externally or the watchdog timer, the power-fail, internal regulator, and crystal remain on during the CPU reset. In these cases, the CPU exits the reset state in less than 20 crystal cycles after the reset source is removed. Power-Fail Detection MAXQ61C VDD t < tPFW C t ≥ tPFW t ≥ tPFW t ≥ tPFW VPFW VRST E F B D G H VPOR A I INTERNAL RESET (ACTIVE HIGH) Figure 10. Power-Fail Detection During Normal Operation ______________________________________________________________________________________ 21 16-Bit Microcontroller with Infrared Module MAXQ61C Table 3. Power-Fail Detection States During Normal Operation STATE A B POWER-FAIL On On INTERNAL REGULATOR Off On CRYSTAL OSCILLATOR Off On SRAM RETENTION — — VDD < VPOR. VPOR < VDD < VRST. Crystal warmup time, tXTAL_RDY. CPU held in reset. VDD > VRST. CPU normal operation. Power drop too short. Power-fail not detected. VRST < VDD < VPFW. PFI is set when VRST < VDD < VPFW and maintains this state for at least tPFW, at which time a power-fail interrupt is generated (if enabled). CPU continues normal operation. VPOR < VDD < VRST. Power-fail detected. CPU goes into reset. Power-fail monitor turns on periodically. VDD > VRST. Crystal warmup time, tXTAL_RDY. CPU resumes normal operation from 8000h. VPOR < VDD < VRST. Power-fail detected. CPU goes into reset. Power-fail monitor turns on periodically. VDD < VPOR. Device held in reset. No operation allowed. COMMENTS C D On On On On On On — — E On On On — F On (Periodically) Off Off Yes G On On On — H On (Periodically) Off Off Yes I Off Off Off — 22 _____________________________________________________________________________________ 16-Bit Microcontroller with Infrared Module MAXQ61C VDD A t < tPFW t ≥ tPFW t ≥ tPFW VPFW VRST B C D E VPOR F STOP INTERNAL RESET (ACTIVE HIGH) Figure 11. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled Table 4. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled STATE POWER-FAIL INTERNAL REGULATOR Off CRYSTAL OSCILLATOR Off SRAM RETENTION Yes COMMENTS Application enters stop mode. VDD > VRST. CPU in stop mode. Power drop too short. Power-fail not detected. VRST < VDD < VPFW. Power-fail warning detected. Turn on regulator and crystal. Crystal warmup time, tXTAL_RDY. Exit stop mode. Application enters stop mode. VDD > VRST. CPU in stop mode. VPOR < VDD < VRST. Power-fail detected. CPU goes into reset. Power-fail monitor turns on periodically. VDD < VPOR. Device held in reset. No operation allowed. A On B On Off Off Yes C On On On Yes D On Off Off Yes E On (Periodically) Off Off Yes F Off Off Off — ______________________________________________________________________________________ 23 16-Bit Microcontroller with Infrared Module MAXQ61C VDD A D VPFW VRST B C E VPOR F STOP INTERNAL RESET (ACTIVE HIGH) INTERRUPT Figure 12. Stop Mode Power-Fail Detection with Power-Fail Monitor Disabled Table 5. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled STATE POWER-FAIL INTERNAL REGULATOR Off CRYSTAL OSCILLATOR Off SRAM RETENTION Yes COMMENTS Application enters stop mode. VDD > VRST. CPU in stop mode. VDD < VPFW. Power-fail not detected because power-fail monitor is disabled. VRST < VDD < VPFW. An interrupt occurs that causes the CPU to exit stop mode. Power-fail monitor is turned on, detects a power-fail warning, and sets the power-fail interrupt flag. Turn on regulator and crystal. Crystal warmup time, tXTAL_RDY. On stop mode exit, CPU vectors to the higher priority of power-fail and the interrupt that causes stop mode exit. A Off B Off Off Off Yes C On On On Yes 24 _____________________________________________________________________________________ 16-Bit Microcontroller with Infrared Module Table 5. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled (continued) STATE POWER-FAIL INTERNAL REGULATOR Off CRYSTAL OSCILLATOR Off SRAM RETENTION Yes COMMENTS Application enters stop mode. VDD > VRST. CPU in stop mode. VPOR < VDD < VRST. An interrupt occurs that causes the CPU to exit stop mode. Power-fail monitor is turned on, detects a power-fail, and puts CPU in reset. Power-fail monitor is turned on periodically. VDD < VPOR. Device held in reset. No operation allowed. MAXQ61C D Off E On (Periodically) Off Off Yes F Off Off Off — Applications Information The low-power, high-performance RISC architecture of this device makes it an excellent fit for many portable or battery-powered applications. It is ideally suited for applications such as universal remote controls that require the cost-effective integration of IR transmit/ receive capability. Careful PCB layout significantly minimizes system-level digital noise that could interact with the microcontroller or peripheral components. The use of multilayer boards is essential to allow the use of dedicated power planes. The area under any digital components should be a continuous ground plane if possible. Keep bypass capacitor leads short for best noise rejection and place the capacitors as close to the leads of the devices as possible. CMOS design guidelines for any semiconductor require that no pin be taken above VDD or below GND. Violation of this guideline can result in a hard failure (damage to the silicon inside the device) or a soft failure (unintentional modification of memory contents). Voltage spikes above or below the device’s absolute maximum ratings can potentially cause a devastating IC latchup. Microcontrollers commonly experience negative voltage spikes through either their power pins or general- purpose I/O pins. Negative voltage spikes on power pins are especially problematic as they directly couple to the internal power buses. Devices such as keypads can conduct electrostatic discharges directly into the microcontroller and seriously damage the device. System designers must protect components against these transients that can corrupt system memory. Grounds and Bypassing Additional Documentation Designers must have the following documents to fully use all the features of this device. This data sheet contains pin descriptions, feature overviews, and electrical specifications. Errata sheets contain deviations from published specifications. The user’s guides offer detailed information about device features and operation. The following documents can be downloaded from www.maxim-ic.com/microcontrollers. • This MAXQ61C data sheet, which contains electrical/ timing specifications, pin descriptions, and package information. • The MAXQ61C revision-specific errata sheet (www.maximic.com/errata). • The MAXQ610 User’s Guide, which contains detailed information on features and operation, including programming. ______________________________________________________________________________________ 25 16-Bit Microcontroller with Infrared Module MAXQ61C The MAXQ610 User’s Guide contains all the information that is needed to develop application code for the MAXQ61C microcontroller. However, even though the MAXQ610 and the MAXQ61C are largely code-compatible, there are certain differences between the two devices that must be kept in mind when referring to the MAXQ610 User’s Guide. • The MAXQ61C is a ROM-only microcontroller, unlike the MAXQ610, which contains programmable flash program memory. Therefore, all sections in the MAXQ610 User’s Guide relating to the flash controller, the JTAG bootloader, and the debug engine should be disregarded. • The following registers on the MAXQ610 (which are described in the MAXQ610 User’s Guide) do not exist on the MAXQ61C, and all references to them should be disregarded: • Port 4 Output Register (PO4) • Port 4 Direction Register (PD4) • Port 4 Input Register (PI4) Deviations from the MAXQ610 User’s Guide for the MAXQ61C Development and Technical Support Maxim and third-party suppliers provide a variety of highly versatile, affordably priced development tools for this microcontroller, including the following: • Compilers • In-circuit emulators • Integrated Development Environments (IDEs) • Serial-to-JTAG and USB-to-JTAG interface boards for programming and debugging (for microcontrollers with rewritable memory) A partial list of development tool vendors can be found at www.maxim-ic.com/MAXQ_tools. For technical support, go to https://support.maxim-ic. com/micro. Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 32 TQFN-EP 32 LQFP 44 TQFN-EP 44 TQFP PACKAGE CODE T3255+3 C32+2 T4477+2 C44+2 DOCUMENT NO. 21-0140 21-0054 21-0144 21-0293 26 _____________________________________________________________________________________ 16-Bit Microcontroller with Infrared Module Revision History REVISION NUMBER 0 REVISION DATE 4/10 Initial release DESCRIPTION PAGES CHANGED — MAXQ61C Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 27 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.