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MX25U12835FMI0A

MX25U12835FMI0A

  • 厂商:

    MCNIX(旺宏电子)

  • 封装:

    SOP-16_10.3X7.52MM

  • 描述:

    IC FLASH 128MBIT SPI/QUAD 16SOP

  • 数据手册
  • 价格&库存
MX25U12835FMI0A 数据手册
MX25U12835F MX25U12835F 1.8V, 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY Key Features • 1.65 to 2.0 volt for read, erase, and program operations • Multi I/O Support - Single I/O, Dual I/O and Quad I/O • Quad Peripheral Interface (QPI) Read / Program Mode • Program Suspend/Resume & Erase Suspend/Resume • 23-ball WLCSP (Ball Diameter 0.30mm) P/N: PM1728 Macronix Proprietary 1 Rev. 1.9, March 13, 2019 MX25U12835F Contents 1. FEATURES............................................................................................................................................................... 5 2. GENERAL DESCRIPTION...................................................................................................................................... 6 Table 1. Read Performance.........................................................................................................................6 3. PIN CONFIGURATIONS .......................................................................................................................................... 7 4. PIN DESCRIPTION................................................................................................................................................... 7 5. BLOCK DIAGRAM.................................................................................................................................................... 8 6. DATA PROTECTION................................................................................................................................................. 9 Table 2. Protected Area Sizes....................................................................................................................10 Table 3. 4K-bit Secured OTP Definition..................................................................................................... 11 7. Memory Organization............................................................................................................................................ 12 Table 4. Memory Organization...................................................................................................................12 8. DEVICE OPERATION............................................................................................................................................. 13 8-1. Quad Peripheral Interface (QPI) Read Mode........................................................................................... 15 9. COMMAND DESCRIPTION.................................................................................................................................... 16 9-1. 9-2. 9-3. 9-4. 9-5. 9-6. 9-7. 9-8. 9-9. 9-10. 9-11. 9-12. 9-13. 9-14. 9-15. 9-16. 9-17. 9-18. 9-19. 9-20. 9-21. 9-22. 9-23. 9-24. 9-25. 9-26. P/N: PM1728 Table 5. Command Set...............................................................................................................................16 Write Enable (WREN)............................................................................................................................... 20 Write Disable (WRDI)................................................................................................................................ 21 Read Identification (RDID)........................................................................................................................ 22 Release from Deep Power-down (RDP), Read Electronic Signature (RES)............................................ 23 Read Electronic Manufacturer ID & Device ID (REMS)............................................................................ 25 QPI ID Read (QPIID)................................................................................................................................ 26 Table 6. ID Definitions ...............................................................................................................................26 Read Status Register (RDSR).................................................................................................................. 27 Read Configuration Register (RDCR)....................................................................................................... 28 Write Status Register (WRSR).................................................................................................................. 33 Table 7. Protection Modes..........................................................................................................................34 Read Data Bytes (READ)......................................................................................................................... 37 Read Data Bytes at Higher Speed (FAST_READ)................................................................................... 38 Dual Read Mode (DREAD)....................................................................................................................... 40 2 x I/O Read Mode (2READ).................................................................................................................... 41 Quad Read Mode (QREAD)..................................................................................................................... 42 4 x I/O Read Mode (4READ).................................................................................................................... 43 Burst Read................................................................................................................................................ 47 Performance Enhance Mode.................................................................................................................... 48 Sector Erase (SE)..................................................................................................................................... 52 Block Erase (BE32K)................................................................................................................................ 53 Block Erase (BE)...................................................................................................................................... 54 Chip Erase (CE)........................................................................................................................................ 55 Page Program (PP).................................................................................................................................. 56 4 x I/O Page Program (4PP)..................................................................................................................... 58 Deep Power-down (DP)............................................................................................................................ 59 Enter Secured OTP (ENSO)..................................................................................................................... 60 Exit Secured OTP (EXSO)........................................................................................................................ 60 Macronix Proprietary 2 Rev. 1.9, March 13, 2019 MX25U12835F 9-27. Read Security Register (RDSCUR).......................................................................................................... 60 Table 8. Security Register Definition..........................................................................................................61 9-28. Write Security Register (WRSCUR).......................................................................................................... 61 9-29. Write Protection Selection (WPSEL)......................................................................................................... 62 9-30. Single Block Lock/Unlock Protection (SBLK/SBULK)............................................................................... 65 9-31. Read Block Lock Status (RDBLOCK)....................................................................................................... 67 9-32. Gang Block Lock/Unlock (GBLK/GBULK)................................................................................................ 67 9-33. Program Suspend and Erase Suspend ................................................................................................... 68 Table 9. Readable Area of Memory While a Program or Erase Operation is Suspended..........................68 Table 10. Acceptable Commands During Program/Erase Suspend after tPSL/tESL.................................69 Table 11. Acceptable Commands During Suspend (tPSL/tESL not required)............................................69 9-34. Program Resume and Erase Resume...................................................................................................... 70 9-35. No Operation (NOP)................................................................................................................................. 71 9-36. Software Reset (Reset-Enable (RSTEN) and Reset (RST)).................................................................... 71 9-37. Read SFDP Mode (RDSFDP)................................................................................................................... 73 Table 12. Signature and Parameter Identification Data Values .................................................................74 Table 13. Parameter Table (0): JEDEC Flash Parameter Tables...............................................................75 Table 14. Parameter Table (1): Macronix Flash Parameter Tables............................................................77 10. RESET.................................................................................................................................................................. 79 Table 15-1. Reset Timing-(Power On)........................................................................................................79 Table 15-2. Reset Timing-(Other Operation)..............................................................................................79 11. POWER-ON STATE.............................................................................................................................................. 80 12. ELECTRICAL SPECIFICATIONS......................................................................................................................... 81 Table 16. Absolute Maximum Ratings........................................................................................................81 Table 17. Capacitance TA = 25°C, f = 1.0 MHz..........................................................................................81 Table 18. DC Characteristics......................................................................................................................83 Table 19. AC Characteristics......................................................................................................................84 13. OPERATING CONDITIONS.................................................................................................................................. 86 Table 20. Power-Up Timing and VWI Threshold........................................................................................88 Table 21. Power-Up/Down and Voltage Drop ............................................................................................89 13-1. Initial Delivery State.................................................................................................................................. 89 14. ERASE AND PROGRAMMING PERFORMANCE............................................................................................... 89 15. LATCH-UP CHARACTERISTICS......................................................................................................................... 89 16. ORDERING INFORMATION................................................................................................................................. 90 17. PART NAME DESCRIPTION................................................................................................................................ 91 18. PACKAGE INFORMATION................................................................................................................................... 92 18-1. 16-pin SOP (300mil)................................................................................................................................. 92 18-2. 8-land WSON (6x5mm)............................................................................................................................ 93 18-3. 8-land WSON (8x6mm)............................................................................................................................ 94 18-4. 23-ball WLCSP (Ball Diameter 0.30mm).................................................................................................. 95 18-5. 8-pin SOP (200mil)................................................................................................................................... 96 18-6. 24-Ball BGA (5x5 ball array)..................................................................................................................... 97 19. REVISION HISTORY ............................................................................................................................................ 98 P/N: PM1728 Macronix Proprietary 3 Rev. 1.9, March 13, 2019 MX25U12835F Figures P/N: PM1728 Figure 1. Serial Modes Supported................................................................................................................................................13 Figure 2. Serial Input Timing.........................................................................................................................................................14 Figure 3. Output Timing................................................................................................................................................................14 Figure 4. Enable QPI Sequence (Command 35h)........................................................................................................................15 Figure 5. Reset QPI Mode (Command F5h).................................................................................................................................15 Figure 6. Write Enable (WREN) Sequence (SPI Mode)...............................................................................................................20 Figure 7. Write Enable (WREN) Sequence (QPI Mode)...............................................................................................................20 Figure 8. Write Disable (WRDI) Sequence (SPI Mode)................................................................................................................21 Figure 9. Write Disable (WRDI) Sequence (QPI Mode)...............................................................................................................21 Figure 10. Read Identification (RDID) Sequence (SPI mode only)...............................................................................................22 Figure 11. Read Electronic Signature (RES) Sequence (SPI Mode)...........................................................................................23 Figure 12. Read Electronic Signature (RES) Sequence (QPI Mode)..........................................................................................24 Figure 13. Release from Deep Power-down (RDP) Sequence (SPI Mode)................................................................................24 Figure 14. Release from Deep Power-down (RDP) Sequence (QPI Mode)................................................................................24 Figure 15. Read Electronic Manufacturer & Device ID (REMS) Sequence (SPI Mode only)......................................................25 Figure 16. Read Status Register (RDSR) Sequence (SPI Mode)................................................................................................27 Figure 17. Read Status Register (RDSR) Sequence (QPI Mode)................................................................................................27 Figure 18. Read Configuration Register (RDCR) Sequence (SPI Mode).....................................................................................28 Figure 19. Read Configuration Register (RDCR) Sequence (QPI Mode).....................................................................................28 Figure 20. Program/Erase flow with read array data....................................................................................................................29 Figure 21. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag)....................................................................30 Figure 22. Write Status Register (WRSR) Sequence (SPI Mode)...............................................................................................33 Figure 23. Write Status Register (WRSR) Sequence (QPI Mode)..............................................................................................33 Figure 24. WRSR flow..................................................................................................................................................................35 Figure 25. WP# Setup Timing and Hold Timing during WRSR when SRWD=1...........................................................................36 Figure 26. Read Data Bytes (READ) Sequence (SPI Mode only)................................................................................................37 Figure 27. Read at Higher Speed (FAST_READ) Sequence (SPI Mode)....................................................................................39 Figure 28. Read at Higher Speed (FAST_READ) Sequence (QPI Mode)....................................................................................39 Figure 29. Dual Read Mode Sequence (Command 3B)...............................................................................................................40 Figure 30. 2 x I/O Read Mode Sequence (SPI Mode only)..........................................................................................................41 Figure 31. Quad Read Mode Sequence (Command 6B)..............................................................................................................42 Figure 32. 4 x I/O Read Mode Sequence (SPI Mode)..................................................................................................................44 Figure 33. 4 x I/O Read Mode Sequence (SPI Mode), for MX25U12835FZNI-08G only.............................................................44 Figure 34. 4 x I/O Read Mode Sequence (QPI Mode)..................................................................................................................45 Figure 35. 4 x I/O Read Mode Sequence (QPI Mode), for MX25U12835FZNI-08G only.............................................................45 Figure 36. W4READ (Quad Read with 4 dummy cycles) Sequence ...........................................................................................46 Figure 37. Burst Read (SPI Mode)...............................................................................................................................................47 Figure 38. Burst Read (QPI Mode)...............................................................................................................................................47 Figure 39. 4 x I/O Read Performance Enhance Mode Sequence (SPI Mode).............................................................................49 Figure 40. 4 x I/O Read Performance Enhance Mode Sequence (SPI Mode), for MX25U12835FZNI-08G only........................50 Figure 41. 4 x I/O Read Performance Enhance Mode Sequence (QPI Mode).............................................................................51 Figure 42. 4 x I/O Read Performance Enhance Mode Sequence (QPI Mode), for MX25U12835FZNI-08G only........................51 Figure 43. Sector Erase (SE) Sequence (SPI Mode)..................................................................................................................52 Figure 44. Sector Erase (SE) Sequence (QPI Mode)..................................................................................................................52 Figure 45. Block Erase 32KB (BE32K) Sequence (SPI Mode)....................................................................................................53 Figure 46. Block Erase 32KB (BE32K) Sequence (QPI Mode)...................................................................................................53 Figure 47. Block Erase (BE) Sequence (SPI Mode).....................................................................................................................54 Figure 48. Block Erase (BE) Sequence (QPI Mode)....................................................................................................................54 Figure 49. Chip Erase (CE) Sequence (SPI Mode).....................................................................................................................55 Figure 50. Chip Erase (CE) Sequence (QPI Mode).....................................................................................................................55 Figure 51. Page Program (PP) Sequence (SPI Mode).................................................................................................................57 Figure 52. Page Program (PP) Sequence (QPI Mode)................................................................................................................57 Figure 53. 4 x I/O Page Program (4PP) Sequence (SPI Mode only)............................................................................................58 Figure 54. Deep Power-down (DP) Sequence (SPI Mode)..........................................................................................................59 Figure 55. Deep Power-down (DP) Sequence (QPI Mode)..........................................................................................................59 Figure 56. Write Security Register (WRSCUR) Sequence (Command 2F)..................................................................................61 Figure 57. BP and SRWD if WPSEL=0........................................................................................................................................62 Figure 58. The individual block lock mode is effective after setting WPSEL=1............................................................................63 Figure 59. Write Protection Selection (WPSEL) Sequence (Command 68).................................................................................63 Figure 60. WPSEL Flow................................................................................................................................................................64 Figure 61. Block Lock Flow...........................................................................................................................................................65 Figure 62. Block Unlock Flow.......................................................................................................................................................66 Figure 63. Suspend to Read Latency...........................................................................................................................................68 Figure 64. Resume to Suspend Latency......................................................................................................................................70 Figure 65. Suspend to Program Latency......................................................................................................................................70 Figure 66. Resume to Read Latency............................................................................................................................................70 Figure 67. Software Reset Recovery............................................................................................................................................72 Figure 68. Reset Sequence (SPI mode).......................................................................................................................................72 Figure 69. Reset Sequence (QPI mode)......................................................................................................................................72 Figure 70. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence.............................................................................73 Figure 71. RESET Timing.............................................................................................................................................................79 Figure 72. Maximum Negative Overshoot Waveform...................................................................................................................81 Figure 73. Maximum Positive Overshoot Waveform.....................................................................................................................81 Figure 74. Input Test Waveforms and Measurement Level..........................................................................................................82 Figure 75. Output Loading............................................................................................................................................................82 Figure 76. SCLK TIMING DEFINITION........................................................................................................................................82 Figure 77. AC Timing at Device Power-Up...................................................................................................................................86 Figure 78. Power-Down Sequence...............................................................................................................................................87 Figure 79. Power-up Timing..........................................................................................................................................................88 Figure 80. Power Up/Down and Voltage Drop..............................................................................................................................88 Macronix Proprietary 4 Rev. 1.9, March 13, 2019 MX25U12835F 1.8V 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY 1. FEATURES • Deep Power Down: 1.5uA(typ.) • Typical 100,000 erase/program cycles • 20 years data retention GENERAL • Supports Serial Peripheral Interface -- Mode 0 and Mode 3 • 134,217,728 x 1 bit structure or 67,108,864 x 2 bits (two I/O mode) structure or 33,554,432 x 4 bits (four I/O mode) structure • Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each - Any Block can be erased individually • Single Power Supply Operation - 1.65 to 2.0 volt for read, erase, and program operations • Latch-up protected to 100mA from -1V to Vcc +1V • Low Vcc write inhibit is from 1.0V to 1.4V SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Advanced Security Features - Block lock protection The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions - Additional 4k-bit secured OTP for unique identifier • Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector or block - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) • Status Register Feature • Command Reset • Program/Erase Suspend • Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - REMS command for 1-byte manufacturer ID and 1-byte device ID • Support Serial Flash Discoverable Parameters (SFDP) mode PERFORMANCE • High Performance - Fast read for SPI mode - 1 I/O: 104MHz with 8 dummy cycles - 2 I/O: 84MHz with 4 dummy cycles, equivalent to 168MHz - 4 I/O: 104MHz with 2+4 dummy cycles, equivalent to 416MHz - 4 I/O: 133MHz with 2+6 dummy cycles, equivalent to 532MHz (for MX25U12835FZNI-08G only) - Fast read for QPI mode - 4 I/O: 84MHz with 2+2 dummy cycles, equivalent to 336MHz - 4 I/O: 104MHz with 2+4 dummy cycles, equivalent to 416MHz - 4 I/O: 133MHz with 2+6 dummy cycles, equivalent to 532MHz (for MX25U12835FZNI-08G only) - Fast program time: 0.5ms(typ.) and 3ms(max.)/page (256-byte per page) - Byte program time: 12us (typical) - 8/16/32/64 byte Wrap-Around Burst Read Mode - Fast erase time: 35ms (typ.)/sector (4K-byte per sector); 200ms(typ.)/block (32K-byte per block), 350ms(typ.) /block (64K-byte per block) • Low Power Consumption - Low active read current: 20mA(typ.) at 104MHz, 15mA(typ.) at 84MHz, 27mA(typ.) at 133MHz (for MX25U12835FZNI-08G only) - Low active erase current: 18mA (typ.) at Sector Erase, Block Erase (32KB/64KB); 20mA at Chip Erase - Low active programming current: 20mA (typ.) - Standby current: 15uA (typ.) P/N: PM1728 HARDWARE FEATURES • SCLK Input - Serial clock input • SI/SIO0 - Serial Data Input or Serial Data Input/ Output for 2 x I/O read mode and 4 x I/O read mode • SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • WP#/SIO2 - Hardware write protection or serial data Input/Output for 4 x I/O read mode • RESET#/SIO3 - Hardware Reset pin or Serial input & Output for 4 x I/O read mode • PACKAGE - 16-pin SOP (300mil) - 8-land WSON (6x5mm) - 8-land WSON (8x6mm) - 23-ball WLCSP (Ball Diameter 0.30mm) - 8-pin SOP (200mil) - 24-Ball BGA (5x5 ball array) All devices are RoHS Compliant and Halogen-free Macronix Proprietary 5 Rev. 1.9, March 13, 2019 MX25U12835F 2. GENERAL DESCRIPTION MX25U12835F is 128Mb bits Serial NOR Flash memory, which is configured as 16,777,216 x 8 internally. When it is in two or four I/O mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x 4. MX25U12835F features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and RESET# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output. The MX25U12835F MXSMIO® (Serial Multi I/O) provides sequential read operation on the whole chip. After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis. Erase command is executed on 4K-byte sector, 32K-byte block, or 64K-byte block, or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced security features enhance the protection and security functions, please refer to security features section for more details. The MX25U12835F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. Table 1. Read Performance Read Performance MX25U12835F SPI QPI I/O 1 I/O 1I /2O 2 I/O 1I/4O 4 I/O 4 I/O 4 I/O 4 I/O 4 I/O Dummy Cycle 8 8 4 8 6 8 4 6 8 MHz 104 MHz 104MHz 84 MHz 104MHz 104 MHz 133 MHz* 84 MHz 104 MHz 133 MHz* * For MX25U12835FZNI-08G only P/N: PM1728 Macronix Proprietary 6 Rev. 1.9, March 13, 2019 MX25U12835F 3. PIN CONFIGURATIONS 24-BALL BGA (5x5 ball array) 16-PIN SOP (300mil) RESET#/SIO3 VCC NC NC NC NC CS# SO/SIO1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SCLK SI/SIO0 NC NC NC NC GND WP#/SIO2 5 4 3 8-WSON (6x5mm, 8x6mm) 1 2 3 4 CS# SO/SIO1 WP#/SIO2 GND NC NC RESET# VCC WP#/SIO2 DNU/SIO3 NC NC GND NC SI/SIO0 NC NC SCLK CS# SO/SIO1 NC NC NC NC NC B C D E VCC RESET#/SIO3 SCLK SI/SIO0 8 7 6 5 8-PIN SOP (200mil) VCC RESET#/SIO3 SCLK SI/SIO0 8 7 6 5 23-BALL BGA (WLCSP) TOP View A B 3 4 5 6 NC NC NC NC CS# NC NC RESET#/SIO3 SO/SIO1 NC D NC SCLK WP#/SIO2 NC E NC SI/SIO0 GND NC F NC C P/N: PM1728 VCC NC NC 1 4. PIN DESCRIPTION 1 2 3 4 1 2 NC 2 A CS# SO/SIO1 WP#/SIO2 GND NC NC NC Symbol CS# Description Chip Select Serial Data Input (for 1 x I/O)/ Serial SI/SIO0 Data Input & Output (for 2xI/O or 4xI/O read mode) Serial Data Output (for 1 x I/O)/ Serial SO/SIO1 Data Input & Output (for 2xI/O or 4xI/O read mode) SCLK Clock Input Write Protection Active low or Serial WP#/SIO2 Data Input & Output (for 4xI/O read mode)Note 1 Hardware Reset Pin Active low or Serial RESET#/SIO3 Data Input & Output (for 4xI/O read mode)Note 1 DNU/SIO3Note 2 Do Not Use or Serial Data Input & (24BGA) Output (for 4xI/O read mode) VCC + 1.8V Power Supply GND Ground Notes: 1. When using 1 I/O or 2 I/O (QE bit not enabled), the DNU/SIO3 pin of 24BGA can not connect to GND. We suggest user to connect this pin to VCC or floating. 2. The pin of RESET#/SIO3 or WP#/SIO2 will remain internal pull up function while this pin is not physically connected in system configuration. However, the internal pull up function will be disabled if the system has physical connection to RESET#/SIO3 or WP#/SIO2 pin. Macronix Proprietary 7 Rev. 1.9, March 13, 2019 MX25U12835F 5. BLOCK DIAGRAM X-Decoder Address Generator SI/SIO0 SO/SIO1 SIO2 * SIO3 * WP# * HOLD# * RESET# * CS# SCLK Memory Array Y-Decoder Data Register Sense Amplifier SRAM Buffer Mode Logic State Machine HV Generator Clock Generator Output Buffer * Depends on part number options. P/N: PM1728 Macronix Proprietary 8 Rev. 1.9, March 13, 2019 MX25U12835F 6. DATA PROTECTION During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully. In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise. • Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. • Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. • Deep Power Down Mode: By entering deep power down mode, the flash device is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES) and softreset command. • Advanced Security Features: there are some protection and security features which protect content from inadvertent write and hostile access. I. Block lock protection - The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The protected area definition is shown as "Table 2. Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. - The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status Register Write Protect bit. - In four I/O and QPI mode, the feature of HPM will be disabled. P/N: PM1728 Macronix Proprietary 9 Rev. 1.9, March 13, 2019 MX25U12835F Table 2. Protected Area Sizes Protected Area Sizes (T/B bit = 0) Status bit BP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BP2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Protect Level BP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128Mb 0 (none) 1 (1 block, protected block 255th) 2 (2 blocks, protected block 254th-255th) 3 (4 blocks, protected block 252nd-255th) 4 (8 blocks, protected block 248th-255th) 5 (16 blocks, protected block 240th-255th) 6 (32 blocks, protected block 224th-255th) 7 (64 blocks, protected block 192nd-255th) 8 (128 blocks, protected block 128th-255th) 9 (256 blocks, protected all) 10 (256 blocks, protected all) 11 (256 blocks, protected all) 12 (256 blocks, protected all) 13 (256 blocks, protected all) 14 (256 blocks, protected all) 15 (256 blocks, protected all) Protected Area Sizes (T/B bit = 1) Status bit BP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 P/N: PM1728 BP2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Protect Level BP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128Mb 0 (none) 1 (1 block, protected block 0th) 2 (2 blocks, protected block 0th-1st) 3 (4 blocks, protected block 0th-3rd) 4 (8 blocks, protected block 0th-7th) 5 (16 blocks, protected block 0th-15th) 6 (32 blocks, protected block 0th-31st) 7 (64 blocks, protected block 0th-63rd) 8 (128 blocks, protected block 0th-127th) 9 (256 blocks, protected all) 10 (256 blocks, protected all) 11 (256 blocks, protected all) 12 (256 blocks, protected all) 13 (256 blocks, protected all) 14 (256 blocks, protected all) 15 (256 blocks, protected all) Macronix Proprietary 10 Rev. 1.9, March 13, 2019 MX25U12835F II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit one-time program area for setting device unique serial number - Which may be set by factory or system customer. - Security register bit 0 indicates whether the secured OTP area is locked by factory or not. - To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with Enter Security OTP command), and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing Exit Security OTP command. - Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to "Table 9. Security Register Definition" for security register bit definition and "Table 3. 4K-bit Secured OTP Definition" for address range definition. - Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit secured OTP mode, array access is not allowed. Table 3. 4K-bit Secured OTP Definition Address range Size Standard Factory Lock xxx000 - xxx00F 128-bit ESN (electrical serial number) xxx010 - xxx1FF 3968-bit N/A P/N: PM1728 Macronix Proprietary 11 Customer Lock Determined by customer Rev. 1.9, March 13, 2019 MX25U12835F 7. Memory Organization Table 4. Memory Organization Block(64K-byte) Block(32K-byte) Sector 254 508 individual block lock/unlock unit:64K-byte 507 253 506 FF7FFFh individual 16 sectors lock/unlock unit:4K-byte … FF8FFFh FF7000h 4080 FF0000h FF0FFFh 4079 FEF000h FEFFFFh … 509 FF8000h 4087 4072 FE8000h FE8FFFh 4071 FE7000h FE7FFFh … 510 4088 4064 FE0000h FE0FFFh 4063 FDF000h FDFFFFh 4056 FD8000h FD8FFFh 4055 FD7000h FD7FFFh 4048 FD0000h FD0FFFh 47 02F000h 02FFFFh 40 028000h 028FFFh 39 027000h 027FFFh … 255 FFFFFFh … 511 Address Range FFF000h … 4095 5 … individual block lock/unlock unit:64K-byte individual block lock/unlock unit:64K-byte 3 01FFFFh 24 018000h 018FFFh 23 017000h 017FFFh 16 010000h 010FFFh 15 00F000h 00FFFFh 8 008000h 008FFFh 7 007000h 007FFFh 000000h 000FFFh 0 P/N: PM1728 individual 16 sectors lock/unlock unit:4K-byte … 0 0 020FFFh 01F000h … 1 020000h 31 … 1 2 32 … 4 … 2 Macronix Proprietary 12 Rev. 1.9, March 13, 2019 MX25U12835F 8. DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this device, this device becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this device should be High-Z. 3. When correct command is inputted to this device, this device becomes active mode and keeps the active mode until next CS# rising edge. 4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as "Figure 1. Serial Modes Supported". 5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, DREAD, 2READ, QREAD, 4READ, W4READ, RDSFDP, RES, REMS, QPIID, RDBLOCK, the shifted-in instruction sequence is followed by a dataout sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE32K, BE, CE, PP, 4PP, DP, ENSO, EXSO, WRSCUR, WPSEL, SBLK, SBULK, GBULK, SUSPEND, RESUME, NOP, RSTEN, RST, EQIO, RSTQIO the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Modes Supported CPOL CPHA shift in (Serial mode 0) 0 0 SCLK (Serial mode 3) 1 1 SCLK SI shift out MSB SO MSB Note: CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM1728 Macronix Proprietary 13 Rev. 1.9, March 13, 2019 MX25U12835F Figure 2. Serial Input Timing tSHSL CS# tCHSL tSLCH tCHSH tSHCH SCLK tDVCH tCHCL tCHDX tCLCH LSB MSB SI High-Z SO Figure 3. Output Timing CS# tCH SCLK tCLQV tCLQX tCL tCLQV tCLQX LSB SO SI P/N: PM1728 tSHQZ ADDR.LSB IN Macronix Proprietary 14 Rev. 1.9, March 13, 2019 MX25U12835F 8-1. Quad Peripheral Interface (QPI) Read Mode QPI protocol enables user to take full advantage of Quad I/O Serial NOR Flash by providing the Quad I/O interface in command cycles, address cycles and as well as data output cycles. Enable QPI mode By issuing EQIO command (35h), the QPI mode is enabled. Figure 4. Enable QPI Sequence (Command 35h) CS# MODE 3 SCLK 0 1 2 3 4 5 6 7 MODE 0 SIO0 35 SIO[3:1] Reset QPI (RSTQIO) To reset the QPI mode, the RSTQIO (F5h) command is required. After the RSTQIO command is issued, the device returns from QPI mode (4 I/O interface in command cycles) to SPI mode (1 I/O interface in command cycles). Note: For EQIO and RSTQIO commands, CS# high width has to follow "write spec" tSHSL (as defined in "Table 19. AC Characteristics") for next instruction. Figure 5. Reset QPI Mode (Command F5h) CS# SCLK SIO[3:0] P/N: PM1728 F5 Macronix Proprietary 15 Rev. 1.9, March 13, 2019 MX25U12835F 9. COMMAND DESCRIPTION Table 5. Command Set Read/Write Array Commands Mode SPI SPI/QPI Command (byte) READ (normal read) FAST READ (fast read data) 1st byte 03 (hex) 0B (hex) nd 2 byte SPI 2READ (2 x I/O read command) BB (hex) SPI/QPI SPI/QPI 4READ (4 x I/O read) 4READ (4 x I/O read) EB (hex) EB (hex) ADD1(8) ADD1(8) ADD1(4) ADD1(2) ADD1(2) 3rd byte ADD2(8) ADD2(8) ADD2(8) ADD2(4) ADD2(2) ADD2(2) 4th byte ADD3(8) ADD3(8) ADD3(8) ADD3(4) ADD3(2) ADD3(2) Dummy(6) Dummy(Note 2) Quad I/O read with 6 dummy cycles Quad I/O read with configurable dummy cycles SPI/QPI SPI/QPI 5th byte Action Mode ADD1(8) (Note 4) SPI DREAD (1I / 2O read command) 3B (hex) Dummy(8)/(4) Dummy(8) Dummy(4)(Note 3) (Note 1) n bytes read out n bytes read out n bytes read out n bytes read out until CS# goes until CS# goes by Dual Output by 2 x I/O until high high until CS# goes CS# goes high high SPI SPI SPI/QPI SPI 1st byte E7 (hex) 6B (hex) 02 (hex) 4PP (quad page program) 38 (hex) 20 (hex) BE 32K (block erase 32KB) 52 (hex) 2nd byte ADD1(2) ADD1(8) ADD1 ADD1 ADD1 ADD1 ADD2(2) ADD2(8) ADD2 ADD2 ADD2 ADD2 ADD3 ADD3 ADD3 ADD3 to program the selected page quad input to program the selected page to erase the selected sector to erase the selected 32K block Command (byte) rd 3 byte th W4READ QREAD (1I/4O read) PP (page program) 4 byte ADD3(2) ADD3(8) 5th byte Dummy(4) Dummy(8) Action Mode Quad I/O read n bytes read out for with 4 dummy by Quad output cycles until CS# goes high SPI/QPI 1st byte BE (block erase 64KB) D8 (hex) 2nd byte ADD1 Command (byte) 3rd byte ADD2 4th byte ADD3 SE (sector erase) SPI/QPI CE (chip erase) 60 or C7 (hex) 5th byte Action to erase the selected block to erase whole chip Note 1: The fast read command (0Bh) when under QPI mode, the dummy cycle is 4 clocks. Note 2: Dummy cycle number will be different, depending on the bit7 (DC) setting of Configuration Register. Please refer to "Configuration Register" Table. Only MX25U12835FZNI-08G supports 4READ with 8 dummy cycles. Note 3: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SO/SIO1, which is different from 1 x I/O condition. Note 4: The number in parentheses after "ADD" or "Data" stands for how many clock cycles it has. For example, "Data(8)" represents there are 8 clock cycles for the data in. P/N: PM1728 Macronix Proprietary 16 Rev. 1.9, March 13, 2019 MX25U12835F Register/Setting Commands Mode SPI/QPI SPI/QPI SPI/QPI RDCR (read configuration register) SPI/QPI 1st byte 06 (hex) 04 (hex) 05 (hex) 15 (hex) Command (byte) WREN WRDI (write enable) (write disable) RDSR (read status register) WRSR (write status/ configuration register) SPI/QPI 01 (hex) 2nd byte Values 3rd byte Values WPSEL (Write Protect Selection) EQIO (Enable QPI) SPI/QPI SPI 68 (hex) 35 (hex) 4th byte 5th byte Action sets the (WEL) resets the to read out the to read out the write enable (WEL) write values of the values of the latch bit enable latch bit status register configuration register Command (byte) RSTQIO (Reset QPI) Mode 1st byte QPI F5 (hex) PGM/ERS Suspend (Suspends Program/ Erase) SPI/QPI B0 (hex) PGM/ERS Resume (Resumes Program/ Erase) SPI/QPI 30 (hex) to write new to enter and values of the enable individal status/ block protect configuration mode register DP (Deep power down) RDP (Release from deep power down) SBL (Set Burst Length) SPI/QPI B9 (hex) SPI/QPI AB (hex) SPI/QPI C0 (hex) 2nd byte Entering the QPI mode Value rd 3 byte 4th byte 5th byte Action P/N: PM1728 Exiting the QPI mode enters deep power down mode Macronix Proprietary 17 release from deep power down mode to set Burst length Rev. 1.9, March 13, 2019 MX25U12835F ID/Security Commands Command (byte) Mode 1st byte RDID RES (read (read identificelectronic ID) ation) SPI 9F (hex) SPI/QPI AB (hex) REMS (read electronic QPIID manufacturer (QPI ID Read) & device ID) SPI QPI 90 (hex) AF (hex) RDSFDP SPI/QPI 5A (hex) 2nd byte x x ADD1(8) 3rd byte x x ADD2(8) 4th byte x ADD(Note 5) 5 byte COMMAND (byte) Mode 1st byte outputs JEDEC to read out output the ID: 1-byte 1-byte Device Manufacturer Manufacturer ID ID & Device ID ID & 2-byte Device ID RDSCUR WRSCUR (read security (write security register) register) SPI/QPI SPI/QPI 2B (hex) 2F (hex) SPI/QPI B1 (hex) SPI/QPI C1 (hex) ADD3(8) th Action ENSO (enter EXSO (exit secured OTP) secured OTP) SBLK (single block lock SPI/QPI 36 (hex) ID in QPI interface SBULK (single block unlock) SPI/QPI 39 (hex) Dummy(8) n bytes read to enter the to exit the 4Kout until CS# 4K-bit secured bit secured goes high OTP mode OTP mode RDBLOCK (block protect read) SPI/QPI 3C (hex) 2nd byte ADD1 ADD1 ADD1 3rd byte ADD2 ADD2 ADD2 4th byte ADD3 ADD3 ADD3 GBLK (gang block lock) SPI/QPI 7E (hex) GBULK (gang block unlock) SPI/QPI 98 (hex) whole chip write protect whole chip unprotect 5th byte Action to read value to set the lockindividual individual block read individual of security down bit as block (64K(64K-byte) or block or sector register "1" (once lock- byte) or sector sector (4Kwrite protect down, cannot (4K-byte) write byte) unprotect status be update) protect Note 5: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first. P/N: PM1728 Macronix Proprietary 18 Rev. 1.9, March 13, 2019 MX25U12835F Reset Commands Mode SPI/QPI SPI/QPI RST (Reset Memory) SPI/QPI 1st byte 00 (hex) 66 (hex) 99 (hex) COMMAND (byte) NOP RSTEN (No Operation) (Reset Enable) nd 2 byte 3rd byte 4th byte 5th byte Action (Note 6) Note 5: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode. Note 6: The RSTEN command must be executed before executing the RST command. If any other command is issued in-between RSTEN and RST, the RST command will be ignored. P/N: PM1728 Macronix Proprietary 19 Rev. 1.9, March 13, 2019 MX25U12835F 9-1. Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP, SE, BE32K, BE, CE, and WRSR, which are intended to change the device content WEL bit should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. Figure 6. Write Enable (WREN) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 Command SI 06h High-Z SO Figure 7. Write Enable (WREN) Sequence (QPI Mode) CS# 0 Mode 3 1 SCLK Mode 0 Command 06h SIO[3:0] P/N: PM1728 Macronix Proprietary 20 Rev. 1.9, March 13, 2019 MX25U12835F 9-2. Write Disable (WRDI) The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. The WEL bit is reset by following situations: - Power-up - Reset# pin driven low - WRDI command completion - WRSR command completion - PP command completion - 4PP command completion - SE command completion - BE32K command completion - BE command completion - CE command completion - PGM/ERS Suspend command completion - Softreset command completion - WRSCUR command completion - WPSEL command completion - GBLK command completion - GBULK command completion Figure 8. Write Disable (WRDI) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 Command SI 04h High-Z SO Figure 9. Write Disable (WRDI) Sequence (QPI Mode) CS# 0 Mode 3 1 SCLK Mode 0 Command 04h SIO[3:0] P/N: PM1728 Macronix Proprietary 21 Rev. 1.9, March 13, 2019 MX25U12835F 9-3. Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix Manufacturer ID and Device ID are listed as "Table 6. ID Definitions". The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out on SO→ to end RDID operation can drive CS# to high at any time during data out. While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. Figure 10. Read Identification (RDID) Sequence (SPI mode only) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 SCLK Mode 0 Command SI 9Fh Manufacturer Identification SO High-Z 7 6 5 3 2 1 MSB P/N: PM1728 Device Identification 0 15 14 13 3 2 1 0 MSB Macronix Proprietary 22 Rev. 1.9, March 13, 2019 MX25U12835F 9-4. Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, the transition to the Stand-by Power mode is delayed by tRES1, and Chip Select (CS#) must remain High for at least tRES1(max), as specified in "Table 19. AC Characteristics". AC Characteristics. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The RDP instruction is only for releasing from Deep Power Down Mode. Reset# pin goes low will release the Flash from deep power down mode. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 6. ID Definitions". This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. Figure 11. Read Electronic Signature (RES) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 SCLK Mode 0 Command SI ABh tRES2 3 Dummy Bytes 23 22 21 3 2 1 0 MSB SO Electronic Signature Out High-Z 7 6 5 4 3 2 1 0 MSB Deep Power-down Mode P/N: PM1728 Macronix Proprietary 23 Stand-by Mode Rev. 1.9, March 13, 2019 MX25U12835F Figure 12. Read Electronic Signature (RES) Sequence (QPI Mode) CS# MODE 3 0 1 2 3 4 5 6 7 SCLK MODE 0 3 Dummy Bytes Command SIO[3:0] X ABh X X X X X H0 L0 MSB LSB Data In Data Out Stand-by Mode Deep Power-down Mode Figure 13. Release from Deep Power-down (RDP) Sequence (SPI Mode) CS# 0 Mode 3 1 2 3 4 5 6 tRES1 7 SCLK Mode 0 Command SI ABh High-Z SO Deep Power-down Mode Stand-by Mode Figure 14. Release from Deep Power-down (RDP) Sequence (QPI Mode) CS# Mode 3 tRES1 0 1 SCLK Mode 0 Command SIO[3:0] ABh Deep Power-down Mode P/N: PM1728 Macronix Proprietary 24 Stand-by Mode Rev. 1.9, March 13, 2019 MX25U12835F 9-5. Read Electronic Manufacturer ID & Device ID (REMS) The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID values are listed in "Table 6. ID Definitions". The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed by two dummy bytes and one address byte (A7-A0). After which the manufacturer ID for Macronix (C2h) and the device ID are shifted out on the falling edge of SCLK with the most significant bit (MSB) first. If the address byte is 00h, the manufacturer ID will be output first, followed by the device ID. If the address byte is 01h, then the device ID will be output first, followed by the manufacturer ID. While CS# is low, the manufacturer and device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Figure 15. Read Electronic Manufacturer & Device ID (REMS) Sequence (SPI Mode only) CS# SCLK Mode 3 0 1 2 Mode 0 3 4 5 6 7 8 Command SI 9 10 2 Dummy Bytes 15 14 13 90h 3 2 1 0 High-Z SO CS# 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK ADD (1) SI 7 6 5 4 3 2 1 0 Manufacturer ID SO 7 6 5 4 3 2 1 Device ID 0 7 6 5 4 3 2 MSB MSB 1 0 7 MSB Notes: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first. (2) Instruction is 90h (hex). P/N: PM1728 Macronix Proprietary 25 Rev. 1.9, March 13, 2019 MX25U12835F 9-6. QPI ID Read (QPIID) User can execute this ID Read instruction to identify the Device ID and Manufacturer ID. The sequence of issue QPIID instruction is CS# goes low→sending QPI ID instruction→Data out on SO→CS# goes high. Most significant bit (MSB) first. After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID, memory type, and device ID data byte will be output continuously, until the CS# goes high. Table 6. ID Definitions Command Type Command RDID / QPIID 9Fh / AFh RES ABh REMS 90h P/N: PM1728 MX25U12835F Manufacturer ID C2 Memory Type 25 Electronic ID 38 Device ID 38 Manufacturer ID C2 Macronix Proprietary 26 Memory Density 38 Rev. 1.9, March 13, 2019 MX25U12835F 9-7. Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data out on SO. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. Figure 16. Read Status Register (RDSR) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Mode 0 command 05h SI SO Status Register Out High-Z 7 6 5 4 3 2 Status Register Out 1 0 7 6 5 4 3 2 1 0 7 MSB MSB Figure 17. Read Status Register (RDSR) Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 N SCLK Mode 0 SIO[3:0] 05h H0 L0 H0 L0 H0 L0 H0 L0 MSB LSB Status Byte Status Byte Status Byte P/N: PM1728 Macronix Proprietary 27 Status Byte Rev. 1.9, March 13, 2019 MX25U12835F 9-8. Read Configuration Register (RDCR) The RDCR instruction is for reading Configuration Register Bits. The Read Configuration Register can be read at any time (even in program/erase/write configuration register condition). It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write configuration register operation is in progress. The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configuration Register data out on SO. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. Figure 18. Read Configuration Register (RDCR) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Mode 0 command 15h SI SO Configuration register Out High-Z 7 6 5 4 3 2 1 0 Configuration register Out 7 6 5 4 3 2 1 0 7 MSB MSB Figure 19. Read Configuration Register (RDCR) Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 N SCLK Mode 0 SIO[3:0] 15h H0 L0 H0 L0 H0 L0 H0 L0 MSB LSB Config. Byte Config. Byte Config. Byte P/N: PM1728 Macronix Proprietary 28 Config. Byte Rev. 1.9, March 13, 2019 MX25U12835F For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows: Figure 20. Program/Erase flow with read array data start WREN command RDSR command* WEL=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command WIP=0? No Yes RDSR command Read WEL=0, BP[3:0], QE, and SRWD data Read array data (same address of PGM/ERS) Verify OK? No Yes Program/erase successfully Program/erase another block? No Program/erase fail Yes * Issue RDSR to check BP[3:0]. * If WPSEL = 1, issue RDBLOCK to check the block status. Program/erase completed P/N: PM1728 Macronix Proprietary 29 Rev. 1.9, March 13, 2019 MX25U12835F Figure 21. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag) start WREN command RDSR command* WEL=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command WIP=0? No Yes RDSR command Read WEL=0, BP[3:0], QE, and SRWD data RDSCUR command Yes P_FAIL/E_FAIL =1 ? No Program/erase fail Program/erase successfully Program/erase another block? No Yes * Issue RDSR to check BP[3:0]. * If WPSEL = 1, issue RDBLOCK to check the block status. Program/erase completed P/N: PM1728 Macronix Proprietary 30 Rev. 1.9, March 13, 2019 MX25U12835F Status Register The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit is a volatile bit that is set to “1” by the WREN instruction. WEL needs to be set to “1” before the device can accept program and erase instructions, otherwise the program and erase instructions are ignored. WEL automatically clears to “0” when a program or erase operation completes. To ensure that both WIP and WEL are “0” and the device is ready for the next program or erase operation, it is recommended that WIP be confirmed to be “0” before checking that WEL is also “0” (Please refer to "Figure 24. WRSR flow"). If a program or erase instruction is applied to a protected memory area, the instruction will be ignored and WEL will clear to “0”. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined in "Table 2. Protected Area Sizes") of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase 32KB (BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if Block Protect bits (BP3:BP0) set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default, which is unprotected. QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP#, RESET# are enable. While QE is "1", it performs Quad I/O mode and WP#, RESET# are disabled. In the other word, if the system goes into four I/O mode (QE=1), the feature of HPM and RESET will be disabled. SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The SRWD bit defaults to be "0". Table 7. Status Register bit7 bit6 SRWD (status register write protect) QE (Quad Enable) 1=status register write 1=Quad disabled Enable 0=status 0=not Quad register write Enable enabled Non-volatile bit Non-volatile bit bit5 BP3 (level of protected block) bit4 BP2 (level of protected block) bit3 BP1 (level of protected block) bit2 BP0 (level of protected block) (note 1) (note 1) (note 1) (note 1) Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit bit1 bit0 WEL WIP (write enable (write in latch) progress bit) 1=write 1=write enable operation 0=not write 0=not in write enable operation volatile bit volatile bit Note 1: Please refer to the "Table 2. Protected Area Sizes". P/N: PM1728 Macronix Proprietary 31 Rev. 1.9, March 13, 2019 MX25U12835F Configuration Register The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured after the CR bit is set. ODS bit The output driver strength (ODS2, ODS1, ODS0) bits are volatile bits, which indicate the output driver level (as defined in Output Driver Strength Table) of the device. The Output Driver Strength is defaulted as 30 Ohms when delivered from factory. To write the ODS bits requires the Write Status Register (WRSR) instruction to be executed. TB bit The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as “0”, which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory device. To write the TB bits requires the Write Status Register (WRSR) instruction to be executed. Configuration Register bit7 bit6 DC (Dummy Reserved Cycle) (note 2) bit5 bit4 Reserved Reserved x x x bit3 bit2 bit1 bit0 TB ODS 2 ODS 1 ODS 0 (top/bottom (output driver (output driver (output driver selected) strength) strength) strength) 0=Top area protect (note 1) (note 1) (note 1) 1=Bottom area protect (Default=0) OTP volatile bit volatile bit volatile bit Volatile bit x x x Note 1: Please refer to "Output Driver Strength Table" Note 2: For 4READ command on MX25U12835FZNI-08G (f=133MHz) only. Please refer to "Dummy Cycle and Frequency Table" for details. Output Driver Strength Table ODS2 0 0 0 0 1 1 1 1 ODS1 0 0 1 1 0 0 1 1 ODS0 0 1 0 1 0 1 0 1 Description Reserved 90 Ohms 60 Ohms 45 Ohms Reserved 20 Ohms 15 Ohms 30 Ohms (Default) Note Impedance at VCC/2 Dummy Cycle and Frequency Table DC Numbers of Dummy clock cycles Quad I/O Read 1 8 133 0 (default) 6 104 Note: For 4READ command on MX25U12835FZNI-08G (f=133MHz) only. P/N: PM1728 Macronix Proprietary 32 Rev. 1.9, March 13, 2019 MX25U12835F 9-9. Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in "Table 2. Protected Area Sizes"). The WRSR also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register data on SI→CS# goes high. The CS# must go high exactly at the 8 bites or 16 bits data boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. Figure 22. Write Status Register (WRSR) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK Mode 0 SI SO command 01h Status Register In 7 6 4 5 2 3 Configuration Register In 0 15 14 13 12 11 10 9 1 8 MSB High-Z Note: The CS# must go high exactly at 8 bits or 16 bits data boundary to completed the write register command. Figure 23. Write Status Register (WRSR) Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 Mode 3 SCLK Mode 0 Mode 0 Command SIO[3:0] P/N: PM1728 SR in H0 01h L0 CR in H1 Macronix Proprietary 33 L1 Rev. 1.9, March 13, 2019 MX25U12835F Software Protected Mode (SPM): - When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM). - When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM) Note: If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed. Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification. Note: To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0. If the system enter QPI or set QE=1, the feature of HPM will be disabled. Table 8. Protection Modes Mode Software protection mode (SPM) Hardware protection mode (HPM) Status register condition WP# and SRWD bit status Memory Status register can be written in (WEL bit is set to "1") and the SRWD, BP0-BP3 bits can be changed WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1 The protected area cannot be program or erase. The SRWD, BP0-BP3 of status register bits cannot be changed WP#=0, SRWD bit=1 The protected area cannot be program or erase. Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in "Table 2. Protected Area Sizes". P/N: PM1728 Macronix Proprietary 34 Rev. 1.9, March 13, 2019 MX25U12835F Figure 24. WRSR flow start WREN command RDSR command No WEL=1? Yes WRSR command Write status register and Configuration register data RDSR command No WIP=0? Yes RDSR command Read WEL=0, BP[3:0], QE, and SRWD data No Verify OK? Yes WRSR successfully P/N: PM1728 WRSR fail Macronix Proprietary 35 Rev. 1.9, March 13, 2019 MX25U12835F Figure 25. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 WP# tSHWL tWHSL CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK 01h SI SO P/N: PM1728 High-Z Macronix Proprietary 36 Rev. 1.9, March 13, 2019 MX25U12835F 9-10. Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte address on SI→ data out on SO→to end READ operation can use CS# to high at any time during data out. Figure 26. Read Data Bytes (READ) Sequence (SPI Mode only) CS# Mode 3 0 1 2 3 4 5 6 7 8 28 29 30 31 32 33 34 35 36 37 38 39 9 10 SCLK Mode 0 SI command 03h 24-Bit Address 23 22 21 3 2 1 0 MSB SO Data Out 1 High-Z 7 6 5 4 3 2 Data Out 2 1 0 7 MSB P/N: PM1728 Macronix Proprietary 37 Rev. 1.9, March 13, 2019 MX25U12835F 9-11. Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. Read on SPI Mode The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→ 3-byte address on SI→1-dummy byte (default) address on SI→ data out on SO→ to end FAST_ READ operation can use CS# to high at any time during data out. Read on QPI Mode The sequence of issuing FAST_READ instruction in QPI mode is: CS# goes low→ sending FAST_READ instruction, 2 cycles→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→4 dummy cycles→data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QPI FAST_READ operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. P/N: PM1728 Macronix Proprietary 38 Rev. 1.9, March 13, 2019 MX25U12835F Figure 27. Read at Higher Speed (FAST_READ) Sequence (SPI Mode) CS# SCLK Mode 3 0 1 2 Mode 0 3 4 5 6 7 8 9 10 Command SI 28 29 30 31 24-Bit Address 23 22 21 0Bh 3 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Cycle 7 SI 6 5 4 3 2 0 1 DATA OUT 2 DATA OUT 1 7 SO 6 5 4 3 2 1 0 7 6 5 4 3 2 1 MSB MSB 0 7 MSB Figure 28. Read at Higher Speed (FAST_READ) Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 A5 A4 A3 A2 A1 A0 8 9 10 11 12 13 14 15 H1 L1 SCLK Mode 0 Command SIO(3:0) 0Bh Data In P/N: PM1728 X X X X H0 L0 MSB LSB MSB LSB 24-Bit Address Data Out 1 Data Out 2 Macronix Proprietary 39 Rev. 1.9, March 13, 2019 MX25U12835F 9-12. Dual Read Mode (DREAD) The DREAD instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 3-byte address on SI → 8-bit dummy cycle → data out interleave on SIO1 & SIO0 → to end DREAD operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Figure 29. Dual Read Mode Sequence (Command 3B) CS# 0 1 2 3 4 5 6 7 8 SCLK … Command SI/SIO0 SO/SIO1 P/N: PM1728 30 31 32 9 3B … 24 ADD Cycle A23 A22 … 39 40 41 42 43 44 45 A1 A0 High Impedance 8 dummy cycle Data Out 1 Data Out 2 D6 D4 D2 D0 D6 D4 D7 D5 D3 D1 D7 D5 Macronix Proprietary 40 Rev. 1.9, March 13, 2019 MX25U12835F 9-13. 2 x I/O Read Mode (2READ) The 2READ instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address interleave on SIO1 & SIO0→ 4 dummy cycles on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end 2READ operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Figure 30. 2 x I/O Read Mode Sequence (SPI Mode only) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Mode 3 SCLK Mode 0 Command SI/SIO0 SO/SIO1 P/N: PM1728 BBh 12 ADD Cycles 4 Dummy cycle Data Out 1 Data Out 2 A22 A20 A18 A4 A2 A0 D6 D4 D2 D0 D6 D4 D2 D0 A23 A21 A19 A5 A3 A1 D7 D5 D3 D1 D7 D5 D3 D1 Macronix Proprietary 41 Mode 0 Rev. 1.9, March 13, 2019 MX25U12835F 9-14. Quad Read Mode (QREAD) The QREAD instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before sending the QREAD instruction. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit. The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte address on SI → 8-bit dummy cycle → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Figure 31. Quad Read Mode Sequence (Command 6B) CS# 0 1 2 3 4 5 6 7 8 … Command SI/SIO0 SO/SIO1 SIO2 SIO3 P/N: PM1728 29 30 31 32 33 9 SCLK 6B … 24 ADD Cycles A23 A22 … 38 39 40 41 42 A2 A1 A0 High Impedance 8 dummy cycles Data Data Out 1 Out 2 Data Out 3 D4 D0 D4 D0 D4 D5 D1 D5 D1 D5 High Impedance D6 D2 D6 D2 D6 High Impedance D7 D3 D7 D3 D7 Macronix Proprietary 42 Rev. 1.9, March 13, 2019 MX25U12835F 9-15. 4 x I/O Read Mode (4READ) The 4READ instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. 4 x I/O Read on SPI Mode (4READ) The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→2+4 dummy cycles→data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out. 4 x I/O Read on QPI Mode (4READ) The 4READ instruction also support on QPI command mode. The sequence of issuing 4READ instruction QPI mode is: CS# goes low→ sending 4READ instruction→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→2+4 dummy cycles (default) →data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out. Another sequence of issuing 4READ instruction especially useful in random access is: CS# goes low→send 4READ instruction→3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0→performance enhance toggling bit P[7:0]→ 4 dummy cycles →data out until CS# goes high → CS# goes low (The following 4READ instruction is not allowed, hence 8 cycles of 4READ can be saved comparing to normal 4READ mode) → 24-bit random access address. In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh,00h,AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. W4READ instruction (E7h) is also available for 4 I/O read. Please refer to "Figure 36. W4READ (Quad Read with 4 dummy cycles) Sequence". P/N: PM1728 Macronix Proprietary 43 Rev. 1.9, March 13, 2019 MX25U12835F Figure 32. 4 x I/O Read Mode Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Mode 3 SCLK Mode 0 Command 6 ADD Cycles EBh Performance enhance indicator (Note2) 4 Dummy Cycles Data Out 1 Data Out 2 Data Out 3 A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 D4 D0 SIO1 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 D1 SIO2 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 D2 SIO3 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 D3 SIO0 Mode 0 Figure 33. 4 x I/O Read Mode Sequence (SPI Mode), for MX25U12835FZNI-08G only CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Mode 3 SCLK Mode 0 Command 6 ADD Cycles Configurable Dummy cycles (Note 3) Performance enhance indicator (Note2) EBh Data Out 1 Data Out 2 Data Out 3 A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 D4 D0 SIO1 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 D1 SIO2 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 D2 SIO3 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 D3 SIO0 Mode 0 Note: 1. Hi-impedance is inhibited for the two clock cycles. 2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited. 3. The Configurable Dummy Cycle (default = 6) is set by Configuration Register Bit . Please check "Dummy Cycle and Frequency Table" for details. P/N: PM1728 Macronix Proprietary 44 Rev. 1.9, March 13, 2019 MX25U12835F Figure 34. 4 x I/O Read Mode Sequence (QPI Mode) CS# MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MODE 3 SCLK MODE 0 MODE 0 SIO[3:0] EB A5 A4 A3 A2 A1 A0 Data In 24-bit Address X X X X X X H0 L0 H1 L1 H2 L2 H3 L3 MSB Data Out Figure 35. 4 x I/O Read Mode Sequence (QPI Mode), for MX25U12835FZNI-08G only CS# MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MODE 3 SCLK MODE 0 SIO[3:0] MODE 0 EB Data In A5 A4 A3 A2 24-bit Address (Note) A1 A0 X X X X X Configurable Dummy cycle X H0 L0 H1 L1 H2 L2 H3 L3 MSB Data Out Note: The Configurable Dummy Cycle (default = 6) is set by Configuration Register Bit. Please check "Dummy Cycle and Frequency Table" for details. P/N: PM1728 Macronix Proprietary 45 Rev. 1.9, March 13, 2019 MX25U12835F Figure 36. W4READ (Quad Read with 4 dummy cycles) Sequence CS# Mode 3 SCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 0 4 Dummy Cycles Data Out 2 Data Out 3 A20 A16 A12 A8 A4 A0 D4 D0 D4 D0 D4 D0 D4 SIO1 A21 A17 A13 A9 A5 A1 D5 D1 D5 D1 D5 D1 D5 SIO2 A22 A18 A14 A10 A6 A2 D6 D2 D6 D2 D6 D2 D6 SIO3 A23 A19 A15 A11 A7 A3 D7 D3 D7 D3 D7 D3 D7 Command SIO0 P/N: PM1728 E7h 6 ADD Cycles Macronix Proprietary 46 Data Out 1 Rev. 1.9, March 13, 2019 MX25U12835F 9-16. Burst Read This device supports Burst Read in both SPI and QPI mode. To set the Burst length, following command operation is required Issuing command: “C0h” in the first Byte (8-clocks), following 4 clocks defining wrap around enable with “0h” and disable with“1h”. Next 4 clocks is to define wrap around depth. Definition as following table: Data 00h 01h 02h 03h 1xh Wrap Around Yes Yes Yes Yes No Wrap Depth 8-byte 16-byte 32-byte 64-byte X The wrap around unit is defined within the 256Byte page, with random initial address. It’s defined as “wrap-around mode disable” for the default state of the device. To exit wrap around, it is required to issue another “C0h” command in which data=‘1xh”. Otherwise, wrap around status will be retained until power down or reset command. To change wrap around depth, it is requried to issue another “C0h” command in which data=“0xh”. QPI “0Bh” “EBh” and SPI “EBh” “E7h” support wrap around feature after wrap around enable. However, the RDID command is default without Burst read. Figure 37. Burst Read (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 D7 D6 10 11 12 13 14 15 SCLK Mode 0 SIO C0h D5 D4 D3 D2 D1 D0 Figure 38. Burst Read (QPI Mode) CS# Mode 3 0 1 2 3 H0 L0 SCLK Mode 0 SIO[3:0] C0h MSB LSB Note: MSB=Most Significant Bit LSB=Least Significant Bit P/N: PM1728 Macronix Proprietary 47 Rev. 1.9, March 13, 2019 MX25U12835F 9-17. Performance Enhance Mode The device could waive the command cycle bits if the two cycle bits after address cycle toggles. Performance enhance mode is supported in both SPI and QPI mode. In QPI mode, “EBh” “0Bh” and SPI “EBh” “E7h” commands support enhance mode. The performance enhance mode is not supported in dual I/O mode. After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of the first clock as address instead of command cycle. To exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. Or issue ”FFh” data cycle to exit enhance mode. P/N: PM1728 Macronix Proprietary 48 Rev. 1.9, March 13, 2019 MX25U12835F Figure 39. 4 x I/O Read Performance Enhance Mode Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 n SCLK Mode 0 Data Out 2 Data Out n A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 D4 D0 SIO1 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 D1 SIO2 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 D2 SIO3 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 D3 Command EBh SIO0 6 ADD Cycles Performance enhance indicator (Note) 4 Dummy Cycles Data Out 1 CS# n+1 ........... n+7 ...... n+9 ........... n+13 ........... Mode 3 SCLK 6 ADD Cycles Performance enhance indicator (Note) 4 Dummy Cycles Data Out 1 Data Out 2 Data Out n SIO0 A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 D4 D0 SIO1 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 D1 SIO2 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 D2 SIO3 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 D3 Mode 0 Note: 1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F, if not using performance enhance recommend to keep 1 or 0 in performance enhance indicator. 2. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF. P/N: PM1728 Macronix Proprietary 49 Rev. 1.9, March 13, 2019 MX25U12835F Figure 40. 4 x I/O Read Performance Enhance Mode Sequence (SPI Mode), for MX25U12835FZNI-08G only CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 n SCLK Mode 0 Configurable Dummy cycles Data Out 2 Data Out n A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 D4 D0 SIO1 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 D1 SIO2 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 D2 SIO3 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 D3 Command EBh SIO0 6 ADD Cycles Performance enhance indicator (Note1) (Note 2) Data Out 1 CS# n+1 ........... n+7 ...... n+9 ........... n+13 ........... Mode 3 SCLK 6 ADD Cycles Configurable Dummy cycles Performance enhance indicator (Note1) Data Out 1 (Note 2) Data Out 2 Data Out n SIO0 A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 D4 D0 SIO1 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 D1 SIO2 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 D2 SIO3 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 D3 Mode 0 Note: 1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F, if not using performance enhance recommend to keep 1 or 0 in performance enhance indicator. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF. 2. The Configurable Dummy Cycle (default = 6) is set by Configuration Register Bit. Please refer to "Dummy Cycle and Frequency Table" for details. P/N: PM1728 Macronix Proprietary 50 Rev. 1.9, March 13, 2019 MX25U12835F Figure 41. 4 x I/O Read Performance Enhance Mode Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 A1 A0 8 9 10 11 12 13 14 15 16 17 H0 L0 H1 L1 SCLK Mode 0 SIO[3:0] A5 EBh A4 A3 A2 X X X X MSB LSB MSB LSB P(7:4) P(3:0) Data In 4 dummy cycles performance enhance indicator Data Out CS# n+1 ............. SCLK Mode 0 SIO[3:0] A5 A4 A3 A2 A1 X A0 X X X P(7:4) P(3:0) 6 Address cycles H0 L0 H1 L1 MSB LSB MSB LSB 4 dummy cycles performance enhance indicator Data Out Note: Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF. Figure 42. 4 x I/O Read Performance Enhance Mode Sequence (QPI Mode), for MX25U12835FZNI-08G only CS# MODE 3 0 1 2 3 4 5 6 7 A1 A0 8 9 10 11 12 13 14 15 16 17 H0 L0 H1 L1 SCLK MODE 0 SIO[3:0] EBh A5 A4 A3 A2 X X X X MSB LSB MSB LSB P(7:4) P(3:0) Data In performance enhance indicator Configurable Dummy cycles (Note) Data Out CS# n+1 ............. SCLK MODE 0 SIO[3:0] A5 A4 A3 A2 A1 6 Address cycles X A0 X X X H0 L0 H1 L1 MSB LSB MSB LSB P(7:4) P(3:0) performance enhance indicator Configurable Dummy cycles (Note) Data Out Note: 1. The Configurable Dummy Cycle (default = 6) is set by Configuration Register Bit . Please refer to "Dummy Cycle and Frequency Table" for details. 2. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF. P/N: PM1728 Macronix Proprietary 51 Rev. 1.9, March 13, 2019 MX25U12835F 9-18. Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (Please refer to "Table 4. Memory Organization") is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of the address been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte address on SI→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the tSE timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the sector is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the sector. Figure 43. Sector Erase (SE) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Mode 0 24-Bit Address Command SI 23 22 20h 2 1 0 MSB Figure 44. Sector Erase (SE) Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 24-Bit Address Command SIO[3:0] 20h A5 A4 A3 A2 A1 A0 MSB LSB P/N: PM1728 Macronix Proprietary 52 Rev. 1.9, March 13, 2019 MX25U12835F 9-19. Block Erase (BE32K) The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (Please refer to "Table 4. Memory Organization") is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE32K instruction is: CS# goes low→ sending BE32K instruction code→ 3-byte address on SI→CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Block Erase cycle is in progress. The WIP sets 1 during the tBE32K timing, and sets 0 when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (tBE32K) instruction will not be executed on the block. Figure 45. Block Erase 32KB (BE32K) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Mode 0 Command SI 24-Bit Address 23 22 52h 2 1 0 MSB Figure 46. Block Erase 32KB (BE32K) Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 24-Bit Address Command SIO[3:0] 52h A5 A4 A3 A2 A1 A0 MSB P/N: PM1728 Macronix Proprietary 53 Rev. 1.9, March 13, 2019 MX25U12835F 9-20. Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to "Table 4. Memory Organization") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the block is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the block. Figure 47. Block Erase (BE) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Mode 0 Command SI 24-Bit Address 23 22 D8h 2 1 0 MSB Figure 48. Block Erase (BE) Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 24-Bit Address Command SIO[3:0] D8h A5 A4 A3 A2 A1 A0 MSB P/N: PM1728 Macronix Proprietary 54 Rev. 1.9, March 13, 2019 MX25U12835F 9-21. Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Chip Erase cycle is in progress. The WIP sets during the tCE timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the chip is protected by BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP3, BP2, BP1, BP0 all set to "0". Figure 49. Chip Erase (CE) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 Command SI 60h or C7h Figure 50. Chip Erase (CE) Sequence (QPI Mode) CS# Mode 3 0 1 SCLK Mode 0 Command SIO[3:0] P/N: PM1728 60h or C7h Macronix Proprietary 55 Rev. 1.9, March 13, 2019 MX25U12835F 9-22. Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. The last address byte (the 8 least significant address bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. There will be no effort on the other data bytes of the same page. The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at least 1-byte on data on SI→ CS# goes high. The CS# must be kept low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary (the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. P/N: PM1728 Macronix Proprietary 56 Rev. 1.9, March 13, 2019 MX25U12835F Figure 51. Page Program (PP) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK 1 0 7 6 5 3 2 1 0 2079 2 2078 3 2077 23 22 21 02h SI Data Byte 1 24-Bit Address 2076 Command 2075 Mode 0 4 1 0 MSB MSB 2074 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2073 2072 CS# SCLK Data Byte 2 7 SI 6 5 4 3 2 Data Byte 3 1 MSB 0 7 6 5 4 3 2 Data Byte 256 1 7 0 MSB 6 5 4 3 2 MSB Figure 52. Page Program (PP) Sequence (QPI Mode) CS# Mode 3 0 1 2 SCLK Mode 0 Command SIO[3:0] 02h Data In P/N: PM1728 24-Bit Address A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2 H3 L3 Data Byte Data Byte Data Byte Data Byte 1 2 3 4 Macronix Proprietary 57 H255 L255 ...... Data Byte 256 Rev. 1.9, March 13, 2019 MX25U12835F 9-23. 4 x I/O Page Program (4PP) The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and SIO3 as address and data input, which can improve programmer performance and the effectiveness of application. The 4PP operation frequency supports as fast as 104MHz. The other function descriptions are as same as standard page program. The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high. Figure 53. 4 x I/O Page Program (4PP) Sequence (SPI Mode only) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 SCLK Mode 0 SIO0 P/N: PM1728 Command 38h 6 ADD cycles Data Data Data Data Byte 1 Byte 2 Byte 3 Byte 4 A20 A16 A12 A8 A4 A0 D4 D0 D4 D0 D4 D0 D4 D0 SIO1 A21 A17 A13 A9 A5 A1 D5 D1 D5 D1 D5 D1 D5 D1 SIO2 A22 A18 A14 A10 A6 A2 D6 D2 D6 D2 D6 D2 D6 D2 SIO3 A23 A19 A15 A11 A7 A3 Macronix Proprietary 58 D7 D3 D7 D3 D7 D3 D7 D3 Rev. 1.9, March 13, 2019 MX25U12835F 9-24. Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in deep power-down mode not standby mode. It's different from Standby mode. The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. Once the DP instruction is set, all instructions will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction and softreset command. (those instructions allow the ID being reading out). When Power-down, or software reset command the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For DP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not be executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode. Figure 54. Deep Power-down (DP) Sequence (SPI Mode) CS# 0 Mode 3 1 2 3 4 5 6 tDP 7 SCLK Mode 0 Command B9h SI Stand-by Mode Deep Power-down Mode Figure 55. Deep Power-down (DP) Sequence (QPI Mode) CS# Mode 3 0 tDP 1 SCLK Mode 0 Command SIO[3:0] B9h Stand-by Mode P/N: PM1728 Deep Power-down Mode Macronix Proprietary 59 Rev. 1.9, March 13, 2019 MX25U12835F 9-25. Enter Secured OTP (ENSO) The ENSO instruction is for entering the additional 4K-bit secured OTP mode. The additional 4K-bit secured OTP is independent from main array, which may use to store unique serial number for system identifier. After entering the Secured OTP mode, and then follow standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated again once it is lock-down. The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP mode→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once security OTP is lock down, only read related commands are valid. 9-26. Exit Secured OTP (EXSO) The EXSO instruction is for exiting the additional 4K-bit secured OTP mode. The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP mode→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. 9-27. Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register data out on SO→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. The definition of the Security Register bits is as below: Secured OTP Indicator bit. The Secured OTP indicator bit shows the secured OTP area is locked by factory before exit factory or not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock. Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP area cannot be update any more. While it is in 4K-bit secured OTP mode, main array access is not allowed. P/N: PM1728 Macronix Proprietary 60 Rev. 1.9, March 13, 2019 MX25U12835F Table 9. Security Register Definition bit7 bit6 bit5 bit4 bit3 bit2 WPSEL E_FAIL P_FAIL Reserved 0=BP protection mode 1=individual mode (default=0) 0=normal Erase succeed 1=individual Erase failed (default=0) 0=normal Program succeed 1=indicate Program failed (default=0) - 0=Erase is not suspended 1= Erase suspended (default=0) Non-volatile bit (OTP) Volatile bit Volatile bit Volatile bit Volatile bit ESB PSB (Erase (Program Suspend bit) Suspend bit) bit1 bit0 LDSO Secured OTP (indicate if indicator bit lock-down) 0 = not lock0=Program 0 = nondown is not factory 1 = lock-down suspended lock (cannot 1= Program 1 = factory program/ suspended erase lock (default=0) OTP) Volatile bit Non-volatile bit (OTP) Non-volatile bit (OTP) 9-28. Write Security Register (WRSCUR) The WRSCUR instruction is for setting the values of Security Register Bits. The WREN (Write Enable) instruction is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more. The LDSO bit is an OTP bit. Once the LDSO bit is set, the value of LDSO bit can notbe altered any more. The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. Figure 56. Write Security Register (WRSCUR) Sequence (Command 2F) CS# 0 1 2 3 4 5 6 7 SCLK Command SI P/N: PM1728 2F Macronix Proprietary 61 Rev. 1.9, March 13, 2019 MX25U12835F 9-29. Write Protection Selection (WPSEL) There are two write protection methods, (1) BP protection mode (2) individual block protection mode. If WPSEL=0, flash is under BP protection mode . If WPSEL=1, flash is under individual block protection mode. The default value of WPSEL is “0”. WPSEL command can be used to set WPSEL=1. Please note that WPSEL is an OTP bit. Once WPSEL is set to 1, there is no chance to recover WPSEL bit back to “0”. If the flash is under BP mode, the individual block protection mode is disabled. Contrarily, if flash is on the individual block protection mode, the BP mode is disabled. Every time after the system is powered-on, and the Security Register bit 7 is checked to be WPSEL=1, all the blocks or sectors will be write protected by default. User may only unlock the blocks or sectors via SBULK and GBULK instruction. Program or erase functions can only be operated after the Unlock instruction is conducted. BP protection mode, WPSEL=0: ARRAY is protected by BP3-BP0 and BP3-BP0 bits are protected by “SRWD=1 and WP#=0”, where SRWD is bit 7 of status register that can be set by WRSR command. Individual block protection mode, WPSEL=1: Blocks are individually protected by their own SRAM lock bits which are set to “1” after power up. SBULK and SBLK command can set SRAM lock bit to “0” and “1”. When the system accepts and executes WPSEL instruction, the bit 7 in security register will be set. It will activate SBLK, SBULK, RDBLOCK, GBLK, GBULK etc instructions to conduct block lock protection and replace the original Software Protect Mode (SPM) use (BP3-BP0) indicated block methods.Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0. Once WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits. The sequence of issuing WPSEL instruction is: CS# goes low → sending WPSEL instruction to enter the individual block protect mode → CS# goes high. Please refer to "Figure 59. Write Protection Selection (WPSEL) Sequence (Command 68)". WPSEL instruction function flow is as follows: Figure 57. BP and SRWD if WPSEL=0 WP# pin BP3 BP2 BP1 BP0 SRWD 64KB 64KB 64KB . . . (1) BP3-BP0 is used to define the protection group region. (For the protected area size, please refer to "Table 2. Protected Area Sizes") (2) “SRWD=1 and WP#=0” is used to protect BP3-BP0. In this case, SRWD and BP3-BP0 of status register bits can not be changed by WRSR 64KB P/N: PM1728 Macronix Proprietary 62 Rev. 1.9, March 13, 2019 MX25U12835F Figure 58. The individual block lock mode is effective after setting WPSEL=1 SRAM SRAM … … TOP 4KBx16 Sectors 4KB 4KB 4KB SRAM SRAM • SBLK/SBULK(36h/39h): - SBLK(36h): Set SRAM bit=1 (protect) : array can not be programmed/erased - SBULK(39h): Set SRAM bit=0 (unprotect): array can be programmed/erased - All top 4KBx16 sectors and bottom 4KBx16 sectors and other 64KB uniform blocks can be protected and unprotected by SRAM bits individually by SBLK/SBULK command set. … 64KB • Power-Up: All SRAM bits=1 (all blocks are default protected). All array cannot be programmed/erased SRAM … • GBLK/GBULK(7Eh/98h): - GBLK(7Eh): Set all SRAM bits=1,whole chip is protected and cannot be programmed/erased. - GBULK(98h): Set all SRAM bits=0,whole chip is unprotected and can be programmed/erased. - All sectors and blocks SRAM bits of whole chip can be protected and unprotected at one time by GBLK/GBULK command set. …… Uniform 64KB blocks 64KB SRAM … … Bottom 4KBx16 Sectors 4KB 4KB SRAM • RDBLOCK(3Ch): - use RDBLOCK mode to check the SRAM bits status after SBULK /SBLK/GBULK/GBLK command set. SBULK / SBLK / GBULK / GBLK / RDBLOCK Figure 59. Write Protection Selection (WPSEL) Sequence (Command 68) CS# 0 1 2 3 4 5 6 7 SCLK Command SI P/N: PM1728 68 Macronix Proprietary 63 Rev. 1.9, March 13, 2019 MX25U12835F Figure 60. WPSEL Flow start WREN command RDSCUR(2Bh) command Yes WPSEL=1? No WPSEL disable, block protected by BP[3:0] WPSEL(68h) command RDSR command No WIP=0? Yes RDSCUR(2Bh) command No WPSEL=1? Yes WPSEL set successfully WPSEL set fail WPSEL enable. Block protected by individual lock (SBLK, SBULK, … etc). P/N: PM1728 Macronix Proprietary 64 Rev. 1.9, March 13, 2019 MX25U12835F 9-30. Single Block Lock/Unlock Protection (SBLK/SBULK) These instructions are only effective after WPSEL was executed. The SBLK instruction is for write protection a specified block (or sector) of memory, using AMAX-A16 or (AMAX-A12) address bits to assign a 64Kbyte block (or 4K bytes sector) to be protected as read only. The SBULK instruction will cancel the block (or sector) write protection state. This feature allows user to stop protecting the entire block (or sector) through the chip unprotect command (GBULK). The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction. The sequence of issuing SBLK/SBULK instruction is: CS# goes low → send SBLK/SBULK (36h/39h) instruction→send 3-byte address assign one block (or sector) to be protected on SI pin → CS# goes high. The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. SBLK/SBULK instruction function flow is as follows: Figure 61. Block Lock Flow Start RDSCUR(2Bh) command WPSEL=1? No WPSEL command Yes WREN command SBLK command ( 36h + 24bit address ) RDSR command WIP=0? No Yes RDBLOCK command ( 3Ch + 24bit address ) Data = FFh ? No Yes Block lock successfully Lock another block? Block lock fail Yes No Block lock P/N: PM1728 completed Macronix Proprietary 65 Rev. 1.9, March 13, 2019 MX25U12835F Figure 62. Block Unlock Flow start RDSCUR(2Bh) command WPSEL=1? No WPSEL command Yes WREN command SBULK command ( 39h + 24bit address ) RDSR command No WIP=0? Yes RDBLOCK command to verify ( 3Ch + 24bit address ) Data = FF ? Yes No Block unlock successfully Unlock another block? Block unlock fail Yes Unlock block completed? P/N: PM1728 Macronix Proprietary 66 Rev. 1.9, March 13, 2019 MX25U12835F 9-31. Read Block Lock Status (RDBLOCK) This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status of protection lock of a specified block (or sector), using AMAX-A16 (or AMAX-A12) address bits to assign a 64K bytes block (4K bytes sector) and read protection lock status bit which the first byte of Read-out cycle. The status bit is"1" to indicate that this block has be protected, that user can read only but cannot write/program /erase this block. The status bit is "0" to indicate that this block hasn't be protected, and user can read and write this block. The sequence of issuing RDBLOCK instruction is: CS# goes low → send RDBLOCK (3Ch) instruction → send 3-byte address to assign one block on SI pin → read block's protection lock status bit on SO pin → CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. 9-32. Gang Block Lock/Unlock (GBLK/GBULK) These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is for enable/disable the lock protection block of the whole chip. The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction. The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction →CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed. P/N: PM1728 Macronix Proprietary 67 Rev. 1.9, March 13, 2019 MX25U12835F 9-33. Program Suspend and Erase Suspend The Suspend instruction interrupts a Page Program, Sector Erase, or Block Erase operation to allow access to the memory array. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. After the program or erase operation has entered the suspended state, the memory array can be read except for the page being programmed or the sector or block being erased ("Table 10. Readable Area of Memory While a Program or Erase Operation is Suspended"). Table 10. Readable Area of Memory While a Program or Erase Operation is Suspended Suspended Operation Readable Region of Memory Array Page Program All but the Page being programmed Sector Erase (4KB) All but the 4KB Sector being erased Block Erase (32KB) All but the 32KB Block being erased Block Erase (64KB) All but the 64KB Block being erased When the Serial NOR Flash receives the Suspend instruction, there is a latency of tPSL or tESL ("Figure 63. Suspend to Read Latency") before the Write Enable Latch (WEL) bit clears to “0” and the PSB or ESB sets to “1”, after which the device is ready to accept one of the commands listed in "Table 11. Acceptable Commands During Program/Erase Suspend after tPSL/tESL" (e.g. FAST READ). Refer to "Table 19. AC Characteristics" for tPSL and tESL timings. "Table 12. Acceptable Commands During Suspend (tPSL/tESL not required)" lists the commands for which the tPSL and tESL latencies do not apply. For example, RDSR, RDSCUR, RSTEN, and RST can be issued at any time after the Suspend instruction. Security Register bit 2 (PSB) and bit 3 (ESB) can be read to check the suspend status (please refer to "Table 9. Security Register Definition"). The PSB (Program Suspend Bit) sets to “1” when a program operation is suspended. The ESB (Erase Suspend Bit) sets to “1” when an erase operation is suspended. The PSB or ESB clears to “0” when the program or erase operation is resumed. Figure 63. Suspend to Read Latency tPSL / tESL CS# Suspend Command Read Command tPSL: Program Latency tESL: Erase Latency P/N: PM1728 Macronix Proprietary 68 Rev. 1.9, March 13, 2019 MX25U12835F Table 11. Acceptable Commands During Program/Erase Suspend after tPSL/tESL Command Name Command Code READ 03h FAST READ 0Bh DREAD 3Bh QREAD 6Bh 2READ BBh 4READ EBh W4READ E7h RDSFDP 5Ah RDID 9Fh QPIID AFh REMS 90h ENSO B1h EXSO C1h WREN 06h EQIO 35h RSTQIO F5h RESUME 30h SBL C0h PP 02h 4PP 38h Suspend Type Program Suspend Erase Suspend • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Table 12. Acceptable Commands During Suspend (tPSL/tESL not required) Command Name Command Code WRDI 04h RDSR 05h RDCR 15h RDSCUR 2Bh RES ABh RSTEN 66h RST 99h NOP 00h P/N: PM1728 Suspend Type Program Suspend • • • • • • • Macronix Proprietary 69 Erase Suspend • • • • • • • Rev. 1.9, March 13, 2019 MX25U12835F Figure 64. Resume to Suspend Latency CS# tPRS / tERS Resume Command Suspend Command tPRS: Program Resume to another Suspend tERS: Erase Resume to another Suspend 9-33-1. Erase Suspend to Program The “Erase Suspend to Program” feature allows Page Programming while an erase operation is suspended. Page Programming is permitted in any unprotected memory except within the sector of a suspended Sector Erase operation or within the block of a suspended Block Erase operation. The Write Enable (WREN) instruction must be issued before any Page Program instruction. A Page Program operation initiated within a suspended erase cannot itself be suspended and must be allowed to finish before the suspended erase can be resumed. The Status Register can be polled to determine the status of the Page Program operation. The WEL and WIP bits of the Status Register will remain “1” while the Page Program operation is in progress and will both clear to “0” when the Page Program operation completes. Figure 65. Suspend to Program Latency CS# Suspend Command tPSL / tESL Program Command tPSL: Program Latency tESL: Erase Latency 9-34. Program Resume and Erase Resume The Resume instruction resumes a suspended Page Program, Sector Erase, or Block Erase operation. Before issuing the Resume instruction to restart a suspended erase operation, make sure that there is no Page Program operation in progress. Immediately after the Serial NOR Flash receives the Resume instruction, the WEL and WIP bits are set to “1” and the PSB or ESB is cleared to “0”. The program or erase operation will continue until finished ("Figure 66. Resume to Read Latency") or until another Suspend instruction is received. A resume-to-suspend latency of tPRS or tERS must be observed before issuing another Suspend instruction ("Figure 64. Resume to Suspend Latency"). Please note that the Resume instruction will be ignored if the Serial NOR Flash is in “Performance Enhance Mode”. Make sure the Serial NOR Flash is not in “Performance Enhance Mode” before issuing the Resume instruction. Figure 66. Resume to Read Latency tSE/tBE/tPP CS# P/N: PM1728 Read Command Resume Command Macronix Proprietary 70 Rev. 1.9, March 13, 2019 MX25U12835F 9-35. No Operation (NOP) The "No Operation" command is only able to terminate the Reset Enable (RSTEN) command and will not affect any other command. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. 9-36. Software Reset (Reset-Enable (RSTEN) and Reset (RST)) The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST) command. It returns the device to standby mode. All the volatile bits and settings will be cleared then, which makes the device return to the default status as power on. To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will be invalid. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. If the Reset command is executed during program or erase operation, the operation will be disabled, the data under processing could be damaged or lost. The reset time is different depending on the last operation. For details, please refer to "Table 15-2. Reset Timing-(Other Operation)" for tREADY2. P/N: PM1728 Macronix Proprietary 71 Rev. 1.9, March 13, 2019 MX25U12835F Figure 67. Software Reset Recovery Stand-by Mode 66 CS# 99 tReady2 Mode Note: Refer to "Table 15-2. Reset Timing-(Other Operation)" for tREADY2 data. Figure 68. Reset Sequence (SPI mode) CS# SCLK Mode 3 Mode 3 Mode 0 Mode 0 Command Command 99h 66h SIO0 Figure 69. Reset Sequence (QPI mode) tSHSL CS# MODE 3 MODE 3 MODE 3 SCLK MODE 0 SIO[3:0] P/N: PM1728 Command MODE 0 66h Command MODE 0 99h Macronix Proprietary 72 Rev. 1.9, March 13, 2019 MX25U12835F 9-37. Read SFDP Mode (RDSFDP) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. The sequence of issuing RDSFDP instruction is same as CS# goes low→send RDSFDP instruction (5Ah)→send 3 address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS# to high at any time during data out. SFDP is a JEDEC Standard, JESD216. Figure 70. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI SO 24 BIT ADDRESS 23 22 21 5Ah 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Cycle SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 4 3 2 0 7 MSB MSB P/N: PM1728 1 Macronix Proprietary 73 6 5 4 3 2 1 0 7 MSB Rev. 1.9, March 13, 2019 MX25U12835F Table 12. Signature and Parameter Identification Data Values SFDP Table (JESD216) below is for MX25U12835FZNI-10G, MX25U12835FZ2I-10G, MX25U12835FZNI-08G, MX25U12835FMI-10G and MX25U12835FM2I-10G Description SFDP Signature Comment Fixed: 50444653h Add (h) DW Add Data (h/b) Data (Byte) (Bit) (Note1) (h) 00h 07:00 53h 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h SFDP Minor Revision Number Start from 00h 04h 07:00 00h 00h SFDP Major Revision Number Start from 01h This number is 0-based. Therefore, 0 indicates 1 parameter header. 05h 15:08 01h 01h 06h 23:16 01h 01h 07h 31:24 FFh FFh 00h: it indicates a JEDEC specified header. 08h 07:00 00h 00h Start from 00h 09h 15:08 00h 00h Start from 01h 0Ah 23:16 01h 01h How many DWORDs in the Parameter table 0Bh 31:24 09h 09h 0Ch 07:00 30h 30h 0Dh 15:08 00h 00h 0Eh 23:16 00h 00h 0Fh 31:24 FFh FFh it indicates Macronix manufacturer ID 10h 07:00 C2h C2h Start from 00h 11h 15:08 00h 00h Start from 01h 12h 23:16 01h 01h How many DWORDs in the Parameter table 13h 31:24 04h 04h 14h 07:00 60h 60h 15h 15:08 00h 00h 16h 23:16 00h 00h 17h 31:24 FFh FFh Number of Parameter Headers Unused ID number (JEDEC) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) First address of JEDEC Flash Parameter table Unused ID number (Macronix manufacturer ID) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) First address of Macronix Flash Parameter table Unused P/N: PM1728 Macronix Proprietary 74 Rev. 1.9, March 13, 2019 MX25U12835F Table 13. Parameter Table (0): JEDEC Flash Parameter Tables SFDP Table below is for MX25U12835FZNI-10G, MX25U12835FZ2I-10G, MX25U12835FZNI-08G, MX25U12835FMI-10G and MX25U12835FM2I-10G Description Comment Block/Sector Erase sizes 00: Reserved, 01: 4KB erase, 10: Reserved, 11: not support 4KB erase Write Granularity 0: 1Byte, 1: 64Byte or larger Write Enable Instruction Required 0: not required 1: required 00h to be written to the for Writing to Volatile Status status register Registers Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 01b 02 1b 03 0b 30h 0: use 50h opcode, 1: use 06h opcode Write Enable Opcode Select for Note: If target flash status register is Writing to Volatile Status Registers nonvolatile, then bits 3 and 4 must be set to 00b. Contains 111b and can never be Unused changed 4KB Erase Opcode 01:00 31h Data (h) E5h 04 0b 07:05 111b 15:08 20h 16 1b 18:17 00b 19 0b 20 1b 20h (1-1-2) Fast Read (Note2) 0=not support 1=support Address Bytes Number used in addressing flash array Double Transfer Rate (DTR) Clocking 00: 3Byte only, 01: 3 or 4Byte, 10: 4Byte only, 11: Reserved (1-2-2) Fast Read 0=not support 1=support (1-4-4) Fast Read 0=not support 1=support 21 1b (1-1-4) Fast Read 0=not support 1=support 22 1b 23 1b 33h 31:24 FFh 37h:34h 31:00 07FF FFFFh 0=not support 1=support 32h Unused Unused Flash Memory Density (1-4-4) Fast Read Number of Wait states (Note3) (1-4-4) Fast Read Number of Mode Bits (Note4) 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 Mode Bits: 000b: Not supported; 010b: 2 bits (1-4-4) Fast Read Opcode (1-1-4) Fast Read Number of Wait states (1-1-4) Fast Read Number of Mode Bits 39h 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 Mode Bits: 000b: Not supported; 010b: 2 bits (1-1-4) Fast Read Opcode P/N: PM1728 38h 3Ah 3Bh Macronix Proprietary 75 04:00 0 0100b 07:05 010b 15:08 EBh 20:16 0 1000b 23:21 000b 31:24 6Bh F1h FFh 44h EBh 08h 6Bh Rev. 1.9, March 13, 2019 MX25U12835F SFDP Table below is for MX25U12835FZNI-10G, MX25U12835FZ2I-10G, MX25U12835FZNI-08G, MX25U12835FMI-10G and MX25U12835FM2I-10G Description Comment (1-1-2) Fast Read Number of Wait states (1-1-2) Fast Read Number of Mode Bits 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 Mode Bits: 000b: Not supported; 010b: 2 bits (1-1-2) Fast Read Opcode (1-2-2) Fast Read Number of Wait states (1-2-2) Fast Read Number of Mode Bits 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 Mode Bits: 000b: Not supported; 010b: 2 bits 3Eh 3Fh 0=not support 1=support Unused (4-4-4) Fast Read 3Ch 3Dh (1-2-2) Fast Read Opcode (2-2-2) Fast Read Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 0=not support 1=support 40h Unused 04:00 0 1000b 07:05 000b 15:08 3Bh 20:16 0 0100b 23:21 000b 31:24 BBh 00 0b 03:01 111b 04 1b 07:05 111b Data (h) 08h 3Bh 04h BBh FEh Unused 43h:41h 31:08 FFh FFh Unused 45h:44h 15:00 FFh FFh 20:16 0 0000b 23:21 000b 47h 31:24 FFh FFh 49h:48h 15:00 FFh FFh 20:16 0 0100b 23:21 010b 4Bh 31:24 EBh EBh 4Ch 07:00 0Ch 0Ch 4Dh 15:08 20h 20h 4Eh 23:16 0Fh 0Fh 4Fh 31:24 52h 52h 50h 07:00 10h 10h 51h 15:08 D8h D8h 52h 23:16 00h 00h 53h 31:24 FFh FFh (2-2-2) Fast Read Number of Wait states (2-2-2) Fast Read Number of Mode Bits 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 Mode Bits: 000b: Not supported; 010b: 2 bits (2-2-2) Fast Read Opcode Unused (4-4-4) Fast Read Number of Wait states (4-4-4) Fast Read Number of Mode Bits 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 Mode Bits: 000b: Not supported; 010b: 2 bits (4-4-4) Fast Read Opcode Sector Type 1 Size Sector/block size = 2^N bytes (Note5) 0Ch: 4KB; 0Fh: 32KB; 10h: 64KB Sector Type 1 erase Opcode Sector Type 2 Size Sector/block size = 2^N bytes 00h: N/A; 0Fh: 32KB; 10h: 64KB Sector Type 2 erase Opcode Sector Type 3 Size Sector/block size = 2^N bytes 00h: N/A; 0Fh: 32KB; 10h: 64KB Sector Type 3 erase Opcode Sector Type 4 Size 00h: N/A, This sector type doesn't exist Sector Type 4 erase Opcode P/N: PM1728 Macronix Proprietary 76 46h 4Ah 00h 44h Rev. 1.9, March 13, 2019 MX25U12835F Table 14. Parameter Table (1): Macronix Flash Parameter Tables SFDP Table below is for MX25U12835FZNI-10G, MX25U12835FZ2I-10G, MX25U12835FZNI-08G, MX25U12835FMI-10G and MX25U12835FM2I-10G Description Vcc Supply Maximum Voltage Vcc Supply Minimum Voltage Comment 2000h=2.000V 2700h=2.700V 3600h=3.600V 1650h=1.650V, 1750h=1.750V 2250h=2.250V, 2300h=2.300V 2350h=2.350V, 2650h=2.650V 2700h=2.700V Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) Data (h) 61h:60h 07:00 15:08 00h 20h 00h 20h 63h:62h 23:16 31:24 50h 16h 50h 16h H/W Reset# pin 0=not support 1=support 00 1b H/W Hold# pin 0=not support 1=support 01 0b Deep Power Down Mode 0=not support 1=support 02 1b S/W Reset 0=not support 1=support 03 1b S/W Reset Opcode Reset Enable (66h) should be issued before Reset Opcode Program Suspend/Resume 0=not support 1=support 12 1b Erase Suspend/Resume 0=not support 1=support 13 1b 14 1b 15 1b 66h 23:16 C0h C0h 67h 31:24 64h 64h 65h:64h Unused Wrap-Around Read mode 0=not support 1=support Wrap-Around Read mode Opcode 11:04 1001 1001b F99Dh (99h) Wrap-Around Read data length 08h:support 8B wrap-around read 16h:8B&16B 32h:8B&16B&32B 64h:8B&16B&32B&64B Individual block lock 0=not support 1=support 00 1b Individual block lock bit (Volatile/Nonvolatile) 0=Volatile 1=Nonvolatile 01 0b 09:02 0011 0110b (36h) 10 0b 11 1b Individual block lock Opcode Individual block lock Volatile protect bit default protect status 0=protect 1=unprotect Secured OTP 0=not support 1=support Read Lock 0=not support 1=support 12 0b Permanent Lock 0=not support 1=support 13 0b Unused 15:14 11b Unused 31:16 FFh FFh 31:00 FFh FFh 6Bh:68h Unused 6Fh:6Ch C8D9h MX25U12835FZNI-10G-SFDP_2015-12-03,SF10 P/N: PM1728 Macronix Proprietary 77 Rev. 1.9, March 13, 2019 MX25U12835F Note 1: h/b is hexadecimal or binary. Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2), and (4-4-4) Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits. Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller if they are specified. (eg,read performance enhance toggling bits) Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h Note 6: All unused and undefined area data is blank FFh for SFDP Tables that are defined in Parameter Identification Header. All other areas beyond defined SFDP Table are reserved by Macronix. P/N: PM1728 Macronix Proprietary 78 Rev. 1.9, March 13, 2019 MX25U12835F 10. RESET Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the device is at the following states: - Standby mode - All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on. If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation and data could be lost. During the resetting cycle, the SO data becomes high impedance and the current will be reduced to minimum. Figure 71. RESET Timing CS# tRHSL SCLK tRH tRS RESET# tRLRH tREADY1 / tREADY2 Table 15-1. Reset Timing-(Power On) Symbol Parameter tRHSL Reset# high before CS# low tRS Reset# setup time tRH Reset# hold time tRLRH Reset# low pulse width tREADY1 Reset Recovery time Min. 10 15 15 10 35 Typ. Max. Unit us ns ns us us Min. 10 15 15 10 40 40 310 12 25 100 40 Typ. Max. Unit us ns ns us us us us ms ms ms ms Table 15-2. Reset Timing-(Other Operation) Symbol tRHSL tRS tRH tRLRH Parameter Reset# high before CS# low Reset# setup time Reset# hold time Reset# low pulse width Reset Recovery time (During instruction decoding) Reset Recovery time (for read operation) Reset Recovery time (for program operation) tREADY2 Reset Recovery time(for SE operation) Reset Recovery time (for BE64KB/BE32KB operation) Reset Recovery time (for Chip Erase operation) Reset Recovery time (for WRSR operation) P/N: PM1728 Macronix Proprietary 79 Rev. 1.9, March 13, 2019 MX25U12835F 11. POWER-ON STATE The device is at the following states after power-up: - Standby mode (please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage until the VCC reaches the following levels: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and the flash device has no response to any command. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The write, erase, and program command should be sent after the below time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the "Figure 79. Power-up Timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF) - At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during this stage if a write, program, erase cycle is in progress. P/N: PM1728 Macronix Proprietary 80 Rev. 1.9, March 13, 2019 MX25U12835F 12. ELECTRICAL SPECIFICATIONS Table 16. Absolute Maximum Ratings Rating Value Ambient Operating Temperature Industrial grade -40°C to 85°C Storage Temperature -65°C to 150°C Applied Input Voltage -0.5V to VCC+0.5V Applied Output Voltage -0.5V to VCC+0.5V VCC to Ground Potential -0.5V to 2.5V NOTICE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot to VCC+1.0V or -1.0V for period up to 20ns. Figure 73. Maximum Positive Overshoot Waveform Figure 72. Maximum Negative Overshoot Waveform 20ns 0V VCC+1.0V -1.0V 2.0V 20ns Table 17. Capacitance TA = 25°C, f = 1.0 MHz Symbol Parameter CIN COUT P/N: PM1728 Min. Typ. Max. Unit Input Capacitance 6 pF VIN = 0V Output Capacitance 8 pF VOUT = 0V Macronix Proprietary 81 Conditions Rev. 1.9, March 13, 2019 MX25U12835F Figure 74. Data Input Test Waveforms and Measurement Level Input timing referance level 0.8VCC Output timing referance level 0.7VCC AC Measurement Level 0.3VCC 0.2VCC 0.5VCC Note: Input pulse rise and fall time are
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