MX29F004B

MX29F004T/B 4M-BIT [512KX8] CMOS FLASH MEMORY FEATURES • 524,288 x 8 only • Single power supply operation - 5.0V only operation for read, erase and program operation • Fast access time: 70/90/120ns • Low power consumption - 30mA maximum active current (5MHz) - 1uA typical standby current • Command register architecture - Byte Programming (7us typical) - Sector Erase (Sector structure:16KB/8KB/8KB/32KB and 64KBx7) • Auto Erase (chip & sector) and Auto Program - Automatically erase any combination of sectors with Erase Suspend capability. - Automatically program and verify data at specified address • Erase suspend/Erase Resume - Suspends an erase operation to read data from, or program data to, another sector that is not being erased, then resumes the erase. • Status Reply - Data polling & Toggle bit for detection of program and erase cycle completion. • Chip protect/unprotect for 5V only system or 5V/12V system. • 100,000 minimum erase/program cycles • Latch-up protected to 100mA from -1V to VCC+1V • Low VCC write inhibit is equal to or less than 3.2V • Package type: - 32-pin PLCC, TSOP or PDIP • Compatibility with JEDEC standard - Pinout and software compatible with single-power supply Flash • 20 years data retention GENERAL DESCRIPTION The MX29F004T/B is a 4-mega bit Flash memory organized as 512K bytes of 8 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write nonvolatile random access memory. The MX29F004T/B is packaged in 32-pin PLCC, TSOP, PDIP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard MX29F004T/B offers access time as fast as 70ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29F004T/B has separate chip enable (CE) and output enable (OE) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F004T/B uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cycling. The MX29F004T/B uses a 5.0V±10% VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V. P/N:PM0554 REV. 1.9, OCT. 19, 2004 1 MX29F004T/B PIN CONFIGURATIONS 32 PDIP A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE A17 A14 A13 A8 A9 A11 OE A10 CE Q7 Q6 Q5 Q4 Q3 32 PLCC VCC A12 A15 A16 A18 A17 30 29 WE A7 A6 A5 A4 A3 A2 A1 A0 Q0 5 4 1 32 A14 A13 A8 A9 MX29F004T/B 9 MX29F004T/B 25 A11 OE A10 CE 13 14 Q1 Q2 GND 17 Q3 Q4 Q5 21 20 Q6 Q7 32 TSOP (Standard Type) (8mm x 20mm) A11 A9 A8 A13 A14 A17 WE VCC A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE Q7 Q6 Q5 Q4 Q3 GND Q2 Q1 Q0 A0 A1 A2 A3 MX29F004T/B PIN DESCRIPTION SYMBOL A0~A18 Q0~Q7 CE WE OE GND VCC PIN NAME Address Input Data Input/Output Chip Enable Input Write Enable Input Output Enable Input Ground Pin +5.0V single power supply P/N:PM0554 REV. 1.9, OCT. 19, 2004 2 MX29F004T/B SECTOR STRUCTURE MX29F004T TOP BOOT SECTOR ADDRESS TABLE Sector Size Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 A18 0 0 0 0 1 1 1 1 1 1 1 A17 0 0 1 1 0 0 1 1 1 1 1 A16 0 1 0 1 0 1 0 1 1 1 1 A15 X X X X X X X 0 1 1 1 A14 X X X X X X X X 0 0 1 A13 X X X X X X X X 0 1 X (Kbytes) 64 64 64 64 64 64 64 32 8 8 16 Address Range (in hexadecimal) (x8) Address Range 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-77FFFh 78000h-79FFFh 7A000h-7BFFFh 7C000h-7FFFFh MX29F004B BOTTOM BOOT SECTOR ADDRESS TABLE Sector Size Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 A18 0 0 0 0 0 0 0 1 1 1 1 A17 0 0 0 0 0 1 1 0 0 1 1 A16 0 0 0 0 1 0 1 0 1 0 1 A15 0 0 0 1 X X X X X X X A14 0 1 1 X X X X X X X X A13 X 0 1 X X X X X X X X (Kbytes) 16 8 8 32 64 64 64 64 64 64 64 Address Range (in hexadecimal) (x8) Address Range 00000h-03FFFh 04000h-05FFFh 06000h-07FFFh 08000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh P/N:PM0554 REV. 1.9, OCT. 19, 2004 3 MX29F004T/B BLOCK DIAGRAM WRITE CE OE WE CONTROL INPUT LOGIC HIGH VOLTAGE MACHINE (WSM) PROGRAM/ERASE STATE X-DECODER MX29F004T/B FLASH ARRAY ARRAY STATE REGISTER ADDRESS LATCH A0-A18 AND BUFFER SENSE AMPLIFIER Y-DECODER Y-PASS GATE SOURCE HV COMMAND DATA DECODER PGM DATA HV COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q7 I/O BUFFER P/N:PM0554 REV. 1.9, OCT. 19, 2004 4 MX29F004T/B AUTOMATIC PROGRAMMING The MX29F004T/B is byte programmable using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29F004T/B is less than 4 seconds. AUTOMATIC ERASE ALGORITHM MXIC's Automatic Erase algorithm requires the user to write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verification the entire array. Then the device automatically times the erase pulse width, provides the erase verify, and counts the number of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the status of the programming operation. Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a system write cycle, addresses are latched on the falling edge of WE or CE, whichever happens later, and data are latched on the rising edge of WE or CE, whichever happens first. MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MX29F004T/B electrically erases all bits simultaneously using Fowler- tunneling. The bytes are programmed by using the EPROM programming mechanism of hot electron injection. During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command register to respond to its full command set. AUTOMATIC CHIP ERASE The entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. Typical erasure at room temperature is accomplished in less than 4 second. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device. AUTOMATIC SECTOR ERASE The MX29F004T/B is sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase modes allow sectors of the array to be erased in one erase cycle. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device. AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm requires the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the program verification, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation. P/N:PM0554 REV. 1.9, OCT. 19, 2004 5 MX29F004T/B TABLE1. SOFTWARE COMMAND DEFINITIONS First Bus Command Reset Read Read Silicon ID Chip Protect Verify Program Chip Erase Sector Erase Sector Erase Suspend Sector Erase Resume Unlock for chip protect/unprotect Note: 1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 =1 for device code A2~A18=Do not care. (Refer to table 3) DDI = Data of Device identifier : C2H for manufacture code, 45H/46H for device code. X = X can be VIL or VIH RA=Address of memory location to be read. RD=Data to be read at location RA. 2. PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. SA = Address to the sector to be erased. 3. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0. Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA). Write Sequence may be initiated with A11~A18 in either state. 4. For Chip Protect Verify Operation :If read out data is 01H, it means the chip has been protected. If read out data is 00H, it means the chip is still not being protected. Bus Cycle 1 1 4 4 4 6 6 1 1 6 Cycle Addr XXXH RA 555H 555H 555H 555H 555H XXXH XXXH 555H Data F0H RD AAH AAH AAH AAH AAH B0H 30H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 20H 2AAH 55H 2AAH 55H 2AAH 55H 2AAH 55H 2AAH 55H 555H 90H 555H 90H 555H A0H 555H 80H 555H 80H ADI SA x02 PA DDI 00H 01H PD 2AAH 55H 2AAH 55H 555H 10H SA 30H Second Bus Cycle Addr Third Bus Cycle Data Addr Data Fourth Bus Cycle Fifth Bus Cycle Data Sixth Bus Cycle Addr Data Addr Data Addr 555H AAH 555H AAH COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 1 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Either of the two reset command sequences will reset the device (when applicable). P/N:PM0554 REV. 1.9, OCT. 19, 2004 6 MX29F004T/B TABLE 2. MX29F004T/B BUS OPERATION Mode Read Silicon ID Manufacturer Code (1) Read Silicon ID Device Code (1) Read Standby Output Disable Write Chip Protect with 12V system (6) Chip Unprotect with 12V system (6) Verify Chip Protect with 12V system Chip Protect without 12V system (6) Chip Unprotect without 12V system (6) Verify Chip Protect/Unprotect without 12V system (7) Reset Pins CE L L L H L L L L L L L L X OE L L L X H H VID(2) VID(2) L H H L X WE H H H X H L L L H L L H X A0 L H A0 X X A0 X X X X X X X A1 L L A1 X X A1 X X H X X H X A6 X X A6 X X A6 L H X L H X X A9 VID(2) VID(2) A9 X X A9 VID(2) VID(2) VID(2) H H H X Q0 ~ Q7 C2H 45H/46H DOUT HIGH Z HIGH Z DIN(3) X X Code (5) X X Code (5) HIGH Z NOTES: 1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1. 2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V. 3. Refer to Table 1 for valid Data-In during a write operation. 4. X can be VIL or VIH. 5. Code=00H means unprotected. Code=01H means protected. 6. Refer to chip protect/unprotect algorithm and waveform. Must issue "unlock for chip protect/unprotect" command before "chip protect/unprotect without 12V system" command. 7. The "verify chip protect/unprotect without 12V system" is only following "Chip protect/unprotect without 12V system" command. P/N:PM0554 REV. 1.9, OCT. 19, 2004 7 MX29F004T/B READ/RESET COMMAND The read or reset operation is initiated by writing the read/ reset command sequence into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered. If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid command must then be written to place the device in the desired state. SET-UP AUTOMATIC CHIP/SECTOR ERASE Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H. The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). If the Erase operation was unsuccessful, the data on Q5 is "1" (see Table 4), indicating the erase operation exceed internal timing limit. The automatic erase begins on the rising edge of the last WE or CE, whichever happens first pulse in the command sequence and terminates when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. SILICON-ID-READ COMMAND Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not generally desired system design practice. The MX29F004T/B contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology. The operation is initiated by writing the read silicon ID command sequence into the command register. Following the command write, a read cycle with A1=VIL,A0=VIL retrieves the manufacturer code of C2H. A read cycle with A1=VIL, A0=VIH returns the device code of 45H/46H for MX29F004T/B. TABLE 3. EXPANDED SILICON ID CODE Pins Manufacture code Device code for MX29F004T Device code for MX29F004B Chip Protection Verification A0 VIL VIH VIH X X A1 VIL VIL VIL VIH VIH Q7 1 0 0 0 0 Q6 1 1 1 0 0 Q5 0 0 0 0 0 Q4 0 0 0 0 0 Q3 0 0 0 0 0 Q2 0 1 1 0 0 Q1 1 0 1 0 0 Q0 Code (Hex) 0 C2H 1 45H 0 46H 1 01H(Protected) 0 00H(Unprotected) P/N:PM0554 REV. 1.9, OCT. 19, 2004 8 MX29F004T/B SECTOR ERASE COMMANDS The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. The system is not required to provide any control or timing during these operations. When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are complete when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic Sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. The sector address is latched on the falling edge of WE or CE, whichever happens later, while the command (data) is latched on the rising edge of WE or CE, whichever happens first. Sector addresses selected are loaded into internal register on the sixth falling edge of WE or CE, whichever happens later. Each successive sector load cycle started by the falling edge of WE or CE, whichever happens later must begin within 30us from the rising edge of the preceding WE or CE, whichever happens first. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Sector Erase(30H) or Erase Suspend(B0H) during the time-out period resets the device to read mode. TABLE 4. WRITE OPERATION STATUS Status Q7 Note1 Byte Program in Auto Program Algorithm Auto Erase Algorithm Erase Suspend Read In Progress Erase Suspended Mode (Erase Suspended Sector) Erase Suspend Read (Non-Erase Suspended Sector) Erase Suspend Program Byte Program in Auto Program Algorithm Exceeded Auto Erase Algorithm Time Limits Erase Suspend Program Q7 Q7 0 Q7 Toggle Toggle Toggle Toggle 0 1 1 1 N/A N/A 1 N/A N/A No Toggle Toggle N/A Data Q7 0 1 Toggle Toggle No Toggle Data Data Data Data Q6 Q5 Note2 0 0 0 N/A 1 N/A No Toggle Toggle Toggle Q3 Q2 Note: 1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits. See "Q5:Exceeded Timing Limits " for more information. P/N:PM0554 REV. 1.9, OCT. 19, 2004 9 MX29F004T/B ERASE SUSPEND This command only has meaning while the state machine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 100us to suspend the erase operations. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode automatically after suspend is ready. At this time, state machine only allows the command register to respond to the Read Memory Array, Erase Resume and program commands. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend program operation is complete, the system can once again read array data within non-suspended sectors. ings. The device will automatically provide an adequate internally generated program pulse and verify margin. If the program operation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the program operation exceed internal timing limit. The automatic programming operation is completed when the data read on Q6 stops toggling for two consecutive read cycles and the data on Q7 and Q6 are equivalent to data written to these two bits, at which time the device returns to the Read mode (no program verify command is required). DATA POLLING-Q7 The MX29F004T/B also features Data Polling as a method to indicate to the host system that the Automatic Program or Erase algorithms are either in progress or completed. While the Automatic Programming algorithm is in operation, an attempt to read the device will produce the complement data of the data last written to Q7. Upon completion of the Automatic Program Algorithm an attempt to read the device will produce the true data last written to Q7. The Data Polling feature is valid after the rising edge of the fourth WE or CE, whichever happens first pulse of the four write pulse sequences for automatic program. While the Automatic Erase algorithm is in operation, Q7 will read "0" until the erase operation is competed. Upon completion of the erase operation, the data on Q7 will read "1". The Data Polling feature is valid after the rising edge of the sixth WE or CE, whichever happens first pulse of six write pulse sequences for automatic chip/ sector erase. The Data Polling feature is active during Automatic Program/Erase algorithm or sector erase time-out. (see section Q3 Sector Erase Timer) ERASE RESUME This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. Another Erase Suspend command can be written after the chip has resumed erasing. SET-UP AUTOMATIC PROGRAM COMMANDS To initiate Automatic Program mode, A three-cycle command sequence is required. There are two "unlock" write cycles. These are followed by writing the Automatic Program command A0H. Once the Automatic Program command is initiated, the next WE or CE pulse causes a transition to an active programming operation. Addresses are latched on the falling edge, and data are internally latched on the rising edge of the WE or CE, whichever happens first pulse. The rising edge of WE or CE, whichever happens first also begins the programming operation. The system is not required to provide further controls or tim- P/N:PM0554 REV. 1.9, OCT. 19, 2004 10 MX29F004T/B Q6:Toggle BIT I Toggle Bit I on Q6 indicates whether an Automatic Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE or CE, whichever happens first pulse in the command sequence (prior to the program or erase operation), and during the sector time-out. During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6 to toggle. The system may use either OE or CE to control the read cycles. When the operation is complete, Q6 stops toggling. After an erase command sequence is written, if the chip has been protected, Q6 toggles and returns to reading array data. The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase suspended. When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use Q7. If a program address falls within a protected sector, Q6 toggles for approximately 2us after the program command sequence is written, then returns to reading array data. Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algorithm is complete. Table 4 shows the outputs for Toggle Bit I on Q6. Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 4 to compare outputs for Q2 and Q6. Reading Toggle Bits Q6/ Q2 Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Q2:Toggle Bit II The "Toggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively erasing (that is, the Automatic Erase algorithm is in process), or whether that sector is erase-suspended. Toggle Bit I is valid after the rising edge of the final WE or CE, whichever happens first pulse in the command sequence. P/N:PM0554 REV. 1.9, OCT. 19, 2004 11 MX29F004T/B Q5 Exceeded Timing Limits Q5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data Polling and Toggle Bit are the only operating functions of the device under this condition. If this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device. If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. If this time-out condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused). The time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Automatic Algorithm operation. Hence, the system never reads a valid data on Q7 bit and Q6 never stops toggling. Once the Device has exceeded timing limits, the Q5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used. specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. Q3 Sector Erase Timer After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted. WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 5ns(typical) on CE or WE will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. DATA PROTECTION POWER SUPPLY DECOUPLING The MX29F004T/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its VCC and GND. P/N:PM0554 REV. 1.9, OCT. 19, 2004 12 MX29F004T/B CHIP PROTECTION WITH 12V SYSTEM The MX29F004T/B features chip protection, which will disable both program and erase operations. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID=12V) A6=VIL and CE=VIL.(see Table 2) Programming of the protection circuitry begins on the falling edge of the WE or CE, whichever happens later pulse and is terminated on the rising edge. Please refer to chip protect algorithm and waveform. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 ( with CE and OE at VIL and WE at VIH). When A1=1, it will produce a logical "1" code at device output Q0 for the protected status. Otherwise the device will produce 00H for the unprotected status. In this mode, the addresses, except for A1, are don't care. Address locations with A1 = VIL are reserved to read manufacturer and device codes. (Read Silicon ID) It is also possible to determine if chip is protected in the system by writing a Read Silicon ID command. Performing a read operation with A1=VIH, it will produce a logical "1" at Q0 for the protected status. POWER-UP SEQUENCE The MX29F004T/B powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences. CHIP PROTECTION WITHOUT 12V SYSTEM The MX29F004T/B also feature a chip protection method in a system without 12V power supply. The programming equipment do not need to supply 12 volts to protect all sectors. The details are shown in chip protect algorithm and waveform. CHIP UNPROTECT WITHOUT 12V SYSTEM The MX29F004T/B also feature a chip unprotection method in a system without 12V power supply. The programming equipment do not need to supply 12 volts to unprotect all sectors. The details are shown in chip unprotect algorithm and waveform. CHIP UNPROTECT WITH 12V SYSTEM The MX29F004T/B also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. To activate this mode, the programming equipment must force VID on control pin OE and address pin A9. The CE pins must be set at VIL. Pins A6 must be set to VIH. (see Table 2) Refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. The unprotection mechanism begins on the falling edge of the WE or CE, whichever happens later pulse and is terminated on the rising edge. It is also possible to determine if the chip is unprotected in the system by writing the Read Silicon ID command. Performing a read operation with A1=VIH, it will produce 00H at data outputs(Q0-Q7) for an unprotected sector. It is noted that all sectors are unprotected after the chip unprotect algorithm is completed. P/N:PM0554 REV. 1.9, OCT. 19, 2004 13 MX29F004T/B CAPACITANCE (TA = 25oC, f = 1.0 MHz) SYMBOL CIN1 CIN2 COUT PARAMETER Input Capacitance Control Pin Capacitance Output Capacitance MIN. TYP MAX. 8 12 12 UNIT pF pF pF CONDITIONS VIN = 0V VIN = 0V VOUT = 0V READ OPERATION DC CHARACTERISTICS (TA = 0° C TO 70° C, VCC = 5V±10%) SYMBOL ILI ILO ISB1 ISB2 ICC1 ICC2 VIL VIH VOL VOH1 VOH2 Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage(TTL) Output High Voltage(CMOS) 2.4 Vcc-0.4 -0.3(NOTE 1) 2.0 Operating VCC current PARAMETER Input Leakage Current Output Leakage Current Standby VCC current 1 MIN. TYP MAX. 1 10 1 5 30 50 0.8 VCC + 0.3 0.45 UNIT uA uA mA uA mA mA V V V V V IOL = 2.1mA IOH = -2mA IOH = -100uA,VCC=VCC min CONDITIONS VIN = GND to VCC VOUT = GND to VCC CE = VIH CE = VCC + 0.3V IOUT = 0mA, f=5MHz IOUT = 0mA, f=10MHz NOTES: 1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns. 2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns. VIL min. = -2.0V for pulse width is equal to or less than 20 ns. If VIH is over the specified maximum value, read operation cannot be guaranteed. AC CHARACTERISTICS (TA = 0oC to 70oC, VCC = 5V±10%) 29F004T/B-55 29F004T/B-70 Symbol PARAMETER tACC tCE tOE tDF tOH Address to Output Delay CE to Output Delay OE to Output Delay OE High to Output Float 0 (Note 1) Address to Output hold 0 0 0 NOTE: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 0 ns CE=OE=VIL MIN. MAX. 55 55 40 30 0 MIN. 29F004T/B-90 29F004T/B-12 MAX. MIN. 90 90 40 0 40 0 MAX. 120 120 50 40 UNIT CONDITIONS ns ns ns ns CE=OE=VIL OE=VIL CE=VIL CE=VIL MAX. MIN. 70 70 40 30 TEST CONDITIONS: • Input pulse levels: 0.45V/2.4V • Input rise and fall times is equal to or less than 10ns • Output load: 1 TTL gate + 100pF (Including scope and jig) • Reference levels for measuring timing: 0.8V, 2.0V P/N:PM0554 REV. 1.9, OCT. 19, 2004 14 MX29F004T/B ABSOLUTE MAXIMUM RATINGS RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential A9 & OE VALUE 0oC to 70oC -65oC to 125oC -0.5V to 7.0V -0.5V to 7.0V -0.5V to 7.0V -0.5V to 13.5V NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. NOTICE: Specifications contained within the following tables are subject to change. READ TIMING WAVEFORMS VIH Addresses VIL ADD Valid tCE VIH CE VIL WE VIH VIL VIH VIL tACC tOH tOE tDF OE Outputs VOH VOL HIGH Z DATA Valid HIGH Z COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION DC CHARACTERISTICS (TA = 0oC to 70oC, VCC = 5V±10%) SYMBOL ICC1 (Read) ICC2 ICC3 (Program) ICC4 (Erase) ICCES NOTES: 1. VIL min. = -0.6V for pulse width is equal to or less than 20ns. 2. If VIH is over the specified maximum value, programming operation cannot be guaranteed. 3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is the sum of ICCES and ICC1 or ICC2. 4. All current are in RMS unless otherwise noted. P/N:PM0554 REV. 1.9, OCT. 19, 2004 PARAMETER Operating VCC Current MIN. TYP MAX. 30 50 50 50 UNIT mA mA mA mA mA CONDITIONS IOUT=0mA, f=5MHz IOUT=0mA, f=10MHz In Programming In Erase CE=VIH, Erase Suspended VCC Erase Suspend Current 2 15 MX29F004T/B AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V ± 10% 29F004T/B-55 29F004T/B-70 SYMBOL PARAMETER tOES tCWC tCEP tCEPH1 tCEPH2 tAS tAH tDS tDH tCESC tDF tAETC tAETB tAVT tBAL tCH tCS tVLHT tOESP tWPP1 tWPP2 OE setup time Command programming cycle WE programming pulse width WE programming pulse width High WE programming pulse width High Address setup time Address hold time Data setup time Data hold time CE setup time before command write Output disable time (Note 1) Total erase time in auto chip erase Total erase time in auto sector erase Total programming time in auto verify Sector address load time CE Hold Time CE setup to WE going low Voltage Transition Time OE Setup Time to WE Active Write pulse width for chip protect Write pulse width for chip unprotect 4(TYP.) 29F004T/B-90 MAX. 29F004T/B-12 MIN. 50 120 50 20 20 0 50 50 0 0 MIN. 50 55 45 20 20 0 45 30 0 0 MAX. MIN. 50 70 45 20 20 0 45 30 0 0 30 32 4(TYP.) MAX. MIN. 50 90 45 20 20 0 45 45 0 0 30 32 4(TYP.) MAX. UNIT ns ns ns ns ns ns ns ns ns ns 40 ns s s us us ns ns us us us ms 40 32 4(TYP.) 32 1.3(TYP.) 10.4 7 100 0 0 4 4 10 12 210 1.3(TYP.) 10.4 7 100 0 0 4 4 10 12 210 1.3(TYP.) 10.4 7 100 0 0 4 4 10 12 210 1.3(TYP.) 10.4 7 100 0 0 4 4 10 12 210 NOTES: 1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven. P/N:PM0554 REV. 1.9, OCT. 19, 2004 16 MX29F004T/B SWITCHING TEST CIRCUITS DEVICE UNDER TEST 1.6K ohm +5V CL 1.2K ohm DIODES=IN3064 OR EQUIVALENT CL=100pF Including jig capacitance SWITCHING TEST WAVEFORMS 2.4V 2.0V 2.0V TEST POINTS 0.8V 0.45V INPUT 0.8V OUTPUT AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall times are 100K cycles 2. To add data retention minimum 20 years 3. To modify timing of sector address loading period while operating multi-sector erase from 80us to 30us 4. To modify tBAL from 80us to 100us 5. To remove A9 from "timing waveform for sector protection for system without 12V" To remove A9 from "timing waveform for chip unprotection for system without 12V" Add erase suspend ready max. 100us in ERASE SUSPEND's section at page 10 To modify "Package Information" 1. To corrected typing error 1. Add 55ns speed option 2. Add industrial grade level 1. Removed industrial grade To modify Package Information 1. Added Pb-free part no. in Ordering Information Page P1 P1,14,15,33 P1,34 P1,34 P9 P16 P28 P29 P10 P35~37 All P14,16,33 P14,15,16,33 P14~16,33 P35~37 P33 MAY/30/2000 JUN/12/2001 JUL/01/2002 JUL/18/2002 AUG/12/2002 NOV/21/2002 OCT/18/2004 Date JUL/01/1999 JUL/12/1999 DEC/20/1999 1.3 1.4 1.5 1.6 1.7 1.8 1.9 P/N:PM0554 REV. 1.9, OCT. 19, 2004 38 MX29F004T/B MACRONIX INTERNATIONAL CO., LTD. Headquarters: TEL:+886-3-578-6688 FAX:+886-3-563-2888 Europe Office : TEL:+32-2-456-8020 FAX:+32-2-456-8021 Hong Kong Office : TEL:+86-755-834-335-79 FAX:+86-755-834-380-78 Japan Office : Kawasaki Office : TEL:+81-44-246-9100 FAX:+81-44-246-9105 Osaka Office : TEL:+81-6-4807-5460 FAX:+81-6-4807-5461 Singapore Office : TEL:+65-6346-5505 FAX:+65-6348-8096 Taipei Office : TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 MACRONIX AMERICA, INC. TEL:+1-408-262-8887 FAX:+1-408-262-8810 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.