MPC2F35

MPC2F35 Low-speed USB micro-controller GENERAL DESCRIPTION The MPC2F35 is a 65C02 MCU with an embedded 8k bytes flash ROM, a 256 bytes RAM, a watch-dog timer, a USB and PS/2 combo interfaces, can be implemented via the USB bus line, D+ and D- pins, by the user’s program. The USB features fully meets the low-speed USB Specification version 1.1. It will be very suitable for the low-cost keyboard, joystick, I-toy, and some products like the hand-held devices, which need to download/ upload data through the PC system. FEATURES • • • 8-bit 65C02 micro-controller with 6 MHz external crystal or ceramic resonator Operation voltage: 4.35V to 5.5V Memory: − − 8K Bytes Flash ROM 256 Bytes RAM • 34 programmable GPIO: − − − − 4 LED direct sink pins shared with Port0 (LED0/1/2/3) 2 external interrupt pins (INT0, INT1) Port3 provides the pin interrupt 26 bi-directional I/O pins for Port1/ 2/3/4 • • • • One 8-bit programmable timer Built-in power-on reset One watchdog timer Low-speed USB Specification version 1.1 compliance − − − Supports 4 endpoints, where EP0 is control endpoint, and EP1/2/3 are data endpoints Integrated USB transceiver, and 3.3V regulated output for USB pull-up resistor Provides remote wake-up • • • • Built-in low-voltage detector USB and PS/2 combo interfaces Support two power-saving modes: stop and halt mode − − Packages: 28-SSOP: MPC2F35L 40-PDIP: MPC2F35E2 This document contains information on a new product under development by MEGAWIN. MEGAWIN reserves the right to change or discontinue this product without notice. © MEGAWIN Technology Co., Ltd. 2008 All rights reserved. 2008/12 version A4 MEGAWIN PAD DESCRIPTION PIN Name I/O Description P0.0~0.3 P0.4/- INT0 P0.5/- INT1 P0.6~0.7 P1.0~1.7 P2.0~2.7 P3.0~3.7 P4.0~4.1 - RST XTAL1 XTAL2 D+/SCLK D-/SDATA VCC VSS V3.3 I/O I/O I/O I/O I/O I/O I/O I/O I I I I/O I/O I I O Bi-directional I/O, and sink LED directly Bi-directional I/O with external interrupt 1 Bi-directional I/O with external interrupt 2 Bi-directional I/O Bi-directional I/O Bi-directional I/O Bi-directional I/O Bi-directional I/O Reset pin, low active 6MHz crystal or resonator in 6MHz crystal or resonator out USB data + with PS/2 compatible I/O USB data - with PS/2 compatible I/O Voltage supply Ground 3.3V regulated output, a capacitor should be added on this pin 2 MPC2F35_USB Data Sheet MEGAWIN BLOCK DIAGRAM 256 bytes RAM Port 0.0 ~ 0.7 Port 1.0 ~ 1.7 Port 2.0 ~ 2.7 Port 3.0 ~ 3.7 Port 4.0 ~ 4.1 I/O PORTs 8K bytes Flash ROM 8-bit Timer DPM Control Power Controller Acess Control 8-bit CPU USB and PS/2 Engine D+, DV3.3 Interrupt Controller Power-on Reset Watch Dog Timer Clock Generator XTAL1 MEGAWIN XTAL2 MPC2F35_USB Data Sheet 3 PACKAGES V3.3 DVss XTAL1 XTAL2 P0.4 P0.6 P0.7 P1.4 P1.5 P1.7 P2.0 P2.1 P2.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 D+ Vcc P0.2 P0.1 P0.0 - RST P3.7 P3.4 P3.0 P2.7 P2.6 P2.5 P2.4 P2.3 MPC2F35L D +/SCLK V3.3 D -/SDATA Vss Xtal1 Xtal2 P0.4/-INT0 P0.5/-INT1 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc P0.3/LED3 P0.2/LED2 P0.1/LED1 P0.0/LED0 - RST P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 MPC2F35E2 4 MPC2F35_USB Data Sheet MEGAWIN FUNCTION DESCRIPTION Registers A Y X P PCL S PCH 1 Accumulator The accumulator is a 8-bit register, which stores the results of most arithmetic and logic operations. In addition, the accumulator usually contains one of two data words used in these operations. Index Register (X, Y) There are two 8-bit index registers (X and Y), which may be used to count program steps or to provide an index value to be used in generating an effective address. When executing an instruction, which specifies indexed addressing, the MCU fetches the OP Code and the base address, and modifies the address by adding the index register to the base address before performing the desired operation. Pre- or post-index of index address is possible. Processor Status Register (P) The 8-bit processor status register contains seven status flags. Some flags are controlled by the program, Bit 7 N and others Bit 6 V may Bit 5 1 be controlled Bit 4 B by both the program and Bit 1 Z the MCU. Bit 0 C Bit 3 D Bit 2 I N: Signed flag, 1 = negative, 0 = positive V: Overflow flag, 1 = true, 0 = false B: BRK interrupt command, 1 = BRK, 0 = IRQB D: Decimal mode, 1 = true, 0 = false I: IRQB disable flag, 1 = disable, 0 = enable Z: Zero flag, 1 = true, 0 = false C: Carry flag, 1 = true, 0 = false Program Counter (PC) The 16-bit program counter register provides the addresses, which steps MPC2F35 through the sequential program instructions. Each time this MCU fetches an instruction from program memory, the lower byte of the program counter (PCL) is placed on the low-order 8 bits of the address bus, and the higher byte of the program counter (PCH) is placed on the high-order 8 bits. The counter is incremented each time when an instruction or data is fetched from program memory. MEGAWIN MPC2F35_USB Data Sheet 5 Stack Pointer (S) The stack pointer is an 8-bit register, which is used to control the addressing of the variable-length stack. The stack pointer is automatically incremented and decremented under the control of the MCU to perform the stack manipulations. The stack allows simple implementation of nested subroutines and multiple level interrupts. The stack pointer is initialized by the user’s firmware. Memory Map There is a zero page working RAM (0000H ~ 007FH), a stack area (0180H ~ 01FFH) and two special function register areas (SFR, 00C0H ~ 00FFH and 0200H ~ 027FH) in MPC2F35. The locations 0100H to 017FH and the locations 0000H to 007FH share the same memory block, so MPC2F35 has a 256 bytes on-chip SRAM (zero page working RAM and stack area) and an 8k bytes on-chip flash ROM, which are addressed from 8000H to 9FFFH. The address mapping of MPC2F35 is shown as below. Memory Map 0000H 007FH 0080H~00BFH 00C0H~00FFH 0100H 017FH 0180H 01FFH 0200H 027FH Zero Page Working RAM SFR RAM Stack Area SFR 7FFFH 8000H ~ 800FH 8010H 9FFFH A000H Interrupt Vector Area Program FFFFH 6 MPC2F35_USB Data Sheet MEGAWIN Special Function Register (SFR) The address 00C0H to 00FFH and 0200H to 027FH are reserved for the special function registers (SFR). MPC2F35 has 36 SFRs to be used to control or store the status of I/O, timers, system clock and other peripherals. Symbol IRQ_EN IRQ_ST IRQ_CLR TM0 TM0_CTL P0_BUF P1_BUF P2_BUF P3_BUF P4_BUF P0 P1 P2 P3 P4 WDT_ST WDT_CLR USB_CTL USB_ADDR USB_DI / USB_DO DPM_CTL DPMO DPMI PWR_CTL FCPU_SR RLH_EN P0_CR P0_MR P1_CR P1_MR P2_CR P2_MR P3_CR P3_MR P4_CR P4_MR Address 00C1 00C2 00C3 00C5 00C6 00D0 00D1 00D2 00D3 00D4 00D8 00D9 00DA 00DB 00DC 00DE 00DF 00E0 00E1 00E2 00E8 00E9 00EA 0200 0201 0202 0240 0241 0244 0245 0248 0249 024C 024D 0250 0251 Description Interrupt request enable Interrupt request status flag Interrupt request clear Timer 0 Timer 0 control Port 0 output buffer Port 1 output buffer Port 2 output buffer Port 3 output buffer Port 4 output buffer Port 0 pad value Port 1 pad value Port 2 pad value Port 3 pad value Port 4 pad value Watchdog timer status flag Watchdog clear USB bus control USB register address USB register data buffer USB bus mode control USB bus output for the PS/2 mode USB bus value for the PS/2 mode Power-saving control FCPU selector Release the halt mode enable Port 0 control register Port 0 mode register Port 1 control register Port 1 mode register Port 2 control register Port 2 mode register Port 3 control register Port 3 mode register Port 4 control register Port 4 mode register Initial Value X 00 00 00 00 00 00 00 00 00 X X X X X 00 X 00 00 00 00 00 X 00 00 00 00 00 00 00 00 00 00 00 00 00 MEGAWIN MPC2F35_USB Data Sheet 7 Interrupt Vectors Vector Address 8002H, 8003H 8006H, 8007H 8008H, 8009H 800AH, 800BH 800CH, 800DH 800EH, 800FH Item RESET USB TM0 P3 INT0 INT1 Priority 1 2 3 4 5 6 Properties External. Internal Internal External. External. External. Description Initial reset USB interrupt Timer 0 overflow interrupt Port 3 interrupt vector INT0 external interrupt vector INT1 external interrupt vector There are six interrupt sources provided in MPC2F35. The flag IRQ_EN and IRQ_ST are used to control the interrupts. When flag IRQ_ST is set to ‘1’ by the hardware and the corresponding bits of flag IRQ_EN has been set by firmware, an interrupt is generated. When an interrupt occurs, all interrupts are inhibited until the CLI or STA IRQ_EN, #I instruction is invoked. Executing the SEI instruction can also disable the interrupts. STA IRQ_EN, #I USB Interrupt signal IRQ_ST.1 Initial Reset CLI instruction Enable SQ R IRQ_EN.1 8002H, 8003H TM0 Interrupt signal . . . INT1 Trigger signal SQ R IRQ_ST.2 IRQ_EN.2 Interrupt Process Logic Interrupt Vector Generator Logic 8006H, 8007H 8008H, 8009H 800AH, 800BH 800CH, 800DH 800EH, 800FH SQ R IRQ_ST.5 IRQ_EN.5 Initial Reset STA IRQ_CLR, #I Disable SEI instruction 8 MPC2F35_USB Data Sheet MEGAWIN Interrupt Registers IRQ enable flag Address 00C1H Name IRQ_EN Bit 7 Bit 6 Bit 5 INT1 Bit 4 INT0 Bit 3 P3 Bit 2 TM0 Bit 1 USB Bit 0 R W √ √ Program can enable (setting to “1”) or disable (clearing to “0”) the ability of triggering IRQ through this register. USB: USB finishes Rx or Tx data TM0: Timer0 underflow P3: Falling edge trigger signal occurs at port 3 input mode INT0, INT1: Falling edge trigger signal occurs at P0.4 and P0.5 input mode IRQ status flag Address 00C2H Name IRQ_ST Bit 7 Bit 6 Bit 5 INT1 Bit 4 INT0 Bit 3 P3 Bit 2 TM0 Bit 1 USB Bit 0 R W √ - When IRQ occurs, program can read this register to know which source triggering IRQ. IRQ clear flag Address 00C3H Name IRQ_CLR Bit 7 Bit 6 Bit 5 INT1 Bit 4 INT0 Bit 3 P3 Bit 2 TM0 Bit 1 USB Bit 0 R W - √ Program can clear the interrupt event by writing ‘1’ into the corresponding bit. Watchdog Timer (WDT) Address 00DEH 00DFH Name WDT_ST WDT_CLR Bit 7 RSTS CLR Bit 6 Bit 5 Bit 4 Bit 3 Bit 3 Bit 2 Bit 2 Bit 1 Bit 1 Bit 0 Bit 0 R W √ - √ Bit 3 ~ Bit 0: Contents of WDT RSTS: WDT reset status, set by the hardware when WDT overflows, and clear by the firmware or the hardware reset CLR: RSTS clear and WDT reset control bit, the program can clear the RSTS bit and reset WDT by writing “1” into the CLR bit The watchdog timer (WDT) is organized as a 4-bit counter, which is designed to prevent the program from unknown errors. If the WDT overflows, the WDT reset function will be performed. RSTS (Bit 7 of WDT_ST) is set by hardware when the WDT overflows. It also can be cleared by hardware reset or writing 1 to bit 7 of WDT_CLR. The interval of WDT to cause reset is around 0.7s at 6MHz external oscillator. Programming one into the bit 7 of WDT_CLR register can reset the contents of the WDT. In normal operation, the application program must reset WDT before it overflows. A WDT overflow indicates that operation is not under control and the chip will be reset. The organization of the watchdog timer is shown as below MEGAWIN MPC2F35_USB Data Sheet 9 WDT Fosc/2^18 Overflow signal Qw1 Qw2 Qw3 Qw4 R R R R S Q R System Reset WDT_ST.7 Hardware reset WDT_CLR.7 System Control Registers Power saving control Address 0200H Name PWR_CTL Bit 7 LVDT Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 CKC Bit 0 HALT R W - √ LVDT: Low-voltage detector disable bit. 1: Disable, 0: Enable (default) CKC: Oscillator control bit. 1: Disable OSC, 0: Enable OSC (default) HALT: FCPU off-line control bit. 1: FCPU off-line, 0: FCPU on-line (default) When the low-voltage detector is enabled, and if it senses the power voltage is lower than 3.3V, then MPC2F35 will be reset automatically. Programmer can switch the normal operation mode to the power-saving mode for reducing power consumption through this register. There are two power saving modes in MPC2F35. Stop mode: (PWR_CTL.CKC = 1) System clock stops the built-in oscillator if setting the CKC bit in the PWR_CTL SFR. MPC2F35 can be awakened from the stop mode by 4 ways: the port 3 interrupt, the hardware reset, the power-on reset and the USB wake-up. Halt mode: (PWR_CTL.HALT = 1) Setting the HALT bit to let the clock source of MPC2F35 to be in the off-line status, but the oscillator works or not will be depended on the content of the CKC bit in the PWR_CTL SFR. MPC2F35 can be awakened from the halt mode by 3 ways: the interrupts (USB, Timer 0, Port3, INT0 and INT1) can be assigned by the RLH_EN register, the hardware reset, or the power-on reset. FCPU selector Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W 10 MPC2F35_USB Data Sheet MEGAWIN 0201H FCPU_SR - - - - - - - CKS - √ At the 6M Hz external crystal, the internal clock source of MPC2F35 is 3M Hz by the default value. CKS: FCPU clock source select register. 0: FOSC/2 (default), 1:FOSC Release halt mode enable flag Address 0202H Name RLH_EN Bit 7 Bit 6 Bit 5 INT1 Bit 4 INT0 Bit 3 P3 Bit 2 TM0 Bit 1 USB Bit 0 R W - √ Programmer can select the interrupt sources to release the halt mode through this register. 0: Disable (default), 1: Enable After setting RLH_EN register, once there is one interrupt to release the halt mode, the programmer can check the corresponding bit of the IRQ_ST register to know which interrupt source to execute this release process. Timer Timer 0 Address 00C5H 00C6H Name TM0 TM0_CTL Bit 7 T7 Bit 6 T6 STC Bit 5 T5 RL/S Bit 4 T4 Bit 3 T3 Bit 2 T2 TKI2 Bit 1 T1 TKI1 Bit 0 T0 TKI0 R W √ √ √ √ STC: Timer clock disable/enable. 0: Disable timer clock (default), 1: Enable timer clock RL/S: Auto-reload disable/enable. 0: Enable auto-reload (default), 1: Disable auto-reload Timer 0 clock source (FTM0CK) FOSC / 8 FOSC / 16 FOSC / 32 FOSC / 64 FOSC / 128 FOSC / 256 FOSC / 512 FOSC / 1024 TKI2 0 0 0 0 1 1 1 1 TKI1 0 0 1 1 0 0 1 1 TKI0 0 1 0 1 0 1 0 1 When timer 0 is used, it starts to pre-load value to this down-counter by setting the STC bit in the TM0_CTL SFR and its underflow frequency (FTM0_UV) of timer 0 can be calculated by the following equation: FTM0_UV = FTM0CK / (TM0+1), where FTM0CK is selected by TKI2, TKI1 and TKI0 For example: if FOSC=6M Hz and TKI2=0, TKI1=1, TKI0=0, then FTM0CK= FOSC / 32 MEGAWIN MPC2F35_USB Data Sheet 11 TM0 00H 01H 02H … FFH FTM0_UV Frequency Invalid 93.75 KHz 62.5 KHz … 732.42 Hz General Purpose I/O Ports Port 0 Address 00D0H 00D8H 0240H 0241H Name P0_BUF P0 P0_CR P0_MR Bit 7 BP07 P07 CP07 Bit 6 BP06 P06 CP06 Bit 5 BP05 P05 CP05 MP05 Bit 4 BP04 P04 CP04 MP04 Bit 3 BP03 P03 CP03 Bit 2 BP02 P02 CP02 Bit 1 BP01 P01 CP01 MP01 Bit 0 BP00 P00 CP00 MP00 R W √ √ √ √ √ √ √ Port 0 is an 8-bit I/O port; each pin can be programmed as input or output individually. P0_BUF: Port 0 output buffer. When P0.n is configured as an output pin, it outputs the content of P0_BUF.n. P0: Values on the pin of Port 0 while reading from Port 0. P0_CR: Configure P0.0 ~ P0.7 to be input or output individually. 0: Input (default), 1: Output P0_MR: Configure the output mode of P0.0 ~ P0.7 with a 17k ohm pull-high resistor, CMOS or NMOS open drain − − − − MP00 (P0_MR.0): P0.0 ~ P0.3 with the pull-high control bit, 0: Disable (default), 1:Enable MP01 (P0_MR.1): P0.0 ~ P0.3 with the CMOS or NMOS selector, 0: CMOS (default), 1: NMOS MP04 (P0_MR.4): P0.4 ~ P0.7 with the pull-high control bit, 0: Disable (default), 1: Enable MP05 (P0_MR.5): P0.4 ~ P0.7 with the CMOS or NMOS selector, 0: CMOS (default), 1: NMOS At initial reset, Port 0 is all in the input mode. Each pin of Port 0 can be specified as the input or output mode independently by the P0_CR SFR. When Port 0 is used as the output port, CMOS or NMOS open drain output type can be selected by the P0_MR register. Port 0 has 17k ohm internal pull-high resistors that can be enabled/disabled by specifying the MP00 and MP04 in the P0_MR register respectively. The pull-high resistor is automatically disabled only when the port is configured as CMOS output. Schmitt trigger circuit is added in the input path of P0.0~P0.3. User should be carefully on setting pin as input with no pull high resistor since this setting has potential to cause leakage. When P0.4 and P0.5 are set as input pins, they are INT0 and INT1 interrupt sources. A falling edge at the two pins will set the corresponding bits in the IRQ_ST register to 1, and the external interrupt subroutines will be executed if the corresponding bits in the IRQ_EN register are also set. Port 1 12 MPC2F35_USB Data Sheet MEGAWIN Address 00D1H 00D9H 0244H 0245H Name P1_BUF P1 P1_CR P1_MR Bit 7 BP17 P17 CP17 - Bit 6 BP16 P16 CP16 - Bit 5 BP15 P15 CP15 MP15 Bit 4 BP14 P14 CP14 MP14 Bit 3 BP13 P13 CP13 - Bit 2 BP12 P12 CP12 - Bit 1 BP11 P11 CP11 MP11 Bit 0 BP10 P10 CP10 MP10 R W √ √ √ √ √ √ √ Port 1 is an 8-bit I/O port. Its structure is the same with Port 0, and refers to Port 0 for more information. P1_BUF: Port 1 output buffer. When P1.n is configured as an output pin, it outputs the content of P1_BUF.n. P1: Values on Port 1 pins while reading from Port 1. P1_CR: Configure P1.0 ~ P1.7 to be input or output individually. 0: input, 1: output P1_MR: Configure the output mode of P1.0 ~ P1.7 with a 17k ohm pull-high resistor, CMOS or NMOS open drain Port 2 Address 00D2H 00DAH 0248H 0249H Name P2_BUF P2 P2_CR P2_MR Bit 7 BP27 P27 CP27 Bit 6 BP26 P26 CP26 Bit 5 BP25 P25 CP25 MP25 Bit 4 BP24 P24 CP24 MP24 Bit 3 BP23 P23 CP23 Bit 2 BP22 P22 CP22 Bit 1 BP21 P21 CP21 MP21 Bit 0 BP20 P20 CP20 MP20 R W √ √ √ √ √ √ √ Port 2 is an 8-bit I/O port, its structure is the same with Port 0 and refers to Port 0 for more information. P2_BUF: Port 2 output buffer. When P2.n is configured as an output pin, it outputs the content of P2_BUF.n. P2: Values on Port 2 pins while reading from Port 2. P2_CR: Configure P2.0 ~ P2.7 to be input or output individually. 0: input, 1: output P2_MR: Configure the output mode of P2.0 ~ P2.7 with a 17k ohm pull-high resistor, CMOS or NMOS open drain Port 3 Address 00D3H 00D9H 0244H 0245H Name P3_BUF P3 P3_CR P3_MR Bit 7 BP37 P37 CP37 Bit 6 BP36 P36 CP36 Bit 5 BP35 P35 CP35 MP35 Bit 4 BP34 P34 CP34 MP34 Bit 3 BP33 P33 CP33 Bit 2 BP32 P32 CP32 Bit 1 BP31 P31 CP31 MP31 Bit 0 BP30 P30 CP30 MP30 R √ √ √ √ W √ √ √ Port 3 is an 8-bit I/O port, its structure is the same with Port 0 and refers to Port 0 for more information. P3_BUF: Port 3 output buffer. When P3.n is configured as an output pin, it outputs the content of P3_BUF.n. P3: Values on Port 3 pins while reading from Port 3. MEGAWIN MPC2F35_USB Data Sheet 13 P3_CR: Configure P3.0 ~ P3.7 to be input or output individually. 0: input, 1: output P3_MR: Configure the output mode of P3.0 ~ P3.7 with a 17k ohm pull-high resistor, CMOS or NMOS open drain When port 3 is used as the input mode, it provides the pin interrupt function while a falling edge occurs at any pin of the port 3 and will set the P3 bit of the IRQ_ST SFR. The same event can release the stop mode to enable the oscillator, and this interrupt also can release the halt mode if the P3 bit in the RLH_EN SFR is set. Finally, an interrupt subroutine will be executed if setting the P3 bit in the IRQ_E SFR. Port 4 Address 00D1H 00DCH 0250H 0251H Name P4_BUF P4 P4_CR P4_MR Bit 7 BP47 Bit 6 BP46 Bit 5 BP45 Bit 4 BP44 Bit 3 BP43 Bit 2 BP42 Bit 1 BP41 P41 CP41 MP41 Bit 0 BP40 P40 CP40 MP40 R W √ √ √ √ √ √ √ MPC2F35 only provide two pins (P4.0 and P4.1) on the port 4, and these pins also are I/O pins. The structure is the same with Port 0, and please refers to Port 0 for more information. P4_BUF: Port 4 output buffer. When P4.n is configured as an output pin, it outputs the content of P4_BUF.n. P4: Values on Port 4 pins while reading from Port 4. P4_CR: Configure P4.0 and P4.1 to be input or output individually. 0: input, 1: output P4_MR: Configure the output mode of P4.0 and P4.1 with a 17k ohm pull-high resistor, CMOS or NMOS open drain Input/Output Pin --- P0~P4 Vdd P0_MR.1 Enable Output Buffer DATA BUS P0_CR.x LDA P0_BUF Instruction P0_MR.0 P0_CR.x P0_MR.1 Enable Enable I/O PIN P0.n LDA P0 Instruction 14 MPC2F35_USB Data Sheet MEGAWIN USB INTERFACE MPC2F35 provides the interface of PS/2 and USB combinative operation by programming the below registers, the user can be easily change the configuration between USB and PS/2 for meeting the environment of the host. USB register access control Address 00E0H 00E1H 00E2H 00E2H Name USB_CTL USB_ADDR USB_DI USB_DO Bit 7 REGC UDI7 UDO7 Bit 6 UDI6 UDO6 Bit 5 UA5 UDI5 UDO5 Bit 4 UA4 UDI4 UDO4 Bit 3 UA3 UDI3 UDO3 Bit 2 UA2 UDI2 UDO2 Bit 1 UWT UA1 UDI1 UDO1 Bit 0 URD UA0 UDI0 UDO0 R W √ √ √ √ √ √ - USB_CTL: USB bus control register, − − REGC: 3.3V regulator control. 0: Disable (default), 1: Enable URD: USB register read control, writing 1 into this bit to read the USB register addressed by the USB_ADDR SFR − UWT: USB register write control, writing 1 into this bit to write the USB register addressed by the USB_ADDR SFR USB_ADDR: One USB register address to be accessed USB_DI: Data to be written into the USB register addressed by the USB_ADDR SFR USB_DO: Data to be read out from the USB register addressed by the USB_ADDR SFR MPC2F35 is a Low-speed USB 1.1 version compliant with the USB transceiver and a built-in 3.3V regulator. The 3.3V regulator can be controlled by programming the REGC bit in the USB_CTL SFR. There are some USB registers in MPC2F35. The user can access these USB registers through the access the control registers, which is provided by MPC2F35. The sequence to access USB register should be as the following: A. Write sequence: 1. Write the address of USB register to be accessed into the USB_ADDR SFR 2. Write 1 into the UWT bit in the USB_CTL SFR 3. Write data into the USB_DI SFR 4. Write 0 into the UWT bit B. Read sequence: 1. Write the address of USB register to be accessed into the USB_ADDR SFR 2. Write 1 into the URD bit in the USB_CTL SFR 3. Read data from the USB_DO SFR MEGAWIN MPC2F35_USB Data Sheet 15 4. Write 0 into the URD bit Whenever USB engine finished a transaction, it will generate an interrupt to acknowledge MPC2F35. The user can get information about the transaction through the above sequence. When USB engine received a reset instruction from the host, it will reset by itself and generate an interrupt. When USB engine received a wake-up instruction from the host while the device is being in the stop mode, it will generate a signal to enable the oscillator. If the host and the device are both in the stop mode, a falling edge on Port 3 can wake-up the device, and then remote wake up the host through USB engine. DPM control Address 00E8H 00E9H 00EAH Name DPM_CTL DPMO DPMI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 C1 DPO DPI Bit 0 C0 DMO DMI R W √ √ √ √ √ - C1, C0: USB bus (D+ and D-) mode control selector. 1. 0x: USB bus is at the USB operation (Default) 2. 10: USB bus is at the PS/2 interface operation DPMO: PS/2 data output on USB data bus line (D+/D-), 0: output low, 1: pull-high DPMI: Value on the USB data bus line (Read only) while working at the PS/2 operation MPC2F35’s USB bus lines (D+ and D -) have two operating modes: USB low speed and PS/2 interface mode. User can program the C0 and C1 bit in the CDPM_CTL SFR to determine the operating mode of USB bus. The DPI and DMI bit in the DPMI SFR will record the content on the D+ and D- pin respectively. The firmware can judge the USB bus line (D+ and D-) connection will be USB or PS/2 protocol by reading the value of the DPI and DMI bit in the DPMI SFR. For PS/2 interface application, the C1 and C0 in the DPM_CTL SFR have to set “10” first, thus the USB function will be unavailable. The user programs the value of USB bus (D+/D-) into the DPO and DMO bit in the DPMO SFR when MPC2F35 controls the D+/D- pin for the PS/2 operation. When DPO/DMO is programming as writing 0, it will make the D+/D- pin to output low. On the other hand, writing 1 will cause these pins to be pulled high. This I/O control operation would be easy to perform the PS/2 interface. 16 MPC2F35_USB Data Sheet MEGAWIN USB Special Function Registers (SFRs) Summary There are 18 special function registers for the operation of Universal Serial Bus (USB). The detail definition is described as the following: Mnemonic DCON FADDR FPCON Mnemonic FIE FIFLG IEN1 Mnemonic EPINDEX EPCON* RXCNT* RXCON* RXDAT* RXSTAT* TXCNT* TXCON* TXDAT* TXSTAT* USB Device SFRs Device Control Register Function Address Register Function Power Control Register USB Interrupt System SFRs USB Function Interrupt Enable Register USB Function Interrupt Flag Register USB Interrupt Enable Register USB Endpoint SFRs Endpoint Index Register Endpoint Control Register Receive FIFO Byte-Count Register Receive FIFO Control Register Receive FIFO Data Register Endpoint Receive Status Register Transmit FIFO Byte-Count Register Transmit FIFO Control Register Transmit FIFO Data Register Endpoint Transmit Status Register Address 01H 08H 12H Address 18H 1AH 10H Address 31H 21H 26H 24H 23H 22H 36H 34H 33H 32H – RXSTL – RXCLR RD7 RXSEQ – TXCLR TD7 TXSEQ – TXSTL – – RD6 RXSETUP – – TD6 – – – – – RD5 STOVW – – TD5 – – – – – – – – – – – – TESTEN – – – A6 – – A5 FRWU – Description – A3 URST Description FRXIE3 FRXD3 – FTXIE2 FTXD2 EFSR Description – – RXBC3 – RD3 RXSOVW TXBC3 – TD3 TXSOVW – RXEPEN RXBC2 – RD2 – TXBC2 – TD2 – EPINX1 – RXBC1 – RD1 – TXBC1 – TD1 – EPINX0 TXEPEN RXBC0 – RD0 – TXBC0 – TD0 – FTXIE1 FTXD1 – FRXIE0 FRXD0 EF FTXIE0 FTXD0 – – A2 – PUREN A1 FRSM CONPUEN A4 – A0 FSUS RXFFRC RD4 EDOVW – – TD4 – MEGAWIN MPC2F35_USB Data Sheet 17 USB SFR Description DCON: Device Control Register Read/Write Default: 0XXX_XX00 Bit Number 7 6 5 4 3 2 1 Bit Mnemonic TESTEN PUREN Function TEST mode Enable: Use for test only. In normal operation, this bit should be cleared to “0”. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Internal Pull-Up Resistor Enable: When this bit is set to ‘1’, enable internal D- pull-up resistor. After setting this bit, the device will act a connection to USB host. Device USP Connection Pull-up Enable: This bit is used by FW to control whether device is connected to upper host/hub via driving bus SE0. Set ‘1’ to release bus to expose the D- pullup resistor. Clear ‘0’ to force bus SE0 to inhibit the D- pull-up resistor. Default is cleared to ‘0’ after reset. FW should set ‘1’ to enable connection to upper host/hub. Address: 01H System Reset 0 CONPUEN 18 MPC2F35_USB Data Sheet MEGAWIN FADDR: USB Function Address Register Read/Write Default: X000_0000 Bit Number 7 6:0 Bit Mnemonic A [6:0] Function Reserved: Write zero to this bit. Function Address: This register holds the address for the USB function. During bus enumeration, it is written with a unique value assigned by the host. Address: 08H System Reset or USB Reset MEGAWIN MPC2F35_USB Data Sheet 19 FPCON: Function Power Control Register Read/Write Default: XX0X_xX00 Bit Number 7 6 5 Bit Mnemonic FRWU Function Reserved: Write zero to this bit. Reserved: Write zero to this bit. Function Remote Wake-up Trigger: This bit is used by the function to initiate a remote wake-up on the USB bus when uC is wake-up by the external trigger. Reserved: Write zero to this bit. USB Reset Flag: Set by hardware when the function detects the USB bus reset. If this bit is set, and then the chip will generate the interrupt. Should be cleared by firmware when serving the USB reset interrupt. Reserved: Write zero to this bit. Function Resume Flag: Set by hardware when the function detects the resume state on the USB bus. If this bit is set, and then the chip will generate the interrupt. Cleared by firmware when servicing the function resume interrupt. Function Suspend Flag: Set by hardware when the function detects the suspend state on the USB bus. If this bit is set, and then the chip will generate the interrupt. During the function suspend ISR, firmware should clear this bit before enter the suspend mode. Address: 12H System Reset or USB Reset 4 3 URST 2 1 FRSM 0 FSUS 20 MPC2F35_USB Data Sheet MEGAWIN FIE: Function Interrupt Enable Register Read/Write Default: XXX0_0000 Bit Number 7 6 5 4 3 2 1 0 Bit Mnemonic FRXIE3 FTXIE2 FTXIE1 FRXIE0 FTXIE0 Function Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Function Receive Interrupt Enable 3: Enables the receive done interrupt for function endpoint 3 (FRXD3). Function Transmit Interrupt Enable 2: Enables the transmit done interrupt for function endpoint 2 (FTXD2). Function Transmit Interrupt Enable 1: Enables the transmit done interrupt for function endpoint 1 (FTXD1). Function Receive Interrupt Enable 0: Enables the receive done interrupt for function endpoint 0 (FRXD0). Function Transmit Interrupt Enable 0: Enables the transmit done interrupt for function endpoint 0 (FTXD0). Address: 18H System Reset or USB Reset MEGAWIN MPC2F35_USB Data Sheet 21 FIFLG: Function Interrupt Flag Register Read/Write Default: XXX0_0000 Bit Number 7 6 5 4 Bit Mnemonic FRXD3 Function Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Function Receive Done Flag 3: For endpoint 3, uC can read/write-clear firmware writes ‘1’ to it. Function Transmit Done Flag 2: For endpoint 2, uC can read/write-clear firmware writes ‘1’ to it. Function Transmit Done Flag 1: For endpoint 1, uC can read/write-clear firmware writes ‘1’ to it. Function Receive Done Flag 0: For endpoint 0, uC can read/write-clear firmware writes ‘1’ to it. Function Transmit Done Flag 0: For endpoint 0, uC can read/write-clear firmware writes ‘1’ to it. Address: 1AH System Reset or USB Reset on this bit. This bit is cleared when 3 FTXD2 on this bit. This bit is cleared when 2 FTXD1 on this bit. This bit is cleared when 1 FRXD0 on this bit. This bit is cleared when 0 FTXD0 on this bit. This bit is cleared when 22 MPC2F35_USB Data Sheet MEGAWIN IEN1: USB Interrupt Enable Register Read/Write Default: XXXX_0X0X Bit Number 7 6 5 4 3 Bit Mnemonic EFSR Reserved: Write “one” to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Enable Function Suspend/Resume: Function suspend/resume/USB reset interrupt enable bit. Reserved: Write zero to this bit. Enable Function: Transmit/receive done interrupt enable bit for USB function endpoints. Reserved: Write zero to this bit. Function Address: 10H System Reset 2 1 0 EF - MEGAWIN MPC2F35_USB Data Sheet 23 EPINDEX: Endpoint Index Register Read/Write Default: XXXX_XX00 Bit Number 7 6 5 4 3 2 1:0 Bit Mnemonic EPINX1:0 Function Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Endpoint index bit 1:0: EPINDEX = : Function Endpoint 0 = : Function Endpoint 1 = : Function Endpoint 2 = : Function Endpoint 3 Address: 31H System Reset or USB Reset 24 MPC2F35_USB Data Sheet MEGAWIN EPCON: Endpoint Control Register (Endpoint-Indexed) Read/Write Default: 00XX_X0X0 Bit Number 7 6 5 4 3 2 Bit Mnemonic RXSTL TXSTL RXEPEN Function Stall Receive Endpoint: Set this bit to stall the receive endpoint. Stall Transmit Endpoint: Set this bit to stall the transmit endpoint. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write “one” to this bit. Receive Endpoint Enable: Set this bit to enable the receive endpoint. When disabled, the endpoint does not respond to a valid OUT or SETUP token. Reserved: Write “one” to this bit. Transmit Endpoint Enable: This bit is used to enable the transmit endpoint. When disabled, the endpoint does not respond to a valid IN token. Address: 21H System Reset or USB Reset 1 0 TXEPEN MEGAWIN MPC2F35_USB Data Sheet 25 RXCNT: Receive FIFO Byte-Count Register (Endpoint-Indexed) Read Only Default: XXXX_0000 Bit Number 7 6 5 4 3 2 1 0 Bit Mnemonic RXBC3 RXBC2 RXBC1 RXBC0 Function Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Receive Byte Count Bit 3: Store receive byte count. Maximum is 8 bytes. Receive Byte Count Bit 2: Store receive byte count. Maximum is 8 bytes. Receive Byte Count Bit 1: Store receive byte count. Maximum is 8 bytes. Receive Byte Count Bit 0: Store receive byte count. Maximum is 8 bytes. Address: 26H System Reset or USB Reset 26 MPC2F35_USB Data Sheet MEGAWIN RXCON: Receive FIFO Control Register (Endpoint-Indexed) Read/Write Default: 0XX0_XXXX Bit Number 7 Bit Mnemonic RXCLR Function Receive FIFO Clear: Set this bit to flush the entire receive FIFO. All FIFO statuses are reverted to their reset states. Hardware clears this bit when the flush operation is completed. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Receive FIFO Read Complete: Set this bit to release the receive FIFO when data set read is complete. Hardware clears this bit after the FIFO release operation has been finished. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Address: 24H System Reset or USB Reset 6 5 4 RXFFRC 3 2 1 0 - MEGAWIN MPC2F35_USB Data Sheet 27 RXDAT: Receive FIFO Data Register (Endpoint-Indexed) Read Only Default: XXXX_XXXX Bit Number 7:0 Bit Mnemonic RD [7:0] Function Receive FIFO data specified by EPINDEX is stored and read from this register. Address: 23H System Reset or USB Reset 28 MPC2F35_USB Data Sheet MEGAWIN RXSTAT: Endpoint Receive Status Register (Endpoint-Indexed) Read/Write Default: 0000_0XXX Bit Number 7 Bit Mnemonic RXSEQ Function Receive Endpoint Sequence Bit (read, conditional write): The bit will be toggled on completion of an ACK handshake in response to an OUT token. This bit can be written by firmware if the RXOVW bit is set when written along with the new RXSEQ value. Received Setup Transaction: This bit is set by hardware when a valid SETUP transaction has been received. Clear this bit upon detection of a SETUP transaction or the firmware ready to handle the data/status stage of control transfer. Start Overwrite Flag (read-only): Set by hardware upon receipt of a SETUP token for any control endpoint to indicate that the receive FIFO is being overwritten with new SETUP data. This bit is used only for control endpoints. End Overwrite Flag: This flag is set by hardware during the handshake phase of a SETUP stage. This bit is cleared by firmware to read FIFO data. This bit is only used for control endpoints. Receive Data Sequence Overwrite Bit: Write ‘1’ to this bit to allow the value of the RXSEQ bit to be overwritten. Writing a ‘0’ to this bit, it has no effect on RXSEQ. This bit always returns to ‘0’ when read. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Address: 22H System Reset or USB Reset 6 RXSETUP 5 STOVW 4 EDOVW 3 RXSOVW 2 1 0 - MEGAWIN MPC2F35_USB Data Sheet 29 TXCNT: Transmit FIFO Byte-Count Register (Endpoint-Indexed) Write Only Default: XXXX_XXXX Bit Number 7 6 5 4 3 2 1 0 Bit Mnemonic TXBC3 TXBC2 TXBC1 TXBC0 Function Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Transmit Byte Count Bit 3: Store transmit byte count. Maximum is 8 bytes. Transmit Byte Count Bit 2: Store transmit byte count. Maximum is 8 bytes. Transmit Byte Count Bit 1: Store transmit byte count. Maximum is 8 bytes. Transmit Byte Count Bit 0: Store transmit byte count. Maximum is 8 bytes. Address: 36H System Reset or USB Reset 30 MPC2F35_USB Data Sheet MEGAWIN TXCON: Transmit FIFO Control Register (Endpoint-Indexed) Read/Write Default: 0XXX_XXXX Bit Number 7 Bit Mnemonic TXCLR Function Transmit FIFO Clear: Set this bit to flush the entire transmit FIFO. All FIFO statuses are reverted to their reset states. Hardware clears this bit when the flush operation is completed. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Address: 34H System Reset or USB Reset 6 5 4 3 2 1 0 - MEGAWIN MPC2F35_USB Data Sheet 31 TXDAT: Transmit FIFO Data Register (Endpoint-Indexed) Write Only Default: XXXX_XXXX Bit Number 7:0 Bit Mnemonic TD [7:0] Function Data to be transmitted in the FIFO specified by EPINDEX is written to this register. Address: 33H System Reset or USB Reset 32 MPC2F35_USB Data Sheet MEGAWIN TXSTAT: Endpoint Transmit Status Register (Endpoint-Indexed) Read/Write Default: 0XXX_0XXX Bit Number 7 Bit Mnemonic TXSEQ Function Transmit Endpoint Sequence Bit (read, conditional write): The bit will be transmitted in the next PID and toggled on a valid ACK handshake of an IN transaction. This bit can be written by firmware if the TXSOVW bit is set when written along with the new TXSEQ value. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Transmit Data Sequence Overwrite Bit: Write a "1" to this bit to allow the value of the TXSEQ bit to be overwritten. Writing a "0" to this bit has no effect on TXSEQ. This bit always returns to "0" when read. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Reserved: Write zero to this bit. Address: 32H System Reset or USB Reset 6 5 4 3 TXSOVW 2 1 0 - MEGAWIN MPC2F35_USB Data Sheet 33 APPLICATION CIRCUIT 1. Normal: VBus DD+ GND 30 Ω 30 Ω 15 pF 15 pF DD+ Vcc + Vss 10 uF 0.1 uF P0/P1/P2/ P3/P4 -RST 0.1 uF V3.3 1 uF 30 pF + - XTAL1 Vss XTAL2 30 pF 6M Hz Note: The capacitor between RESB-pin and ground must be below 0.1uF. 2. USB keyboard: VCC connector 1 2 3 4 VCC C2 15P option C1 15P option R1 30 3 1 R2 30 2 C8 4 1u 5 6 U1 DD+ V3.3 Vss Xtal1 Xtal2 P0.4/-INT0 P0.5/-INT1 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 Vcc P0.3/LED3 P0.2/LED2 P0.1/LED1 P0.0/LED0 /RST P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 40 39 C5 10u C6 0.1u VCC ScrollLock 38 D1 37 D2 36 D3 35 C7 34 33 32 31 30 29 28 27 26 25 24 23 22 21 R7 R6 R5 R4 R3 R2 R1 R0 C17 C16 C0 C9 C8 C10 0.1u NumLock CapsLock Y1 6MHz C3 option 30P C4 30P C1 C2 C3 C4 C5 C6 C7 C14 C13 C12 C11 C15 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MPC2F35E2_40 pin DIP 34 MPC2F35_USB Data Sheet MEGAWIN Absolute Maximum Rating PARAMETER Supply Voltage to Ground Potential Maximum current per pin excluding VDD and VSS Maximum current out of GND Maximum current out of VCC Ambient Operating Temperature Storage Temperature RATING -0.5 to +6.0 25 100 100 0 to +70 -40 to +125 UNIT V mA mA mA °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC Characteristics (VDD-VSS = 5.0 V, FOSC = 6MHz, Ta = 25° C; unless otherwise specified) PARAMETER Op. Voltage Op. Current Suspend Current Input High Voltage Input Low Voltage Port 0, 1, 2, 3 drive current Port 0.4~0.7, 1, 2, 3 sink current Port 0.0~0.3 sink current Internal Pull-high Resistor SYM. VDD IOP ISTB VIH VIL IOH IOL1 IOL2 RPH CONDITIONS 3.0V≦V3.3≧3.6V No load (Ext.-V) In normal operation Internal 7.5KΩ with No load VOH = 4.5V, VDD = 5.0V VOL = 0.4V, VDD = 5.0V VOL = 3.2V, VDD = 5.0V VIL = 0V MIN. 4.35 2 0 6 - TYP. 12.5 2.5 4.0 8 27K MAX. 5.5 20 500 VDD 0.8 - UNIT V mA μA V V mA mA mA Ω AC Characteristics PARAMETER CPU Op. Frequency POR duration SYM. FCPU TPOR CONDITIONS VDD = 5.0V FOSC = 6 MHz MIN. 0.5 10 TYP. 3 MAX. UNIT MHz mS MEGAWIN MPC2F35_USB Data Sheet 35 PACKAGE DIMENSIONS 40-pin DIP 28-SSOP 36 MPC2F35_USB Data Sheet MEGAWIN Instruction Set Summary Symbol Description ACC: Accumulator (ACC): ACC.n: X: Y: SP: PC: #data: C: Z: I: B: D: V: S: addr16: addr8: addr+(index): addr →16: Contents of Accumulator Accumulator bit n Index Register X Index Register Y Stack Pointer Register Program Counter Constant parameter Carry Flag Zero Flag Interrupt Disable Status Break Status Decimal Mode Status Overflow Flag Sign Flag Absolute Address Zero Page/Relative Address Combined Address Address Extend to Absolute Address (Get two addr8 contents continuously) Address Variable 1’s compliment AND OR Exclusive OR Transfer direction, result label: ~: ∩: ∪: ⊕: ←: MEGAWIN MPC2F35_USB Data Sheet 37 Instruction Set Summary (212 instructions) Mnemonic ADC Operand(s) addr8 #data (addr8) addr8, X (addr8, X) (addr8), Y addr16 addr16, X addr16, Y Operation description (ACC) ← (ACC) + (addr8) + (C) (ACC) ← (ACC) + #data + (C) (ACC) ← (ACC) + [(addr8)] + (C) (ACC) ← (ACC) + [addr8 + (X)] + (C) (ACC) ← (ACC) + {[addr8 + (X) →16]} + (C) (ACC) ← (ACC) + [(addr8→16) + (Y)] + (C) (ACC) ← (ACC) + (addr16) + (C) (ACC) ← (ACC) + [addr16 + (X)] + (C) (ACC) ← (ACC) + [addr16 + (Y)] + (C) (ACC) ← (ACC) – (addr8) – (~C) (ACC) ← (ACC) – #data – (~C) (ACC) ← (ACC) – [(addr8)] – (~C) (ACC) ← (ACC) – [addr8 + (X)] – (~C) (ACC) ← (ACC) – {[addr8 + (X) →16]} – (~C) (ACC) ← (ACC) – [(addr8→16) + (Y)] – (~C) (ACC) ← (ACC) – (addr16) – (~C) (ACC) ← (ACC) – [addr16 + (X)] – (~C) (ACC) ← (ACC) – [addr16 + (Y)] – (~C) (ACC) ← (ACC) ∩ (addr8) (ACC) ← (ACC) ∩ #data (ACC) ← (ACC) ∩ [(addr8)] (ACC) ← (ACC) ∩ [addr8 + (X)] (ACC) ← (ACC) ∩ {[addr8 + (X) →16]} (ACC) ← (ACC) ∩ [(addr8→16) + (Y)] (ACC) ← (ACC) ∩ (addr16) (ACC) ← (ACC) ∩ [addr16 + (X)] (ACC) ← (ACC) ∩ [addr16 + (Y)] Flag C, Z, V,S C, Z, V,S C, Z, V,S C, Z, V,S C, Z, V,S C, Z, V,S C, Z, V,S C, Z, V,S C, Z, V,S C, Z, V,S C, Z, V,S C, Z, V,S C, Z, V,S C, Z, V,S C, Z, V,S C, Z, V,S C, Z, V,S C, Z, V,S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Byte Cycle 2 2 2 2 2 2 3 3 3 2 2 2 2 2 2 3 3 3 2 2 2 2 2 2 3 3 3 3 2 5 4 6 5 * 4 4 4 * * SBC addr8 #data (addr8) addr8, X (addr8, X) (addr8), Y addr16 addr16, X addr16, Y 3 2 5 4 6 5 * 4 4 4 * * AND addr8 #data (addr8) addr8, X (addr8, X) (addr8), Y addr16 addr16, X addr16, Y 3 2 5 4 6 5 4 4 * 4 * * Note: Add one clock period of page boundary is crossed. * 38 MPC2F35_USB Data Sheet MEGAWIN Mnemonic ORA Operand(s) addr8 #data (addr8) addr8, X (addr8, X) (addr8), Y addr16 addr16, X addr16, Y Operation description (ACC) ← (ACC) ∪ (addr8) (ACC) ← (ACC) ∪ #data (ACC) ← (ACC) ∪ [(addr8)] (ACC) ← (ACC) ∪ [addr8 + (X)] (ACC) ← (ACC) ∪ {[addr8 + (X) →16]} (ACC) ← (ACC) ∪ [(addr8→16) + (Y)] (ACC) ← (ACC) ∪ (addr16) (ACC) ← (ACC) ∪ [addr16 + (X)] (ACC) ← (ACC) ∪ [addr16 + (Y)] (ACC) ← (ACC) ⊕ (addr8) (ACC) ← (ACC) ⊕ #data (ACC) ← (ACC) ⊕ [(addr8)] (ACC) ← (ACC) ⊕ [addr8 + (X)] (ACC) ← (ACC) ⊕ {[addr8 + (X) →16]} (ACC) ← (ACC) ⊕ [(addr8→16) + (Y)] (ACC) ← (ACC) ⊕ (addr16) (ACC) ← (ACC) ⊕ [addr16 + (X)] (ACC) ← (ACC) ⊕ [addr16 + (Y)] (ACC) – (addr8) – (~C) (ACC) – #data – (~C) (ACC) – [(addr8)] – (~C) (ACC) – [addr8 + (X)] – (~C) (ACC) – {[addr8 + (X) →16]} – (~C) (ACC) – [(addr8→16) + (Y)] – (~C) (ACC) – (addr16) – (~C) (ACC) – [addr16 + (X)] – (~C) (ACC) – [addr16 + (Y)] – (~C) (X) – #data (X) – (addr8) (X) – (addr16) (Y) – #data (Y) – (addr8) (Y) – (addr16) Flag Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S Byte Cycle 2 2 2 2 2 2 3 3 3 2 2 2 2 2 2 3 3 3 2 2 2 2 2 2 3 3 3 2 2 3 2 2 3 3 2 5 4 6 5 4 4 * 4 * * EOR addr8 #data (addr8) addr8, X (addr8, X) (addr8), Y addr16 addr16, X addr16, Y 3 2 5 4 6 5 4 4 * 4 * * CMP addr8 #data (addr8) addr8, X (addr8, X) (addr8), Y addr16 addr16, X addr16, Y 3 2 5 3 6 5* 4 4* 4* 2 3 4 2 3 4 CPX #data addr8 addr16 CPY #data addr8 addr16 Note: Add one clock period of page boundary is crossed. * MEGAWIN MPC2F35_USB Data Sheet 39 Mnemonic CLC CLI CLD CLV RMB0 … RMB7 SEC SEI SED SMB0 … SMB7 INC INC Operand(s) Operation description (C) ← 0 (I) ← 0 (D) ← 0 (V) ← 0 Flag C I D V Z Z C I D Z Z C, Z Z, S Z, S Z, S Z, S Z, S Z, S C, Z Z, S Z, S Z, S Z, S Z, S Z, S Byte Cycle 1 1 1 1 2 2 1 1 1 2 2 1 2 2 3 3 1 1 1 2 2 3 3 1 1 2 2 2 2 5 5 2 2 2 5 5 2 5 6 6 6 * addr8 addr8 (addr8.0) ← 0 (addr8.7) ← 0 (C) ← 1 (I) ← 1 (D) ← 1 addr8 addr8 A addr8 addr8, X addr16 addr16, X (addr8.0) ← 1 (addr8.7) ← 1 (ACC) ← (ACC) + 1 (addr8) ← (addr8) + 1 [addr8 + (X)] ← [addr8 + (X)] + 1 (addr16) ← (addr16) + 1 [addr16 + (X)] ← [addr16 + (X)] + 1 (X) ← (X) + 1 (Y) ← (Y) + 1 INX INY DEC DEC A addr8 addr8, X addr16 addr16, X DEX DEY * 2 2 2 5 6 6 6 * (ACC) ← (ACC) – 1 (addr8) ← (addr8) – 1 [addr8 + (X)] ← [addr8 + (X)] – 1 (addr16) ← (addr16) – 1 [addr16 + (X)] ← [addr16 + (X)] – 1 (X) ← (X) – 1 (Y) ← (Y) – 1 2 2 Note: Add one clock period of page boundary is crossed. If the assembler does not support this instruction, please use DB to implement it. The OP code of RMB0 ~ RMB7 is 07 ~ 77, and the SMB0 ~ SMB7 is 87 ~ F7. 40 MPC2F35_USB Data Sheet MEGAWIN Mnemonic ROL ROL Operand(s) A addr8 addr8, X addr16 addr16, X Operation description (C) ← (ACC.7), (ACC.(n+1)) ← (ACC. n), (ACC.0 ) ← (C) (C) ← (addr8.7), (addr8.(n+1)) ← (addr8.n), (addr8.0 ) ← (C) (C) ← [addr8 + (X).7], [addr8 + (X).(n+1)] ← [addr8 + (X).n], [addr8 + (X).0] ← (C) (C) ← (addr16.7), (addr16.(n+1) )← (addr16.n), (addr16.0 ) ← (C) (C) ← [addr16 + (X).7], [addr16 + (X).(n+1)] ← [addr16 + (X).n], [addr16 + (X).0] ← (C) (ACC.7 ) ← (C), (ACC. n) ← (ACC.(n+1) ), (C) ← (ACC.0) (addr8.7 ) ← (C), (addr8. n) ← (addr8.(n+1) ), (C) ← (addr8.0) [addr8 + (X).7] ← (C), [addr8 + (X).n] ← [addr8 + (X).(n+1)], (C) ← [addr8 + (X).0] (addr16.7 ) ← (C), (addr16. n) ← (addr16.(n+1) ), (C) ← (addr16.0) [addr16 + (X).7] ← (C), [addr16 + (X).n] ← [addr16 + (X).(n+1)], (C) ← [addr16 + (X).0] (C) ← (ACC.7), (ACC.(n+1) ) ← (ACC. n), (ACC.0) ← 0 (C) ← (addr8.7), (addr8.(n+1) ) ← (addr8. n), (addr8.0) ← 0 (C) ← [addr8 + (X).7], [addr8 + (X).(n+1)] ← [addr8 + (X).n], [addr8 + (X).0] ← 0 (C) ← (ACC.7), (ACC.(n+1) ) ← (ACC. n), (ACC.0) ← 0 (C) ← [addr16 + (X).7], [addr16 + (X).(n+1)] ← [addr16 + (X).n], [addr16 + (X).0] ← 0 (ACC.7 ) ← 0, (ACC. n) ← (ACC.(n+1) ), (C) ← (ACC.0) (addr8.7 ) ← 0, (addr8. n) ← (addr8.(n+1) ), (C) ← (addr8.0) [addr8 + (X).7] ← 0, [addr8 + (X).n] ← [addr8 + (X).(n+1)], (C) ← [addr8 + (X).0] (addr16.7 ) ← 0, (addr16. n) ← (addr16.(n+1) ), (C) ← (addr16.0) [addr16 + (X).7] ← 0, [addr16 + (X).n] ← [addr16 + (X).(n+1)], (C) ← [addr16 + (X).0] Flag C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S Byte Cycle 1 2 2 3 3 2 5 6 6 6 ROR ROR A addr8 addr8, X addr16 addr16, X C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S 1 2 2 3 3 2 5 6 6 6 ASL ASL A addr8 addr8, X addr16 addr16, X C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S 1 2 2 3 3 2 5 6 6 6 LSR LSR A addr8 addr8, X addr16 addr16, X C, Z, S C, Z, S C, Z, S C, Z, S C, Z, S 1 2 2 3 3 2 5 6 6 6 MEGAWIN MPC2F35_USB Data Sheet 41 Mnemonic LDA LDA Operand(s) #data addr8 (addr8) addr8, X (addr8, X) (addr8), Y addr16 addr16, X addr16, Y Operation description (ACC) ← #data (ACC) ← (addr8) (ACC) ← [(addr8)] (ACC) ← [addr8 + (X)] (ACC) ← {[addr8 + (X) →16]} (ACC) ← [(addr8→16) + (Y)] (ACC) ← (addr16) (ACC) ← [addr16 + (X)] (ACC) ← [addr16 + (Y)] (X) ← #data (X) ← (addr8) (X) ← [addr8 + (Y)] (X) ← (addr16) (X) ← [addr16 + (Y)] (Y) ← #data (Y) ← (addr8) (Y) ← [addr8 + (X)] (Y) ← (addr16) (Y) ← [addr16 + (X)] Flag Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Z, S Byte Cycle 2 2 2 2 2 2 3 3 3 2 2 2 3 3 2 2 2 3 3 2 3 5 4 6 6 4 4 * 4 * * LDX #data addr8 addr8, Y addr16 addr16, Y 2 3 4 4 4 * LDY #data addr8 addr8, X addr16 addr16, X 2 3 4 4 4 * Note: Add one clock period of page boundary is crossed. * 42 MPC2F35_USB Data Sheet MEGAWIN Mnemonic STA Operand(s) addr8 (addr8) addr8, X (addr8, X) (addr8), Y addr16 addr16, X addr16, Y Operation description (addr8) ← (ACC) [(addr8)] ← (ACC) [addr8 + (X)] ← (ACC) {[addr8 + (X) →16]} ← (ACC) [(addr8→16) + (Y)] ← (ACC) (addr16) ← (ACC) [addr16 + (X)] ← (ACC) [addr16 + (Y)] ← (ACC) (addr8) ← (X) [addr8 + (Y)] ← (X) (addr16) ← (X) (addr8) ← (Y) [addr8 + (X)] ← (Y) (addr16) ← (Y) (addr8) ← 00H [addr8 + (X)] ← 00H (addr16) ← 00H [addr16 + (X)] ← 00H (X) ← (ACC) (ACC) ← (X) (Y) ← (ACC) (ACC) ← (Y) (X) ← (SP) (SP) ← (X) Flag Z, S Z, S Z, S Z, S Z, S - Byte Cycle 2 2 2 2 2 3 3 3 2 2 3 2 2 3 2 2 3 3 1 1 1 1 1 1 2 3 2 3 3 5 4 6 6 4 4 * 4 * * STX addr8 addr8, Y addr16 3 4 4 3 4 4 3 4 4 5 2 2 2 2 2 2 5 6 5 6 STY addr8 addr8, X addr16 STZ addr8 addr8, X addr16 addr16, X TAX TXA TAY TYA TSX TXS TRB TSB * addr8 addr16 addr8 addr16 (addr8) ← (~ACC) ∩ (addr8) (addr16) ← (~ACC) ∩ (addr16) (addr8) ← (ACC) ∪ (addr8) (addr16) ← (ACC) ∪ (addr16) Note: Add one clock period of page boundary is crossed. MEGAWIN MPC2F35_USB Data Sheet 43 Mnemonic JMP Operand(s) label (label) (label, X) Operation description (PC) ← label; the label may be address or variable. (PC) ← (label) (PC) ← {[label + (X) →16]} (PC) ← (PC)+addr8 (PC) ← (PC)+addr8 if Z == 1 (+/- relative) (PC) ← (PC)+addr8 if Z == 0 (+/- relative) (PC) ← (PC)+addr8 if C == 1 (+/- relative) (PC) ← (PC)+addr8 if C == 0 (+/- relative) (PC) ← (PC)+addr8 if (S == 1) (PC) ← (PC)+addr8 if (S == 0) (PC) ← (PC)+addr8 if (V == 1) (PC) ← (PC)+addr8 if (V == 0) (ACC) ∩ (addr8) (ACC) ∩ [addr8 + (X)] (ACC) ∩ (addr16) (ACC) ∩ [addr16 + (X)] (ACC) ∩ #data (PC) ← (PC)+addr8 if ACC.0 == 0 (+/- relative) (PC) ← (PC)+addr8 if ACC.7 == 0 (+/- relative) (PC) ← (PC)+addr8 if ACC.0 == 1 (+/- relative) (PC) ← (PC)+addr8 if ACC.7 == 1 (+/- relative) Flag Z Z Z Z Z - Byte Cycle 3 3 3 2 2 2 2 2 2 2 2 2 2 2 3 3 2 3 3 3 3 3 6 6 3 2 2 2 2 2 2 2 2 ** BRA BEQ BNE BCS BCC BMI BPL BVS BVC BIT addr8 addr8 (relative) addr8 addr8 addr8 addr8 addr8 addr8 addr8 addr8 addr8, X addr16 addr16, X #data ** ** ** ** ** ** ** 3 4 4 4 2 5 5 5 5 BBR0 … BBR7 BBS0 … BBS7 ** addr8 addr8 addr8 addr8 Note: Add one clock period if branch occurs to location in same page. Add two clock periods if branch to another page occurs. If the assembler does not support this instruction, please use DB to implement it. The OP code of BBR0 ~ BBR7 is 0F ~ 7F, and the BBS0 ~ BBS7 is 8F ~ FF. 44 MPC2F35_USB Data Sheet MEGAWIN Mnemonic JSR RTS RTI PHA PHP PHX PHY PLA PLP PLX PLY NOP Note: ** Operand(s) label Operation description stack ← (PC), (PC) ← label (PC) ← pop stack (PC) ← pop stack, restore status register P [(SP)] ← (ACC), (SP) ← (SP) – 1 [(SP)] ← (P), (SP) ← (SP) – 1 [(SP)] ← (X), (SP) ← (SP) – 1 [(SP)] ← (Y), (SP) ← (SP) – 1 (ACC) ← [(SP+1)], (SP) ← (SP) + 1 (P) ← [(SP+1)], (SP) ← (SP) + 1 (X) ← [(SP+1)], (SP) ← (SP) + 1 (Y) ← [(SP+1)], (SP) ← (SP) + 1 No operation Flag C, Z, I, D, V, S Z, S C, Z, I, D, V, S Z, S Z, S - Byte Cycle 3 1 1 1 1 1 1 1 1 1 1 1 6 6 6 3 3 3 3 4 4 4 4 2 Add one clock period if branch occurs to location in same page. Add two clock periods if branch to another page occurs. MEGAWIN MPC2F35_USB Data Sheet 45 Revision History VERSION A1 A2 A3 A4 DATE 2004/04 2005/01 2005/07 2008/12 39 17~33 PAGE Initial issue Application circuit has been modified. Revised USB Special Function Registers (SFRs) Summary and USB SFR Description. Formatting DESCRIPTION 46 MPC2F35_USB Data Sheet MEGAWIN