EVB71122C-915-C

EVB71122 300 to 930MHz Receiver Evaluation Board Description Features ! ! ! ! ! ! ! ! ! ! ! ! ! Programmable PLL synthesizer 8-channel preconfigured or fully programmable SPI mode Double super-heterodyne receiver architecture with 2nd mixer as image rejection mixer Reception of FSK, FM and ASK modulated signals Low shut-down and operating currents Build-in acceptance of input frequency variations On-chip IF filter Fully integrated FSK/FM demodulator RSSI for level indication and ASK detection 2nd order low-pass data filter Positive and negative peak detectors Data slicer (with averaging or peak-detector adaptive threshold) EVB programming software is available on Melexis web site Ordering Information Part No. (see paragraph 6) EVB71122C-315-C EVB71122C-433-C Note: SPI mode is default population, ABC mode according to paragraph 4.2 Application Examples ! General digital and analog RF receivers at 300 to 930MHz ! Tire pressure monitoring systems (TPMS) ! Remote keyless entry (RKE) ! Low power telemetry systems ! Alarm and security systems ! Active RFID tags ! Remote controls ! Garage door openers ! Home and building automation Y R A IN IM L E R P EVB71122C-868-C EVB71122C-915-C Evaluation Board Example General Description The MLX71122 is a multi-channel RF receiver IC based on a double-conversion super-heterodyne architecture. It is designed to receive FSK and ASK modulated RF signals either in 8 predefined frequency channels or frequency programmable via a 3-wire serial programming interface (SPI). The IC is designed for a variety of applications, for example in the European bands at 433MHz and 868MHz or for the use in North America or Asia, e.g. at 315MHz, 447MHz or 915MHz. 39012 71122 01 Rev. 001 Page 1 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description Document Content 1 Theory of Operation ...................................................................................................4 1.1 1.2 1.3 1.4 1.5 1.6 1.7 General............................................................................................................................. 4 EVB Data Overview .......................................................................................................... 4 Block Diagram .................................................................................................................. 5 Enable/Disable in ABC Mode ........................................................................................... 6 Demodulation Selection in ABC Mode.............................................................................. 6 Programming Modes ........................................................................................................ 6 Preconfigured Frequencies in ABC Mode ........................................................................ 6 2 Functional Description .............................................................................................. 7 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 Frequency Planning.......................................................................................................... 7 Calculation of Counter Settings ........................................................................................ 8 Calculation of LO1 and IF1 frequency for Low Frequency Bands............................................... 8 Calculation of LO1 and IF1 frequency for High Frequency Bands.............................................. 9 Counter Setting Examples for SPI Mode ..................................................................................... 9 Counter Settings in ABC Mode – 8 Preconfigured Channels.................................................... 10 PLL Counter Ranges ................................................................................................................. 11 2.3 2.3.1 2.3.2 2.3.3 SPI Description............................................................................................................... 11 General ...................................................................................................................................... 11 Read / Write Sequences............................................................................................................ 12 Serial Programming Interface Timing ........................................................................................ 12 3 Register Description ................................................................................................ 13 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 3.1.8 Register Overview .......................................................................................................... 13 Control Word R0 ........................................................................................................................ 15 Control Word R1 ........................................................................................................................ 16 Control Word R2 ........................................................................................................................ 17 Control Word R3 ........................................................................................................................ 17 Control Word R4 ........................................................................................................................ 18 Control Word R5 ........................................................................................................................ 18 Control Word R6 ........................................................................................................................ 18 Control Word R7 (Read-only Register)...................................................................................... 19 Y R A IN IM L E R P 4 Application Circuits ................................................................................................. 20 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 Standard FSK & ASK Circuit in SPI Mode...................................................................... 20 Averaging Data Slicer Configured for Bi-Phase Codes............................................................. 20 Component Arrangement Top Side for SPI Mode (Averaging Data Slicer) .............................. 21 Peak Detector Data Slicer Configured for NRZ Codes ............................................................. 22 Component Arrangement Top Side for SPI Mode (Peak Detector Data Slicer)........................ 23 Board Component Values List (SPI mode)................................................................................ 24 39012 71122 01 Rev. 001 Page 2 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 4.2 4.2.1 4.2.2 4.2.3 Standard FSK & ASK circuit in 8-Channel Preconfigured (ABC) Mode.......................... 25 Averaging Data Slicer Configured for Bi-Phase Codes............................................................. 25 Component Arrangement Top Side for ABC Mode (averaging data slicer) .............................. 26 Board Component Values List (ABC mode) .............................................................................. 27 5 6 7 Evaluation Board Layouts ....................................................................................... 28 Board Variants.......................................................................................................... 28 Package Description ................................................................................................ 29 7.1 Soldering Information ..................................................................................................... 29 8 9 10 Reliability Information ............................................................................................. 30 ESD Precautions ...................................................................................................... 30 Disclaimer .................................................................................................................32 Y R A IN IM L E R P 39012 71122 01 Rev. 001 Page 3 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 1 1.1 Theory of Operation General The MLX71122 receiver architecture is based on a double-conversion super-heterodyne approach. The two LO signals are derived from an on-chip integer-N PLL frequency synthesizer. The PLL reference frequency is derived from a crystal (XTAL). The PLL synthesizer consists of an integrated voltage-controlled oscillator with external inductor, a programmable feedback divider chain, a programmable reference divider, a phasefrequency detector with a charge pump and an external loop filter. In the receiver’s down-conversion chain, two mixers MIX1 and MIX2 are driven by the internal local oscillator signals LO1 and LO2, respectively. The second mixer MIX2 is an image-reject mixer. As the first intermediate frequency (IF1) is very high (typically above 100 MHz), a reasonably high degree of image rejection is provided even without using an RF front-end filter. At applications asking for very high image rejections, cost-efficient RF front-end filtering can be realized by using a SAW filter in front of the LNA. The receiver signal chain is setup by a low noise amplifier (LNA), two down-conversion mixers (MIX1 and MIX2), an on-chip IF filter (IFF) as well as an IF amplifier (IFA). By choosing the required modulation via an FSK/ASK switch (at pin MODSEL), either the on-chip FSK demodulator (FSK DEMOD) or the RSSI-based ASK detector is selected. A second order data filter (OA1) and a data slicer (OA2) follow the demodulator. The data slicer threshold can be generated from the mean-value of the data stream or by means of the positive and negative peak detectors (PKDET+/-). In general the MLX71122 can be set to shut-down mode, where all receiver functions are completely turned off, and to several other operating modes. There are two global operating modes that are selectable via the logic level at pin SPISEL: • • 8-channel preconfigured mode (ABC mode) fully programmable mode (SPI mode). In ABC mode the number of frequency channels is limited to eight but no microcontroller programming is required. In this case the three lines of the serial programming interface (SPI) are used to select one of the eight predefined frequency channels via simple 3-bit parallel programming. Pins ENRX and MODSEL are used to enable/disable the receiver and to select FSK or ASK demodulation, respectively. SPI mode is recommended for full programming flexibility. In this case the three lines of the SPI are configured as a standard 3-wire bus (SDEN, SDTA and SCLK). This allows changing many parameters of the receiver, for example more operating modes, channels, frequency resolutions, gains, demodulation types, data slicer settings and more. The pin MODSEL has no effect in this mode. Y R A IN IM L E R P -3 1.2 ! ! ! ! ! ! ! EVB Data Overview ! Total image rejection: > 65dB (with external RF front-end filter) ! FSK/FM deviation range: ±10 to ±50kHz ! Spurious emission: < -70dBm ! Linear RSSI range: > 70dB ! FSK input frequency acceptance range: 170kHz (3dB) ! Crystal reference frequency: 10MHz Input frequency ranges: 300 to 930MHz Power supply range: 3.0 to 5.5V Temperature range: -40 to +105°C Shutdown current: 50nA Operating current: 11mA (typ.) Internal IF2: 2MHz with 230kHz 3dB bandwidth Maximum data rate: 100kbps NRZ code, 50kbps bi-phase code ! Minimum frequency resolution: 10kHz ! Input Sensitivity: at 4 kbps NRZ, BER = 3·10 Frequency FSK: ±20 kHz deviation ASK 315 MHZ -106dBm -108dBm 433 MHz -104dBm -108dBm 868 MHz -101dBm -106dBm 915 MHz -101dBm -106dBm 39012 71122 01 Rev. 001 Page 4 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 1.3 Block Diagram LNAO VEELNA VCCANA RSSI 3 4 8 9 MODSEL DF2 2 VEEIF 6 MIXP 5 MIXN DF1 1 28 200k 29 200k ASK OA1 DFO 27 MIX1 LNAI 31 200k 1M LNA LO1 IF1 MIX2 IF2 IFF IFA FSK SW1 PKDET+ 25 LO2 FSK DEMOD 1M PDP LO2DIV N/A counter VCO LF VCCVCO VEEVCO MFO PKDET_ PDN 26 PFD R counter Control Logic C/SDEN B/SDTA SPISEL A/SCLK SLCSEL SW2 CP RO BIAS VEEANA VCCDIG VEEDIG OA2 DTAO 22 SLC RBIAS 32 11 14 TNK1 12 13 TNK2 15 ENRX ROI LF 23 24 7 17 18 19 10 16 20 21 30 Fig. 1: MLX71122 block diagram The MLX71122 receiver IC consists of the following building blocks: • • • • • • • • • • • • PLL synthesizer (PLL SYNTH) to generate the first and second local oscillator signals LO1 and LO2, parts of the PLL SYNTH are the voltage-controlled oscillator (VCO), the feedback dividers N/A and R, the phase-frequency detector (PFD), the charge pump (CP) and the crystal-based reference oscillator (RO) Low-noise amplifier (LNA) for high-sensitivity RF signal reception First mixer (MIX1) for down-conversion of the RF signal to the first IF (intermediate frequency) Second mixer (MIX2) with image rejection for down-conversion from the first to the second IF IF Filter (IFF) with a 2MHz center frequency and a 230kHz 3dB bandwidth IF amplifier (IFA) to provide a large amount of voltage gain and an RSSI signal output FSK demodulator (FSK DEMOD) Operational amplifiers OA1 and OA2 for low-pass filtering and data slicing, respectively Positive (PKDET+) and negative (PKDET-) peak detectors Switches SW1 to select between FSK and ASK as well as SW2 to chose between averaging or peak detector data slicer Control logic with 3-wire bus serial programming interface (SPI) Biasing circuit with modes control Y R A IN IM L E R P For more detailed information, please refer to the latest MLX71122 data sheet revision. 39012 71122 01 Rev. 001 Page 5 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 1.4 Enable/Disable in ABC Mode ENRX 0 1 Description Shutdown mode Receive mode Pin ENRX is pulled down internally. Device is in shutdown by default, after power supply on. If ENRX = 0 and SPISEL = 1 then operating modes according to OPMODE bit (refer to control word R0). If ENRX = 1 then OPMODE bit has no effect (hardwired receive mode). 1.5 Demodulation Selection in ABC Mode MODSEL 0 1 Description FSK demodulation ASK demodulation Pin MODSEL has no effect in SPI mode (SPISEL = 1). We recommend connecting it to ground to avoid a floating CMOS gate. 1.6 Programming Modes SPISEL 0 1 1.7 Preconfigured Frequencies in ABC Mode A 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 C 0 0 0 0 1 1 1 1 Y R A IN IM L E R P Description ABC mode (8 channels preconfigured) SPI mode (programming via 3-wire bus) Receive Frequency FSK1: 369.5 MHz FSK5: 388.3 MHz FSK2: 371.1 MHz FSK4: 376.9 MHz FSK3: 375.3 MHz FSK7: 394.3 MHz FSK6: 391.5 MHz FSK8: 395.9 MHz As all pins, pins A, B, and C are equipped with ESD protection diodes that are tied to VCC and to VEE. Therefore these pins should not be directly connected to positive supply (a logic “1”) before the supply voltage is applied to the IC. Otherwise the IC will be supplied through these control lines and it may enter into an unpredictable mode. In case the user wants to apply a positive supply voltage to these pins before the supply voltage is applied to the IC, a protection resistor should be inserted in each control line. 39012 71122 01 Rev. 001 Page 6 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 2 2.1 Functional Description Frequency Planning Because of the double conversion architecture that employs two mixers and two IF signals, there are four different combinations for injecting the LO1 and LO2 signals: • • • • LO1 high side and LO2 high side: LO1 high side and LO2 low side: LO1 low side and LO2 high side: LO1 low side and LO2 low side: receiving at fRF(high-high) receiving at fRF(high-low) receiving at fRF(low-high) receiving at fRF(low-low) As a result, four different radio frequencies (RFs) could yield one and the same second IF (IF2). Fig. 2 shows this for the case of receiving at fRF(high-high). In the example of Fig. 2, the image signals at fRF(lowhigh) and fRF(low-low) are suppressed by the bandpass characteristic provided by the RF front-end. The bandpass shape can be achieved either with a SAW filter (featuring just a couple of MHz bandwidth), or by the tank circuits at the LNA input and output (this typically yields 30 to 60MHz bandwidth). In any case, the high value of the first IF (IF1) helps to suppress the image signals at fRF(low-high) and fRF(low-low). The two remaining signals at IF1 resulting from fRF(high-high) and fRF(high-low) are entering the second mixer MIX2. This mixer features image rejection with so-called single-sideband (SSB) selection. This means either the upper or lower sideband of IF1 can be selected. In the example of Fig. 2, LO2 high-side injection has been chosen to select the IF2 signal resulting from fRF(high-high). f RF Fig. 2: Y R A IN IM L E R P f LO2 f LO2 f RF f LO1 f RF f RF The four receiving frequencies in a double conversion superhet receiver It can be seen from the block diagram of Fig. 1 that there is a fixed relationship between the LO1 signal frequency fLO1 and the LO2 signal frequency fLO2. LO2DIV = N LO2 = f LO1 f LO2 (1) The LO1 signal frequency fLO1 is directly synthesized from the crystal reference oscillator frequency fRO by means of an integer-N PLL synthesizer. The PLL consists of a dual-modulus prescaler (P/P+1), a program counter N and a swallow counter A. f LO1 = f RO (N ⋅ P + A) = f PFD (N ⋅ P + A) = f PFD ⋅ N tot R (2) 39012 71122 01 Rev. 001 Page 7 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description Due to the double superhet receiver architecture, the channel frequency step size fCH is not equal to the phase-frequency detector (PFD) frequency fPFD. For high-side injection, the channel step size fCH is given by: f CH = f RO N LO2 − 1 N −1 = f PFD LO2 R N LO2 N LO2 (3) While the following equation is valid for low-side injection: f CH = f RO N LO2 + 1 N +1 = f PFD LO2 R N LO2 N LO2 (4) 2.2 Calculation of Counter Settings Frequency planning and the selection of the MLX71122’s PLL counter settings are straightforward and can be laid out on the following procedure. Usually the receive frequency fRF and the channel step size fCH are given by system requirements. The N and A counter settings can be derived from Ntot or fLO1 and fPFD by using the following equations. N = floor( 2.2.1 Calculation of LO1 and IF1 frequency for Low Frequency Bands High-high injection must be used for the low frequency bands. First of all choose a PFD frequency fPFD according to below table. The R counter values are valid for a 10MHz crystal reference frequency fRO. The PFD frequency is given by fPFD = fRO /R. Injection Type h-h h-h h-h h-h h-h h-h h-h fCH [kHz] 10 20 25 50 12.5 fPFD [kHz] 13.3 26.7 33.3 66.7 16.7 R Y R A IN IM L E R P 750 600 375 300 150 75 30 100 250 133.3 333.3 N tot N ) = floor( tot ) ; A = N tot − N ⋅ P = N tot − N ⋅ 32 P 32 (5) The second step is to calculate the missing parameters fLO1, fIF1, Ntot, N and A. While the second IF (fIF2), the NLO2 divider ratio and the prescaler divider ratio P are bound to fIF2 = 2MHz, NLO2 = 4 (or 8) and P =32. f LO1 = N LO2 (f RF − f IF2 ) N LO2 − 1 f LO1 = 4 (f RF − 2MHz) 3 (6) f IF1 = f RF − N LO2 f IF2 N LO2 − 1 f IF1 = f RF − 8MHz 3 (7) Finally N and A can be calculated with formula (5). 39012 71122 01 Rev. 001 Page 8 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 2.2.2 Calculation of LO1 and IF1 frequency for High Frequency Bands Typical ISM band operating frequencies like 868.3 and 915MHz can be covered without changing the crystal nor the VCO inductor. Low-low injection should be used for the high frequency bands. First of all choose a PFD frequency fPFD according to below table. The R counter values are valid for a 10MHz crystal reference. The PFD frequency is given by fPFD = fRO /R. Injection Type l-l l-l l-l l-l l-l l-l fCH [kHz] 20 25 50 100 250 500 fPFD [kHz] 16 20 40 80 200 400 R 625 500 250 125 50 25 The second step is to calculate the missing parameters fLO1, fIF1, Ntot, N and A. While the second IF (fIF2), the NLO2 divider ratio and the prescaler divider ratio P are bound to fIF2 = 2MHz, NLo2 = 4 (or 8) and P =32. f LO1 = f IF1 = Finally N and A can be calculated with formula (5). 2.2.3 Counter Setting Examples for SPI Mode To provide some examples, the following table shows some counter settings for the reception of the wellknown ISM and SRD frequency bands. The channel spacing is assumed to be fCH = 100kHz. In below table all frequency units are in MHz. Inj h-h h-h h-h h-h l-l l-l l-l l-l fRF 300 315 434 470 850 868 915 930 fIF1 fLO1 Ntot N P A 4 26 0 8 0 20 10 0 fPFD R fREF 10 10 10 10 10 10 10 10 fLO2 fIF2 2 2 2 2 2 2 2 2 Y R A IN IM L E R P f RF + N LO2f IF2 N LO2 + 1 f IF1 = f RF + 8MHz 5 (9) 397.3 417.3 576 624 678.4 692.8 730.4 742.4 2980 3130 4320 4680 8480 8660 9130 9280 93 97 135 146 256 270 285 290 32 32 32 32 32 32 32 32 0.133 0.133 0.133 0.133 0.08 0.08 0.08 0.08 75 75 75 75 125 125 125 125 99.3 104.3 144 156 169.6 173.2 182.6 185.6 N LO2 (f RF − f IF2 ) N LO2 + 1 f LO1 = 4 (f RF − 2MHz) 5 (8) 97.3 102.3 142 154 171.6 175.2 184.6 187.6 39012 71122 01 Rev. 001 Page 9 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 2.2.4 Counter Settings in ABC Mode – 8 Preconfigured Channels In ABC mode (SPISEL=0), the counter settings are hard-wired. In below table all frequency units are in MHz. FSK 1 2 3 4 5 6 7 8 fRF 369.5 371.1 375.3 376.9 388.3 391.5 394.3 395.9 fIF1 120.5 121.0 122.4 123.0 126.8 127.8 128.8 129.3 fLO1 490.0 492.0 497.7 499.9 515.1 519.3 523.1 525.2 Ntot 3675 3691 3733 3749 3863 3895 3923 3939 N 114 115 116 117 120 121 122 123 P 32 32 32 32 32 32 32 32 A 27 11 21 5 23 23 19 3 fPFD 0.133 0.133 0.133 0.133 0.133 0.133 0.133 0.133 R 75 75 75 75 75 75 75 75 fREF 10 10 10 10 10 10 10 10 fLO2 122.5 123.0 124.4 125.0 128.8 129.8 130.8 131.3 fIF2 2 2 2 2 2 2 2 2 List of Mathematical Acronyms A f FB floor (x) f PFD f RO = fR R f RO divider ratio of the swallow counter (part of feedback divider) f VCO N tot = N ⋅ P + A N N LO2 P R Y R A IN IM L E R P frequency at the feedback divider output The floor function gives the largest integer less than or equal to x. For example, floor(5.4) gives 5, floor(-6.3) gives -7. PFD frequency in locked state reference frequency of the PLL frequency of the crystal reference oscillator frequency of the VCO (equals the LO1 signal of the first mixer) total divider ratio of the PLL feedback path divider ratio of the program counter (part of feedback divider) LO2DIV divider ratio, to derive the LO2 signal from LO1 (N1 = 4 or 8) divider ratio of the prescaler (part of feedback divider) divider ratio of the reference divider R 39012 71122 01 Rev. 001 Page 10 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 2.2.5 PLL Counter Ranges In order to cover the frequency range of about 300 to 930MHz the following counter values are implemented in the receiver: PLL Counter Ranges A 0 to 31 (5bit) N 3 to 2047 (11bit) R 3 to 2047 (11bit) P 32 Therefore the minimum and maximum divider ratios of the PLL feedback divider are given by: N totmin = 32 ⋅ 32 = 1024 N totmax = 2047 ⋅ 32 + 31 = 65535 2.3 2.3.1 SPI Description General Serial programming interface (SPI) mode can be activated by choosing SPISEL = 1 (e.g. at positive supply voltage VCC). In this mode, the input pins 17, 18 and 19 are used as a 3-wire unidirectional serial bus interface (SDEN, SDTA, SCLK). The internal latches contain all user programmable variables including counter settings, mode bits etc. In addition the MFO pin can be programmed as an output (see section 4.1.4) in order to read data from the internal latches and it can be used as an output for different test modes as well. At each rising edge of the SCLK signal, the logic value at the SDTA terminal is written into a shift register. The programming information is taken over into internal latches with the rising edge of SDEN. Additional leading bits are ignored, only the last bits are serially clocked into the shift register. A normal write operation shifts 16 bits into the SPI, a normal read operation shifts 4 bits into the SPI and reads additional 12 bits from the MFO pin. If less than 12 data bits are shifted into SDTA during the write operation then the control register may contain invalid information. In general a control word has the following format. Bit 0 is the Read/Write bit that determines whether it is a read (R/W = 1) or a write (R/W = 0) sequence. The R/W bit is preceding the latch address and the corresponding data bits. Y R A IN IM L E R P Control Word Format LSB MSB LSB MSB Bit 0 Data D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Latch Address A2 A2 A0 Mode R/W There are two control word formats for read and for write operation. Data bits are only needed in write mode. Read operations require only a latch address and a R/W bit. Due to the static CMOS design, the serial interface consumes virtually no current. The SPI is a fully separate building block and can therefore be programmed in every operational mode. 39012 71122 01 Rev. 001 Page 11 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 2.3.2 Read / Write Sequences Fig. 6 Typical write sequence diagram 2.3.3 Serial Programming Interface Timing SDEN t CWH Y R A IN IM L E R P Fig. 7 Typical read sequence diagram t CR tEW tEH t CWL t CF t ES t DES t DSO SCLK t CS t CH SDTA MFO Fig. 8 SPI timing diagram 39012 71122 01 Rev. 001 Page 12 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 3 Register Description The following tables are to describe the functionality of the registers. Sec. 4.1 provides a register overview with all the control words R0 to R7. The subsequent sections. 4.1.1 to 4.1.8 show the content of the control words in more detail. Programming the registers requires SPI mode (SPISEL = 1). Default settings are for ABC mode. 3.1 Register Overview DATA LSB 10 9 8 7 6 5 4 3 2 1 0 CONTROL WORD MSB Bit No. 11 LATCH ADDRESS MSB LSB default 1 DTAPOL 0 SLCSEL 1 SSBSEL 1 DEMGAIN 1 IFFGAIN [ 1 :0 ] 0 0 MIX2GAIN 0 MIX1GAIN 1 LNAGAIN [1 : 0 ] 0 0 0 OPMODE [1:0] 0 0 0 R0 Bit No. 11 10 default 1 SHOWLD R1 Bit No. 11 10 default 1 N [6:0] A [4:0] Y R A IN IM L E R P 9 8 7 6 5 4 3 2 1 0 MSB read/ w rite LSB 0 0 0 1 0 1 1 0 1 0 0 0 0 1 VCORANGE PRESCUR VCOCUR LDMODE VCOBUF PFDPOL LDTIME [ 1 :0 ] CPCUR [1:0] LDERR read/ w rite 9 8 7 6 5 4 3 2 1 0 MSB LSB 1 1 0 1 1 1 0 1 1 0 0 0 1 0 R2 Bit No. 11 10 9 read/ w rite 8 7 6 5 4 3 2 1 0 MSB LSB default 0 1 0 MFO [3:0] 0 0 AGCDEL [1:0] 0 0 AGCEN 0 LO2DIV 0 0 0 N [ 10 : 7 ] 0 0 1 1 R3 read/ w rite 39012 71122 01 Rev. 001 Page 13 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description CONTROL WORD MSB Bit No. 11 10 9 8 7 DATA LSB 6 5 4 3 2 1 0 LATCH ADDRESS MSB LSB default 0 AGCMODE 0 0 0 0 1 0 R [ 10 : 0 ] 0 1 0 1 1 1 0 0 R4 Bit No. read/ w rite 11 10 9 8 7 6 5 4 3 2 1 0 MSB LSB default 0 MODSEL 0 1 0 1 0 0 RIFF [ 10 : 0 ] 1 1 0 1 1 1 0 1 R5 Bit No. read/ w rite 11 10 9 8 7 6 5 4 3 2 1 0 MSB LSB default 1 R6 Bit No. 11 10 default RSSIH R7 Note: ∗ depends on bit 11 in R4, 0 = RSSIL, 1 = LD Y R A IN IM L E R P IFFTUNE IFFPRES [7:0] IFFHLT 9 8 7 6 5 4 3 2 1 0 MSB 0 1 0 0 1 1 0 1 1 0 0 1 1 0 ROCUR [ 1 :0 ] read/ w rite LSB 1 1 1 IFFSTATE [ 1 :0 ] LDRSSIL∗ IFFVAL [7:0] readonly 39012 71122 01 Rev. 001 Page 14 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 3.1.1 Control Word R0 Name Bits 00 01 10 11 00 01 10 11 Description operation mode OPMODE [1:0] shutdown receive mode reference oscillator & BIAS only synthesizer only lowest gain low gain high gain highest gain LNA gain (-18dB) (-4dB) (0dB) (+2dB) 1st Mixer gain MIX1GAIN [4] 0 1 0 1 high gain low gain high gain low gain (14dB) (0dB) 2nd Mixer gain MIX2GAIN [5] (9dB) (-2dB) #default #default LNAGAIN [3:2] #default gain values are relative to gain at default #default IFFGAIN [7:6] DEMGAIN [8] SSBSEL [9] Y R A IN IM L E R P intermediate frequency filter gain (-14dB) (-6dB) (0dB) (+6dB) 00 01 10 11 0 1 0 1 lowest gain low gain high gain highest gain low gain high gain demodulator gain (~ 4mV/kHz) (~ 15mV/kHz) single side band selection upper side band lower side band Internal IF2 = 2MHz #default #default LO2 low-side inj. (IF1 = LO2 + IF2) LO2 high-side inj. (IF1 = LO2 – IF2) slicer mode select #default SLCSEL [9] 0 1 0 averaging Data Slicer mode peak detector Data Slicer mode data output polarity OA2 inverted ‘1’ for space at ASK or fmin at FSK, ‘0’ for mark at ASK or fmax at FSK #default DTAPOL [11] 1 normal ‘0’ for space at ASK or fmin at FSK, ‘1’ for mark at ASK or fmax at FSK #default 39012 71122 01 Rev. 001 Page 15 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 3.1.2 Control Word R1 Name Bits 00 01 10 11 0 1 0 1 00 01 10 11 100µA 400µA 400µA static down 400µA static up PFD output polarity PFDPOL [2] negative positive lock detector time error LDERR [3] 15ns 30ns lock detection time 2/fR 4/fR 8/fR 16/fR minimum time span before lock in fR is the reference oscillator frequency fRO divided by R, see section 4.1.5 (R4) Description charge pump current setting #default CPCUR [1:0] #default #default LDTIME [5:4] #default LDMODE [6] VCORANGE [7] VCOCUR [8] VCOBUF [9] Y R A IN IM L E R P lock detector mode 0 1 0 1 check lock condition permanently check lock condition until 1st lock in VCO range 3V supply 5V supply VCO range setting for different VCCs. #default #default VCO core current 0 1 0 1 0 1 450µA 520µA #default VCO buffer current 900µA 1040µA 20µA 30µA #default prescaler 32/33 reference current PRESCUR [10] #default 30µA may be used for fRF = 868/915MHz function of LDRSSIL bit SHOWLD [11] 0 1 RSSIL (RSSI low flag) LD (lock detection flag) select output data of LDRSSIL, see section 4.1.8 (R7) #default 39012 71122 01 Rev. 001 Page 16 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 3.1.3 Control Word R2 Name A Bits [4:0] 01100 value is 12 swallow counter range: 0 to 31 Description swallow counter value #default program counter value (bits 0 – 6) N [11:5] 000 0111 0111 N value is 119 N counter range: 3 to 2047 #default 3.1.4 Control Word R3 program counter range (bits 7 – 10) N [3:0] 000 0111 0111 N value is 119 N counter range: 3 to 2047 #default LO2 divider ratio LO2DIV [4] AGCEN [5] AGCDEL [7:6] MFO [11:8] Y R A IN IM L E R P AGC enable mode 0 1 disabled enabled no delay 3/fIFF 15/fIFF 31/fIFF AGC delay settings 00 01 10 11 multi functional output 0000 0001 0010 0011 0100 0101 1000 MFO is in Z state MFO is SPI read-out MFO = 0 MFO = 1 MFO is analog RO output MFO is IFF output MFO is lock detector output 0 1 divide by 4 divide by 8 #default #default #default fIFF is the reference oscillator frequency fRO divided by RIFF, see section 4.1.6 (R6) #default 39012 71122 01 Rev. 001 Page 17 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 3.1.5 Control Word R4 Name R Bits [10:0] 000 0100 1011 value is 75 R counter range: 3 to 2047 Description reference divider range #default AGC delay mode AGCMODE [11] 0 1 gain decrease and increase with delay gain decrease without delay, gain increase with delay #default selects AGC delay mode in combination with AGCDEL bits, see section 4.1.4 (R3) 3.1.6 Control Word R5 Name RIFF Bits [10:0] 010 1001 1011 value is 667 IFF counter range: 4 to 2047 Description reference divider value for IFF adjustment #default MODSEL [11] 3.1.7 Control Word R6 Name Bits IFFPRES [7:0] Y R A IN IM L E R P demodulation selection 0 1 FSK demodulation ASK demodulation selects modulation type when chip is controlled via SPI mode #default Description IFF preset value 0110 1100 value is 108 #default IFF DAC preset at start of automatic tuning IFF halt IFFHLT [8] 0 1 auto tuning running auto tuning halted suspends IFF automatic tuning #default IFF tuning IFFTUNE [9] 0 1 00 01 10 11 disable and load DAC with IFFPRES enable reference Oscillator core current ROCUR [11:10] 85µA 170µA 270µA 355µA #default #default 39012 71122 01 Rev. 001 Page 18 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 3.1.8 Control Word R7 (Read-only Register) Name IFFVAL Bits [7:0] see also IFFPRES in section 4.1.7 (R6) Description IFF adjustment value IFF automatic tuning state IFFSTATE [9:8] 00 01 10 11 0 1 filter tuned or auto-tuning disabled tuning up the filter frequency tuning down the filter frequency master oscillator of filter deactivated lock detector or RSSI low flag LDRSSIL [10] PLL not locked or RSSI value in lower region PLL locked or RSSI value above lower region RSSI high flag RSSIH [11] 0 1 RSSI value below upper region RSSI value in upper region depends on SHOWLD in section 4.1.2 (R1) Y R A IN IM L E R P 39012 71122 01 Rev. 001 Page 19 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 4 4.1 4.1.1 Application Circuits Standard FSK & ASK Circuit in SPI Mode Averaging Data Slicer Configured for Bi-Phase Codes MFO DFO 12345 DTAO VCC RS1 123 12 CB3 RB0 XTAL CX VCCDIG 21 ROI 24 MFO 23 DTAO 22 VEEDIG 20 RS2 MFO GND SCLK SDTA SDEN A/SCLK 19 B/SDTA 18 L1 C1 50 Y R A IN IM L E R P 25 PDP ENRX 16 C/SDEN 17 RS3 CF2 26 PDN LF 15 27 DFO 28 DF1 29 DF2 VCCVCO 14 TNK2 13 TNK1 12 RF CF1 C8 C9 MLX71122 L0 CB2 30 VEEANA 31 LNAI VEEVCO 11 VEELNA VCCANA VEEIF LNAO MIXN MIXP RSSI 32 SLC SPISEL 1 3 SAWFIL 4 6 L2 RBS RSSI C2 RBIAS 10 9 MODSEL GND VCC 12 C10 1 2 3 4 5 6 7 8 12 L3 C5 C6 C4 C7 CB0 CB1 Fig. 6: Application circuit for SPI Mode (averaging data slicer option) Note • EVB71122 default population is SPI mode 39012 71122 01 Rev. 001 Page 20 of 32 VCC EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 4.1.2 Component Arrangement Top Side for SPI Mode (Averaging Data Slicer) Board size is 49mm x 35.6mm DFO GND MFO GND DTAO Melexis 1 1 GND VCC 1 MFO A RS1 GND SCLK SDTA SDEN 3 XTAL B RS2 RB0 1 C RS3 CX RF_input RF_input EVB71122_002 Y R A IN IM L E R P C1 RF C8 CF2 CF1 L1 L0 CB2 CB3 ENRX RBS 0 MODSEL FSK/ASK C10 L3 C5 C6 C2 C7 L2 1 C4 CB0 VCC 0 CB1 1 GND GND RSSI SPI mode selected 39012 71122 01 Rev. 001 Page 21 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 4.1.3 Peak Detector Data Slicer Configured for NRZ Codes MFO DFO 12345 DTAO VCC RS1 123 12 CB3 RB0 XTAL CX VCCDIG 21 ROI 24 MFO 23 DTAO 22 VEEDIG 20 RS2 MFO GND SCLK SDTA SDEN A/SCLK 19 B/SDTA 18 L1 C1 50 Y R A IN IM L E R P C12 26 PDN LF 15 27 DFO 28 DF1 29 DF2 VCCVCO 14 TNK2 13 TNK1 12 C11 25 PDP C/SDEN 17 ENRX 16 RS3 CF2 RF CF1 C8 C9 MLX71122 L0 CB2 30 VEEANA 31 LNAI SLC VEEVCO 11 VEELNA VCCANA VEEIF SPISEL 1 3 SAWFIL 4 6 L2 RBS RSSI C2 RBIAS 10 9 LNAO MIXN MIXP MODSEL RSSI GND VCC 12 1 2 3 4 5 6 7 8 12 L3 C5 C6 C4 C7 CB0 CB1 Fig. 7: Application circuit for SPI Mode (peak detector option) Note • EVB71122 default population is SPI mode 39012 71122 01 Rev. 001 Page 22 of 32 VCC EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 4.1.4 Component Arrangement Top Side for SPI Mode (Peak Detector Data Slicer) Board size is 49mm x 35.6mm DFO GND MFO GND DTAO Melexis 1 1 GND VCC 1 MFO A RS1 GND SCLK SDTA SDEN 3 XTAL B RS2 RB0 1 C RS3 CX RF_input RF_input EVB71122_002 Y R A IN IM L E R P C11 C1 C12 RF C8 CF2 CF1 L1 L0 CB2 CB3 ENRX RBS 0 MODSEL FSK/ASK L3 C6 C2 C5 C7 L2 1 C4 CB0 VCC 0 CB1 1 GND GND RSSI SPI mode selected 39012 71122 01 Rev. 001 Page 23 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 4.1.5 Board Component Values List (SPI mode) Below table is for all application circuits show in Figures 6 and 7 Part C1 C2 C4 C5 C6 C7 Size 0603 0603 0603 0603 0603 0603 Value @ 315 MHz NIP NIP 4.7 pF 100 pF 100 pF 1 nF Value @ 433.9 MHz NIP NIP 3.3 pF 100 pF 100 pF 1 nF Value @ 868.3 MHz 3.3 pF NIP 2.7 pF 100 pF 100 pF 1 nF Value @ 915 MHz NIP NIP 2.2 pF 100 pF 100 pF 1 nF Tol. ±5% ±5% ±5% ±5% ±5% ±10% Description matching capacitor matching capacitor LNA output tank capacitor MIX1 negative input matching capacitor MIX1 negative input matching capacitor RSSI output low pass capacitor, this value for data rates 4 kbps NRZ data low-pass filter capacitor, this value for data rates 4 kbps NRZ data low-pass filter capacitor, this value for data rates 4 kbps NRZ data slicer capacitor peak detector positive filtering capacitor peak detector negative filtering capacitor C8 0603 330 pF 330 pF 330 pF 330 pF ±10% C9 C10 C11 C12 0603 0603 0603 0603 150 pF 33 nF 33 nF 33 nF 150 pF 33 nF 33 nF 33 nF 150 pF 33 nF 33 nF 33 nF 150 pF 33 nF 33 nF 33 nF ±10% ±10% ±10% ±10% not required in Figure 7 not required in Figures 6 not required in Figures 6 10 μF 10 μF CB0 CB1 CB2 CB3 CF1 CF2 CX RB0 RF RBS RS1…RS3 L0 L1 L2 L3 XTAL SAW FIL 1210 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 SMD 5x3.2 SMD 3x3 10 μF 470 pF 33 nF 33 nF 2.2 nF 27 pF 10 Ω 220 pF 27 kΩ 30 kΩ 10 kΩ 33 nH 0Ω 82 nH 33 nH Y R A IN IM L E R P 10 μF ±10% 470 pF 33 nF 33 nF 470 pF 33 nF 33 nF 470 pF 33 nF 33 nF ±10% ±10% ±10% ±5% ±5% decoupling capacitor decoupling capacitor decoupling capacitor loop filter capacitor loop filter capacitor protection resistor 2.2 nF 27 pF 10 Ω 2.2 nF 27 pF 10 Ω 2.2 nF 27 pF 10 Ω 220 pF 220 pF 220 pF ±5% crystal series capacitor ±5% 27 k Ω 47 k Ω 47 k Ω ±5% loop filter resistor 30 k Ω 30 k Ω 30 k Ω ±2% reference bias resistor VCO tank inductor matching inductor matching inductor LNA output tank inductor 10 k Ω 10 k Ω 10 k Ω 0Ω 8.2 nH 5.6 nH ±5% protection resistor 15 nH 56 nH 82 nH 22 nH 8.2 nH 22 nH 22 nH 5.6 nH 8.2 nH ±5% ±5% ±5% ±5% 10.00000 MHz / ±20ppm cal., ±30ppm temp. SAFCC433MB L0X00 (433.92 MHz) SAFCC868MS SAFCH915MA L0N00 L0X00 (915 MHz) (868.3 MHz) decoupling capacitor, low-noise power supply recommended fundamental-mode crystal low-loss SAW filter from Murata or equivalent part SAFDC315MS M0T00 (315 MHz) Note: - NIP – not in place, may be used optionally 39012 71122 01 Rev. 001 Page 24 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 4.2 4.2.1 Standard FSK & ASK circuit in 8-Channel Preconfigured (ABC) Mode Averaging Data Slicer Configured for Bi-Phase Codes DFO 12 DTAO VCC 12 3 A VCC 12 12 3 B CB3 RB0 XTAL CX MFO 23 VCCDIG 21 DTAO 22 VEEDIG 20 ROI 24 C/SDEN 17 A/SCLK 19 B/SDTA 18 12 3 C ENRX 12 3 C1 Y R A IN IM L E R P 25 PDP ENRX 16 CF2 MODSEL 12 3 26 PDN LF 15 27 DFO 28 DF1 29 DF2 VCCVCO 14 TNK2 13 TNK1 12 RF CF1 C8 C9 MLX71122 L0 CB2 L1 30 VEEANA 31 LNAI VEEVCO 11 C3 RBS RBIAS 10 9 VEELNA VCCANA LNAO VEEIF MIXN MIXP 50 RSSI C2 32 SLC SPISEL MODSEL RSSI GND VCC 12 C10 1 2 3 4 5 6 7 8 12 L3 C5 C6 C4 C7 CB0 CB1 Fig. 8: Application circuit for ABC Mode Note • ABC mode population can be easily modified from default SPI mode population by changing the connection at SPISEL from VCC to ground. 39012 71122 01 Rev. 001 Page 25 of 32 VCC EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 4.2.2 Component Arrangement Top Side for ABC Mode (averaging data slicer) Board size is 49mm x 35.6mm DFO GND MFO GND DTAO Melexis 1 1 GND 1 VCC 1 MFO A B SDTA C SDEN GND SCLK 3 XTAL 1 RB0 1 1 CX RF_input RF_input EVB71122_002 Y R A IN IM L E R P C1 CF2 C8 CF1 L1 C2 RF CB3 1 ENRX L0 CB2 RBS 1 MODSEL 0 FSK/ASK C10 C5 C6 C7 C3 L3 0 1 C4 CB0 VCC CB1 1 GND GND RSSI ABC mode selected 39012 71122 01 Rev. 001 Page 26 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 4.2.3 Board Component Values List (ABC mode) Below table is for all application circuits show in Figures 8 Part C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 CB0 CB1 CB2 CB3 CF1 CF2 CX RB0 RF RBS RS1…RS3 L0 L1 L3 XTAL Size 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 1210 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 SMD 5x3.2 Value @ 369 MHz to 396 MHz NIP NIP 100 pF 3.3 pF 100 pF 100 pF 1 nF 330 pF 150 pF 33 nF 10 μF 470 pF 33 nF 33 nF Tol. ±5% ±5% ±5% ±5% ±5% ±5% ±10% ±10% ±10% ±10% ±10% ±10% ±10% ±10% ±5% ±5% Description matching capacitor matching capacitor LNA input filtering capacitor LNA output tank capacitor MIX1 negative input matching capacitor MIX1 negative input matching capacitor RSSI output low pass capacitor, this value for data rates 4 kbps NRZ data low-pass filter capacitor, this value for data rates 4 kbps NRZ data low-pass filter capacitor, this value for data rates 4 kbps NRZ data slicer capacitor decoupling capacitor, low-noise power supply recommended decoupling capacitor decoupling capacitor decoupling capacitor loop filter capacitor loop filter capacitor Note: - NIP – not in place, may be used optionally Y R A IN IM L E R P 2.2 nF 27 pF 10 Ω 220 pF ±5% crystal series capacitor loop filter resistor ±5% protection resistor 27 kΩ ±5% 30 kΩ ±2% reference bias resistor 10 kΩ ±5% protection resistor 18 nH 27 nH ±5% ±5% ±5% VCO tank inductor matching inductor 39 nH LNA output tank inductor 10.00000 MHz / ±20ppm cal., ±30ppm temp. fundamental-mode crystal 39012 71122 01 Rev. 001 Page 27 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 5 Evaluation Board Layouts • Board layout data in Gerber format is available, board size is 35.6mm x 49mm. MODSEL SDEN SCLK SDTA MFO GND ENRX A B VCC C FSK/ASK GND VCC DFO GND MFO GND DTAO PCB top view 6 Board Variants Type EVB71122 C A B Y R A IN IM L E R P EVB71122_002 Melexis GND RSSI GND PCB bottom view Regional Code world wide Europe, Asia Frequency/MHz –315 –433 –915 Modulation –FSK –ASK –FM –A –C Board Execution antenna version connector version USA, Canada –868 Note: possible combinations 39012 71122 01 Rev. 001 Page 28 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 7 Package Description • The device MLX71122 is RoHS compliant. D 24 25 17 A3 16 E 32 9 8 b A1 A 1 e Y R A IN IM L E R P exp osed pad E2 L D2 The “exposed pad” is not connected to internal ground, it should not be connected to the PCB. Fig 12: 32L QFN 5x5 Quad all Dimension in mm D min max min max 4.75 5.25 0.187 0.207 E 4.75 5.25 0.187 0.207 D2 3.00 3.25 0.118 0.128 E2 3.00 3.25 0.118 0.128 A 0.80 1.00 0.0315 0.0393 A1 0 0.05 0 0.002 A3 0.20 L 0.3 0.5 0.0118 0.0197 e 0.50 b 0.18 0.30 0.0071 0.0118 all Dimension in inch 0.0079 0.0197 7.1 Soldering Information • The device MLX71122 is qualified for MSL3 with soldering peak temperature 260 deg C according to JEDEC J-STD-20 39012 71122 01 Rev. 001 Page 29 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 8 Reliability Information This Melexis device is classified and qualified regarding soldering technology, solderability and moisture sensitivity level, as defined in this specification, according to following test methods: Reflow Soldering SMD’s (Surface Mount Devices) IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices (classification reflow profiles according to table 5-2)” EIA/JEDEC JESD22-A113 “Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing (reflow profiles according to table 2)” Wave Soldering SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices) EN60749-20 “Resistance of plastic- encapsulated SMD’s to combined effect of moisture and soldering heat” EIA/JEDEC JESD22-B106 and EN60749-15 “Resistance to soldering temperature for through-hole mounted devices” Iron Soldering THD’s (Through Hole Devices) EN60749-15 “Resistance to soldering temperature for through-hole mounted devices” Solderability SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices) EIA/JEDEC JESD22-B102 and EN60749-21 “Solderability” For all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature, temperature gradient, temperature profile etc) additional classification and qualification tests have to be agreed upon with Melexis. The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of adhesive strength between device and board. Melexis is contributing to global environmental conservation by promoting lead free solutions. For more information on qualification of RoHS compliant products (RoHS = European directive on the Restriction Of the Use of Certain Hazardous Substances) please visit the quality page on our website: http://www.melexis.com/quality_leadfree.aspx Y R A IN IM L E R P 9 ESD Precautions Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static Discharge control procedures whenever handling semiconductor products. 39012 71122 01 Rev. 001 Page 30 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description Your Notes Y R A IN IM L E R P 39012 71122 01 Rev. 001 Page 31 of 32 EVB Description Sept/06 EVB71122 300 to 930MHz Receiver Evaluation Board Description 10 Disclaimer Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Melexis reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Melexis for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Melexis for each application. The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis’ rendering of technical or other services. © 2006 Melexis NV. All rights reserved. Y R A IN IM L E R P For the latest version of this document, go to our website at: www.melexis.com Or for additional information contact Melexis Direct: Europe and Japan: Phone: +32 1367 0495 E-mail: sales_europe@melexis.com All other locations: Phone: +1 603 223 2362 E-mail: sales_usa@melexis.com ISO/TS 16949 and ISO14001 Certified 39012 71122 01 Rev. 001 Page 32 of 32 EVB Description Sept/06