KSZ8842-PMBL

KSZ8842-PMQL/PMBL 2-Port Ethernet Switch with PCI Interface Rev.1.5 General Description The KSZ8842-series of 2-port switches includes PCI and non-PCI CPU interfaces. This datasheet describes the KSZ8842-PMQL/PMBL PCI CPU interface chips. KSZ8842-PMQL is PQFP package chip, KSZ8842-PMBL is LFBGA package chip. For information on the KSZ8842-MQL/MBL CPU non-PCI interface switches, refer to the KSZ8842-MQL/MBL datasheet. The KSZ8842-PMQL/PMBL is the industry’s first fully managed 2-port switch with a 32 bit/33MHz PCI processor interface. It is a proven, 4th generation, integrated Layer 2 switch that is compliant with the IEEE 802.3u standard. An industrial temperature grade version of the KSZ8842-PMQL/PMBL, also can be ordered the KSZ8842-PMQLI/PMBL AM. The KSZ8842-PMQL/PMBL can be configured as a switch or as a low-latency ( 1 = Loop back at PMD/PMA of port 2’s PHY End: TXP2/TXM2 (port 2) 0 = normal operation. VCT fault count Distance to the fault. It’s approximately 0.4m*vct_fault_count KSZ8842-PMQL/PMBL Is the same as: P2VCT, bit 12 P2VCT, bits 14-13 12 0 RW SC (selfclear) RW P2VCT, bit 15 11 0 P2PHYCTRL, bit 3 P2PHYCTRL, bit 2 P2PHYCTRL, bit 1 10 1 RW 9 0 RW 8–0 0 RO P2VCT, bits 8-0 Port 2 Control Register 4 (Offset 0x0532): P2CR4 This register contains the global per port control for the switch port 2 function. Bit 15 Default 0 R/W RW Description LED off 1 = Turn off all port 2’s LEDs (LED2_3, LED2_2, LED2_1, LED2_0. These pin/balls will be driven high if this bit is set to one. 0 = normal operation Txids 1 = disable port’s transmitter 0 = normal operation Restart AN 1 = restart auto-negotiation 0 = normal operation Disable Far end fault 1 = disable far end fault detection & pattern transmission. 0 = enable far end fault detection & pattern transmission. Is the same as: P2MBCR, bit 0 14 0 RW P2MBCR, bit 1 13 0 RW P2MBCR, bit 9 12 0 RW P2MBCR, bit 2 October 2007 92 M9999-100207-1.5 Micrel, Inc. Bit 11 Default 0 R/W RW Description Power down 1 = power down 0 = normal operation Disable auto MDI/MDIX 1 = disable auto MDI/MDIX function 0 = enable auto MDI/MDIX function Force MDIX 1 = If auto MDI/MDIX is disabled, force PHY into MDIX mode 0 = Do not force PHY into MDIX mode Loop back 1 = perform loop back, as indicated: Start: RXP1/RXM1 (port 1) Loop back: PMD/PMA of port 2’s PHY End: TXP1/TXM1 (port 1) 0 = normal operation Auto Negotiation Enable 0 = disable auto negotiation, speed and duplex are decided by bit 6 and 5 of the same register. 1 = auto negotiation is ON Force Speed 1 = force 100Base-T if AN is disabled (bit 7) 0 = force 10Base-T if AN is disabled (bit 7) Force duplex 1 = force full duplex if (1) AN is disabled or (2) AN is enabled but failed. 0 = force half duplex if (1) AN is disabled or (2) AN is enabled but failed. Advertised flow control capability 1 = advertise flow control (pause) capability 0 = suppress flow control (pause) capability from transmission to link partner Advertised 100BT Full duplex capability 1 = advertise 100Base-T Full duplex capability 0 = suppress 100Base-T Full duplex capability from transmission to link partner Advertised 100BT half duplex capability 1 = advertise 100Base-T Half duplex capability 0 = suppress 100Base-T Half duplex capability from transmission to link partner Advertised 10BT Full duplex capability 1 = advertise 10Base-T Full duplex capability 0 = suppress 10Base-T Full duplex capability from transmission to link partner Advertised 10BT half duplex capability 1 = advertise 10Base-T Half duplex capability 0 = suppress 10Base-T Half duplex capability from transmission to link partner KSZ8842-PMQL/PMBL Is the same as: P2MBCR, bit 11 10 0 RW P2MBCR, bit 3 9 0 RW P2MBCR, bit 4 8 0 RW P2MBCR, bit 14 7 1 RW P2MBCR, bit 12 6 0 RW P2MBCR, bit 13 5 0 RW P2MBCR, bit 9 4 1 RW P1ANAR, bit 4 3 1 RW P1ANAR, bit 3 2 1 RW P1ANAR, bit 2 1 1 RW P1ANAR, bit 1 0 1 RW P1ANAR, bit 0 October 2007 93 M9999-100207-1.5 Micrel, Inc. Port 2 Status Register (Offset 0x0534): P2SR This register contains the global per port status for the switch port 2 function. Bit 15 Default 0 R/W RW Description HP_mdix 1 = HP Auto MDIX mode 0 = Micrel Auto MDIX mode Reserved Polarity reverse 1 = polarity is reversed 0 = polarity is not reversed Receive flow control enable 1 = Receive flow control feature is active 0 = Receive flow control feature is inactive Transmit flow control enable 1 = transmit flow control feature is active 0 = transmit flow control feature is inactive Operation Speed 1 = link speed is 100Mbps 0 = link speed is 10Mbps Operation duplex 1 = link duplex is full 0 = link duplex is half Far end fault 1 = Far end fault status detected 0 = no Far end fault status detected MDIX status 1 = MDIX 0 = MDI AN done 1 = AN done 0 = AN not done Link good 1 = Link good 0 = Link not good Partner flow control capability 1 = link partner flow control (pause) capable 0 = link partner not flow control (pause) capable Partner 100BT full duplex capability 1 = link partner 100Base-T full duplex capable 0 = link partner not 100Base-T full duplex capable Partner 100BT half duplex capability 1 = link partner 100Base-T half duplex capable 0 = link partner not 100Base-T half duplex capable Partner 10BT full duplex capability 1 = link partner 10Base-T full duplex capable 0 = link partner not 10Base-T full duplex capable KSZ8842-PMQL/PMBL Is the same as: P2MBCR, bit 5 14 13 0 0 RO RO P2PHYCTRL, bit 5 12 0 RO 11 0 RO 10 0 RO 9 0 RO 8 0 RO P2MBCR, bit 4 7 0 RO P2PHYCTRL, bit 4 P2MBSR, bit 5 6 0 RO 5 0 RO P2MBSR, bit 2 4 0 RO P2ANLPR, bit 10 3 0 RO P2ANLPR, bit 8 2 0 RO P2ANLPR, bit 7 1 0 RO P2ANLPR, bit 6 October 2007 94 M9999-100207-1.5 Micrel, Inc. Bit 0 Default 0 R/W RO Description Partner 10BT half duplex capability 1 = link partner 10Base-T half duplex capable 0 = link partner not 10Base-T half duplex capable KSZ8842-PMQL/PMBL Is the same as: P2ANLPR, bit 5 Port 2 Reserved (Offset 0x0536 – 0x053A) This register is reserved. Bit 15 – 0 Default 0x0000 R/W RO Description Reserved Host Control Register 1 (Offset 0x0540): P3CR1 This register contains the global per port control for the switch host port function. Bit 15 – 8 7 Default 0x00 0 R/W RO RW Description Reserved Broadcast storm protection enable 1 = enable broadcast storm protection for ingress packets on the port 0 = disable broadcast storm protection Diffserv priority classification enable 1 = enable diffserv priority classification for ingress packets on port 0 = disable diffserv function 802.1p priority classification enable 1 = enable 802.1p priority classification for ingress packets on port 0 = disable 802.1p Port based priority classification 00 = ingress packets on port 1 will be classified as priority 0 queue if “Diffserv” or “802.1p” classification is not enabled or fails to classify. 01 = ingress packets on port 1 will be classified as priority 1 queue if “Diffserv” or “802.1p” classification is not enabled or fails to classify. 10 = ingress packets on port 1 will be classified as priority 2 queue if “Diffserv” or “802.1p” classification is not enabled or fails to classify. 11 = ingress packets on port 1 will be classified as priority 3 queue if “Diffserv” or “802.1p” classification is not enabled or fails to classify. Note: “Diffserv”, “802.1p” and port priority can be enabled at the same time. The OR’ed result of 802.1p and DSCP overwrites the port priority. 2 0 RW Tag insertion 1 = when packets are output on the port, the switch will add 802.1p/q tags to packets without 802.1p/q tags when received. The switch will not add tags to packets already tagged. The tag inserted is the ingress port’s “port VID”. 0 = disable tag insertion Tag removal 1 = when packets are output on the port, the switch will remove 802.1p/q tags from packets with 802.1p/q tags when received. The switch will not modify packets received without tags. 0 = disable tag removal TX Multiple Queues Select Enable 1 = the port output queue is split into fourpriority queues. 0 = single output queue on the port. There is no priority differentiation even though packets are classified into high or low priority. 6 0 RW 5 0 RW 4–3 00 RW 1 0 RW 0 0 RW October 2007 95 M9999-100207-1.5 Micrel, Inc. Host Control Register 2 (Offset 0x0542): P3CR2 This register contains the global per port control for the switch host port function. Bit 15 14 Default 0 0 R/W RW RW Description reserved KSZ8842-PMQL/PMBL Ingress VLAN filtering 1 = the switch will discard packets whose VID port membership in VLAN table bits [18:16] does not include the ingress port. 0 = no ingress VLAN filtering. Discard Non PVID packets 1 = the switch will discard packets whose VID does not match ingress port default VID. 0 = no packets will be discarded. Reserved. For factory testing purpose only. Always write 0. Reserved Must be 0 Transmit enable 1 = enable packet transmission on the port 0 = disable packet transmission on the port Receive enable 1 = enable packet reception on the port 0 = disable packet reception on the port Learning disable 1 = disable switch address learning capability 0 = enable switch address learning Sniffer port 1 = Port is designated as sniffer port and will transmit packets that are monitored. 0 = Port is a normal port Receive sniff 1 = All the packets received on the port will be marked as “monitored packets” and forwarded to the designated “sniffer port” 0 = no receive monitoring Transmit sniff 1 = All the packets transmitted on the port will be marked as “monitored packets” and forwarded to the designated “sniffer port” 0 = no transmit monitoring Reserved User Priority Field 1 = if the packet’s “user priority field” is greater than the “user priority bits” in host’s VID Control register bits [15:13], replace the packet’s “user priority field” with the “user priority bits” in host’s VID Control register bits [15:13]. 0 = do not compare and replace the packet’s ‘user priority field” Port VLAN membership Define the port’s Port VLAN membership. Bit 2 stands for host port, bit 1 for port 2, and bit 0 for port 1. The Port can only communicate within the membership. An ‘1’ includes a port in the membership; an ‘0’ excludes a port from the membership. 13 0 RW 12 11 10 0 0 1 RW RW RW 9 1 RW 8 0 RW 7 0 RW 6 0 RW 5 0 RW 4 3 0 0 RW R/W 2–0 111 RW October 2007 96 M9999-100207-1.5 Micrel, Inc. Host VID Control Register (Offset 0x0544): P3VIDCR This register contains the global per port control for the switch host port function. Bit 15-13 12 11-0 Default 000 0 0x001 R/W RW RW RW Description User Priority bits Host Port default tag bits [15-13] for user priority CFI bit Host Port default tag bit 12 for CFI VID bits Host Port default tag bits [11-0] for VID KSZ8842-PMQL/PMBL Note: P3VIDCR serve two purposes: (1) Associated with the ingress untagged packets, and used for egress tagging. (2) Default VID for the ingress untagged or null-VID-tagged packets, and used for address look up. Host Control Register 3 (Offset 0x0546): P3CR3 This register contains the host port control register for the switch host port function. Bit 15 – 5 4 3-2 Default 000 0 00 Name Reserved Reserved 0 RW Ingress Limit Mode These bits determine what kinds of frames are limited and counted against Ingress limiting as follows: 00 = Limit and count all frames 01 = Limit and count Broadcast, Multicast, and flooded unicast frames 10 = Limit and count Broadcast and Multicast frames only 11 = Limit and count Broadcast frames only Count IFG bytes 1 = each frame’s minimum inter frame gap (IFG) bytes (12 per frame) are included in Ingress and Egress rate limiting calculations. 0 = IFG bytes are not counted Count Preamble bytes 1 = each frame’s preamble bytes (8 per frame) are included in Ingress and Egress rate limiting calculations. 0 = preamble bytes are not counted R/W RO Description Reserved 1 0 0 RW 0 0 0 RW October 2007 97 M9999-100207-1.5 Micrel, Inc. Host Ingress Rate Control Register (Offset 0x0548): P3IRCR This register contains the host port ingress rate control register for the switch host port function. Bit 15 – 12 Default 0x0 Name 0 R/W RW Description KSZ8842-PMQL/PMBL Ingress Pri3 Rate Priority 3 frames will be discarded after the ingress rate selected as shown below, is reached or exceeded: 0000 = Not limited (Default) 0001 = 64 Kbps 0010 = 128 Kbps 0011 = 256 Kbps 0100 = 512 Kbps 0101 = 1 Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 1100 = 64 Mbps 1101 = 72 Mbps 1110 = 80 Mbps 1111 = 88 Mbps Note: For 10Base-T, rate settings above 10Mbps are set to the default value 0000 (Not limited). 11 – 8 0x0 0 RW Ingress Pri2 Rate Priority 2 frames will be discarded after the ingress rate selected as shown below, is reached or exceeded: 0000 = Not limited (Default) 0001 = 64 Kbps 0010 = 128 Kbps 0011 = 256 Kbps 0100 = 512 Kbps 0101 = 1 Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 1100 = 64 Mbps 1101 = 72 Mbps 1110 = 80 Mbps 1111 = 88 Mbps Note: For 10Base-T, rate settings above 10Mbps are set to the default value 0000 (Not limited). October 2007 98 M9999-100207-1.5 Micrel, Inc. Bit 7–4 Default 0x0 Name 0 R/W RW Description KSZ8842-PMQL/PMBL Ingress Pri1 Rate Priority 1 frames will be discarded after the ingress rate selected as shown below, is reached or exceeded: 0000 = Not limited (Default) 0001 = 64 Kbps 0010 = 128 Kbps 0011 = 256 Kbps 0100 = 512 Kbps 0101 = 1 Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 1100 = 64 Mbps 1101 = 72 Mbps 1110 = 80 Mbps 1111 = 88 Mbps Note: For 10Base-T, rate settings above 10Mbps are set to the default value 0000 (Not limited). 3–0 0x0 0 RW Ingress Pri0 Rate Priority 0 frames will be discarded after the ingress rate selected as shown below, is reached or exceeded: 0000 = Not limited (Default) 0001 = 64 Kbps 0010 = 128 Kbps 0011 = 256 Kbps 0100 = 512 Kbps 0101 = 1 Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 1100 = 64 Mbps 1101 = 72 Mbps 1110 = 80 Mbps 1111 = 88 Mbps Note: For 10Base-T, rate settings above 10Mbps are set to the default value 0000 (Not limited). October 2007 99 M9999-100207-1.5 Micrel, Inc. Host Egress Rate Control Register (Offset 0x054A): P3ERCR This register contains the host port egress rate control register for the switch host port function. Bit 15 – 12 Default 0x0 Name 0 R/W RW Description KSZ8842-PMQL/PMBL Egress Pri3 Rate Egress data rate limit for priority 3 frames. Output traffic from this priority queue is shaped according to the egress rate selected as shown below: 0000 = Not limited (Default) 0001 = 64 Kbps 0010 = 128 Kbps 0011 = 256 Kbps 0100 = 512 Kbps 0101 = 1 Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 1100 = 64 Mbps 1101 = 72 Mbps 1110 = 80 Mbps 1111 = 88 Mbps Note: For 10Base-T, rate settings above 10Mbps are set to the default value 0000 (Not limited). Note: When multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. 11 – 8 0x0 0 RW Egress Pri2 Rate Egress data rate limit for priority 2 frames. Output traffic from this priority queue is shaped according to the egress rate selected as shown below: 0000 = Not limited (Default) 0001 = 64 Kbps 0010 = 128 Kbps 0011 = 256 Kbps 0100 = 512 Kbps 0101 = 1 Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 1100 = 64 Mbps 1101 = 72 Mbps 1110 = 80 Mbps 1111 = 88 Mbps October 2007 100 M9999-100207-1.5 Micrel, Inc. Bit Default Name R/W Description KSZ8842-PMQL/PMBL Note: For 10Base-T, rate settings above 10Mbps are set to the default value 0000 (Not limited). Note: When multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. 7–4 0x0 0 RW Egress Pri1 Rate Egress data rate limit for priority 1 frames. Output traffic from this priority queue is shaped according to the egress rate selected as shown below: 0000 = Not limited (Default) 0001 = 64 Kbps 0010 = 128 Kbps 0011 = 256 Kbps 0100 = 512 Kbps 0101 = 1 Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 1100 = 64 Mbps 1101 = 72 Mbps 1110 = 80 Mbps 1111 = 88 Mbps Note: For 10Base-T, rate settings above 10Mbps are set to the default value 0000 (Not limited). Note: When multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. 3–0 0x0 0 RW Egress Pri0 Rate Egress data rate limit for priority 0 frames. Output traffic from this priority queue is shaped according to the egress rate selected as shown below: 0000 = Not limited (Default) 0001 = 64 Kbps 0010 = 128 Kbps 0011 = 256 Kbps 0100 = 512 Kbps 0101 = 1 Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps October 2007 101 M9999-100207-1.5 Micrel, Inc. Bit Default Name R/W Description 1100 = 64 Mbps 1101 = 72 Mbps 1110 = 80 Mbps 1111 = 88 Mbps KSZ8842-PMQL/PMBL Note: For 10Base-T, rate settings above 10Mbps are set to the default value 0000 (Not limited). Note: When multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. Reserved (Offset 0x0550) This register is reserved. Bit 15 – 0 Default 0x0000 R/W RO Description Reserved Reserved (Offset 0x0554) This register is reserved. Bit 15 – 0 Default 0x0000 R/W RO Description Reserved Reserved (Offset 0x0556) This register is reserved. Bit 15 – 0 Default 0x0000 R/W RO Description Reserved Reserved (Offset 0x0560) This register is reserved for internal testing. Bit 15 – 10 9–0 Default 0x00 – R/W RO RO Description Reserved Reserved October 2007 102 M9999-100207-1.5 Micrel, Inc. KSZ8842-PMQL/PMBL MIB (Management Information Base) Counters The KSZ8842-PMQL/PMBL provides 32 MIB counters for port 1, port 2, and the host port. These counters are used to monitor the port activity for network management. The MIB counters are formatted “per port” as shown in Table 8, and “per all port dropped packet” as shown in Table 8. Bit 31 30 29-0 Name Overflow Count valid Counter values R/W RO RO RO Description 1 = counter overflow. 0 = no counter overflow. 1 = counter value is valid. 0 = counter value is not valid. Counter value Default 0 0 0 Table 8. Format of Per Port MIB Counters “Per Port” MIB counters are read using indirect memory access. The base address offsets and address ranges for both Ethernet ports are: Port 1, base address of the MIB counter is 0x00 and range is (0x00-0x1f) as shown in Table 9. Port 2, base address of the MIB counter is 0x20 and range is (0x20-0x3f) as refer in Table 9. Host port, base address of the MIB counter is 0x40 and range is (0x40-0x5f) as refer in Table 9. Per Port MIB counters read/write functions use Access Control register IACR (0x04A0) bit 12. The base address offset and address range for port 1 is 0x00 and range is (0x00-0x1F) that can be changed in register IACR (0x04A0) bits[9:0]. The data of MIB counters are from the Indirect Access data register IADR4 (0x04A8) and IADR5 (0x04AA) based on Table 9. Offset 0x0 (base address) 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA Counter Name RxLoPriorityByte RxHiPriorityByte RxUndersizePkt RxFragments RxOversize RxJabbers RxSymbolError RxCRCError RxAlignmentError RxControl8808Pkts RxPausePkts Description Rx lo-priority (default) octet count including bad packets Rx hi-priority octet count including bad packets Rx undersize packets w/ good CRC Rx fragment packets w/ bad CRC, symbol errors or alignment errors Rx oversize packets w/ good CRC (max: 1536 or 1522 bytes) Rx packets longer than 1522 bytes w/ either CRC errors, alignment errors, or symbol errors (depends on max packet size setting) Rx packets w/ invalid data symbol and legal packet size. Rx packets within (64,1522) bytes w/ an integral number of bytes and a bad CRC (upper limit depends on max packet size setting) Rx packets within (64,1522) bytes w/ a non-integral number of bytes and a bad CRC (upper limit depends on max packet size setting) Number of MAC control frames received by a port with 88-08h in EtherType field Number of PAUSE frames received by a port. PAUSE frame is qualified with EtherType (88-08h), DA, control opcode (00-01), data length (64B min), and a valid CRC Rx good broadcast packets (not including error broadcast packets or valid multicast packets) Rx good multicast packets (not including MAC control frames, error multicast packets or valid broadcast packets) Rx good unicast packets Total Rx packets (bad packets included) that were 64 octets in length Total Rx packets (bad packets included) that are between 65 and 127 octets in length Total Rx packets (bad packets included) that are between 128 and 255 octets in 0xB 0xC 0xD 0xE 0xF 0x10 RxBroadcast RxMulticast RxUnicast Rx64Octets Rx65to127Octets Rx128to255Octets October 2007 103 M9999-100207-1.5 Micrel, Inc. Offset 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Counter Name Rx256to511Octets Rx512to1023Octets Rx1024to1522Octets TxLoPriorityByte TxHiPriorityByte TxLateCollision TxPausePkts TxBroadcastPkts TxMulticastPkts TxUnicastPkts TxDeferred TxTotalCollision TxExcessiveCollision TxSingleCollision TxMultipleCollision Description length KSZ8842-PMQL/PMBL Total Rx packets (bad packets included) that are between 256 and 511 octets in length Total Rx packets (bad packets included) that are between 512 and 1023 octets in length Total Rx packets (bad packets included) that are between 1024 and 1522 octets in length (upper limit depends on max packet size setting) Tx lo-priority good octet count, including PAUSE packets Tx hi-priority good octet count, including PAUSE packets The number of times a collision is detected later than 512 bit-times into the Tx of a packet Number of PAUSE frames transmitted by a port Tx good broadcast packets (not including error broadcast or valid multicast packets) Tx good multicast packets (not including error multicast packets or valid broadcast packets) Tx good unicast packets Tx packets by a port for which the 1st Tx attempt is delayed due to the busy medium Tx total collision, half duplex only A count of frames for which Tx fails due to excessive collisions Successfully Tx frames on a port for which Tx is inhibited by exactly one collision Successfully Tx frames on a port for which Tx is inhibited by more than one collision Table 9. Port 1s “Per Port” MIB Counters Indirect Memory Offsets Format of “All Port Dropped Packet” MIB Counters Bit 30 – 16 15 – 0 Default – – R/W N/A RO Description Reserved Counter Value Table 10. “All Port Dropped Packet” MIB Counters Format Note: “All Port Dropped Packet” MIB Counters do not indicate overflow or validity; therefore, the application must keep track of overflow and valid conditions. “All Port Dropped Packet” MIB counters are read using indirect memory access. The address offsets for these counters are shown in Table 11. Offset 0x100 0x101 0x103 0x104 Counter Name Port1 TX Drop Packets Port2 TX Drop Packets Port1 RX Drop Packets Port2 RX Drop Packets Description TX packets dropped due to lack of resources TX packets dropped due to lack of resources RX packets dropped due to lack of resources RX packets dropped due to lack of resources Table 11. “All Port Dropped Packet” MIB Counters Indirect Memory Offsets October 2007 104 M9999-100207-1.5 Micrel, Inc. KSZ8842-PMQL/PMBL Examples: 1. MIB Counter Read (read port 1 “Rx64Octets” counter at indirect address offset 0x0E) Write to reg. IACR with 0x1c0e (set indirect address and trigger a read MIB counters operation) Then Read reg. IADR5 (MIB counter value 31-16) // If bit 31 =1, there was a counter overflow // If bit 30 =0, restart (reread) from this register Read reg. IADR4 (MIB counter value 15-0) 2. MIB Counter Read (read port 2 “Rx64Octets” counter at indirect address offset 0x2E) Write to reg. IACR with 0x1c2e (set indirect address and trigger a read MIB counters operation) Then Read reg. IADR5 (MIB counter value 31-16) // If bit 31 =1, there was a counter overflow // If bit 30 =0, restart (reread) from this register Read reg. IADR4 (MIB counter value 15-0) 3. MIB Counter Read (read “Port1 TX Drop Packets” counter at indirect address offset 0x100) Write to reg. IACR with 0x1d00 (set indirect address and trigger a read MIB counters operation) Then Read reg. IADR4 (MIB counter value 15-0) Additional MIB Information Per Port MIB counters are designed as “read clear”. That is, these counters will be cleared after they are read. All Port Dropped Packet MIB counters are not cleared after they are accessed. The application needs to keep track of overflow and valid conditions on these counters. October 2007 105 M9999-100207-1.5 Micrel, Inc. KSZ8842-PMQL/PMBL Static MAC Address Table The KSZ8842-PMQL/PMBL supports both a static and a dynamic MAC address table. In response to a Destination Address (DA) look up, The KSZ8842-PMQL/PMBL searches both tables to make a packet forwarding decision. In response to a Source Address (SA) look up, only the dynamic table is searched for aging, migration and learning purposes. The static DA look up result takes precedence over the dynamic DA look up result. If there is a DA match in both tables, the result from the static table is used. These entries in the static table will not be aged out by the KSZ8842PMQL/PMBL. Bit 57 – 54 53 Default 0000 0 R/W RW R/W Description FID Filter VLAN ID - identifies one of the 16 active VLANs. Use FID 1 =specifies the use of FID+MAC for static table look ups 0 = specifies only the use of MAC for static table look ups Override 1 = overrides the port setting “transmit enable=0” or “receive enable=0” setting. 0 = specifies no override Valid 1 = specifies that this entry is valid, the look up result will be used 0 = specifies that this entry is not valid Forwarding ports These 3 bits control the forwarding port(s): 000 ,no forward 001, forward to port 1 010, forward to port 2 100, forward to port 3 011, forward to port 1 and port 2 110, forward to port 2 and port 3 101, forward to port 1 and port 3 111, broadcasting (excluding the ingress port) MAC address 48 bits MAC Address 52 0 R/W 51 0 R/W 50 – 48 000 R/W 47 – 0 0 R/W Table 12. Static MAC Table Format (8 Entries) Examples: 1. Static Address Table Read (read the second entry at indirect address offset 0x01) Write to reg. IACR with 0x1001 (set indirect address and trigger a read static MAC table operation) Then Read reg. IADR3 (static MAC table bits 57-48) Read reg. IADR2 (static MAC table bits 47-32) Read reg. IADR5 (static MAC table bits 31-16) Read reg. IADR4 (static MAC table bits 15-0) 2. Static Address Table Write (write the eighth entry at indirect address offset 0x07) Write to reg. IADR3 (static MAC table bits 57-48) Write to reg. IADR2 (static MAC table bits 47-32) Write to reg. IADR5 (static MAC table bits 31-16) Write to reg. IADR4 (static MAC table bits 15-0) Write to reg. IACR with 0x0007 (set indirect address and trigger a write static MAC table operation) October 2007 106 M9999-100207-1.5 Micrel, Inc. KSZ8842-PMQL/PMBL Dynamic MAC Address Table The Dynamic MAC address is a read only table. Bit 71 Default R/W RO Description Data not ready 1 = specifies that the entry is not ready, continue retrying until bit is set to 0 0 = specifies that the entry is ready Reserved MAC empty 1 = specifies that there is no valid entry in the table 0 = specifies that there are valid entries in the table No of valid entries Indicates how many valid entries in the table 0x3ff means 1 K entries 0x001 means 2 entries 0x000 and bit 66 = 0 means 1 entry 0x000 and bit 66 = 1 means 0 entry Time Stamp Specifies the 2-bit counter for internal aging. Source port Identifies the source port where FID+MAC is learned: 00, port 1 01, port 2 10, port 3 FID Specifies the filter ID. MAC Address Specifies the 48-bit MAC address. 70 – 67 66 1 RO RO 65 – 56 00_0000_0000 RO 55 – 54 53 – 52 00 RO RO 51 – 48 47 – 0 0x0 0x000_0000_0000 RO RO Table 13. Dynamic MAC Address Table Format (1024 Entries) Example: Dynamic MAC Address Table Read (read the first entry at indirect address offset 0 and retrieve the MAC table size) Write to reg. IACR with 0x1800 (set indirect address and trigger a read dynamic MAC table operation) Then Read reg. IADR1 (dynamic MAC table bits 71-64) // If bit 71 =1, restart (reread) from this register Read reg. IADR3 (dynamic MAC table bits 63-48) Read reg. IADR2 (dynamic MAC table bits 47-32) Read reg. IADR5 (dynamic MAC table bits 31-16) Read reg. IADR4 (dynamic MAC table bits 15-0) October 2007 107 M9999-100207-1.5 Micrel, Inc. KSZ8842-PMQL/PMBL VLAN Table The KSZ8842-PMQL/PMBL uses the VLAN table to perform look ups. If 802.1Q VLAN mode is enabled (SGCR2[15]), this table will be used to retrieve the VLAN information that is associated with the ingress packet. This information includes FID (filter ID), VID (VLAN ID), and VLAN membership as described in table 14: Bit 19 Default 1 R/W RW Description Valid 1 = specifies that this entry is valid, the look up result will be used 0 = specifies that this entry is not valid Membership Specifies which ports are members of the VLAN. If a DA look up fails (no match in both static and dynamic tables), the packet associated with this VLAN will be forwarded to ports specified in this field. For example: 101 means port 3 and 1 are in this VLAN. FID Specifies the Filter ID. The KSZ8842-PMQL/PMBL supports 16 active VLANs represented by these four bit fields. The FID is the mapped ID. If 802.1Q VLAN is enabled, the look up will be based on FID+DA and FID+SA. VID Specifies the IEEE 802.1Q 12 bits VLAN ID. Table 14. VLAN Table Format (16 Entries) 18 – 16 111 R/W 15 – 12 0x0 R/W 11 – 0 0x001 R/W If 802.1Q VLAN mode is enabled, KSZ8842-PMQL/PMBL will assign a VID to every ingress packet. If the packet is untagged or tagged with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with non null VID, the VID in the tag will be used. The look up process will start from the VLAN table look up. If the VID is not valid, the packet will be dropped and no address learning will take place. If the VID is valid, the FID is retrieved. The FID+DA and FID+SA lookups are performed. The FID+DA look up determines the forwarding ports. If FID+DA fails, the packet will be broadcast to all the members (excluding the ingress port) of the VLAN. If FID+SA fails, the FID+SA will be learned. Examples: 1. VLAN Table Read (read the third entry, at the indirect address offset 0x02) Write to reg. IACR with 0x1402 (set indirect address and trigger a read VLAN table operation) Then Read reg. IADR5 (VLAN table bits 19-16) Read reg. IADR4 (VLAN table bits 15-0) 2. VLAN Table Write (write the seventh entry, at the indirect address offset 0x06) Write to reg. IADR5 (VLAN table bits 19-16) Write to reg. IADR4 (VLAN table bits 15-0) Write to reg. IACR with 0x1406 (set indirect address and trigger a read VLAN table operation) October 2007 108 M9999-100207-1.5 Micrel, Inc. KSZ8842-PMQL/PMBL Absolute Maximum Ratings(1) Supply Voltage (VDDATX, VDDARX, VDDIO) ........................... –0.5V to +4.0V Input Voltage (all inputs). ............................. –0.5V to +5.0V Output Voltage (all outputs) ......................... –0.5V to +4.0V Lead Temperature (soldering, 10sec.) ....................... 270°C Storage Temperature (Ts) .........................–55°C to +150°C Operating Ratings(2) Supply Voltage (VDDATX, VDDARX, VDDIO)...................... +3.1V to +3.5V Ambient Temp. of MQL/MBL(TA)............ 0°C to +70°C Ambient Temp. of MQLI/MBL AM(TA) . -40°C to +85°C Junction Temperature (TJ)................................. 125°C Package Thermal Resistance(3) PQFP (θJA) No Air Flow........................ 42.91°C/W PQFP (θJC) No Air Flow .......................... 19.6°C/W LFBGA (θJA) No Air Flow...................... 38.50°C/W LFBGA (θJC) No Air Flow ...................... 12.50°C/W Electrical Characteristics(4) Symbol Parameter Condition Min Typ Max Units Supply Current 100BASE-TX Operation (All Ports @ 100% Utilization) IDDXIO 100BASE-TX (Analog Core + PLL + Digital Core + Transceiver + Digital I/O) 100BASE-T (Analog Core + PLL + Digital Core + Transceiver + Digital I/O) Input High Voltage Input Low Voltage Input Current Output High Voltage Output Low Voltage Output Tri-state Leakage Peak Differential Output Voltage Output Voltage Imbalance Rise/Fall Time Rise/Fall Time Imbalance Duty Cycle Distortion Overshoot VSET Reference Voltage of ISET Output Jitter 10Base-T Receive VSQ VP Squelch Threshold Peak Differential Output Voltage Jitter Added 5MHz square wave 100Ω termination on the differential output. 100Ω termination on the differential output. 400 2.4 1.8 ±3.5 mV V ns 10Base-T Transmit (measured differentially after 1:1 transformer) VDDATX = 3.3V only Peak to peak 0.5 0.7 1.4 100Ω termination on the differential output. 100Ω termination on the differential output. 3 0 0.95 VIN = GND ~ VDDIO IOH = –8mA IOL = 8mA –10 2.4 0.4 10 1.05 2 5 0.5 ±0.5 5 VDDATX, VDDARX, VDDIO = 3.3V 122 mA 10BASE-T Operation (All Ports @ 100% Utilization) IDDXIO VDDATX, VDDARX, VDDIO = 3.3V 90 mA TTL Inputs VIH VIL IIN VOH VOL IOZ VO VIMB tr, tf 2.0 0.8 10 V V µA V V µA V % ns ns ns % V ns TTL Outputs 100Base-TX Transmit (measured differentially after 1:1 transformer) VDDATX = 3.3V only October 2007 109 M9999-100207-1.5 Micrel, Inc. Notes: KSZ8842-PMQL/PMBL 1. Exceeding the absolute maximum rating may damage the device. Stresses greater than those listed in the table above may cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level. 2. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level (Ground to VDD) 3. No (HS) heat spreader in this package. The thermal junction to ambient (θJA) and the thermal junction to case (θJC) are under air velocity 0m/s. 4. Specification for packaged product only. A single port’s transformer consumes an additional 45mA at 3.3V for 100BASE-T and 70mA at 3.3V for 10BASE-T. October 2007 110 M9999-100207-1.5 Micrel, Inc. KSZ8842-PMQL/PMBL Timing Diagrams For PCI Timing, please refer to PCI specification version 2.2. EEPROM Timing EECS *1 EESK 1 EEDO 11 0 An A0 ts th D15 D14 D13 D1 D0 EEDI Hight-Z *1 Start bit Figure 12. EEPROM Read Cycle Timing Diagram Timing Parameter tcyc ts th Description Clock cycle Setup time Hold time Min 20 20 Typ 4000 Max Unit ns ns ns Table 15. EEPROM Timing Parameters October 2007 111 M9999-100207-1.5 Micrel, Inc. Auto Negotiation Timing FLP Burst FLP Burst KSZ8842-PMQL/PMBL TX+/TXtFLPW tBTB Clock Pulse TX+/TXtPW tCTD Data Pulse tPW Clock Pulse Data Pulse tCTC Figure 13. Auto-Negotiation Timing Timing Parameter tBTB tFLPW tPW tCTD tCTC Description FLP burst to FLP burst FLP burst width Clock/Data pulse width Clock pulse to data pulse Clock pulse to clock pulse Number of Clock/Data pulses per burst Min 8 Typ 16 2 100 Max 24 Unit ms ms ns 55.5 111 17 64 128 69.5 139 33 µs µs Table 16. Auto Negotiation Parameters October 2007 112 M9999-100207-1.5 Micrel, Inc. KSZ8842-PMQL/PMBL Reset Timing As long as the stable supply voltages to reset High timing (minimum of 10ms) are met, there is no power-sequencing requirement for the KSZ8842-PMQL/PMBL supply voltages 3.3V. The reset timing requirement is summarized in the Figure 14 and Table 17. Supply Voltage tsr RST_N Figure 14. Reset Timing Symbol tsr Parameter Stable supply voltages to reset High Min 10 Max Unit ms Table 17. Reset Timing Parameters October 2007 113 M9999-100207-1.5 Micrel, Inc. KSZ8842-PMQL/PMBL Selection of Isolation Transformers A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. Table 18 gives recommended transformer characteristics. Parameter Turns ratio Open-circuit inductance (min) Leakage inductance (max) Inter-winding capacitance (max) D.C. resistance (max) Insertion loss (max) HIPOT (min) Value 1 CT : 1 CT 350µH 0.4µH 12pF 0.9Ω 1.0dB 1500Vrms Table 18. Transformer Selection Criteria 0MHz – 65MHz 100mV, 100kHz, 8mA 1MHz (min) Test Condition Magnetic Manufacturer Pulse Pulse (low cost) Transpower Bel Fuse Delta LanKom TDK (Mag Jack) Part Number H1102 H1260 HB726 S558-5999-U7 LF8505 LF-H41S TLA-6T718 Auto MDI-X Yes Yes Yes Yes Yes Yes Yes Number of Port 1 1 1 1 1 1 1 Table 19. Qualified Single Port Magnetics Selection of Reference Crystal Characteristics Frequency Frequency tolerance (max) Load capacitance (max) Series resistance Value 25 ±50 20 25 Table 20. Typical Reference Crystal Characteristics Units MHz ppm pF Ω October 2007 114 M9999-100207-1.5 Micrel, Inc. KSZ8842-PMQL/PMBL Package Information Figure 15. 128-Pin PQFP October 2007 115 M9999-100207-1.5 Micrel, Inc. KSZ8842-PMQL/PMBL Package Information Figure 16. 100-Ball LFBGA October 2007 116 M9999-100207-1.5 Micrel, Inc. KSZ8842-PMQL/PMBL Acronyms and Glossary BPDU Bridge Protocol Data Unit A packet containing ports, addresses, etc. to make sure data being passed through a bridged network arrives at its proper destination. CMOSComplementary Metal Oxide Semiconductor. A common semiconductor manufacturing technique in which positive and negative types of transistors are combined to form a current gate that in turn forms an effective means of controlling electrical current through a chip. CRC Cyclic Redundancy Check A common technique for detecting data transmission errors. CRC for Ethernet is 32 bits long. DA Destination Address The address to send packets. A design in which memory on a chip is controlled independently of the CPU. A bus architecture designed for PCs using 80x86 processors, or an Intel 80386, 80486 or Pentium microprocessor. EISA buses are 32 bits wide and support multiprocessing. A naturally occurring phenomena when the electromagnetic field of one device disrupts, impedes or degrades the electromagnetic field of another device by coming into proximity with it. In computer technology, computer devices are susceptible to EMI because electromagnetic fields are a byproduct of passing electricity through a wire. Data lines that have not been properly shielded are susceptible to data corruption by EMI. See CRC. Specifies the frame identifier. Alternately is the filter identifier. A time delay between successive data packets mandated by the network standard for protocol reasons. In Ethernet, the medium has to be "silent" (i.e., no data transfer) for a short period of time before a node can consider the network idle and start to transmit. IPG is used to correct timing differences between a transmitter and receiver. During the IPG, no data is transferred, and information in the gap can be discarded or additions inserted without impact on data integrity. The disruption of transmitted code caused by adjacent pulses DMA Direct Memory Access EISA Extended Industry Standard Architecture EMI Electro-Magnetic Interference FCS FID IPG Frame Check Sequence Frame or Filter ID Inter-Packet Gap ISI ISA MDI Inter-Symbol Interference Industry Standard Architecture Medium Dependent Interface affecting or interfering with each other. A bus architecture used in the IBM PC/XT and PC/AT. An Ethernet port connection that allows network hubs or switches to connect to other hubs or switches without a null-modem, or crossover, cable. MDI provides the standard interface to a particular media (copper or fiber) and is therefore 'media dependent.' An Ethernet port connection that allows networked end stations (i.e., PCs or workstations) to connect to each other using a null-modem, or crossover, cable. For 10/100 full-duplex networks, an end point (such as a computer) and a switch are wired so that each transmitter connects to the far end receiver. When connecting two computers together, a cable that crosses the TX and RX is required to do this. With auto MDI-X, the PHY senses the correct TX and RX roles, eliminating any cable confusion. The MIB comprises the management portion of network devices. This can include things like monitoring traffic levels and faults (statistical), MDI-X Medium Dependent Interface Crossover MIB Management Information Base October 2007 117 M9999-100207-1.5 Micrel, Inc. KSZ8842-PMQL/PMBL and can also change operating parameters in network nodes (static forwarding addresses). MII NIC Media Independent Interface Network Interface Card The MII accesses PHY registers as defined in the IEEE 802.3 specification. An expansion board inserted into a computer to allow it to be connected to a network. Most NICs are designed for a particular type of network, protocol, and media, although some can serve multiple networks. An electronic circuit that controls an oscillator so that it maintains a constant phase angle (i.e., lock) on the frequency of an input, or reference, signal. A PLL ensures that a communication signal is locked on a specific frequency and can also be used to generate, modulate, and demodulate a signal and divide a frequency. An occurrence that affects the directing of power to different components of a system. The address from which information has been sent. TDR is used to pinpoint flaws and problems in underground and aerial wire, cabling, and fiber optics. They send a signal down the conductor and measure the time it takes for the signal -- or part of the signal -- to return. Commonly a cable containing 4 twisted pairs of wires. The wires are twisted in such a manner as to cancel electrical interference generated in each wire, therefore shielding is not required. A configuration of computers that acts as if all computers are connected by the same physical network but which may be located virtually anywhere. PLL Phase-Locked Loop PME Power Management Event SA Source Address TDR Time Domain Reflectometry UTP Unshielded Twisted Pair VLAN Virtual Local Area Network October 2007 118 M9999-100207-1.5 Micrel, Inc. KSZ8842-PMQL/PMBL MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2007 Micrel, Incorporated. October 2007 119 M9999-100207-1.5