KSZ8864RMN

KSZ8864RMN Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces Rev. 1.4 General Description The KSZ8864RMN is a highly-integrated, Layer 2 managed 4-port switch with optimized design, plentiful features and smallest package size. It is designed for cost-sensitive 10/100Mbps 4-port switch systems with on-chip termination, lowest-power consumption, and small package to save system cost. It has 1.4Gbps highperformance memory bandwidth, shared memory-based switch fabric with full non-blocking configuration. It also provides an extensive feature set such as the power management, programmable rate limiting and priority ratio, tag/port-based VLAN, packet filtering, quality of service (QoS), four queue prioritization, management interface, MIB counters. Port 3 and Port 4 support either MII or RMII interfaces with SW3-MII/RMII and SW4MII/RMII (see Functional Diagram) for KSZ8864RMN data interface. The KSZ8864RMN provides multiple CPU control/data interfaces to effectively address both current and emerging fast Ethernet applications. The KSZ8864RMN consists of 10/100 fast Ethernet PHYs with patented and enhanced mixed-signal technology, media access control (MAC) units, a highspeed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. The KSZ8864RMN contains four MACs and two PHYs. The two PHYs support the 10/100Base-T/TX. All registers of MACs and PHYs units can be managed by the control interface of SPI or the SMI. MIIM registers of the PHYs can be accessed through the MDC/MDIO interface. EEPROM can set all control registers by I2C controller interface for the unmanaged mode. Functional Diagram Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com September 2011 M9999-092011-1.4 Micrel, Inc. KSZ8864RMN Features Advanced Switch Features          IEEE 802.1q VLAN support for up to 128 VLAN groups (full-range 4096 of VLAN IDs). Static MAC table supports up to 32 entries. VLAN ID tag/untag options, per port basis. IEEE 802.1p/q tag insertion or removal on a per port basis based on ingress port (egress). Programmable rate limiting at the ingress and egress on a per port basis. Jitter-free per packet based rate limiting support. Broadcast storm protection with percentage control (global and per port basis). IEEE 802.1d rapid spanning tree protocol RSTP support. Tail tag mode (1 byte added before FCS) support at Port 4 to inform the processor which ingress port receives the packet. 1.4Gbps high-performance memory bandwidth and shared memory based switch fabric with fully nonblocking configuration. Dual MII/RMII with MAC 3 SW3-MII/RMII and MAC 4 SW4-MII/RMII interfaces. Enable/Disable option for huge frame size up to 2000 Bytes per frame. IGMP v1/v2 snooping (Ipv4) support for multicast packet filtering. IPv4/IPv6 QoS support. Support unknown unicast/multicast address and unknown VID packet filtering. Integrated 4-Port 10/100 Ethernet Switch  New generation switch with five MACs and five PHYs that are fully compliant with the IEEE 802.3u standard. Non-blocking switch fabric assures fast packet delivery by utilizing an 1K MAC address lookup table and a store-and-forward architecture. On-chip 64Kbyte memory for frame buffering (not shared with 1K unicast address table). Full-duplex IEEE 802.3x flow control (PAUSE) with force mode option. Half-duplex back pressure flow control. HP Auto MDI/MDI-X and IEEE Auto crossover support. MII interface of MAC supports both MAC mode and PHY mode. Per port LED Indicators for link, activity, and 10/100 speed. Register port status support for link, activity, full/half duplex and 10/100 speed. On-chip terminations and internal biasing technology for cost down and lowest power consumption. Port mirroring/monitoring/sniffing: ingress egress traffic to any port or MII/RMII. and/or                Switch Monitoring Features    MIB counters for fully-compliant statistics gathering 34 MIB counters per port. Loop-back support for MAC, PHY and remote diagnostic of failure.  Self-address filtering. Comprehensive Configuration Register Access  Serial management interface (MDC/MDIO) to all PHYs registers and SMI interface (MDC/MDIO) to all registers. High-speed SPI (up to 25MHz) and I2C master Interface to all internal registers. I/0 pins strapping and EEPROM to program selective registers in unmanaged switch mode. Control registers configurable on the fly (port-priority, 802.1p/d/q, AN…). Per port, 802.1p and DiffServ-based. 1/2/4-queue QoS prioritization selection. Programmable weighted fair queuing for ratio control. Re-mapping of 802.1p priority field per port basis.  Interrupt for the link change on any ports. Low-Power Dissipation:       Full-chip hardware power-down. Full-chip software power-down and per port software power down. Energy-detect mode support