KSZ8993FL

KS8993F/KS8993FL Single Chip Fast Ethernet Media Converter with TS-1000 OAM Revision 1.3 General Description The Micrel KS8993F is the industry’s first single chip Fast Ethernet Media Converter with built-in OAM functions. The KS8993F integrates three MACs, two PHYs, OAM, frame buffer and high performance switch into a single chip. It is ideal for use in 100BASE-FX to 10BASE-T or 100BASETX conversion in the FTTx market. The KS8993F provides remote loop back and OAM (Operation, Administration and Maintenance) to manage subscriber access network from carrier center side to terminal side. The KS8993F supports advanced features such as rate limiting, force flow control and link transparency. The KS8993F with built-in Layer 2 switch capability will filter packets and forward them to valid destination. It will discard any unwanted frames and frames with invalid destination. The KS8993FL is the single supply version with all the identical rich features of the KS8993F. Features • • • • • • • • First single-chip 10BASE-T/100BASE-TX to 100BASE-FX media converter with TS-1000 OAM Integrated 3-Port 10/100 Ethernet Switch with 3 MACs and 2 PHYs Unique User Defined Register (UDR) feature brings OAM to low cost/complexity nodes Automatic MDI/MDI-X crossover with disable and enable option Non-blocking switch fabric assures fast packet delivery by utilizing an 1K MAC Address lookup table and a store-and-forward architecture Comprehensive LED indicator support for link, activity, full/half duplex and 10/100 speed Full complement of MII/SNI, SPI, MIIM, SMI and I2C interfaces Low Power Dissipation:< 800mW (includes PHY transmit drivers) Block Diagram To Control Registers Auto MDI/MDI-X 10/100 T/TX/FX PHY1 O A M 1K look-up Engine 10/100 MAC 1 Queue Management FIFO, Flow Control, VLAN Tagging ,Priority Auto MDI/MDI-X 10/100 T/TX/FX PHY2 10/100 MAC 2 Buffer Management MII / SNI Interface 10/100 MAC 3 Frame Buffers SNI SPI Interface MIIM Interface SMI Interface I2C Bus P1 LED[3:0] P2 LED[3:0] LED Drivers SPI MIB Counters Control Registers EEPROM Interface Strap In Configuration Pins KS8993F / KS8993FL Micrel is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com June 2009 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL Features (continued) • • • • • • • • • • • • • • • • • • • • • • OAM Features: Supports OAM sub-layer which conforms to TS-1000 specification from TTC (Telecommunication Technology Committee) Sends and receives OAM frames to Center or Terminal side Loop back mode to support loop back packet from Center side to Terminal side Far-end fault detection with disable and enable Link Transparency to indicate the link down from link partner Comprehensive Configuration Register access: Serial Management Interface (SMI) to all internal registers MII Management (MIIM) Interface to PHY registers SPI and I2C Interface to all internal registers I/0 Pins Strapping and EEPROM to program selective registers in unmanaged switch mode Control registers configurable on the fly (port-priority, 802.1p/d/q, AN…) QoS / CoS packets prioritization support per-port, 802.1p and DiffServ based Re-mapping of 802.1p priority field per-port basis Advanced Switch Features IEEE 802.1q VLAN support for up to 16 groups (fullrange of VLAN ID) VLAN ID tag/untag options, per-port basis IEEE 802.1p/q tag insertion or removal on a per port basis (egress) Programmable Rate Limiting from 0 to 100 Mbps at the ingress & egress port, rate options for high & low priority, per port basis Broadcast storm protection with % control (global & perport basis) Double Tagging support • • • • • • • • Switch Management Features: Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII MIB (Management Information Base) counters for fully compliant statistics gathering, 34 MIB counters per port Full-chip hardware power-down (register configuration not saved) Per-port based software power-save on PHY (idle link detection, register configuration preserved) 0.18um CMOS technology Voltages: Core 1.8V I/O and Transceiver 3.3V Available in 128-pin PQFP Ordering Information Part Number Pb-Free KSZ8993F KSZ8993FL Standard KS8993F KS8993FL Temperature Range 0 – 70 C 0 – 70 C o o o o Package 128PQFP 128PQFP June 2009 2 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL Revision History Revision P0 P1 Date 1/14/03 2/11/03 Summary of Changes Preliminary Information Added separate Link and activity on port 1 and port 2’s LED (pin #20, pin #23, pin #25). Added disable auto MDI/MDIX (pin #28) Added select of MDI and MDIX (pin #29) Updated register information Started overhaul of datasheet. Updated strap option definition for pin #85. Renamed supply voltages and ground references to match schematics. Corrected Remote Loop back path. Updated MC registers descriptions. Changed 3.3V voltage pins to (3.3V or 2.5V). Completed overhaul of datasheet. Revised datasheet format. Updated KS8993F block diagram. Updated Feature Highlights. Updated MC registers descriptions. Updated Electrical Characteristics (Vih, Vil, Voh, Vol). Updated MC loop back description in pin #19 and register 11 bits[3:2], and path in loop back diagram. Updated flow diagram for Destination Address resolution flowchart, stage2. Changed S10 status bit from RO to R/W in register 81 bit[2]. Added KS8993FL to General Description (page 1) and Functional Description Overview (section 2.1). Updated pin description for pin 22 to the following: VDDC : For KS8993F, this is an input power pin for the 1.8V digital core VDD. VOUT_1V8 : For KS8993FL, this is an 1.8V output power pin to supply the KS8993FL’s input power pins: VDDAP (pin 63), VDDC (pins 91, 123) and VDDA (pins 38, 43, 57). Improved/clarified pin description. Updated PPM spec for 25 MHz crystal/oscillator. Improved/clarified pin description for P1LCRCD (pin 18), P2MDIX (pin 29) and MDIO (pin 95). Corrected aging time. Removed loop back support from MIIM and Port Control Registers, so that there is no confusion with MC loop back which is used exclusively in KS8993F application. Updated HWPOVR description in section 2.2.5. Corrected default definition for FEF in section 2.3.6, and MIIM and Port Control Registers. Added register note to indicate port sniffing is not supported if the unicast packets can cross VLAN boundary bit is set. Improved/clarified switch/PHY registers descriptions for Force MDIX and CRC drop. Improved/clarified MC registers descriptions for Remote Command (registers 74, 75, 76), My Status (registers 80, 81) and LNK Partner Status (registers 88, 89). Added register note to set Register 85: My Model Info (1) to values of 0x22, 0x26, 0x2A and 0x2E if the Remote Command feature is used. Updated MIB counters descriptions to indicate counter overflow must be tracked by application. Corrected VDDIO, VDDATX, VDDARX supply pins to 3.3V only. Updated reset timing requirement. Corrected 10BASE-T Transmitter Jitters Added. Removed Industrial Temperature line from Features and Ordering info. Add the parts KSZ8993F, KSZ8993FL on the order information P2 P3 4/1/03 12/4/03 P4 3/11/04 P5 3/23/04 1.0 8/26/04 1.1 4/7/05 1.2 1.3 5/22/06 6/25/09 June 2009 3 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL Table Of Contents 1 Signal Description.........................................................................................................................9 1.1 1.2 2.1 2.2 KS8993F Pin Diagram ........................................................................................................................................................... 9 Pin Description and I/O Assignment .................................................................................................................................... 10 2 Functional Description ................................................................................................................20 Overview .............................................................................................................................................................................. 20 Media Converter Function.................................................................................................................................................... 20 2.2.1 OAM (Operations, Administration, and Management) Frame Format ..................................................................... 20 2.2.2 MC (Media Converter) Mode ................................................................................................................................... 22 2.2.3 MC Loop Back Function .......................................................................................................................................... 22 2.2.4 Registers for Media Converter Functions ................................................................................................................ 23 2.2.5 Unique I/O Feature Definition .................................................................................................................................. 23 2.2.6 Port 1 LED Indicator Definition ................................................................................................................................ 24 2.2.7 Port 2 LED Indicator Definition ................................................................................................................................ 24 2.3 Physical Transceiver ............................................................................................................................................................ 25 2.3.1 100BASE-TX Transmit ............................................................................................................................................ 25 2.3.2 100BASE-TX Receive ............................................................................................................................................. 25 2.3.3 PLL Clock Synthesizer ............................................................................................................................................ 25 2.3.4 Scrambler/De-scrambler (100BASE-TX only) ......................................................................................................... 25 2.3.5 100BASE-FX Operation and Signal Detection ........................................................................................................ 25 2.3.6 100BASE-FX Far-End Fault (FEF) .......................................................................................................................... 26 2.3.7 10BASE-T Transmit and Receive............................................................................................................................ 26 2.3.8 Power Management................................................................................................................................................. 27 2.3.9 Auto MDI/MDI-X Crossover ..................................................................................................................................... 27 2.3.10 Auto Negotiation ...................................................................................................................................................... 29 2.4 MAC and Switch Function .................................................................................................................................................... 29 2.4.1 Address Look Up ..................................................................................................................................................... 29 2.4.2 Learning................................................................................................................................................................... 30 2.4.3 Migration.................................................................................................................................................................. 30 2.4.4 Aging ....................................................................................................................................................................... 30 2.4.5 Forwarding............................................................................................................................................................... 30 2.4.6 Switching Engine ..................................................................................................................................................... 33 2.4.7 MAC operation......................................................................................................................................................... 33 2.4.8 Back-off Algorithm ................................................................................................................................................... 33 2.4.9 Late Collision ........................................................................................................................................................... 33 2.4.10 Illegal Frames .......................................................................................................................................................... 33 2.4.11 Flow Control ............................................................................................................................................................ 33 2.4.12 Half Duplex Back Pressure...................................................................................................................................... 34 2.4.13 Broadcast Storm Protection..................................................................................................................................... 34 2.5 MII Interface Operation ........................................................................................................................................................ 34 2.6 SNI (7-wire) Interface Operation .......................................................................................................................................... 35 2.7 MII Management Interface (MIIM) ........................................................................................................................................ 36 2.8 Serial Management Interface (SMI) ..................................................................................................................................... 36 2.9 Advanced Switch Function................................................................................................................................................... 37 2.9.1 Port Mirroring Support ............................................................................................................................................. 37 2.9.2 IEEE 802.1Q VLAN support .................................................................................................................................... 38 2.9.3 QoS Priority ............................................................................................................................................................. 39 2.9.4 Rate Limit Support................................................................................................................................................... 41 2.10 Configuration Interface......................................................................................................................................................... 41 2 2.10.1 I C Master Serial Bus Configuration ........................................................................................................................ 42 2 2.10.2 I C Slave Serial Bus Configuration .......................................................................................................................... 43 2.10.3 SPI Slave Serial Bus Configuration ......................................................................................................................... 43 3 MII Management (MIIM) Registers .............................................................................................47 Register 0: Register 1: Register 2: Register 3: Register 4: MII Basic Control .............................................................................................................................................. 47 MII Basic Status................................................................................................................................................ 48 PHYID HIGH ..................................................................................................................................................... 48 PHYID LOW...................................................................................................................................................... 48 Auto-Negotiation Advertisement Ability ............................................................................................................ 49 June 2009 4 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL Register 5: Auto-Negotiation Link Partner Ability ................................................................................................................ 49 4 Register Map: Switch, MC, & PHY (8 bits registers) ..................................................................50 4.1 Global Registers................................................................................................................................................................... 51 Register 0 (0x00): Chip ID0................................................................................................................................................. 51 Register 1 (0x01): Chip ID1 / Start Switch........................................................................................................................... 51 Register 2 (0x02): Global Control 0..................................................................................................................................... 51 Register 3 (0x03): Global Control 1..................................................................................................................................... 52 Register 4 (0x04): Global Control 2..................................................................................................................................... 53 Register 5 (0x05): Global Control 3..................................................................................................................................... 53 Register 6 (0x06): Global Control 4..................................................................................................................................... 54 Register 7 (0x07): Global Control 5..................................................................................................................................... 55 Register 8 (0x08): Global Control 6..................................................................................................................................... 55 Register 9 (0x09): Global Control 7..................................................................................................................................... 55 Register 10 (0x0A): Global Control 8 .................................................................................................................................. 55 Register 11 (0x0B): Global Control 9 .................................................................................................................................. 55 Register 12 (0x0C): Reserved Register .............................................................................................................................. 56 Register 13 (0x0D): User Defined Register 1...................................................................................................................... 56 Register 14 (0x0E): User Defined Register 2 ...................................................................................................................... 57 Register 15 (0x0F): User Defined Register 3 ...................................................................................................................... 57 Port Registers ...................................................................................................................................................................... 57 Register 16 (0x10): Port 1 Control 0 ................................................................................................................................... 57 Register 17 (0x11): Port 1 Control 1 ................................................................................................................................... 58 Register 18 (0x12): Port 1 Control 2 ................................................................................................................................... 58 Register 19 (0x13): Port 1 Control 3 ................................................................................................................................... 59 Register 20 (0x14): Port 1 Control 4 ................................................................................................................................... 59 Register 21 (0x15): Port 1 Control 5 ................................................................................................................................... 60 Register 22 (0x16): Port 1 Control 6 ................................................................................................................................... 60 Register 23 (0x17): Port 1 Control 7 ................................................................................................................................... 60 Register 24 (0x18): Port 1 Control 8 ................................................................................................................................... 60 Register 25 (0x19): Port 1 Control 9 ................................................................................................................................... 60 Register 26 (0x1A): Port 1 Control 10 ................................................................................................................................. 60 Register 27 (0x1B): Port 1 Control 11 ................................................................................................................................. 61 Register 28 (0x1C): Port 1 Control 12 ................................................................................................................................. 61 Register 29 (0x1D): Port 1 Control 13 ................................................................................................................................. 62 Register 30 (0x1E): Port 1 Status 0 .................................................................................................................................... 63 Register 31 (0x1F): Port 1 Status 1..................................................................................................................................... 64 Media Converter Registers .................................................................................................................................................. 65 Register 64 (0x40): PHY Address ....................................................................................................................................... 65 Register 65 (0x41): Center Side Status .............................................................................................................................. 65 Register 66 (0x42): Center Side Command ........................................................................................................................ 66 Register 67 (0x43): PHY-SW Initialize ................................................................................................................................ 66 Register 68 (0x44): Loop Back Setup1 ............................................................................................................................... 68 Register 69 (0x45): Loop Back Setup2 ............................................................................................................................... 68 Register 70 (0x46): Loop Back Result Counter for CRC Error............................................................................................ 69 Register 71 (0x47): Loop Back Result Counter for Timeout................................................................................................ 69 Register 72 (0x48): Loop Back Result Counter for Good Packet........................................................................................ 69 Register 73 (0x49): Additional Status (Center and Terminal side) ...................................................................................... 69 Register 74 (0x4A): Remote Command 1 ........................................................................................................................... 70 Register 75 (0x4B): Remote Command 2 ........................................................................................................................... 70 Register 76 (0x4C): Remote Command 3 ........................................................................................................................... 71 Register 77 (0x4D): Valid MC Packet Transmitted Counter................................................................................................ 71 Register 78 (0x4E): Valid MC Packet Received Counter .................................................................................................... 71 Register 79 (0x4F): Shadow of 0x58h Register .................................................................................................................. 71 Register 80 (0x50): My Status 1 (Terminal and Center side) .............................................................................................. 72 Register 81 (0x51): My Status 2.......................................................................................................................................... 72 Register 82 (0x52): My Vendor Info (1) ............................................................................................................................... 73 Register 83 (0x53): My Vendor Info (2) ............................................................................................................................... 73 Register 84 (0x54): My Vendor Info (3) ............................................................................................................................... 73 Register 85 (0x55): My Model Info (1)................................................................................................................................. 73 Register 86 (0x56): My Model Info (2)................................................................................................................................. 73 Register 87 (0x57): My Model Info (3)................................................................................................................................. 73 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 4.2 4.3 June 2009 5 Micrel, Inc. KS8993F/FL 4.4 4.5 4.6 4.7 4.8 5.1 5.2 5.3 5.4 6.1 6.2 6.3 Register 88 (0x58): LNK Partner Status (1) ........................................................................................................................ 74 Register 89 (0x59): LNK Partner Status (2) ........................................................................................................................ 74 Register 90 (0x5A): LNK Partner Vendor Info (1)............................................................................................................... 74 Register 91 (0x5B): LNK Partner Vendor Info (2)................................................................................................................ 74 Register 92 (0x5C): LNK Partner Vendor Info (3) ............................................................................................................... 74 Register 93 (0x5D): LNK Partner Model Info (1) ................................................................................................................. 74 Register 94 (0x5E): LNK Partner Model Info (2) ................................................................................................................. 74 Register 95 (0x5F): LNK Partner Model Info (3).................................................................................................................. 74 Advanced Control Registers ................................................................................................................................................ 75 Register 96 (0x60): TOS Priority Control Register 0 ........................................................................................................... 75 Register 97 (0x61): TOS Priority Control Register 1 ........................................................................................................... 75 Register 98 (0x62): TOS Priority Control Register 2 ........................................................................................................... 75 Register 99 (0x63): TOS Priority Control Register 3 ........................................................................................................... 75 Register 100 (0x64): TOS Priority Control Register 4 ......................................................................................................... 75 Register 101 (0x65): TOS Priority Control Register 5 ......................................................................................................... 75 Register 102 (0x66): TOS Priority Control Register 6 ......................................................................................................... 75 Register 103 (0x67): TOS Priority Control Register 7 ......................................................................................................... 75 Register 104 (0x68): MAC Address Register 0 ................................................................................................................... 76 Register 105 (0x69): MAC Address Register 1 ................................................................................................................... 76 Register 106 (0x6A): MAC Address Register 2................................................................................................................... 76 Register 107 (0x6B): MAC Address Register 3................................................................................................................... 76 Register 108 (0x6C): MAC Address Register 4................................................................................................................... 76 Register 109 (0x6D): MAC Address Register 5................................................................................................................... 76 Register 110 (0x6E): Indirect Access Control 0 .................................................................................................................. 76 Register 111 (0x6F): Indirect Access Control 1 .................................................................................................................. 76 Register 112 (0x70): Indirect Data Register 8..................................................................................................................... 77 Register 113 (0x71): Indirect Data Register 7..................................................................................................................... 77 Register 114 (0x72): Indirect Data Register 6..................................................................................................................... 77 Register 115 (0x73): Indirect Data Register 5..................................................................................................................... 77 Register 116 (0x74): Indirect Data Register 4..................................................................................................................... 77 Register 117 (0x75): Indirect Data Register 3..................................................................................................................... 77 Register 118 (0x76): Indirect Data Register 2..................................................................................................................... 77 Register 119 (0x77): Indirect Data Register 1..................................................................................................................... 77 Register 120 (0x78): Indirect Data Register 0..................................................................................................................... 77 Register 121 (0x79): Digital Testing Status 0...................................................................................................................... 77 Register 122 (0x7A): Digital Testing Status 1 ..................................................................................................................... 77 Register 123 (0x7B): Digital Testing Control 0 .................................................................................................................... 78 Register 124 (0x7C): Digital Testing Control 1.................................................................................................................... 78 Register 125 (0x7D): Analog Testing Control 0................................................................................................................... 78 Register 126 (0x7E): Analog Testing Control 1.................................................................................................................. 78 Register 127 (0x7F): Analog Testing Status ....................................................................................................................... 78 Static MAC Address Table ................................................................................................................................................... 78 VLAN Table.......................................................................................................................................................................... 79 Dynamic MAC Address Table .............................................................................................................................................. 80 MIB (Management Information Base) Counters................................................................................................................... 81 Absolute Maximum Ratings ................................................................................................................................................. 86 Recommended Operating Conditions .................................................................................................................................. 86 Electrical Characteristics...................................................................................................................................................... 87 100BASE-FX Electrical Specification................................................................................................................................... 88 EEPROM Timing .................................................................................................................................................................. 89 SNI Timing ........................................................................................................................................................................... 90 MII Timing ............................................................................................................................................................................ 91 6.3.1 MAC Mode MII Timing ............................................................................................................................................. 91 6.3.2 PHY Mode MII Timing.............................................................................................................................................. 92 6.3.3 SPI Timing ............................................................................................................................................................... 92 6.3.4 MDC/MDIO Timing................................................................................................................................................... 95 6.3.5 Auto Negotiation Timing .......................................................................................................................................... 96 Reset Timing ........................................................................................................................................................................ 97 Reset Circuit......................................................................................................................................................................... 98 5 Electrical Specifications ..............................................................................................................86 6 Timing Specifications..................................................................................................................89 6.4 6.5 June 2009 6 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL 7 Selection of Isolation Transformer ..............................................................................................99 8 Selection of Crystal/Oscillator.....................................................................................................99 9 Package Information.................................................................................................................100 June 2009 7 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL List of Tables Table 1: FX and TX Mode Selection.................................................................................................................................................. 26 Table 2: MDI/MDI-X Pin Definition..................................................................................................................................................... 27 Table 3: MII Signals........................................................................................................................................................................... 35 Table 4: SNI (7-wire) Signals............................................................................................................................................................. 35 Table 5: MII Management Interface frame format ............................................................................................................................. 36 Table 6: Serial Management Interface (SMI) frame format ............................................................................................................... 37 Table 7: FID+DA look up in VLAN mode........................................................................................................................................... 39 Table 8: FID+SA look up in VLAN mode ........................................................................................................................................... 39 Table 9: KS8993F SPI Connections.................................................................................................................................................. 44 Table 10: Format of Static MAC Table (8 entries) ............................................................................................................................. 79 Table 11: Format of Static VLAN Table (16 entries).......................................................................................................................... 80 Table 12: Format of Dynamic MAC Table (1K entries)...................................................................................................................... 81 Table 13: Format of “Per Port” MIB Counters.................................................................................................................................... 82 Table 14: Port 1’s “Per Port” MIB Counters Indirect Memory Offsets................................................................................................ 82 Table 15: Format of “All Port Dropped Packet” MIB Counters .......................................................................................................... 84 Table 16: “All Port Dropped Packet” MIB Counters Indirect Memory Offsets.................................................................................... 84 Table 17: EEPROM Timing Parameters............................................................................................................................................ 89 Table 18: SNI Timing Parameters ..................................................................................................................................................... 90 Table 19: MAC mode MII Timing Parameters ................................................................................................................................... 91 Table 20: PHY Mode MII Timing Parameters .................................................................................................................................... 92 Table 21: SPI Input Timing Parameters ............................................................................................................................................ 93 Table 22: SPI Output Timing Parameters.......................................................................................................................................... 94 Table 23: Reset Timing Parameters.................................................................................................................................................. 97 Table 24: Transformer Selection Criteria........................................................................................................................................... 99 Table 25: Qualified Single Port Magnetic .......................................................................................................................................... 99 Table 26: Crystal/Oscillator Selection Criteria ................................................................................................................................... 99 List of Figures Figure 1: Typical Straight Cable Connection ..................................................................................................................................... 28 Figure 2: Typical Crossover Cable Connection ................................................................................................................................. 28 Figure 3: Auto Negotiation and Parallel Detection ............................................................................................................................ 29 Figure 4: Destination Address look up flowchart, stage 1 ................................................................................................................. 31 Figure 5: Destination Address resolution flowchart, stage 2 ............................................................................................................. 32 Figure 6: 802.1p Priority Field Format............................................................................................................................................... 40 Figure 7: KS8993F EEPROM Configuration Timing Diagram ........................................................................................................... 42 Figure 8: SPI Write Data Cycle ......................................................................................................................................................... 45 Figure 9: SPI Read Data Cycle ......................................................................................................................................................... 45 Figure 10: SPI Multiple Write............................................................................................................................................................. 46 Figure 11: SPI Multiple Read............................................................................................................................................................. 46 Figure 12: EEPROM Interface Input Timing Diagram ....................................................................................................................... 89 Figure 13: EEPROM Interface Output Timing Diagram..................................................................................................................... 89 Figure 14: SNI Input Timing Diagram ................................................................................................................................................ 90 Figure 15: SNI Output Timing Diagram ............................................................................................................................................. 90 Figure 16: MAC Mode MII Timing - Data received from MII .............................................................................................................. 91 Figure 17: MAC Mode MII Timing - Data transmitted to MII .............................................................................................................. 91 Figure 18: PHY Mode MII Timing – Data received from MII .............................................................................................................. 92 Figure 19: PHY Mode MII Timing - Data transmitted to MII............................................................................................................... 92 Figure 20: SPI Input Timing............................................................................................................................................................... 93 Figure 21: SPI Output Timing ............................................................................................................................................................ 94 Figure 22: MDC/MDIO Timing for MIIM and SMI Interfaces .............................................................................................................. 95 Figure 23: Auto Negotiation Timing................................................................................................................................................... 96 Figure 24: Reset Timing .................................................................................................................................................................... 97 Figure 25: Recommended Reset Circuit ........................................................................................................................................... 98 Figure 26: Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output.................................................................... 98 Figure 27: 128-pin PQFP Package Outline Drawing ....................................................................................................................... 100 June 2009 8 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL 1 Signal Description 1.1 KS8993F Pin Diagram PV31 PS0 PS1 SPIS_N SDA SCL SPIQ MDIO MDC PRSEL0 PRSEL1 VDDC DGND SCONF0 SCONF1 SCRS SCOL SMRXD0 SMRXD1 SMRXD2 SMRXD3 SMRXDV SMRXC VDDIO DGND SMTXC SMTXER SMTXD0 SMTXD1 SMTXD2 SMTXD3 SMTXEN LEDSEL0 SMAC BPEN RST_N X2 X1 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PV32 PV21 PV23 DGND VDDIO PV12 PV13 P3_1PEN P2_1PEN P1_1PEN P3_TXQ2 P2_TXQ2 P1_TXQ2 P3_PP P2_PP P1_PP P3_TAGINS P2_TAGINS P1_TAGINS DGND VDDC P3_TAGRM P2_TAGRM P1_TAGRM TESTEN SCANEN 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 KS8993F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 AGND VDDAP AGND ISET TEST2 TEST1 AGND VDDA TXP2 TXM2 AGND RXP2 RXM2 VDDARX VDDATX TXM1 TXP1 AGND RXM1 RXP1 FXSD1 VDDA AGND MUX2 MUX1 AGND June 2009 P1LED2 P1LED1 P1LED0 P2LED2 P2LED1 P2LED0 DGND VDDIO MCHS MCCS PDD# ADVFC P2ANEN P2SPD P2DPX P2FFC P1FST P1CRCD P1LPBM P2LED3 DGND VDDC LEDSEL1 NC P1LED3 NC HWPOVR P2MDIXDIS P2MDIX P1ANEN P1SPD P1PDX P1FFC ML_EN DIAGF PWRDN AGND VDDA 9 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL 1.2 Pin # Pin Description and I/O Assignment Pin Name Type Description 1 2 3 P1LED2 P1LED1 P1LED0 I(pu)/O I(pu)/O I(pu)/O Port 1 LED indicators, defined as below: P1LED3 P1LED2 P1LED1 P1LED0 [LEDSEL1, LEDSEL0] [0,0] [0,1] ----------LINK/ACT 100LINK/ACT FULLD/COL 10LINK/ACT SPEED FULL_DPX P1LED3 P1LED2 P1LED1 P1LED0 [LEDSEL1, LEDSEL0] [1,0] [1,1] ACT -----LINK -----FULL_DPX/COL -----SPEED ------ Notes: LEDSEL0 is external strap-in pin #70. LEDSEL1 is external strap-in pin #23. P1LED3 is pin #25. During reset, P1LED[2:0] are inputs for internal testing. 4 5 6 P2LED2 P2LED1 P2LED0 I(pu)/O I(pu)/O I(pu)/O Port 2 LED indicators, defined as below: P2LED3 P2LED2 P2LED1 P2LED0 [LEDSEL1, LEDSEL0] [0,0] [0,1] ----------LINK/ACT 100LINK/ACT FULLD/COL 10LINK/ACT SPEED FULL_DPX P2LED3 P2LED2 P2LED1 P2LED0 [LEDSEL1, LEDSEL0] [1,0] [1,1] ACT -----LINK -----FULL_DPX/COL -----SPEED ------ Notes: LEDSEL0 is external strap-in pin #70. LEDSEL1 is external strap-in pin #23. P2LED3 is pin #20. During reset, P2LED[2:0] are inputs for internal testing. 7 8 DGND VDDIO Gnd Pwr Digital ground 3.3V digital VDD June 2009 10 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. Pin # Pin Name Type Description KS8993F/FL 9 10 MCHS MCCS Ipd Ipd KS8993F operating modes, defined as below: (MCHS, MCCS) Description Normal 3 port switch mode (3 MAC + 2 PHY) MC mode is disabled. Port 1 is either Fiber or UTP. Port 2 is UTP. Port 3 (MII) is enabled. Center MC mode (3 MAC + 2 PHY) MC mode is enabled. Port 1 is Fiber and has Center MC enabled. Port 2 is UTP. Port 3 (MII) is enabled. Terminal MC mode (2 MAC + 2 PHY) MC mode is enabled. Port 1 is Fiber and has Terminal MC enabled. Port 2 is UTP. Port 3 (MII) is disabled. Terminal MC mode (3 MAC + 2 PHY) MC mode is enabled. Port 1 is Fiber and has Terminal MC enabled. Port 2 is UTP. Port 3 (MII) is enabled. (0, 0) (0, 1) (1, 0) (1, 1) 11 PDD# Ipu Power Down Detect 1 = normal operation 0 = power down detected In Terminal MC mode (pin MCHS is ‘1’), a high to low transition to this pin will cause port 1 (fiber) to generate and send out an “Indicate Terminal MC Condition” OAM frame with the S0 status bit set to ‘1’. 12 13 14 15 ADVFC P2ANEN P2SPD P2DPX Ipu Ipu Ipd Ipd 16 P2FFC Ipd 17 18 P1FST P1LCRCD Opu Ipd 1= advertise the switch’s flow control capability via auto negotiation. 0 = will not advertise the switch’s flow control capability via auto negotiation. 1 = enable auto negotiation on port 2. 0 = disable auto negotiation on port 2. 1 = Force port 2 to 100BT if P2ANEN = 0. 0 = Force port 2 to 10BT if P2ANEN = 0. 1 = port 2 default to full duplex mode if P2ANEN = 1 and auto negotiation fails. Force port 2 in full duplex mode if P2ANEN = 0. 0 = port 2 default to half duplex mode if P2ANEN = 1 and auto negotiation fails. Force port 2 in half duplex mode if P2ANEN = 0. 1 = always enable (force) port 2 flow control feature. 0 = port 2 flow control feature enable is determined by auto negotiation result. 1 = normal function 0 = MC in loop back mode, or MC abnormal conditions happen In MC loop back mode, 1 = Drop OAM frames and Ethernet frames with the following errors – June 2009 11 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. Pin # Pin Name Type Description KS8993F/FL 19 20 P1LPBM P2LED3 Ipd Opd CRC, undersize, oversize. Loop back Ethernet frames with only good CRC and valid length. 0 = Drop OAM frames only. Loop back all Ethernet frames including those with errors. 0 = perform MC loop back at MAC of port 2 1 = reserve. Do not use. Port 2 LED Indicator Note: Internal pull down is weak; it will not turn ON the LED. See description in pin# (4). Digital ground VDDC : For KS8993F, this is an input power pin for the 1.8V digital core VDD. VOUT_1V8 : For KS8993FL, this is an 1.8V output power pin to supply the KS8993FL’s input power pins: VDDAP (pin 63), VDDC (pins 91, 123) and VDDA (pins 38, 43, 57). 21 22 DGND VDDC / VOUT_1V8 Gnd Pwr 23 LEDSEL1 Ipd LED display mode select See description in pin# (1,4). Reserved Port 1 LED Indicator Note: An external 1K pull down is needed on this pin if it is connected to a LED. See description in pin# (1). Reserved Hardware Pin Overwrite 0 = Disable. All strap-in pins configurations are overwritten by the EEPROM configuration data. 1 = Enable. All strap-in pins configurations are overwritten by the EEPROM configuration data, except for P2ANEN (pin 13), P2SPD (pin 14), P2DPX (pin 15) and ML_EN (pin 34). Port 2 auto MDI/MDI-X 0 = enable (default) 1 = disable Port 2 MDI/MDI-X setting when auto MDI/MDI-X is disabled 0 = MDI-X (default), {transmit on TXP2/TXM2 pins} 1 = MDI, {transmit on RXP2/RXM2 pins} 1 = enable auto negotiation on port 1 0 = disable auto negotiation on port 1 1 = Force port 1 to 100BT if P1ANEN = 0. 0 = Force port 1 to 10BT if P1ANEN = 0. 1 = port 1 default to full duplex mode if P1ANEN = 1 and auto negotiation fails. Force port 1 in full duplex mode if P1ANEN = 0. 0 = port 1 default to half duplex mode if P1ANEN = 1 and auto negotiation fails. Force port 1 in half duplex mode if P1ANEN = 0. 1 = always enable (force) port 1 flow control feature 0 = port 1 flow control feature enable is determined by auto negotiation result. 1 = enable missing link M9999-062509 hbwhelp@micrel.com or (408) 955-1690 24 25 NC P1LED3 Opd Opd 26 27 NC HWPOVR Opd Ipd 28 P2MDIXDIS Ipd 29 P2MDIX Ipd 30 31 32 P1ANEN P1SPD P1DPX Ipu Ipd Ipd 33 P1FFC Ipd 34 ML_EN Ipd June 2009 12 Micrel, Inc. Pin # Pin Name Type Description KS8993F/FL 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 DIAGF PWRDN AGND VDDA AGND MUX1 MUX2 AGND VDDA FXSD1 RXP1 RXM1 AGND TXP1 TXM1 VDDATX VDDARX RXM2 RXP2 AGND TXM2 TXP2 VDDA AGND TEST1 TEST2 ISET AGND VDDAP AGND X1 X2 Ipd I Gnd Pwr Gnd I I Gnd Pwr I I/O I/O Gnd I/O I/O Pwr Pwr I/O I/O Gnd I/O I/O Pwr Gnd I I O Gnd Pwr Gnd I O 0 = disable missing link 1 = diagnostic fail 0 = diagnostic normal Chip power down input (active low) Analog ground 1.8V analog VDD Analog ground Factory test pin – float for normal operation Factory test pin – float for normal operation Analog ground 1.8V analog VDD Fiber signal detect / factory test pin Physical receive or transmit signal (+ differential) Physical receive or transmit signal (- differential) Analog ground Physical transmit or receive signal (+ differential) Physical transmit or receive signal (- differential) 3.3V analog VDD 3.3V analog VDD Physical receive or transmit signal (– differential) Physical receive or transmit signal (+ differential) Analog ground Physical transmit or receive signal (– differential) Physical transmit or receive signal (+ differential) 1.8V analog VDD Analog ground Factory test pin – float for normal operation Factory test pin – float for normal operation Set physical transmit output current. Pull down this pin with a 3.01K 1% resistor to ground. Analog ground 1.8V analog VDD for PLL Analog ground 25 MHz crystal/oscillator clock connections Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant oscillator and X2 is a no connect. Note: Clock is +/- 50ppm for both crystal and oscillator. 67 68 RST_N BPEN Ipu Ipd 69 SMAC Ipd Hardware reset pin (active low) Half Duplex Backpressure 1 = enable 0 = disable Special Mac Mode In this mode, the switch will do faster backoffs than normal. 70 LEDSEL0 Ipd 1 = enable 0 = disable LED display mode select See description in pin# (1,4). Switch MII transmit enable Switch MII transmit data bit 3 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 71 72 SMTXEN SMTXD3 Ipd Ipd June 2009 13 Micrel, Inc. Pin # Pin Name Type Description KS8993F/FL 73 74 75 76 77 SMTXD2 SMTXD1 SMTXD0 SMTXER SMTXC Ipd Ipd Ipd Ipd Ipd/O 78 79 80 DGND VDDIO SMRXC Gnd Pwr Ipd/O 81 82 SMRXDV SMRXD3 O Ipd/O Switch MII transmit data bit 2 Switch MII transmit data bit 1 Switch MII transmit data bit 0 Switch MII transmit error Switch MII transmit clock Output in PHY MII mode Input in MAC MII mode Digital ground 3.3V digital VDD Switch MII receive clock Output in PHY MII mode Input in MAC MII mode Switch MII receive data valid Switch MII receive data bit 3 Strap option: Switch MII full duplex flow control PD (default) = disable PU = enable 83 SMRXD2 Ipd / O Switch MII receive bit 2 Strap option: Switch MII is in PD (default) = full duplex mode PU = half duplex mode 84 SMRXD1 Ipd/O Switch MII receive bit 1 Strap option: Switch MII is in PD (default) = 100Mbps mode PU = 10Mbps mode 85 SMRXD0 Ipd/O Switch MII receive bit 0 Strap option: Switch will accept packet size up to PD (default) = 1536 bytes (inclusive); PU = 1522 bytes (tagged), 1518 bytes (untagged) 86 87 88 89 SCOL SCRS SCONF1 SCONF0 Ipd/O Ipd/O Ipd Ipd Switch MII collision detect Switch MII carrier sense Switch MII interface configuration (SCONF1, SCONF0) (0,0) (0,1) (1,0) (1,1) Description disable, output tri-stated PHY mode MII MAC mode MII PHY mode SNI 90 91 92 DGND VDDC PRSEL1 Gnd Pwr Ipd Digital ground 1.8V digital VDD Priority Select Select queue servicing if using split queues. Use the table June 2009 14 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. Pin # Pin Name Type Description KS8993F/FL 93 PRSEL0 Ipd below to select the desired servicing. Note that this selection affects all split transmit queue ports in the same way. (PRSEL,PRSEL0) (0,0) (0,1) (1,0) (1,1) Description Transmit all high priority before low priority Transmit high priority and low priority at 10:1 ratio. Transmit high priority and low priority at 5:1 ratio. Transmit high priority and low priority at 2:1 ratio. 94 95 MDC MDIO Ipu Ipu/O MII Management interface: clock input MII Management interface: data input/output Note: An external 4.7K pull up is needed on this pin when it is in use. 96 SPIQ Opu SPI slave mode: serial data output See description in pin# (100, 101) SPI slave mode / I2C slave mode: clock input I2C master mode: clock output See description in pin# (100, 101) SPI slave mode: serial data input I2C master/slave mode: serial data input/output See description in pin# (100, 101) SPI slave mode: chip select (active low) When SPIS_N is high, the KS8993F is deselected and SPIQ is held in high impedance state. A high-to-low transition is used to initiate SPI data transfer. See description in pin# (100, 101) 97 SCL Ipu/O 98 SDA Ipu/O 99 SPIS_N Ipu 100 PS1 Ipd Serial bus configuration pins to select mode of access to KS8993F internal June 2009 15 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. Pin # Pin Name Type Description KS8993F/FL 101 PS0 Ipd registers. [PS1, PS0] = [0, 0] --- I2C master (EEPROM) mode (If EEPROM is not detected, the power up default values of the KS8993F internal registers will be used) Interface Signals Type Description SPIQ O Not used. (tri-stated) SCL O I2C clock SDA I/O I2C data I/O SPIS_N Ipu Not used. [PS1, PS0] = [0, 1] --- I2C slave mode The external I2C master will drive the SCL clock. The KS8993F device addresses are: 1011_1111 1011_1110 Interface Signals Type Description SPIQ O Not used. (tri-stated) SCL I I2C clock SDA I/O I2C data I/O SPIS_N Ipu Not used. [PS1, PS0] = [1, 0] --- SPI slave mode Interface Signals SPIQ SCL SDA SPIS_N Type O I I Ipu Description SPI Data Out SPI clock SPI Data In SPI chip select [PS1, PS0] = [1, 1] --- SMI mode In this mode, the KS8993F provides access to all its internal 8 bit registers thru its MDC and MDIO pins. Note W hen (PS1, PS0) ≠ (1,1), the KS8993F provides access to its 16 bit MIIM registers thru its MDC and MDIO pins. 102 103 PV31 PV32 Ipu Ipu Port 3 port based VLAN mask bits. Use to select which ports may transmit packets received on port 3. PV31 = 1, port 1 may transmit packets received on port 3. PV31 = 0, port 1 will not transmit any packets received on port 3. PV32 = 1, port 2 may transmit packets received on port 3. PV32 = 0, port 2 will not transmit any packets received on port 3. 104 105 PV21 PV23 Ipu Ipu Port 2 port based VLAN mask bits. Use to select which ports may transmit packets received on port 2. PV21 = 1, port 1 may transmit packets received on port 2. PV21 = 0, port 1 will not transmit any packets received on port 2. PV23 = 1, port 3 may transmit packets received on port 2. PV23 = 0, port 3 will not transmit any packets received on port 2. 106 DGND Gnd Digital ground June 2009 16 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. Pin # Pin Name Type Description KS8993F/FL 107 108 109 VDDIO PV12 PV13 Pwr Ipu Ipu 3.3V digital VDD Port 1 port based VLAN mask bits. Use to select which ports may transmit packets received on port 1. PV12 = 1, port 2 may transmit packets received on port 1. PV12 = 0, port 2 will not transmit any packets received on port 1. PV13 = 1, port 3 may transmit packets received on port 1. PV13 = 0, port 3 will not transmit any packets received on port 1. 110 P3_1PEN Ipd Enable 802.1p priority classification on port 3 ingress 1 = enable 0 = disable Enable is from the receive perspective. If 802.1p processing is disabled or there is no tag, priority is determined by the P3_PP pin. Enable 802.1p priority classification on port 2 ingress 1 = enable 0 = disable Enable is from the receive perspective. If 802.1p processing is disabled or there is no tag, priority is determined by the P2_PP pin. Enable 802.1p priority classification on port 1 ingress 1 = enable 0 = disable Enable is from the receive perspective. If 802.1p processing is disabled or there is no tag, priority is determined by the P1_PP pin. Select transmit queue split on port 3 1 = split 0 = no split The split sets up high and low priority queues. Packet priority classification is done on ingress ports, via port-based, 802.1p or TOS based scheme. The priority enabled queuing on port 3 is set by P3_TXQ2. Select transmit queue split on port 2 1 = split 0 = no split The split sets up high and low priority queues. Packet priority classification is done on ingress ports, via port-based, 802.1p or TOS based scheme. The priority enabled queuing on port 2 is set by P2_TXQ2. Select transmit queue split on port 1 1 = split 0 = no split The split sets up high and low priority queues. Packet priority classification is done on ingress ports, via port-based, 802.1p or TOS based scheme. The priority enabled queuing on port 1 is set by P1_TXQ2. 111 P2_1PEN Ipd 112 P1_1PEN Ipd 113 P3_TXQ2 Ipd 114 P2_TXQ2 Ipd 115 P1_TXQ2 Ipd 116 P3_PP Ipd Select port-based priority on port 3 ingress June 2009 17 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. Pin # Pin Name Type Description KS8993F/FL 1 = high 0 = low 802.1p and Diffserv, if applicable, will take precedence. 117 P2_PP Ipd Select port-based priority on port 2 ingress 1 = high 0 = low 802.1p and Diffserv, if applicable, will take precedence. Select port-based priority on port 1 ingress 1 = high 0 = low 802.1p and Diffserv, if applicable, will take precedence. Enable tag insertion on port 3 egress 1 = enable 0 = disable All packets transmitted from port 3 will have 802.1Q tag. Packets received with tag will be sent out intact. Packets received without tag will be tagged with ingress port’s default tag. Enable tag insertion on port 2 egress 1 = enable 0 = disable All packets transmitted from port 2 will have 802.1Q tag. Packets received with tag will be sent out intact. Packets received without tag will be tagged with ingress port’s default tag. Enable tag insertion on port 1 egress 1 = enable 0 = disable All packets transmitted from port 1 will have 802.1Q tag. Packets received with tag will be sent out intact. Packets received without tag will be tagged with ingress port’s default tag. Digital ground 1.8V digital VDD Enable tag removal on port 3 egress 1 = enable 0 = disable All packets transmitted from port 3 will not have 802.1Q tag. Packets received with tag will be modified by removing 802.1Q tag. Packets received without tag will be sent out intact. Enable tag removal on port 2 egress 1 = enable 0 = disable All packets transmitted from port 2 will not have 802.1Q tag. Packets received with tag will be modified by removing 802.1Q tag. Packets received without tag will be sent out intact. Enable tag removal on port 1 egress 118 P1_PP Ipd 119 P3_TAGINS Ipd 120 P2_TAGINS Ipd 121 P1_TAGINS Ipd 122 123 124 DGND VDDC P3_TAGRM Gnd Pwr Ipd 125 P2_TAGRM Ipd 126 P1_TAGRM Ipd June 2009 18 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. Pin # Pin Name Type Description KS8993F/FL 1 = enable 0 = disable All packets transmitted from port 1 will not have 802.1Q tag. Packets received with tag will be modified by removing 802.1Q tag. Packets received without tag will be sent out intact. 127 128 TESTEN SCANEN Ipd Ipd Scan Test Enable For normal operation, pull down this pin to ground Scan Test Scan Mux Enable For normal operation, pull down this pin to ground Note: Pwr = power supply; Gnd = ground; I = input; O = output; I/O = bi-directional Ipu = input w/ internal pull up; Ipd = input w/ internal pull down; Ipu/O = input w/ internal pull up during reset, output pin otherwise; Ipd/O = input w/ internal pull down during reset, output pin otherwise; PD = strap pull down; PU = strap pull up; Otri = output tri-stated; Opu = Output with internal pull-up; Opd = Output with internal pull-down June 2009 19 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL 2 Functional Description 2.1 Overview The KS8993F is a single-chip Fast Ethernet media converter. It contains two 10/100 physical layer transceivers, three MAC (Media Access Control) units, layer-2 managed switch, and frame buffer. On the media side, the KS8993F supports IEEE 802.3 10BASE-T, 100BASE-TX on ports 1 and 2, and 100BASE-FX on port 1. The KS8993F implements the unique OAM sub-layer, which resides between RS and PCS layer in the IEEE 802.3 standard. The KS8993F sends and receives an OAM frame that has a fixed length of 96 bits. This special frame is used for the transmission of OAM information between center MC and terminal MC. The KS8993F has the flexibility to reside in an unmanaged or managed design. An unmanaged design is achieved through I/O strapping or EEPROM programming at system reset time. In a managed design, a host processor has 2 complete control of the KS8993F via the SMI, MIIM, SPI or I C interface. The KS8993F supports advanced Quality Of Service, port mirroring, rate limiting, broadcast storm protection, and management via SNMP. The KS8993FL is the single supply version with all the identical rich features of the KS8993F. In the KS8993FL version, pin number 22 provides 1.8V output power to the KS8993FL’s VDDC, VDDA and VDDAP power pins. Refer to the pin description of pin number 22 in section 1.2, Pin Description and I/0 Assignment, for more details. Physical signal transmission and reception are enhanced through the use of patented analog circuitry that makes the design more efficient, and allows for lowest power consumption and smaller chip die size. 2.2 Media Converter Function The KS8993F is the industry’s first single-chip Fast Ethernet media converter that conforms to the TS-1000 spec. The TS-1000 spec. has been standardized by the TELECOMMUNICATION TECHNOLOGY COMMITTEE (TTC) of Japan in May 2002 and can be purchased from TTC. Some key TS-1000 features include: • • • • • • • Private point-to-point communication between two TS-1000 compliant devices 96 bits (12 bytes) frames for the transmission of OAM information between center MC and terminal MC Transmission of MC status between center MC and terminal MC Automatic generation of OAM frame to inform MC link partner of local MC’s status change Transmission of vendor code and model number information between center MC and terminal MC for device identification Inquisition of terminal MC status by center MC Remote loop back for diagnostic by center MC 2.2.1 OAM (Operations, Administration, and Management) Frame Format June 2009 20 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL Bit F0-F7 C0 C1 C2-C3 C4-C7 C8-C15 S0 S1 S2 S3 S4 S5 S6 S7 Command Preamble Conservation Delimiter Direction Delimiter Configuration Delimiter Version Control signal Power Optical UTP link MC Way for information Loop mode Terminal MC Link option Terminal MC Link Speed1 Terminal Speed2 MC Link Description 1010 1010 0 0: Upstream (from terminal MC to center MC) 1: Downstream (from center MC to terminal MC) 10: request 11:reponse 01: indication 00:reserved 0000 1000 0000: Start loop back test 0000 0000: Stop loop back test 0100 0000: Notify status 0: normal operation 1: power down 0: normal 1:abnormal 0: link up 1: link down 0: normal 1:brake 0: use conservation frame 1: use FEFI 0: normal operation 1: in loop mode 0: Center side MC have to set always “0” 1: Terminal side MC have to set always “1” This bit must be set “0” 0: 10Mbps 1: 100Mbps These bits have to be set “0”, if S2 is “1” (Center side MC have to set always “0”) 0: Half Duplex 1: Full Duplex This bit have to be set “0”, if S2 is “1” (Center side MC have to set always “0”) 0: Not Support Auto-Negotiation 1: Support Auto-Negotiation (Center side MC have to set always “0”) 0: one link partner on UTP side 1: multiple link partner on UTP side All bits must be set “0” S8 Status S9 Terminal Duplex MC Link S10 S11 S12 S15 M0-M23 M24-M47 E0-E7 – Terminal MC AutoNegotiation capability Multiple link partner Reserve Vendor code Model number FCS Create FCS at this sub-layer (C0-M47) June 2009 21 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL 2.2.2 MC (Media Converter) Mode MC (Media Converter) mode is selected and configured using hardware pins: MCCS and MCHS. Terminal MC mode without port 3 support is enabled when MCCS=0 and MCHS=1. In this mode, port 1 is 100BASEFX, port 2 is 10BASE-TX or 100BASE-TX and port 3 is disabled. Terminal MC function is enabled, and the OAM sublayer responds to the center MC with OAM frames, such as condition inform reply, loop mode start reply, and loop mode stop reply. Terminal MC mode with port 3 support is enabled when MCCS=1 and MCHS=1. In this mode, port 1 is 100BASE-FX, port 2 is 10BASE-T or 100BASE-TX and port 3 supports MII or SNI interface. Terminal MC function is enabled, and the OAM sub-layer responds to the center MC with OAM frames, such as condition inform reply, loop mode start reply, and loop mode stop reply. Center MC mode with port 3 support is enabled when MCCS=1 and MCHS=0. In this mode, port 1 is 100BASE-FX, port 2 is 10BASE-T or 100BASE-TX and port 3 supports MII or SNI interface. Center MC function is enabled, and the OAM sub-layer generates and sends OAM frames, such as condition inform request, loop mode start request and loop mode stop request to the terminal MC. Center Media Converter management Center office CPU OAM frame Reply command OAM frame Request command Terminal Media Converter Gateway/ Router 2.2.3 MC Loop Back Function June 2009 22 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL MC loop back operation is initiated and enabled by the center MC. The terminal MC provides the loop back path to return the loop back packet back to the center MC. In terminal MC mode, the KS8993F provides the following loop back path: • • • Receive loop back packet from center MC at RXP1/RXM1 input pins of port 1 (fiber). Turn around loop back packet at MAC of port 2 (copper). Transmit loop back packet back to center MC from TXP1/TXM1 output pins of port 1 (fiber). RX+ /RX- TX+ /TX- Fiber Port PMD/PMA PCS OAM MC MAC Switch MAC PCS UTP Port PMD/PMA 2.2.4 Registers for Media Converter Functions The KS8993F provides 32 dedicated registers (0x40 to 0x5F) for MC communication between center MC and terminal MC. Some MC register functions include: • • • • • • PHY address & configuration Loop back counters for CRC error, timeout, good packet Remote commands Counters for valid MC packet transmitted and received MC - status, vendor code, and model number Link Partner - status, vendor code, and model number 2.2.5 Unique I/O Feature Definition June 2009 23 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. Pin #27 Signal Name HWPOVR Type Input KS8993F/FL Description Hardware pin strapping to override the EEPROM value after reset When HWPOVR = 0, the reset sequence for KS8993F are: • Reads HW pin strapping configuration after reset. • Reads EEPROM configuration for all registers. When HWPOVR = 1, the reset sequence for KS8993F are: • Reads HW pin strapping configuration after reset. • Reads EEPROM configuration for all registers, except for port 2 (auto negotiation, speed, duplex) and Missing Link. When HWPOVR = 1 during normal switch operation: 1. Port 2 (auto negotiation, speed, duplex) can be updated via pins P2ANEN, P2SPD and P2DPX, respectively. These three pins are polled by the KS8993F. 2.2.6 Port 1 LED Indicator Definition LEDSEL1 = 0 LEDSEL0=0 P1LED3 Tri-state, Pull-Down Link/Activity LEDSEL0=1 Tri-state, Pull-Down 100BASE-TX Link/Activity 10BASE-T Link/Activity Full Duplex LEDSEL1 = 1 LEDSEL0=0 Activity LEDSEL0=1 --- P1LED2 Link --- P1LED1 Full Duplex/ Collision Speed Full Duplex/ Collision Speed --- P1LED0 --- 2.2.7 Port 2 LED Indicator Definition LEDSEL1 = 0 LEDSEL0=0 P2LED3 Tri-state, Pull-Down Link/Activity LEDSEL0=1 Tri-state, Pull-Down 100BASE-TX Link/Activity 10BASE-T Link/Activity Full Duplex LEDSEL1 = 1 LEDSEL0=0 Activity LEDSEL0=1 --- P2LED2 Link --- P2LED1 Full Duplex/ Collision Speed Full Duplex/ Collision Speed --- P2LED0 --- June 2009 24 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL 2.3 2.3.1 Physical Transceiver 100BASE-TX Transmit The 100BASE-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ to NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel to serial conversion, which converts the MII data from the MAC into a 125 MHz serial bit stream. The data and control stream is then converted into 4B/5B coding followed by a scrambler. The serialized data is further converted from NRZ to NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 3.01 KΩ resistor for the 1:1 transformer ratio. It has a typical rise/fall time of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter. 2.3.2 100BASE-TX Receive The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3 to NRZI conversion, data and clock recovery, NRZI to NRZ conversion, de-scrambling, 4B/5B decoding and serial to parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then it tunes itself for optimization. This is an ongoing process and can self adjust against environmental changes such as temperature variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of base line wander and improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC. 2.3.3 PLL Clock Synthesizer The KS8993F generates 125 MΗz, 31.25 MHz, 25 MΗz and 10 MΗz clocks for system timing. Internal clocks are generated from an external 25 MHz crystal or oscillator. 2.3.4 Scrambler/De-scrambler (100BASE-TX only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). The scrambler can generate a 2047-bit non-repetitive sequence. The receiver will then de-scramble the incoming data stream with the same sequence at the transmitter. 2.3.5 100BASE-FX Operation and Signal Detection 100BASE-FX operation is very similar to 100BASE-TX operation with the differences being that the scrambler/descrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In this mode, the auto negotiation feature is bypassed since there is no standard that supports fiber auto negotiation, and the auto MDI/MDI-X feature is also disabled. June 2009 25 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL For 100BASE-FX operation, the KS8993F FXSD1 (fiber signal detect) input pin is usually connected to the fiber transceiver SD (signal detect) output pin. 100BASE-FX mode is activated when FXSD1 is greater than 1V. When FXSD1 is between 1V and 1.8V, no fiber signal is detected and a Far-End Fault is generated if the feature is enabled. Alternatively, FXSD1 can be tied high to force 100BASE-FX mode if the Far-End Fault feature is not used. When FXSD1 is greater than 2.2V, the fiber signal is detected. 100BASE-FX signal detection is summarized in the following table. Table 1: FX and TX Mode Selection FXSD1 (pin 44) Condition Less than 0.2V Greater than 1V, but less than 1.8V Greater than 2.2V TX mode FX mode No signal detected; Far-End Fault generated (if enabled) FX mode Signal detected To ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver SD output voltage swing to match the KS8993F FXSD1 input voltage threshold. Refer to KS8993F schematic for recommended fiber transceiver connections. 2.3.6 100BASE-FX Far-End Fault (FEF) Far-End Fault (FEF) occurs when the signal detection is logically false on the receive side of the fiber transceiver. The KS8993F detects a FEF when its FXSD1 input is between 1.0V and 1.8V. When a FEF occurs, the transmission side signals the link partner by sending 84 ones followed by 1 zero in the idle period between frames. Upon receiving a FEF, the link will go down (even when the fiber signal is detected) to indicate a fault condition. The transmitting side is not affected when a FEF is received, and will continue to send out its normal transmit pattern from the MAC. By default, FEF is enabled. FEF can be disabled through register setting. 2.3.7 10BASE-T Transmit and Receive The output 10BASE-T driver is incorporated into the 100BASE-TX driver to allow transmission with the same magnetic. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3 V amplitude. The harmonic contents are at least 27 dB below the fundamental when driven by an all-ones Manchester-encoded signal. On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV or with short pulse widths in order to prevent noises at the RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KS8993F decodes a data frame. The receiver clock is maintained active during idle periods in between data reception. June 2009 26 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL 2.3.8 Power Management The KS8993F features a per-port power down mode. To save power, a port that is not being used can be powered down through the port control registers, or MIIM control registers. In addition, there is a full chip power down mode. When activated, the entire chip will be shut down. 2.3.9 Auto MDI/MDI-X Crossover The KS8993F supports auto MDI/MDI-X crossover. This facilitates the use of either a straight connection CAT-5 cable or a crossover CAT-5 cable. The auto-sense function will detect remote transmit and receive pairs, and correctly assign the transmit and receive pairs from the KS8993F device. This feature can be extremely useful when the end users are unaware of cable type differences, and can also save on an additional uplink configuration connection. By default, auto MDI/MDI-X is enabled. It can be disabled through the port control registers. Based on the IEEE 802.3 standard, the MDI and MDI-X definitions are as follows: Table 2: MDI/MDI-X Pin Definition MDI MDI-X RJ45 pins 1 2 3 6 Signals TD+ TDRD+ RD- RJ45 pins 1 2 3 6 Signals RD+ RDTD+ TD- A “Straight Cable” connects a MDI device to a MDI-X device, or a MDI-X device to a MDI device. The following diagram depicts a typical “Straight Cable” connection between a NIC card (MDI) and a switch, or hub (MDI-X). June 2009 27 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. Figure 1: Typical Straight Cable Connection KS8993F/FL 1 0 /1 0 0 E th e rn e t M e d ia D e p e n d e n t I n t e r f a c e 1 0 /1 0 0 E th e rn e t M e d ia D e p e n d e n t I n t e r f a c e 1 1 T r a n s m it P a ir 2 3 4 2 R e c e iv e P a ir S tra ig h t C a b le 3 4 R e c e iv e P a ir 5 6 7 8 5 6 7 8 T r a n s m it P a ir M o d u la r C o n n e c t o r (R J 4 5 ) N IC M o d u la r C o n n e c t o r (R J 4 5 ) HUB ( R e p e a t e r o r S w it c h ) A “Crossover Cable” connects a MDI device to another MDI device, or a MDI-X device to another MDI-X device. The following diagram depicts a typical “Crossover Cable” connection between two switches, or hubs (two MDI-X devices). Figure 2: Typical Crossover Cable Connection 1 0 /1 0 0 E th e rn e t M e d ia D e p e n d e n t In te r f a c e 1 0 /1 0 0 E t h e r n e t M e d ia D e p e n d e n t I n t e r f a c e 1 R e c e iv e P a ir 2 3 4 C ro s s o v e r C a b le 1 R e c e iv e P a ir 2 3 4 T r a n s m it P a ir 5 6 7 8 5 6 7 8 T r a n s m it P a ir M o d u la r C o n n e c t o r ( R J 4 5 ) HUB ( R e p e a te r o r S w itc h ) M o d u la r C o n n e c t o r ( R J 4 5 ) HUB ( R e p e a t e r o r S w it c h ) June 2009 28 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL 2.3.10 Auto Negotiation The KS8993F conforms to the auto negotiation protocol as described by the 802.3 committee. Auto negotiation allows UTP (Unshielded Twisted Pair) link partners to select the best common mode of operation. In auto negotiation the link partners advertise capabilities across the link to each other. If auto negotiation is not supported or the link partner to the KS8993F is forced to bypass auto negotiation, then the mode is set by observing the signal at the receiver. This is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol. The link set up is depicted in the following flow diagram. Figure 3: Auto Negotiation and Parallel Detection Start Auto Negotiation Force Link Setting No Parallel Operation Yes Bypass Auto Negotiation and Set Link Mode Attempt Auto Negotiation Listen for 100BaseTX Idles Listen for 10BaseT Link Pulses No Join Flow Link Mode Set ? Yes Link Mode Set 2.4 2.4.1 MAC and Switch Function Address Look Up The internal look up table stores MAC addresses and their associated information. It contains a 1K uni-cast address table plus switching information. The KS8993F is guaranteed to learn 1K addresses and distinguishes itself from hashbased look up tables, which depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn. June 2009 29 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL 2.4.2 Learning The internal look up engine will update its table with a new entry if the following conditions are met: 1. The received packet's Source Address (SA) does not exist in the look up table. 2. The received packet is good, has no receiving errors, and is of legal length. The look up engine will insert the qualified Source Address into the table, along with the port number and time stamp. If the table is full, the last entry of the table will be deleted to make room for the new entry. 2.4.3 Migration The internal look up engine also monitors whether a station has moved. If so, it will update the table accordingly. Migration happens when the following conditions are met: 1. The received packet's Source Address (SA) is in the table but the associated source port information is different. 2. The received packet is good, has no receiving errors, and is of legal length. The look up engine will update the existing record in the table with the new source port information. 2.4.4 Aging The look up engine will update the time stamp information of a record whenever the corresponding Source Address appears. The time stamp is used in the aging process. If a record is not updated for a period of time, the look up engine will remove the record from the table. The look up engine constantly performs the aging process and will continuously remove aging records. The aging period is 200 seconds. This feature can be enabled or disabled through Global Register 3 (0x03). 2.4.5 Forwarding The KS8993F will forward packets using an algorithm that is depicted in the following flowcharts. Figure 4 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by Spanning Tree, Port Mirroring and Port VLAN processes to come up with “port to forward 2” (PTF2) as shown in Figure 5. PTF2 is where the packet will be sent. June 2009 30 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. Figure 4: Destination Address look up flowchart, stage 1 KS8993F/FL Start PTF1 = NULL NO VLAN ID valid? -Search VLAN table -Ingress VLAN filtering -Discard NPVID check YES Search complete. Get PTF1 from Static MAC Table FOUND Search Static Table This search is based on DA or DA+FID NOT FOUND Search complete. Get PTF1 from Dynamic MAC Table FOUND Dynamic Table Search This search is based on DA+FID NOT FOUND Search complete. Get PTF1 from VLAN Table PTF1 June 2009 31 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. Figure 5: Destination Address resolution flowchart, stage 2 KS8993F/FL PTF1 Port Mirror Process - RX Mirror - TX Mirror - RX or TX Mirror - RX and TX Mirror Port VLAN Membership Check PTF2 June 2009 32 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL The KS8993F will not forward the following packets: 1. Error packets. These include framing errors, FCS errors, alignment errors, and illegal size packet errors. 2. 802.3x pause frames. The KS8993F will intercept these packets and perform the appropriate actions. 3. “Local" packets. Based on Destination Address (DA) look up, if the destination port from the look up table matches the port where the packet was from, the packet is defined as "local". 2.4.6 Switching Engine The KS8993F features a high-performance switching engine to move data to and from the MAC using built-in frame buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The KS8993F has a 32KB internal frame buffer. This resource is shared between all three ports. The buffer sharing mode can be programmed through Global Register 2 (0x02). In one mode, ports are allowed to use any free buffers in the buffer pool. In the second mode, each port is only allowed to use 1/3 of the total buffer pool. There are a total of 250 buffers available. Each buffer is 128 bytes in size. 2.4.7 MAC operation The KS8993F strictly abides by IEEE 802.3 standards to maximize compatibility. Inter Packet Gap (IPG) If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the current packet is experiencing collision, the 96-bit time IPG is measured from MCRS and the next MTXEN. 2.4.8 Back-off Algorithm The KS8993F implements the IEEE Standard 802.3 binary exponential back-off algorithm, and optional "aggressive mode" back-off. After 16 collisions, the packet will be optionally dropped depending on the chip configuration in Global Register 3 (0x03). 2.4.9 Late Collision If a transmit packet experiences collisions after 512 bit times of the transmission, the packet will be dropped. 2.4.10 Illegal Frames The KS8993F discards frames less than 64 bytes long and can be programmed to accept frames up to 1536 bytes long in Global Register 4 (0x04). For special applications, the KS8993F can also be programmed to accept frames up to 1916 bytes long in the same global register. Since the KS8993F supports VLAN tags, the maximum sizing is adjusted when these tags are present. 2.4.11 Flow Control The KS8993F supports standard 802.3x flow control frames on both transmit and receive sides. On the receive side, if the KS8993F receives a pause control frame, the KS8993F will not transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires, the timer will be updated with the new value from the second pause frame. During this period (being flow controlled), only flow control packets from the KS8993F will be transmitted. June 2009 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 33 Micrel, Inc. KS8993F/FL On the transmit side, the KS8993F has intelligent and efficient means to determine when to invoke flow control. The flow control is based on the availability of system resources, including available buffers, available transmit queues and available receive queues. The KS8993F will flow control a port, which just received a packet, if the destination port resource is being used up. The KS8993F will issue a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802.3x. Once the resource is freed up, the KS8993F will send out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent the flow control mechanism from being activated and deactivated too many times. The KS8993F will flow control all ports if the receive queue becomes full. 2.4.12 Half Duplex Back Pressure A half-duplex back-pressure option (Note: not in IEEE 802.3 standards) is also provided. The activation and deactivation conditions are the same as the above in full duplex mode. If back-pressure is required, the KS8993F will send preambles to defer the other stations' transmission (carrier sense deference). To avoid jabber and excessive deference defined in 802.3 standard, after a certain time it will discontinue the carrier sense but it will raise the carrier sense quickly. This short silent time (no carrier sense) is to prevent other stations from sending out packets and keeps other stations in carrier sense deferred state. If the port has packets to send during a back-pressure situation, the carrier sense type back-pressure will be interrupted and those packets will be transmitted instead. If there are no more packets to send, carrier sense type back-pressure will be active again until switch resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is generated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets. To ensure no packet loss in 10 BASE-T or 100 BASE-TX half duplex modes, the following should be enabled: 1. Aggressive back off (set Global Register 3 (0x03), bit 0 to ‘1’, or pull high SMAC (pin 69)) 2. No excessive collision drop (set Global Register 4 (0x04), bit 3 to ‘1’, or pull high SMAC (pin 69)) These bits are not set as defaults because the settings are not part of the IEEE standard. 2.4.13 Broadcast Storm Protection The KS8993F has an intelligent option to protect the switch system from receiving too many broadcast packets. Broadcast packets will be forwarded to all ports except the source port, and thus use too many switch resources (bandwidth and available space in transmit queues). The KS8993F has the option to include “multicast packets” for storm control. The broadcast storm rate parameters are programmed globally, and can be enabled or disabled on a per port basis. The rate is based on a 67ms interval for 100BT and a 500 ms interval for 10BT. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during the interval. The rate definition is described in Global Registers 6 (0x06) and 7 (0x07). The default setting for registers 6 and 7 is 0x63, which is 99 decimal. This is equal to a rate of 1 %, calculated as follows: 148,800 frames/sec * 67 ms/interval * 1% = 99 frames/interval (approx.) = 0x63h This means the KS8993F accepts only 1% of broadcast data and filters out 99%. 2.5 MII Interface Operation June 2009 34 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL The MII (Media Independent Interface) is specified by the IEEE 802.3 committee and provides a common interface between physical layer and MAC layer devices. The MII Interface provided by the KS8993F is connected to the device’s third MAC. The interface contains two distinct groups of signals: one for transmission and the other for reception. The following table describes the signals used in the MII interface. Table 3: MII Signals KS8993F PHY mode connections External MAC signals MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC KS8993F PHY signals SMTXEN SMTXER SMTXD[3] SMTXD[2] SMTXD[1] SMTXD[0] SMTXC SCOL SCRS SMRXDV (not used) SMRXD[3] SMRXD[2] SMRXD[1] SMRXD[0] SMRXC Pin Description Transmit enable Transmit error Transmit data bit 3 Transmit data bit 2 Transmit data bit 1 Transmit data bit 0 Transmit clock Collision detection Carrier sense Receive data valid Receive error Receive data bit 3 Receive data bit 2 Receive data bit 1 Receive data bit 0 Receive clock KS8993F MAC mode connections External PHY signals MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC KS8993F MAC signals SMRXDV (not used) SMRXD[3] SMRXD[2] SMRXD[1] SMRXD[0] SMRXC SCOL SCRS SMTXEN SMTXER SMTXD[3] SMTXD[2] SMTXD[1] SMTXD[0] SMTXC The MII interface operates in either PHY mode or MAC mode. The interface is a nibble wide data interface, and therefore runs at ¼ the network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has indicators that convey when the data is valid and without physical layer errors. For half duplex operation, there is a signal that indicates a collision has occurred during transmission. Note that the signal MRXER is not provided on the interface for PHY mode operation and the signal MTXER is not provided on the interface for MAC mode operation. Normally, MRXER would indicate a receive error coming from the physical layer device. MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for this configuration. For PHY mode operation, if the device interfacing with the KS8993F has an MRXER pin, it should be tied low. For MAC mode operation, if the device interfacing with the KS8993F has an MTXER pin, it should be tied low. 2.6 SNI (7-wire) Interface Operation The SNI (Serial Network Interface) or 7-wire is compatible with some controllers used for network layer protocol processing. In SNI mode, the KS8993F acts like a PHY and the external controller functions as the MAC. The KS8993F can interface directly with external controllers using the 7-wire interface. These signals are divided into two groups, one for transmission and the other for reception. The signals involved are described in the following table. Table 4: SNI (7-wire) Signals Pin Description SNI signals KS8993F signals June 2009 35 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. Transmit enable Serial transmit data Transmit clock Collision detection Carrier sense Serial receive data Receive clock TXEN TXD TXC COL CRS RXD RXC SMTXEN SMTXD[0] SMTXC SCOL SMRXDV SMRXD[0] SMRXC KS8993F/FL The SNI interface is a bit wide data interface and therefore runs at the network bit rate (not encoded). An additional signal on the transmit side indicates when data is valid. Similarly, the receive side has an indicator that conveys when the data is valid. For half duplex operation, the KS8993F SCOL signal is used to indicate that a collision has occurred during transmission. 2.7 MII Management Interface (MIIM) The KS8993F supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input / Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the KS8993F. An external device with MDC/MDIO capability can be used to read the PHY status or configure the PHY settings. Further details on the MIIM interface can be found in section 22.2.4.5 of the IEEE 802.3 specification. The MIIM interface consists of the following: A physical connection that incorporates the data line (MDIO) and the clock line (MDC). A specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with the KS8993F device. Access to a set of six 16-bits registers, consisting of standard MIIM registers [0:5]. The following table depicts the MII Management Interface frame format. Table 5: MII Management Interface frame format PHY Address Bits [4:0] Read 32 1’s 01 10 xx0AA REG Address Bits [4:0] RRRRR Z0 Data TA Bits [15:0] Idle Preamble Start of Frame Read/Write OP Code DDDDDDDD_DDDDDDDD Z Write 32 1’s 01 01 xx0AA RRRRR 10 DDDDDDDD_DDDDDDDD Z For the KS8993F, MIIM register access is selected when bit 2 of the PHY address is set to ‘0’. PHY address bits [4:3] are not defined for MIIM register access, and hence can be set to either 0’s or 1’s in read/write operation. 2.8 Serial Management Interface (SMI) June 2009 36 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL The Serial Management Interface is the KS8993F non-standard MIIM interface that provides access to all KS8993F configuration registers. This interface allows an external device to completely monitor and control the states of the KS8993F. The SMI interface consists of the following: A physical connection that incorporates the data line (MDIO) and the clock line (MDC). A specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with the KS8993F device. Access to all KS8993F configuration registers. Registers access includes the Global, Port and Advanced Control Registers 0-127 (0x00 – 0x7F), and indirect access to the standard MIIM registers [0:5]. The following table depicts the Serial Management Interface frame format. Table 6: Serial Management Interface (SMI) frame format PHY Address Bits [4:0] Read 32 1’s 01 10 RR1xx REG Address Bits [4:0] RRRRR Z0 Preamble Start of Frame Read/Write OP Code Data TA Bits [15:0] Idle 0000_0000_DDDD_DDDD Z Write 32 1’s 01 01 RR1xx RRRRR 10 xxxx_xxxx_DDDD_DDDD Z For the KS8993F, SMI register access is selected when bit 2 of the PHY address is set to ‘1’. PHY address bits [1:0] are not defined for SMI register access, and hence can be set to either 0’s or 1’s in read/write operation. To access the KS8993F registers 0-127 (0x00 – 0x7F), the following applies: PHYAD[4:3] and REGAD[4:0] are concatenated to form the 7-bits address. i.e., {PHYAD[4:3], REGAD[4:0]} = bits [6:0] of the 7-bits address. Registers are 8 data bits wide. For read operation, data bits [15:8] are read back as 0’s. For write operation, data bits [15:8] are not defined, and hence can be set to either 0’s or 1’s. SMI register access is the same as the MIIM register access, except for the register access requirements presented in this section. 2.9 2.9.1 Advanced Switch Function Port Mirroring Support June 2009 37 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F supports “Port Mirroring” comprehensively as: KS8993F/FL 1) “receive only” mirror on a port All the packets received on the port will be mirrored on the sniffer port. For example, port 1 is programmed to be “receive sniff” and port 3 is programmed to be the “sniffer port”. A packet, received on port 1, is destined to port 2 after the internal look up. The KS8993F will forward the packet to both port 2 and port 3. The KS8993F can optionally forward even “bad” received packets to the “sniffer port”. 2) “transmit only” mirror on a port All the packets transmitted on the port will be mirrored on the sniffer port. For example, port 1 is programmed to be “transmit sniff” and port 3 is programmed to be the “sniffer port”. A packet received on port 2 is destined to port 1 after the internal look up. The KS8993F will forward the packet to both port 1 and port 3. 3) “receive and transmit” mirror on two ports All the packets received on port A and transmitted on port B will be mirrored on the sniffer port. To turn on the “AND” feature, set register 5 bit 0 to “1”. For example, port 1 is programmed to be “receive sniff”, port 2 is programmed to be “transmit sniff” and port 3 is programmed to be the “sniffer port”. A packet received on port 1 is destined to port 2 after the internal look up. The KS8993F will forward the packet to both port 2 and 3. Multiple ports can be selected to be “receive sniff” or “transmit sniff”. And any port can be selected to be the “sniffer port”. All these per port features can be selected through registers 17, 33 and 49 for ports 1, 2 and 3, respectively. 2.9.2 IEEE 802.1Q VLAN support The KS8993F supports 16 active VLANs out of the 4096 possible VLANs specified in the IEEE 802.1Q specification. KS8993F provides a 16-entries VLAN Table, which converts the 12-bits VLAN ID (VID) to the 4-bits Filter ID (FID) for address look up. If a non-tagged or null-VID-tagged packet is received, the ingress port default VID is used for look up. In VLAN mode, the look up process starts with VLAN Table look up to determine whether the VID is valid. If the VID is not valid, the packet will be dropped and its address will not be learned. If the VID is valid, the FID is retrieved for further look up. The FID + Destination Address (FID+DA) are used to determine the destination port. The FID + Source Address (FID+SA) are used for address learning. June 2009 38 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL Table 7: FID+DA look up in VLAN mode DA+FID found in Dynamic MAC Table? No DA found in Static MAC Table? Use FID flag? FID match? Action No Don’t care Don’t care Broadcast to the membership ports defined in the VLAN Table bits [18:16] Send to the destination port defined in the Dynamic MAC Address Table bits [53:52] Send to the destination port(s) defined in the Static MAC Address Table bits [50:48] Broadcast to the membership ports defined in the VLAN Table bits [18:16] Send to the destination port defined in the Dynamic MAC Address Table bits [53:52] Send to the destination port(s) defined in the Static MAC Address Table bits [50:48] No Don’t care Don’t care Yes Yes 0 Don’t care Don’t care Yes 1 No No Yes 1 No Yes Yes 1 Yes Don’t care Table 8: FID+SA look up in VLAN mode FID+SA found in Dynamic MAC Table? No Yes Action Learn and add FID+SA to the Dynamic MAC Address Table Update time stamp Advanced VLAN features, such as “Ingress VLAN filtering” and “Discard Non PVID packets” are also supported by the KS8993F. These features can be set on a per port basis, and are defined in register 18, bit 6 and 5, respectively for port 1. 2.9.3 QoS Priority This feature provides Quality of Service (QoS) for applications, such as VoIP and video conferencing. The KS8993F per port transmit queue could be split into two priority queues: a high priority queue and a low priority queue. Bit 0 of registers 16, 32 and 48 is used to enable split transmit queues for ports 1, 2 and 3, respectively. Optionally, the Px_TXQ2 strap-in pins can be used to enable this feature. With split transmit queues, high priority packets will be placed in the high priority queue and low priority packets will be placed in the low priority queue. June 2009 39 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. For split transmit queues, the KS8993F provides four priority schemes: KS8993F/FL 1. “Transmit all high priority packets before low priority packets”, i.e. a low priority packet could be transmitted only when the high priority queue is empty; 2. “Transmit high priority packets and low priority packets at 10:1 ratio”, i.e. transmit a low priority packet after every 10 high priority packets are transmitted, if both queues are busy; 3. “Transmit high priority packets and low priority packets at 5:1 ratio”; 4. “Transmit high priority packets and low priority packets at 2:1 ratio”. If a port's transmit queue is not split, both high priority packets and low priority packets have equal priority in the transmit queue. Register 5 bits [3:2] are used to select the desired priority scheme. Optionally, the PRSEL1 and PRSEL0 strap-in pins can be used. Port based priority W ith port based priority, each ingress port can be individually classified as a high priority receiving port. All packets received at the high priority receiving port are marked as high priority, and will be sent to the high priority transmit queue if the corresponding transmit queue is split. Bit 4 of registers 16, 32 and 48 is used to enable port based priority for ports 1, 2 and 3, respectively. Optionally, the Px_PP strap-in pins can be used to enable this feature. 802.1p based priority For 802.1p based priority, the KS8993F will examine the ingress (incoming) packets to determine whether they are tagged. If tagged, the 3-bits priority field in the VLAN tag is retrieved and compared against the “priority base” value, specified by register 2 bits [6:4]. The “priority base” value is programmable; its default value is 0x4. The following figure illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag. Figure 6: 802.1p Priority Field Format Bytes 8 Preamble 6 DA 6 SA 2 VPID 2 TCI 2 length LLC 46-1500 Data 4 FCS Bits 16 Tagged Packet Type (8100 for Ethernet) 3 802.1p 1 CFI 12 VLAN ID 802.1q VLAN Tag If an ingress packet has an equal or higher priority value than the "priority base" value, the packet will be placed in the high priority transmit queue if the corresponding transmit queue is split. 802.1p based priority is enabled by bit 5 of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. Optionally, the Px_1PEN strap-in pins can be used to enable this feature. The KS8993F provides the option to insert or remove the priority tagged frame's header at each individual egress port. This header, consisting of the 2 bytes VLAN Protocol ID (VPID) and the 2 bytes Tag Control Information field (TCI), is also refer to as the 802.1Q VLAN Tag. June 2009 40 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL Tag insertion is enabled by bit 2 of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. Optionally, the Px_TAGINS strap-in pins can be used to enable this feature. At the egress port, untagged packets are tagged with the ingress port’s default tag. The default tags are programmed in register sets {19,20}, {35,36} and {51,52} for ports 1, 2 and 3, respectively. The KS8993F will not add tags to already tagged packets. Tag removal is enabled by bit 1 of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. Optionally, the Px_TAGRM strap-in pins can be used to enable this feature. At the egress port, tagged packets will have their 802.1Q VLAN Tags removed. The KS8993F will not modify untagged packets. The CRC is recalculated for both tag insertion and tag removal. 802.1p priority field re-mapping is a QoS feature that allows the KS8993F to set the “User Priority Ceiling” at any ingress port. If the ingress packet’s priority field has a higher priority value than the default tag’s priority field of the ingress port, the packet’s priority field is replaced with the default tag’s priority field. The “User Priority Ceiling” is enabled by bit 3 of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. DiffServ based priority DiffServ based priority uses registers 96 to 103. More details are provided at the beginning of the Advanced Control Registers section. 2.9.4 Rate Limit Support The KS8993F supports hardware rate limiting independently on the “receive side” and on the “transmit side” on a per port basis. Rate limiting is supported in both priority and non-priority environment. The rate limit starts from 0 kbps and goes up to the line rate in steps of 32 kbps. The KS8993F uses “one second” as the rate limiting interval. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during the interval. On the “receive side”, if the number of bytes exceeds the programmed limit, the switch will stop receiving packets on the port until the “one second” interval expires. Flow control can be enabled to prevent packet loss. If the rate limit is programmed greater than or equal to 128 kbps and the byte counter is 8 Kbytes below the limit, flow control will be triggered. If the rate limit is programmed lower than 128 kbps and the byte counter is 2 Kbytes below the limit, flow control will also be triggered. On the “transmit side”, if the number of bytes exceeds the programmed limit, the switch will stop transmitting packets on the port until the “one second” interval expires. If priority is enabled, the KS8993F can be programmed to support different rate limits for high priority packets and low priority packets. 2.10 Configuration Interface The KS8993F can operate as both a managed switch and an unmanaged switch. In unmanaged mode, the KS8993F is typically programmed using an EEPROM. If no EEPROM is present, the KS8993F is configured using its default register settings. Some default register settings can be overridden via strap-in pin options. The strap-in pins are indicated in the “KS8993F Pin Description and I/O Assignment” table in section 1.2. June 2009 41 M9999-062509 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. KS8993F/FL 2.10.1 I2C Master Serial Bus Configuration W ith an additional I C (“2-wire”) EEPROM, the KS8993F can perform more advanced switch features like “broadcast storm protection” and “rate control” without the need of an external processor. For KS8993F I C Master configuration, the EEPROM stores the configuration data for register 0 to register 109 (as defined in the KS8993F register map) with the exception of the “Read Only” status registers. After the de-assertion of reset, the KS8993F will sequentially read in the configuration data for all 110 registers, starting from register 0. The configuration access time (tprgm) is less than 15 ms, as depicted in the following figure. Figure 7: KS8993F EEPROM Configuration Timing Diagram 2 2 RST_N SCL SDA .... .... .... tprgm= : classified as high priority < : classified as low priority 3 Pass flow control packet Buffer share mode Reserved Link change age R/W = 1, switch will not filter 802.1x “flow control” packets KS8993F/FL 0x0 2 R/W 1 0 R/W R/W = 1, buffer pool is shared by all ports. A port can use more buffer when other ports are not busy. = 0, a port is only allowed to use 1/3 of the buffer pool Reserved = 1, link change from “link” to “no link” will cause fast aging (