ADC0838BCV

May 1997 ML2281, ML2282*, ML2284#, ML2288# Serial I/O 8-Bit A/D Converters with Multiplexer Options GENERAL DESCRIPTION The ML2281 family are 8-bit successive approximation A/D converters with serial I/O and configurable input multiplexers with up to 8 input channels. All errors of the sample-and-hold, incorporated on the ML2281 family are accounted for in the analog-to-digital converters accuracy specification. The voltage reference can be externally set to any value between GND and VCC, thus allowing a full conversion over a relatively small voltage span if desired. The ML2281 family is an enhanced double polysilicon CMOS pin compatible second source for the ADC0831, ADC0832, ADC0834, and ADC0838 A/D converters. The ML2281 series enhancements are faster conversion time, true sample-and-hold function, superior power supply rejection, improved AC common mode rejection, faster digital timing, and lower power dissipation. All parameters are guaranteed over temperature with a power supply voltage of 5V ±10%. FEATURES s Conversion time: 6µs s Total unadjusted error: ±1/2LSB or ±1LSB s Sample-and-hold: 375ns acquisition s 2, 4 or 8-input multiplexer options s 0 to 5V analog input range with single 5V power supply s Operates ratiometrically or with up to 5V voltage reference s No zero or full-scale adjust required s ML2281 capable of digitizing a 5V, 40kHz sine wave s Low power: 12.5mW MAX s Superior pin compatible replacement for ADC0831, ADC0832, ADC0834, and ADC0838 s Analog input protection: 25mA (min) per input s Now in 8-Pin SOIC Package (ML2281, ML2282) (* Indicates Part is Obsolete) (# Indicates Part is End Of Life as Of July 1, 2000) BLOCK DIAGRAM ML2281 CONTROL AND TIMING CS CLK ML2288 (8-Channel SE or 4-Channel Diff Multiplexer) ML2284 (4-Channel SE or 2-Channel Diff Multiplexer) ML2284 (2-Channel SE or 1-Channel Diff Multiplexer) DI INPUT SHIFT-REGISTER SARS OUTPUT SHIFT-REGISTER DO 4-BIT CONTROL AND TIMING CLK CS VIN+ A/D WITH SAMPLE & HOLD FUNCTION + SUCCESSIVE + APPROXIMATION COMP – – REGISTER 8pF Σ OUTPUT SHIFT-REGISTER CH0 CH2 CH3 CH4 CH5 CH6 CH7 MULTIPLEXER (ML2288 SHOWN) DO CH1 VREF SE VIN– D/A CONVERTER 8pF A/D CONVERTER WITH SAMPLE & HOLD FUNCTION DGND SHUNT REGULATOR AGND VREF VCC V+ VCC GND COMMON 1 ML2281, ML2282, ML2284, ML2288 PIN CONFIGURATION ML2281 Single Differential Input 8-Pin DIP CS VIN+ VIN– GND 1 2 3 4 8 7 6 5 ML2282 2-Channel MUX 8-Pin DIP CS CH0 CH1 GND 1 2 3 4 8 7 6 5 VCC CLK DO VREF VCC (VREF) CLK DO DI TOP VIEW TOP VIEW ML2281 8-Pin SOIC CS VIN+ VIN– GND 1 2 3 4 8 7 6 5 ML2282 8-Pin SOIC VCC CLK DO VREF CS CH0 CH1 GND 1 2 3 4 8 7 6 5 VCC (VREF) CLK DO DI TOP VIEW TOP VIEW ML2284 14-Pin SOIC ML2284 4-Channel MUX 14-Pin DIP VCC DI CLK SARS DO VREF AGND V+ CS CH0 CH1 CH2 CH3 DGND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 V+ CS CH0 CH1 CH2 CH3 DGND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC DI CLK SARS DO VREF AGND TOP VIEW TOP VIEW ML2288 8-Channel MUX 20-Pin PCC CH2 CH1 CH0 VCC V+ ML2288 8-Channel MUX 20-Pin DIP CH0 CH1 CS DI CLK SARS DO 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC V+ CS DI CLK SARS DO SE VREF AGND 3 2 1 20 19 18 17 16 15 14 CH3 CH4 CH5 CH6 CH7 4 5 6 7 8 9 10 11 12 13 CH2 CH3 CH4 CH5 CH6 CH7 COM DGND COM DGND AGND VREF SE TOP VIEW TOP VIEW 2 ML2281, ML2282, ML2284, ML2288 PIN DESCRIPTION NAME FUNCTION NAME FUNCTION VCC DGND AGND Positive supply. 5V ± 10% Digital ground. 0 volts. All digital inputs and outputs are referenced to this point. Analog ground. The negative reference voltage for A/D converter. DO Data out. Digital output which contains result of A/D conversion. The serial data is clocked out on falling edges of CLK. Successive approximation register status. Digital output which indicates that a conversion is in progress. When SARS goes to 1, the sampling window is closed and conversion begins. When SARS goes to 0, conversion is completed. When CS = 1, SARS is in high impedance state. Clock. Digital input which clocks data in on DI on rising edges and out on DO on falling edges. Also used to generate clocks for A/D conversion. Data input. Digital input which contains serial data to program the MUX and channel assignments. Chip select. Selects the chip for multiplexer and channel assignment and A/D conversion. When CS = 1, all digital outputs are in high impedance state. When CS = 0, normal A./D conversion takes place. SARS CH0-7, Analog inputs. Digitally selected to be single VIN+, VIN– ended (VIN) or; VIN+ or VIN– of a differential input. Analog range = GND - VIN - VCC. COM Common reference point for analog inputs. A/D conversion is performed on voltage difference between analog input and this common reference point if single-end conversion is specified. Reference. The positive reference voltage for A/D converter. Shift enable. Input controls whether LSB first bit stream is shifted out on serial output DO. If SE = 1, MSB first is shifted out only. If SE = 0, an MSB first bit stream is shifted out, then a second bit stream with LSB first is shifted out after end of conversion. Input to the Shunt Regulator. CLK VREF SE DI CS V+ 3 ML2281, ML2282, ML2284, ML2288 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Current into V+ ...................................................... 15mA Supply Voltage, VCC ................................................. 6.5V Voltage Logic Inputs ........................................... –7 to VCC +7V Analog Inputs ................................ –0.3V to VCC +0.3V Input Current per Pin (Note 1) .............................. ±25mA Storage Temperature ................................ –65°C to 150°C Package Dissipation at TA = 25°C (Board Mount) ............................. 800mW Lead Temperature (Soldering 10 sec.) Dual-In-Line Package (Molded) .......................... 260°C Dual-In-Line Package (Ceramic) ......................... 300°C Molded Chip Carrier Package Vapor Phase (60 sec.) ..................................... 215°C Infrared (15 sec.) ............................................. 220°C OPERATING CONDITIONS Supply Voltage, VCC ............................ 4.5VDC to 6.3VDC Temperature Range (Note 2) ................. T MIN - TA - TMAX ML2281/2/4/8 BIX .................................. –40°C to 85°C ML2281/2/4/8 CIX ML2281/2/4/8 BCX .................................... 0°C to 70°C ML2281/2/4/8 CCX ELECTRICAL CHARACTERISTICS Unless otherwise specified, TA = TMIN to TMAX, VCC = VREF = 5V ±10%, and fCLK = 1.333MHz. ML228XB TYP MIN NOTE 3 ML228XC TYP NOTE 3 SYMBOL PARAMETER CONDITIONS MAX MIN MAX UNITS CONVERTER AND MULTIPLEXER CHARACTERISTICS Total Unadjusted Error Reference Input Resistance Common-Mode Input Range VREF = VCC (Notes 4, 6) (Notes 4, 7) (Notes 4, 8) 10 GND –0.05 ±1/16 15 ±1/2 20 VCC +0.05 ±1/4 10 GND –0.05 ±1/16 15 ±1 20 VCC +0.05 ±1/4 LSB kW V LSB DC Common-Mode Common mode voltage Error voltage GND to VCC/2 (Note 5) AC Common-Mode Common mode voltage Error GND to VCC/2, 0 to 50kHz (Note 5) DC Power Supply Sensitivity AC Power Supply Sensitivity Change in Zero Error from VCC=5V to Internal Zener Operation VZ Internal Diode Regulated Breakdown (at V+) Input Resistance VCC = 5V ±10% VREF - VCC +0.1V (Note 5) 100mVP-P, 25kHz sine on VCC (Note 5) 15mA into V+ VCC = N.C. VREF = 5V (Note 5) 15mA into V+ ±1/4 ±1/4 LSB ±1/32 ±1/4 ±1/32 ±1/4 LSB ±1/4 ±1/2 ±1/2 ±1/4 LSB LSB 6.9 6.9 V V+ (Note 4) 20 35 20 35 kW 4 ML2281, ML2282, ML2284, ML2288 ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PARAMETER CONDITIONS ML228XB TYP MIN NOTE 3 MAX MIN ML228XC TYP NOTE 3 MAX UNITS CONVERTER AND MULTIPLEXER CHARACTERISTICS (CONTINUED) IOFF Off Channel Leakage Current On channel = VCC Off channel = 0V (Notes 4, 9) On channel = 0V Off channel = VCC (Notes 4, 9) ION On Channel Leakage Current On channel = 0V Off channel = VCC (Notes 4, 9) On channel = VCC Off channel = 0V (Notes 4, 9) –1 –1 –1 µA +1 +1 µA –1 µA +1 +1 µA DIGITAL AND DC CHARACTERISTICS VIN(1) VIN(0) IIN(1) IIN(0) VOUT(1) VOUT(0) IOUT ISOURCE ISINK ICC Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Input Current Logical “0” Input Current Logical “1” Output Voltage Logical “0” Output Voltage HI-Z Output Current Output Source Current (Note 4) (Note 4) VIN = VCC (Note 4) VIN = 0V (Note 4) IOUT = –2mA (Note 4) IOUT = 2mA (Note 4) VOUT = 0V (Note 4) VOUT = VCC VOUT = 0V (Note 4) –1 1 –6.5 8.0 1.3 1.8 2.5 3.5 1.3 1.8 –6.5 8.0 2.5 3.5 –1 4.0 0.4 –1 1 2.0 0.8 1 –1 4.0 0.4 2.0 0.8 1 V V µA µA V V µA µA mA mA mA mA Output Sink Current VOUT = VCC (Note 4) Supply Current ML2281, ML2284 ML2288 (Note 4) ML2282 Includes ladder Current (Note 4) 5 ML2281, ML2282, ML2284, ML2288 ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PARAMETER CONDITIONS MIN TYP NOTE 3 MAX LIMIT UNITS AC ELECTRICAL CHARACTERISTICS fCLK tACQ tC SNR Clock Frequency Sample-and-Hold Acquisition Conversion Time Signal to Noise Ratio ML2281 Not including MUX adddressing time VIN = 40kHz, 5V sine. fCLK = 1.333MHz (fSAMPLING » 120kHz). Noise is sum of all nonfundamental components up to 1/2 of fSAMPLING (Note 11) VIN = 40kHz, 5V sine. fCLK = 1.333MHz (fSAMPLING » 120kHz). THD is sum of 2, 3, 4, 5 harmonics relative to fundamental (Note 11) VIN = fA + fB. fA = 40kHz, 2.5V sine. fB = 39.8kHz, 2.5V Sine, fCLK = 1.333MHz (fSAMPLING » 120kHz). IMD is (fA + fB), (fA – fB), (2fA + fB), (2fA – fB), (fA + 2fB), (fA – 2fB) relative to fundamental (Note 11) (Notes 4, 10) 40 130 80 (Note 4) 10 1/2 8 47 1.333 kHz 1/fCLK 1/fCLK dB THD Total Harmonic Distortion ML2281 –60 dB IMD Intermodulation Distortion ML2281 –60 dB Clock Duty Cycle tSET-UP tHOLD tPD1, tPD0 t1H, t0H 60 % ns ns CS Falling Edge or Data Input (Note 4) Valid to CLK Rising Edge Data Input Valid after CLK Rising Edge CLK Falling Edge to Output Data Valid Rising Edge of CS to Data Output and SARS Hi-Z (Note 4) CL = 100pF (Note 4 & 12) Data MSB first Data LSB first CL = 10pF, RL = 10k (see high impedance test circuits) (Note 5) CL = 100pF, RL = 2k (Note 4) 90 50 40 80 5 5 200 110 90 160 ns ns ns ns pF pF CIN COUT Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Capacitance of Logic Input Capacitance of Logic Outputs When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > VCC) the absolute value of current at that pin should be limited to 25mA or less. 0°C to 70°C and –40°C to +85°C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by correlation with worst-case test conditions. Typicals are parametric norm at 25°C. Parameter guaranteed and 100% production tested. Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation. Total unadjusted error includes offset, full-scale, linearity, multiplexer and sample-and-hold errors. Cannot be tested for ML2282. For VIN– ³ VIN+ the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct—especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50mV forward bias of either diode. This means that as long as the analog V IN or VREF does not exceed the supply voltage by more than 50mV, the output code will be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950VDC over temperature variations, initial tolerance and loading. Leakage current is measured with the clock not switching. Note 9: Note 10: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits, the minimum time the clock is high or the minimum time the clock is low must be at least 300ns. The maximum time the clock can be high or low is 60µs. Note 11: Because of multiplexer addressing, test conditions for the ML2282 would be V IN = 34kHz, 5V sine (fSAMPLING » 102kHz); ML2284 VIN = 32kHz, 5V sine (fSAMPLING » 95kHz); ML2288 VIN = 30kHz, 5V sine (fSAMPLING » 89kHz). Note 12: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow for comparator response time. 6 ML2281, ML2282, ML2284, ML2288 t1H DATA OUTPUT CL RL VCC CS GND VOH GND t1H tr 90% 50% 10% t1H DO AND SARS OUTPUTS 90% t0H VCC VCC RL DATA OUTPUT CL DO AND SARS OUTPUTS CS GND VCC VOL t0H tr 90% 50% 10% t0H 10% Figure 1. High Impedance Test Circuits and Waveforms Data Input Timing CLK CLK tSET-UP CS tHOLD DATA IN (DI) DATA OUT (DO) tSET-UP SE tPD0, tPD1 tPD0, tPD1 Data Output Timing tSET-UP tHOLD ML2281 Start Conversion Timing CLK tSET-UP CS START CONVERSION DO BIT 7 (MSB) BIT 6 Figure 2. Timing Diagrams 7 ML2281, ML2282, ML2284, ML2288 ML2281 Timing 1 CLOCK (CLK) tSET-UP CHIP SELECT (CS) tC DATA OUT (DO) SAMPLE & HOLD ACQUISITION (tACQ) HI-Z 7 (MSB) 6 5 4 3 2 1 0 (LSB) * HI-Z 2 3 4 5 6 7 8 9 10 11 *LSB FIRST OUTPUT NOT AVAILABLE ON ML2281 ML2282 Timing 1 CLOCK (CLK) tSET-UP CHIP SELECT (CS) ADDRESS MUX START BIT DATA IN (DI) SGL/DIF DATA OUT (DO) ODD/ SIGN DON’T CARE (DI DISABLED UNTIL NEXT CONVERSION CYCLE) MSB FIRST DATA LSB FIRST DATA HI-Z 7 (MSB) 6 5 4 3 2 1 0 (LSB) 1 2 3 4 5 6 7 (MSB) OUTPUT DATA 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 HI-Z SAMPLE & HOLD ACQUISITION (tACQ) ML2284 Timing 1 CLOCK (CLK) tSET-UP CHIP SELECT (CS) ADDRESS MUX START BIT ODD/SIGN DATA IN (DI) SGL/DIF SELECT BIT 1 SAR STATUS (SARS) HI-Z MSB FIRST DATA DATA OUT (DO) HI-Z 7 6 (MSB) 5 4 3 2 1 0 (LSB) 1 2 3 4 5 6 7 (MSB) LSB FIRST DATA HI-Z DON’T CARE (DI DISABLED UNTIL NEXT CONVERSION CYCLE) A/D CONVERSION IN PROCESS HI-Z OUTPUT DATA 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SAMPLE & HOLD ACQUISITION (tACQ) Figure 2. Timing Diagrams (Continued) 8 ML2281, ML2282, ML2284, ML2288 ML2288 Timing 1 CLOCK (CLK) tSET-UP CHIP SELECT (CS) ADDRESS MUX START BIT DATA IN (DI) SGL/DIF SELECT BIT 1 SAR STATUS (SARS) HI-Z MSB FIRST DATA SE = “0” DATA OUT (DO) HI-Z 7 6 (MSB) 5 4 3 2 1 0 (LSB) 1 2 3 4 5 6 tSET-UP DATA HELD 7 (MSB) LSB FIRST DATA HI-Z ODD/ SELECT SIGN BIT 0 DON’T CARE (DI DISABLED UNTIL NEXT CONVERSION CYCLE) A/D CONVERSION IN PROCESS HI-Z OUTPUT DATA 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 USING SE TO CONTROL LSB FIRST OUTPUT DO LINEARITY ERROR (LSB)        SE MSB FIRST DATA HI-Z SAMPLE & HOLD ACQUISITION (tACQ) LSB FIRST DATA HI-Z 76 (MSB) 5 4 3 2 1 0 (LSB) 1 2 3 4 5 6 7 (MSB) Figure 2. Timing Diagrams (Continued) 1.0 VCC = 5V VREF = 5V 0.75 0.5 –55 C 0.25 25 C 125 C 0 0 0.01 0.1 1 CLOCK FREQUENCY (MHz) Figure 3. Linearity Error vs fCLK 9 ML2281, ML2282, ML2284, ML2288 1 VCC = 5V fCLK = 1.333MHz 1 LINEARITY ERROR (LSB) 0.75 0.75 VCC = 5V VIN = 0V fCLK = 1.333MHz TA = 25 C 0.5 –55 C 0.25 OFFSET ERROR (LSB) 3 4 5 125 C 25 C 0.5 0.25 0 0 1 2 0 0 1 2 3 4 5 VREF (VDC) VREF (VDC) Figure 4. Linearity Error vs VREF Voltage Figure 5. Unadjusted Offset Error vs VREF Voltage 10 ML2281, ML2282, ML2284, ML2288 DI* CS 17 18 R START R R R 5-BIT SHIFT-REGISTER ODD/ SGL/DIF SELECT 1 SIGN R SELECT 0 D CS C START CLK 16 VCC 1 2 3 4 5 6 7 8 9 COMP 12 TO INTERNAL CIRCUITRY INPUT V CC 13 TO 16 INTERNAL 17 CIRCUITS 18 R LADDER AND DECODER C R B7 B6 B5 SAR LOGIC AND LATCH B4 B3 B2 B1 B0 COMP EOC 9-BIT SHIFT REGISTER R C CS CS EOC C R D ANALOG MUX (EQUIVALENT) C + – 13 MUX ADDRESS NOTE 1 + – NOTE 1 SE* CS SARS* 15 TD TIME DELAY C Q D C D C R D Q R Q R CS DEOC CS DSTART 1 CS CH0* CH1* CH2 CH3 CH4* CH5* CH6* CH7* COM* Σ DSTART 2 CS Q 14 DO VREF VCC V+* DGND* 20 7V SHUNT REGULATOR AGND* INPUT PROTECTION—ALL LOGIC INPUTS LSB FIRST MSB FIRST PARALLEL XFR TO SHIFT REGISTER *SOME OF THESE FUNCTIONS/PINS ARE NOT AVAILABLE WITH OTHER OPTIONS. NOTE 1: FOR THE ML2284 DI IS INPUT DIRECTLY TO THE D INPUT OF SELECT 1. SELECT 0 IS FORCED TO A “1”. FOR THE ML2282, DI IS INPUT DIRECTLY TO THE D INPUT OF ODD/SIGN. SELECT 0 IS FORCED TO A “1” AND SELECT 1 IS FORCED TO A “0”. Figure 6. ML2288 Functional Block Diagram 11 ML2281, ML2282, ML2284, ML2288 FUNCTIONAL DESCRIPTION MULTIPLEXER ADDRESSING The design of these converters utilizes a sample data comparator structure which provides for a differential analog input to be converted by a successive approximation routine. The actual voltage converted is always the difference between an assigned “+” input terminal and a “–” input terminal. The polarity of each input terminal of the pair being converted indicates which line the converter expects to be the most positive. If the assigned “+” input is less than the “–” input, the converter responds with an all zeros output code. A unique input multiplexing scheme has been utilized to provide multiple analog channels with software configurable single ended, differential, or pseudo differential options. The pseudo differential option will convert the difference between the voltage at any analog input and a common terminal. One converter package can now accommodate ground referenced inputs and true differential inputs as well as signals with some arbitrary reference voltage. A particular input configuration is assigned during the MUX addressing sequence, prior to the start of a conversion. The MUX address selects which of the analog inputs are to be enabled and whether this input is single ended or differential. In the differential case, it also assigns the polarity of the analog channels. Differential inputs are restricted to adjacent channel pairs. For example, channel 0 and channel 1 may be selected as a different pair but channel 0 or channel 1 cannot act differentially with any other channel. In addition to selecting the differential mode, the sign may also be selected. Channel 0 may be selected as the positive input and channel 1 as the negative input or vice versa. This programmability is illustrated by the MUX addressing codes shown in Tables 1, 2, and 3. The MUX address is shifted into the converter via the DI input. Since the ML2281 contains only one differential input channel with a fixed polarity assignment, it does not require addressing. The common input line on the ML2288 can be used as a pseudo differential input. In this mode, the voltage on the COM pin is treated as the “–” input for any of the other input channels. This voltage does not have to be analog ground; it can be any reference potential which is common to all of the inputs. This feature is most useful in single supply applications where the analog circuitry may be biased at a potential other than ground and the output signals are all referred to this potential. Since the input configuration is under software control, it can be modified, as required, at each conversion. A channel can be treated as a single-ended, ground referenced input for one conversion; then it can be reconfigured as part of a differential channel for another conversion. Figure 7 illustrates these different input modes. SINGLE-ENDED MUX MODE MUX ADDRESS SGL/ ODD/ DIF SIGN 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 SELECT 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 + + + + 0 + + + + 1 2 3 4 5 6 7 COM – – – – – – – – ANALOG SINGLE-ENDED CHANNEL# DIFFERENTIAL MUX MODE MUX ADDRESS SGL/ ODD/ DIF SIGN 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 SELECT 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 – + – + – + – + 0 + ANALOG DIFFERENTIAL CHANNEL-PAIR# 0 1 – + – + – + – 2 1 3 4 2 5 6 3 7 Table 1. ML2288 MUX Addressing 8 Single-Ended or 4 Differential Channels SINGLE-ENDED MUX MODE MUX ADDRESS SGL/ ODD/ DIF SIGN 1 1 1 1 0 0 1 1 SELECT 1 0 1 0 1 + + COM is internally tied to AGND CHANNEL# 0 + + 1 2 3 DIFFERENTIAL MUX MODE MUX ADDRESS SGL/ ODD/ DIF SIGN 0 0 0 0 0 0 1 1 SELECT 1 0 1 0 1 – + – + 0 + 1 – + – 2 3 CHANNEL# Table 2. ML2284 MUX Addressing 4 Single-Ended or 2 Differential Channel 12 ML2281, ML2282, ML2284, ML2288 SINGLE-ENDED MUX MODE MUX ADDRESS SGL/DIF 1 1 ODD/SIGN 0 1 0 + + CHANNEL# 1 DIGITAL INTERFACE The block diagram and timing diagrams in Figures 2-5 illustrate how a conversion sequence is performed. A conversion is initiated when CS is pulsed low. This line must me held low for the entire conversion. The converter is now waiting for a start bit and its MUX assignment word. A clock is applied to the CLK input. On each rising edge of the clock, the data on DI is clocked into the MUX address shift register. The start bit is the first logic “1” that appears on the DI input (all leading edge zeros are ignored). After the start bit, the device clocks in the next 2 to 4 bits for the MUX assignment word. When the start bit has been shifted into the start location of the MUX register, the input channel has been assigned and a conversion is about to begin. An interval of 1/2 clock period is used for sample & hold settling through the selected MUX channels. The SAR status output goes high at this time to signal that a conversion is now in progress and the DI input is ignored. The DO output comes out of High impedance and provides a leading zero for this one clock period. When the conversion begins, the output of the comparator, which indicates whether the analog input is greater than or less than each successive voltage from the internal DAC, appears at the DO output on each falling edge of the clock. This data is the result of the conversion being shifted out (with MSB coming first) and can be read by external logic or µP immediately. After 8 clock periods, the conversion is completed. The SAR status line returns low to indicate this 1/2 clock cycle later. The serial data is always shifted out MSB first during the conversion. After the conversion has been completed, the data can be shifted out a second time with LSB first, depending on level of SE input. For the case of ML2288, if SE = 1, the data is shifted out MSB first during the conversion only. If SE is brought low before the end of conversion (which is signalled by the high to low transition of SARS), the data is shifted out again immediately after the end of conversion; this time LSB first. If SE is brought low after end of conversion, the LSB first data is shifted out on falling edges of clock after SE goes low. For ML2282 and 2284, SE is internally tied low, so data is shifted out MSB first, then shifted out a second time LSB first at end of conversion. For ML2281, SE is internally tied high, so data is shifted out only once MSB first. All internal registers are cleared when the CS input is high. If another conversion is desired, CS must make a high to low transition followed by address information. The DI input and DO output can be tied together and controlled through a bidirectional µP I/O bit with one connection. This is possible because the DI input is only latched in during the MUX addressing interval while the DO output is still in the high impedance state. DIFFERENTIAL MUX MODE MUX ADDRESS SGL/DIF 0 0 ODD/SIGN 0 1 0 + – CHANNEL# 1 – + Table 3. ML2282 MUX Addressing 2 Single-Ended or 1 Differential Channel 8 Single-Ended 0 1 2 3 4 5 6 7 + + + + + + + + COM (–) VBIAS 8 Pseudo-Differential 0 1 2 3 4 5 6 7 + + + + + + + + + COM (–) 4 Differential 0, 1 + (–) – (+) 2, 3 + (–) – (+) 4, 5 + (–) – (+) 6, 7 + (–) – (+) + VBIAS 2, 3 4 5 6 7 0, 1 Mixed Mode + – – + + + + + COM (–) Figure 7. Analog Input Multiplexer Functional Options for ML2288 13 ML2281, ML2282, ML2284, ML2288 REFERENCE The voltage applied to the reference input to these converters defines the voltage span of the analog input (the difference between VIN MAX and VIN MIN) over which the 256 possible output codes apply. The devices can be used in either ratiometric applications or in systems requiring absolute accuracy. The reference pin must be connected to a voltage source capable of driving the reference input resistance, typically 10k. This pin is the top of a resistor divider string used for the successive approximation conversion. In a ratiometric system, the analog input voltage is proportional to the voltage used for the A/D reference. This voltage is typically the system power supply, so the VREF pin can be tied to VCC. This technique relaxes the stability requirements of the system reference as the analog input and A/D reference move together maintaining the same output code for a given input condition. For absolute accuracy, where the analog input varies between specific voltage limits, the reference pin can be biased with a time and temperature stable voltage source. The maximum value of the reference is limited to the VCC supply voltage. The minimum value, however, can be quire small to allow direct conversion of inputs with less than 5V of voltage span. Particular care must be taken with regard to noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter. The signal at the analog input is sampled during the interval when the sampling switch is closed prior to conversion start. The sampling window (S/H acquisition time) is 1/2 CLK period wide and occurs 1/2 CLK period before DO goes from high impedance to active low state. When the sampling switch closes at the start of the S/H acquisition time, 8pF of capacitance is thrown onto the analog input. 1/2 CLK period later, the sampling switch is opened and the signal present at the analog input is stored. Any error on the analog input at the end of the S/H acquisition time will cause additional conversion error. Care should be taken to allow adequate charging or settling time from the source. If more charging or settling time is needed to reduce these analog input errors, a longer CLK period can be used. The ML2281X family has improved latchup immunity. Each analog input has dual diodes to the supply rails, and a minimum of ±25mA (±100mA typically) can be injected into each analog input without causing latchup. DYNAMIC PERFORMANCE Signal-to-Noise-Ratio Signal-to-noise ration (SNR) is the measured signal-to-noise at the output of the converter. The signal is the RMS magnitude of the fundamental. Noise is the RMS sum of all the nonfundamental signals up to half the sampling frequency. SNR is dependent on the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. The theoretical SNR for a sine wave is given by SNR = (6.02N + 1.76)dB ANALOG INPUTS AND SAMPLE/HOLD An important feature of the ML2281 family of devices is that they can be located at the source of the analog signal and then communicate with a controlling µP with just a few wires. This avoids bussing the analog inputs long distances and thus reduces noise pickup on these analog lines. However, in some cases, the analog inputs have a large common mode voltage or even some noise present along with the valid analog signal. The differential input of these converters reduces the effects of common mode input noise. Thus, if a common mode voltage is present on both “+” and “–” inputs, such as 60Hz, the converter will reject this common mode voltage since it only converts the difference between “+” and “–” inputs. The ML2281 family have a true sample and hold circuit which samples both “+” and “–” inputs simultaneously. This simultaneous sampling with a true S/H will give common mode rejection and AC linearity performance that is superior to devices where the two input terminals are not sampled at the same instant and where true sample and hold capability does not exist. Thus, the ML2281 family of devices can reject AC common mode signals from DC-50kHz as well as maintain linearity for signals from DC-50kHz. where N is the number of bits. Thus for ideal 8-bit converter, SNR = 49.92dB. Harmonic Distortion Harmonic distortion is the ratio of the RMS sum of harmonics to the fundamental. Total harmonic distortion (THD) of the ML2281 Series is defined as  V 2 + V 2 + V 2 + V 2 3 4 5 2  THD = 20 log V1 where V1 is the RMS amplitude of the fundamental and V2, V3, V4, V5 are the RMS amplitudes of the individual harmonics. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fA and fB, any active device with nonlinearities will create distortion products, of order (m + n), at sum and difference frequencies of mfA + nfB, where m, n = 0, 1, 2, 3… . Intermodulation terms are those for which m or n is not equal to zero. The (IMD) intermodulation distortion specification includes the second order terms (fA + fB) and (fA – fB) and the third order terms (2fA + fB), (2fA – fB), (fA + 2fB) and (fA – 2fB) only. 14 ML2281, ML2282, ML2284, ML2288 ZERO ERROR ADJUSTMENT The zero of the A/D does not require adjustment. If the minimum analog input voltage value, VIN MIN is not ground, a zero offset can be done. The converter can be made to output 00000000 digital code for this minimum input voltage by biasing any VIN– input at this VIN MIN value. This utilizes the differential mode operation of the A/D. The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be measured by grounding the VIN– input and applying a small magnitude positive voltage to the VIN+ input. Zero error is the difference between the actual DC input voltage which is necessary to just cause an output digital code transition from 00000000 to 00000001 and the ideal 1/2 LSB value (1/2 LSB = 9.8mV for VREF = 5.000VDC). (where the LSB is calculated for the desired analog span, 1 LSB = analog span/256) is applied to selected “+” input and the zero reference voltage at the corresponding “–” input should then be adjusted to just obtain the 00000000 to 00000001 code transition. The full-scale adjustment should be made by forcing a voltage to the VIN+ input which is given be:  (V − VMIN)  VIN + fs adjust = VMAX − 1.5 ×  MAX  256   where FULL-SCALE ADJUSTMENT The full-scale adjustment can be made by applying a differential input voltage which is 1-1/2 LSB down from the desired analog full-scale voltage range and then adjusting the magnitude of the VREF input or VCC for a digital output code which is just changing from 11111110 to 11111111. VMAX = high end of the analog input range VMIN = low end (offset zero) of the analog range The VREF or VCC voltage is then adjusted to provide a code change from 11111110 to 11111111. SHUNT REGULATOR A unique feature of ML2288 and ML2284 is the inclusion of a shunt regulator connected from V+ terminal to ground which also connects to the VCC terminal (which is the actual converter supply) through a silicon diode as shown in Figure 8. When the regulator is turned on, the V+ voltage is clamped at 11VBE set by the internal resistor ratio. The typical I-V of the shunt regulator is shown in Figure 9. It should be noted that before V+ voltage is high enough to turn on the shunt regulator (which occurs at about 5.5V), 35kW resistance is observed between V+ and GND. When the shunt regulator is not used, V+ pin should be either left floating or tied to GND. The temperature coefficient of the regulator is –22mV/°C. ADJUSTMENT FOR AN ARBITRARY ANALOG INPUT VOLTAGE RANGE If the analog zero voltage of the A/D is shifted away from ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference should be properly adjusted first. A VIN+ voltage which equals this desired zero reference plus 1/2 LSB 12V I+→ V+ 28.8k VCC 15mA I+ CURRENT LIMITING RESISTOR, I+ ≤15mA 3.2k 3.2k GND SLOPE = 1 35k V+ 5.5V 6.9V Figure 8. Shunt Regulator Figure 9. I-V Characteristic of the Shunt Regulator 15 ML2281, ML2282, ML2284, ML2288 APPLICATIONS CH0 CS CLK DI P13 P12 P11 P10 ML2288 8051 CH7 DO 8051 Interface and Controlling Software MNEMONIC START ANL MOV MOV RRC JC ANL SJMP ORL ACALL DJNZ ACALL MOV ACALL MOV RRC RRC MOV RLC MOV DJNZ P1, #0F7H B, #5 A, #ADDR A ONE P1, #0FEH CONT P1, #1 PULSE B, LOOP 1 PULSE B, #8 PULSE A, P1 A A A, C A C, A B, LOOP 2 INSTRUCTION ;SELECT A/D (CS = 0) ;BIT COUNTER ¬ 5 ;A ¬ MUX BIT ;CY ¬ ADDRESS BIT ;TEST BIT ;BIT = 0 ;DI ¬ 0 ;CONTINUE ;BIT = 1 ;D1 ¬ 1 ;PULSE SK 0 ® 1 ® 0 ;CONTINUE UNTIL DONE ;EXTRA CLOCK FOR SYNC ;BIT COUNTER ¬ 8 ;PULSE SK 0 ® 1 ® 0 ;CY ¬ DO ;A ¬ RESULT ;A(0) BIT ¬ AND SHIFT ;C ¬ RESULT ;CONTINUE UNTIL DONE ;PULSE SUBROUTINE LOOP 1: ZERO: ONE: CONT: LOOP 2: RETI PULSE: ORL NOP ANL RET P1, #04 P1, #0FBH ;SK ¬ 1 ;DELAY ;SK ¬ 0 16 ML2281, ML2282, ML2284, ML2288 APPLICATIONS (Continued) MUX ADDRESS 5VDC 51kΩ (4) START BIT SGL/DIF 11 15 CLK + 2 CLK INT 12 13 14 PARALLEL INPUTS 3 4 5 6 7 GND 7 NC DO CLK 1 SHIFT/ LOAD SIN 10 NC 5VDC (OR VIN) INPUT SHIFT REGISTER 74HC165 VCC 14 5VDC DO 9 START 1kΩ (8) 7 6 5 6 4 5 3 4 2 3 1 2 0 1/8 VCC 1 9 COM 17 D1 SE 13 51kΩ 8 START 5 VDC CLK 18 16 CLK NC CLK CLOSE TO START THE A/D CONVERSION 10kΩ 0.001µF CLOCK GENERATOR 7 GND 15 SARS 7 CS ANALOG INPUTS ML2288 VREF 12 VCC 20 5VDC 0.01µF 10kΩ AGND 11 DGND 10 V+ 19 DO 14 1 CLR OUTPUT SHIFT REGISTER 74HC164 14 VCC SI A 1 + 10µF CLK CLK Q D 8 CLK QH 13 12 11 10 6 5 4 2 QA 3 SI B CLK 1.3kΩ (8) 1/2 74HC74 MSB DATA DISPLAY LSB 5VDC ML2288 “Stand-Alone” or Evaluation Circuit 17 ML2281, ML2282, ML2284, ML2288 VCC (5 VDC) TA LM335 3kΩ VIN (+) VCC + 10µF ML2281 10kΩ TA MIN ADJ. VIN (–) VREF 10kΩ TA MAX ADJ. Low-Cost Remote Temperature Sensor 18 ML2281, ML2282, ML2284, ML2288 APPLICATIONS (Continued) VCC (5VDC) 330Ω 10V 6.8kΩ 1kΩ GAIN 2.7kΩ 10kΩ + + – 5.1V VCC VREF DUAL 1MΩ ML2281 CS –IN DUAL +IN 10V DO CLK + VIN VIN (+) VCC + 10µF ML2281 1kΩ VIN (–) SETS ZERO CODE VOLTAGE 2.7kΩ 1kΩ 2VDC ZERO ADJ. 10kΩ FS ADJ. 1.2kΩ STRAIN GAUGE LOAD CELL 300Ω/30mV FS VREF 330Ω 3V + 1µF SET VOLTAGE SPAN – 1MΩ 20kΩ 10kΩ OFFSET 20kΩ • USES ONE MORE WIRE THAN LOAD CELL ITSELF • TWO MINI-DIPs COULD BE MOUNTED INSIDE LOAD CELL FOR DIGITAL OUTPUT TRANSDUCER • ELECTRONIC OFFSET AND GAIN TRIMS RELAX MECHANICAL SPECS FOR GAUGE FACTOR AND OFFSET • LOW LEVEL CELL OUTPUT IS CONVERTED IMMEDIATELY FOR HIGH NOISE IMMUNITY Zero-Shift and Span Adjust: 2V - VIN - 5V Digital Load Cell T1 + – TYPE J tREF 1kΩ + – CH0 88.2k ML2288 VCC 2kΩ 22kΩ 1kΩ + – VCC 910Ω TL064 CH7 SERIAL I/O COM VREF 88.2kΩ 820Ω 1kΩ 3kΩ USES THE PSEUDO-DIFFERENTIAL MODE TO KEEP THE DIFFERENTIAL INPUTS CONSTANT WITH CHANGES IN REFERENCE TEMPERATURE (TREF) Convert 8 Thermocouples with only One Cold-Junction Compensator + – VCC 20kΩ LM385 + T8 – 1kΩ tREF – + – + TYPE J tREF LM335 TL064 TL064 19 ML2281, ML2282, ML2284, ML2288 APPLICATIONS (Continued) VCC (5VDC) VCC VIN 15VDC OP AMP + R – + > 2.5V ≤ 2.5V – + ML2281 R VIN (–) DIODE CLAMPING IS NOT NEEDED IF CURRENT IS LIMITED TO 25mA CONTROLLER PERFORMS A ROUTINE TO DETERMINE WHICH INPUT POLARITY PROVIDES A NON-ZERO OUTPUT CODE. THIS INFORMATION PROVIDES THE EXTRA BITS. Obtaining 9-Bit Resolution VCC (5VDC) 0.1Ω 100Ω VIN (–) 240kΩ ML2281 VCC → ILOAD (2A FULL-SCALE) VCC (5VDC) + 10µF 3kΩ 120kΩ + 1µF Digitizing a Current Flow VCC (5VDC) 20kΩ XDR VXDR 1kΩ ZERO ADJ. 3kΩ VIN (+) VIN (–)* ML2281 VCC + VIN 10kΩ VIN (+) VCC + 10µF + 1µF *VIN (–) = 0.15VCC 15% OF VCC ≤VXDR ≤85% OF VCC + 1µF 24kΩ SET FOR 3V Operating with Ratiometric Transducers Span Adjust: 0V - VIN - 3V 20 + + VREF 0.7 VCC 1kΩ FS ADJ. VIN (–) VREF – + VIN (+) VREF – 100Ω ZERO ADJ. – + VREF – (( – 600Ω VIN (+) VCC + 10µF –15VDC ML2281 Protecting the Input LOAD 2kΩ 9.1kΩ 1kΩ FS ADJ. LM336 VCC (5VDC) + 10µF 10kΩ FS ADJ. 1kΩ 2kΩ ML2281 ML2281, ML2282, ML2284, ML2288 APPLICATIONS (Continued) → → 4mA–20mA + 10µF 1N4148 1/6 74HC14 100kΩ = 50kHZ 100Ω 24kΩ 6.2kΩ 200kΩ VCC 47µF +IN 1000pF INP VO5 50pF ML2281 VCC CD4024 CLK LM385–2.5V 10kΩ –IN CS 100kΩ 6N139 OPTO COUPLER 3 5 68 2 10kΩ VCC V+ VO GND LM385–2.5V 47kΩ 5kΩ 3.9kΩ VREF GND 300kΩ DO • ALL POWER SUPPLIED BY LOOP • 1500V ISOLATION AT OUTPUT 4mA–20mA Current Loop Converter TRANSFORMER TRW-TC-SSD-32 3 10kΩ CLK 2N2222 6V 1 6 6V 470Ω 5 7 2 1N4148 + 47kΩ VCC OUT 100µF 1N4148 VCC 100kΩ CLK CS 4N28 VCC 100kΩ ML2288 D1 4N28 VCC DO 8 ANALOG CHANNELS VCC 10kΩ CS 6V 470Ω 2N2222 10kΩ DI 2N2222 8 6 5 3 2 6.8kΩ 6N139 HIGH GAIN OPTOCOUPLER • NO POWER REQUIRED REMOTELY • 1500V ISOLATION Isolated Data Converter 21 ML2281, ML2282, ML2284, ML2288 APPLICATIONS (Continued) START LS193 LOAD AB B0 COUNT C D DOWN S R TMS320 SERIES D 5V Q Q Q D Q DSP Q D Q Q ML2281 CLK VIN+ VIN– CS DO CLK FSR CLK DR Sampling Rate 111kHz, Data Rate 1.33MHz CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 START CS FSR DO HI-Z D7 D6 D5 D4 D3 D2 D1 D0 HI-Z Interfacing ML2281 to TMS320 Series 22 ML2281, ML2282, ML2284, ML2288 PHYSICAL DIMMENSIONS inches (millimeters) Package: P08 8-Pin PDIP 0.365 - 0.385 (9.27 - 9.77) 0.055 - 0.065 (1.39 - 1.65) 8 PIN 1 ID 0.240 - 0.260 0.299 - 0.335 (6.09 - 6.60) (7.59 - 8.50) 0.020 MIN (0.51 MIN) (4 PLACES) 1 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) 0.016 - 0.020 (0.40 - 0.51) SEATING PLANE 0º - 15º 0.008 - 0.012 (0.20 - 0.31) Package: S08 8-Pin SOIC 0.189 - 0.199 (4.80 - 5.06) 8 PIN 1 ID 0.148 - 0.158 0.228 - 0.244 (3.76 - 4.01) (5.79 - 6.20) 1 0.017 - 0.027 (0.43 - 0.69) (4 PLACES) 0.050 BSC (1.27 BSC) 0.059 - 0.069 (1.49 - 1.75) 0º - 8º 0.055 - 0.061 (1.40 - 1.55) 0.012 - 0.020 (0.30 - 0.51) SEATING PLANE 0.004 - 0.010 (0.10 - 0.26) 0.015 - 0.035 (0.38 - 0.89) 0.006 - 0.010 (0.15 - 0.26) 23 ML2281, ML2282, ML2284, ML2288 PHYSICAL DIMMENSIONS inches (millimeters) Package: P14 14-Pin PDIP 0.740 - 0.760 (18.79 - 19.31) 14 PIN 1 ID 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.25) 0.070 MIN (1.77 MIN) (4 PLACES) 1 0.050 - 0.065 (1.27 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) 0.016 - 0.022 (0.40 - 0.56) SEATING PLANE 0º - 15º 0.008 - 0.012 (0.20 - 0.31) Package: S14 14-Pin SOIC 0.337 - 0.347 (8.56 - 8.81) 14 PIN 1 ID 0.148 - 0.158 0.228 - 0.244 (3.76 - 4.01) (5.79 - 6.20) 1 0.017 - 0.027 (0.43 - 0.69) (4 PLACES) 0.050 BSC (1.27 BSC) 0.059 - 0.069 (1.49 - 1.75) 0º - 8º 0.055 - 0.061 (1.40 - 1.55) 0.012 - 0.020 (0.30 - 0.51) SEATING PLANE 0.004 - 0.010 (0.10 - 0.26) 0.015 - 0.035 (0.38 - 0.89) 0.006 - 0.010 (0.15 - 0.26) 24 ML2281, ML2282, ML2284, ML2288 PHYSICAL DIMMENSIONS inches (millimeters) Package: P20 20-Pin PDIP 1.010 - 1.035 (25.65 - 26.29) 20 PIN 1 ID 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26) 0.060 MIN (1.52 MIN) (4 PLACES) 1 0.055 - 0.065 (1.40 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) 0.016 - 0.022 (0.40 - 0.56) SEATING PLANE 0º - 15º 0.008 - 0.012 (0.20 - 0.31) Package: Q20 20-Pin PLCC 0.385 - 0.395 (9.78 - 10.03) 0.350 - 0.356 (8.89 - 9.04) 1 0.042 - 0.056 (1.07 - 1.42) 0.025 - 0.045 (0.63 - 1.14) (RADIUS) 0.042 - 0.048 (1.07 - 1.22) 6 PIN 1 ID 16 0.350 - 0.356 (8.89 - 9.04) 0.385 - 0.395 (9.78 - 10.03) 0.200 BSC (5.08 BSC) 0.290 - 0.330 (7.36 - 8.38) 11 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.165 - 0.180 (4.19 - 4.57) 0.146 - 0.156 (3.71 - 3.96) 0.009 - 0.011 (0.23 - 0.28) 0.100 - 0.110 (2.54 - 2.79) 0.013 - 0.021 (0.33 - 0.53) SEATING PLANE 25 ML2281, ML2282, ML2284, ML2288 ORDERING INFORMATION PART NUMBER ALTERNATE PART NUMBER TOTAL UNADJUSTED ERROR TEMPERATURE RANGE PACKAGE SINGLE ANALOG INPUT, 8-PIN PACKAGE ML2281BIP (Obsolete) ML2281BCP ML2281BCS (Obsolete ML2281CIP (End of Life) ML2281CCP (End of Life) ML2281CCS (End of Life) ADC0831CCN ADC0831BCN — ADC0831BCN ADC0831CCN — ±1/2 LSB –40°C to 85°C 0°C to 70°C 0°C to 70°C –40°C to 85°C 0°C to 70°C 0°C to 70°C Plastic DIP (P08) Molded DIP (P08) Plastic SOIC (S08) Plastic DIP (P08) Molded DIP (P08) Plastic SOIC (S08) ±1 LSB TWO ANALOG INPUTS, 8-PIN PACKAGE ML2282BIP (Obsolete) ML2282BCP (Obsolete) ML2282BCS (Obsolete) ML2282CIP (Obsolete) ML2282CCP (Obsolete) ML2282CCS (Obsolete) ADC0832CCN ADC0832BCN — ADC0832BCN ADC0832CCN — ±1/2 LSB –40°C to 85°C 0°C to 70°C 0°C to 70°C –40°C to 85°C 0°C to 70°C 0°C to 70°C Plastic DIP (P08) Molded DIP (P08) Plastic SOIC (S08) Plastic DIP (P08) Molded DIP (P08) Plastic SOIC (S08) ±1 LSB FOUR ANALOG INPUTS, 14-PIN PACKAGE ML2284BIP (Obsolete) ML2284BCP (Obsolete) ML2284BCS (Obsolete) ML2284CIP (Obsolete) ML2284CCP (End of Life) ML2284CCS (Obsolete) ADC0834CCN ADC0834BCN — ADC0834BCN ADC0834CCN — ±1/2 LSB –40°C to 85°C 0°C to 70°C 0°C to 70°C –40°C to 85°C 0°C to 70°C 0°C to 70°C Plastic DIP (P14) Molded DIP (P14) Plastic SOIC (S14) Plastic DIP (P14) Molded DIP (P14) Plastic SOIC (S14) ±1 LSB EIGHT ANALOG INPUTS, 20-PIN PACKAGE ML2288BIP (Obsolete) ML2288BCP (Obsolete) ML2288BCQ (Obsolete) ML2288CIP (Obsolete) ML2288CCP (Obsolete) ML2288CCQ (End of Life) ADC0838CCN ADC0838BCN ADC0838BCV ADC0838CCN ADC0838CCN ADC0838CCV ±1/2 LSB –40°C to 85°C 0°C to 70°C 0°C to 70°C –40°C to 85°C 0°C to 70°C 0°C to 70°C Plastic DIP (P20) Molded DIP (P20) Molded PCC (Q20) Plastic DIP (P20) Molded DIP (P20) Molded PCC (Q20) ±1 LSB DS2281_82_84_88-01 © Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 5/5/97 Printed in U.S.A. 26