ML4826CS-1

June 1997 ML4826* PFC and Dual Output PWM Controller Combo GENERAL DESCRIPTION The ML4826 is a high power controller for power factor corrected, switched mode power supplies. PFC allows the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply that fully complies with IEC1000-3-2 specifications. The ML4826 includes circuits for the implementation of a leading edge, average current “boost” type power factor correction and a trailing edge, pulse width modulator (PWM) with dual totem-pole outputs. The device is available in two versions; the ML4826-1 (fPWM = fPFC) and the ML4826-2 (fPWM = 2 x fPFC). Doubling the switching frequency of the PWM allows the user to design with smaller output components while maintaining the optimum operating frequency for the PFC. An over-voltage comparator shuts down the PFC section in the event of a sudden decrease in load. The PFC section also includes peak current limiting and input voltage brown-out protection. The PWM section can be operated in current or voltage mode at up to 250kHz and includes a duty cycle limit to prevent transformer saturation. FEATURES s s s Internally synchronized PFC and PWM in one IC Low total harmonic distortion Reduced ripple current in the storage capacitor between the PFC and PWM sections Average current, continuous boost, leading edge PFC High efficiency trailing edge PWM with dual totem-pole outputs Average line voltage compensation with brown-out control PFC overvoltage comparator eliminates output “runaway” due to load removal Current-fed multiplier for improved noise immunity Overvoltage protection, UVLO, and soft start s s s s s s BLOCK DIAGRAM 20 VEAO VFB 19 2.5V IAC 2 VRMS 4 ISENSE 3 RAMP 1 8 RTCT 7 RAMP 2 9 8V VDC 6 VCC SS 5 8V DC ILIMIT 10 50µA 1.5V + + + + - * This Part Is End Of Life As Of August 1, 2000 1 AGND IEAO POWER FACTOR CORRECTOR OVP 3.5kΩ + 11 17 VCCZ 13.5V VCC 7.5V REFERENCE S -1V + - VEA IEA 2.7V + - VREF 18 Q Q PFC OUT Q Q 15 GAIN MODULATOR 3.5kΩ 8V R S R PFC ILIMIT OSCILLATOR (-2 VERSION ONLY) x2 DUTY CYCLE LIMIT S T Q PWM 2 Q PGND S VFB 2.5V + VCC2 16 14 Q Q VIN OK 1V + VCC2 PWM 1 13 PGND 12 R DC ILIMIT PULSE WIDTH MODULATOR VCCZ UVLO 1 ML4826 PIN CONFIGURATION ML4826 20-Pin PDIP (P20) 20-Pin SOIC (S20) IEAO IAC ISENSE VRMS SS VDC RTCT RAMP 1 RAMP 2 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VEAO VFB VREF VCC2 VCC1 PFC OUT PWM 1 PWM 2 PGND AGND DC ILIMIT 10 TOP VIEW PIN DESCRIPTION PIN NAME FUNCTION PIN NAME FUNCTION 1 2 3 4 5 6 7 8 9 IEAO IAC ISENSE VRMS SS VDC RTCT RAMP 1 RAMP 2 PFC transconductance current error amplifier output PFC gain control reference input Current sense input to the PFC current limit comparator Input for PFC RMS line voltage compensation Connection point for the PWM soft start capacitor PWM voltage feedback input Connection for oscillator frequency setting components PFC ramp input 11 12 13 14 15 16 17 18 19 AGND PGND PWM 2 PWM 1 PFC OUT VCC2 VCC1 VREF VFB VEAO Analog signal ground Return for the PWM totem-pole outputs PWM driver 2 output PWM drive 1 output PFC driver output Positive supply for the PWM drive outputs Positive supply (connected to an internal shunt regulator). Buffered output for the internal 7.5V reference PFC transconductance voltage error amplifier input PFC transconductance voltage error amplifier output When in current mode, this pin functions as the current sense input; when in voltage mode, it is the PWM input from the PFC output (feedforward ramp) PWM current limit comparator input 20 10 DC ILIMIT 2 ML4826 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC Shunt Regulator Current .................................. 55mA ISENSE Voltage ................................................... –3V to 5V Voltage on Any Other Pin .... GND – 0.3V to VCCZ + 0.3V IREF ........................................................................................... 20mA IAC Input Current .................................................... 10mA Peak PFC OUT Current, Source or Sink ................ 500mA Peak PWM OUT Current, Source or Sink ............. 500mA PFC OUT, PWM 1, PWM 2 Energy Per Cycle .......... 1.5mJ Junction Temperature .............................................. 150°C Storage Temperature Range ......................–65°C to 150 °C Lead Temperature (Soldering, 10 sec) ..................... 260°C Thermal Resistance (θJA ) Plastic DIP ....................................................... 67°C/W Plastic SOIC ..................................................... 95°C/W OPERATING CONDITIONS Temperature Range ML4826CX ................................................ 0°C to 70 °C ML4826IX .............................................. –40°C to 85 °C ELECTRICAL CHARACTERISTICS Unless otherwise specified, ICC = 25mA, RRAMP 1 = RT = 52.3kΩ, CRAMP1 = CT = 180pF, TA = Operating Temperature Range (Note 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOLTAGE ERROR AMPLIFIER Input Voltage Range Transconductance Feedback Reference Voltage Input Bias Current Output High Voltage Output Low Voltage Source Current Sink Current Open Loop Gain Power Supply Rejection Ratio CURRENT ERROR AMPLIFIER Input Voltage Range Transconductance Input Offset Voltage Input Bias Current Output High Voltage Output Low Voltage Source Current Sink Current Open Loop Gain Power Supply Rejection Ratio VCCZ – 3V < VCC < VCCZ – 0.5V ∆VIN = ± 0.5V, VOUT = 6V ∆VIN = ± 0.5V, VOUT = 1.5V –40 40 60 60 6.0 VNON INV = VINV, VEAO = 3.75V -1.5 130 195 ±3 –0.5 6.7 0.6 –90 90 75 75 1.0 2 310 ±15 –1.0 V Ω VCCZ – 3V < VCC < VCCZ – 0.5V ∆VIN = ± 0.5V, VOUT = 6V ∆VIN = ± 0.5V, VOUT = 1.5V –40 40 60 60 Note 2 6.0 VNON INV = VINV, VEAO = 3.75V 0 50 2.4 85 2.5 –0.3 6.7 0.6 –80 80 75 75 1.0 7 120 2.6 –1.0 V Ω µ V µA V V µA µA dB dB µ mV µA V V µA µA dB dB 3 ML4826 ELECTRICAL CHARACTERISTICS (Continued) SYMBOL OVP COMPARATOR Threshold Voltage Hysteresis PFC ILIMIT COMPARATOR Threshold Voltage ∆(PFC ILIMIT - Gain Modulator Output) Delay to Output DC ILIMIT COMPARATOR Threshold Voltage Input Bias Current Delay to Output VIN OK COMPARATOR Threshold Voltage Hysteresis GAIN MODULATOR Gain (Note 3) IAC = 100µA, VRMS = VFB = 0V IAC = 50µA, VRMS = 1.2V, VFB = 0V IAC = 50µA, VRMS = 1.8V, VFB = 0V IAC = 100µA, VRMS = 3.3V, VFB = 0V Bandwidth Output Voltage OSCILLATOR Initial Accuracy Voltage Stability Temperature Stability Total Variation Ramp Valley to Peak Voltage Dead Time PFC Only -1 Suffix -2 Suffix CT Discharge Current RAMP 1 Discharge Current REFERENCE Output Voltage Line Regulation Load Regulation Total Variation Long Term Stability TA = 25° C, I(VREF) = 1mA VCCZ – 3V < VCC < VCCZ – 0.5V 1mA < I(VREF) < 20mA Line, Load, Temp TJ = 125°C, 1000 Hours 7.25 5 7.4 7.5 2 7 7.6 10 20 7.65 25 V mV mV V mV VRAMP 1 = 0V, V(RTCT) = 2.5V 125 250 4.5 Line, Temp 170 2.5 310 500 7.5 5 9.5 TA = 25° C VCCZ – 3V < VCC < VCCZ – 0.5V 180 190 1 2 210 200 kHz % % kHz V ns ns mA mA IAC = 100µA IAC = 250µA, VRMS = 1.15V, VFB = 0V 0.72 0.36 1.20 0.55 0.14 0.55 1.80 0.80 0.20 10 0.82 0.95 0.66 2.24 1.01 0.26 MHz V 2.4 0.8 2.5 1.0 2.6 1.2 V V 0.9 1.0 ± 0.3 150 1.1 ±1 300 V µA ns –0.8 100 –1.0 190 150 300 –1.15 V mV ns 2.6 80 2.7 115 2.8 150 V mV PARAMETER CONDITIONS MIN TYP MAX UNITS 4 ML4826 ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PFC Minimum Duty Cycle ML4826-1, VIEAO > 4.0V ML4826-2, VIEAO > 5.7V Maximum Duty Cycle Output Low Voltage VIEAO < 1.2V IOUT = –20mA IOUT = –50mA IOUT = 10mA, VCC = 8V Output High Voltage IOUT = 20mA IOUT = 50mA Rise/Fall Time PWM Duty Cycle Range Output Low Voltage IOUT = –20mA IOUT = –50mA IOUT = 10mA, VCC = 8V Output High Voltage IOUT = 20mA IOUT = 50mA Rise/Fall Time SUPPLY Shunt Regulator Voltage (VCCZ) VCCZ Load Regulation VCCZ Total Variation Start-up Current Operating Current Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Note 2: Includes all bias currents to other circuits connected to the VFB pin. Note 3: Gain = K x 5.3V; K = (IGAINMOD - I OFFSET) x I AC x (VEAO - 1.5V)-1. PARAMETER CONDITIONS MIN TYP MAX UNITS 0 0 90 95 0.4 0.6 0.7 9.5 9.0 10.5 10 50 0.8 3.0 1.5 % % % V V V V V ns CL = 1000pF 0-47 0-48 0.4 0.6 0.7 0-50 0.8 3.0 1.5 % V V V V V ns 9.5 9.0 10.5 10 50 CL = 1000pF 12.8 25mA < ICC < 55mA Load, temp VCC = 11.2V, CL = 0 VCC < VCCZ – 0.5V, CL = 0 12 2.65 12.4 13.5 ±150 14.2 ±300 14.6 V mV V mA mA V V 0.7 22 13 3.0 1.1 28 14 3.35 5 ML4826 TYPICAL PERFORMANCE CHARACTERISTICS 250 250 200 200 Transconductance (µ ) Ω Transconductance (µ ) Voltage Error Amplifier (VEA) Transconductance (gm) 400 Variable Gain Block Constant - K Ω 150 100 50 0 0 1 2 VFB (V) 3 4 5 300 200 100 0 0 1 2 3 VRMS (mV) 20 VEAO VFB 19 2.5V IAC 2 VRMS 4 ISENSE 3 RAMP 1 8 RTCT 7 OSCILLATOR x2 GAIN MODULATOR 3.5kΩ + + - 150 100 50 0 -500 0 IEA Input Voltage (mV) 500 Current Error Amplifier (IEA) Transconductance (gm) 4 5 Variable Gain Control Transfer Characteristic 1 IEAO OVP 3.5kΩ + 17 VCCZ 13.5V VCC 7.5V REFERENCE S -1V + - VEA IEA 2.7V + - VREF 18 Q Q PFC OUT Q Q 15 8V R S R PFC ILIMIT VCCZ UVLO Figure 1. PFC Section Block Diagram. 6 ML4826 FUNCTIONAL DESCRIPTION The ML4826 consists of an average current controlled, continuous boost Power Factor Corrector (PFC) front end and a synchronized Pulse Width Modulator (PWM) back end. The PWM can be used in either current or voltage mode. In voltage mode, feedforward from the PFC output buss can be used to improve the PWM’s line regulation. In either mode, the PWM stage uses conventional trailingedge duty cycle modulation, while the PFC uses leadingedge modulation. This patented leading/trailing edge modulation technique results in a higher useable PFC error amplifier bandwidth, and can significantly reduce the size of the PFC DC buss capacitor. The synchronization of the PWM with the PFC simplifies the PWM compensation due to the controlled ripple on the PFC output capacitor (the PWM input capacitor). The PWM section of the ML4826-1 runs at the same frequency as the PFC. The PWM section of the ML4826-2 runs at twice the frequency of the PFC, which allows the use of smaller PWM output magnetics and filter capacitors while holding down the losses in the PFC stage power components. In addition to power factor correction, a number of protection features have been built into the ML4826. These include soft-start, PFC over-voltage protection, peak current limiting, brown-out protection, duty cycle limit, and under-voltage lockout. POWER FACTOR CORRECTION PFC SECTION Power factor correction makes a non-linear load look like a resistive load to the AC line. For a resistor, the current drawn from the line is in phase with, and proportional to, the line voltage, so the power factor is unity (one). A common class of non-linear load is the input of a most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. The peak-charging effect which occurs on the input filter capacitor in such a supply causes brief high-amplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage. Such a supply presents a power factor to the line of less than one (another way to state this is that it causes significant current harmonics to appear at its input). If the input current drawn by such a supply (or any other non-linear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the AC line and a unity power factor will be achieved. To hold the input current draw of a device drawing power from the AC line in phase with, and proportional to, the input voltage, a way must be found to prevent that device from loading the line except in proportion to the instantaneous line voltage. The PFC section of the ML4826 uses a boost-mode DC-DC converter to accomplish this. The input to the converter is the full wave rectified AC line voltage. No filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges, at twice line frequency, from zero volts to the peak value of the AC input and back to zero. By forcing the boost converter to meet two simultaneous Gain Modulator Figure 1 shows a block diagram of the PFC section of the ML4826. The gain modulator is the heart of the PFC, as it is this circuit block which controls the response of the current loop to line voltage waveform and frequency, rms line voltage, and PFC output voltage. There are three inputs to the gain modulator. These are: 1) A current representing the instantaneous input voltage (amplitude and waveshape) to the PFC. The rectified AC input sine wave is converted to a proportional current via a resistor and is then fed into the gain modulator at IAC . Sampling current in this way minimizes ground noise, as is required in high power switching power conversion environments. The gain modulator responds linearly to this current. 2) A voltage proportional to the long-term rms AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The gain modulator’s output is inversely proportional to VRMS2 (except at unusually low values of V RMS where special gain contouring takes over to limit power dissipation of the circuit components under heavy brown-out conditions). The relationship between VRMS and gain is designated as K, and is illustrated in the Typical Performance Characteristics. conditions, it is possible to ensure that the current which the converter draws from the power line agrees with the instantaneous line voltage. One of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. A commonly used value is 385VDC, to allow for a high line of 270VACrms. The other condition is that the current which the converter is allowed to draw from the line at any given instant must be proportional to the line voltage. The first of these requirements is satisfied by establishing a suitable voltage control loop for the converter, which in turn drives a current error amplifier and switching output driver. The second requirement is met by using the rectified AC line voltage to modulate the output of the voltage control loop. Such modulation causes the current error amplifier to command a power stage current which varies directly with the input voltage. In order to prevent ripple which will necessarily appear at the output of the boost circuit (typically about 10VAC on a 385V DC level) from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. A final refinement is to adjust the overall gain of the PFC such to be proportional to 1/VIN2, which linearizes the transfer function of the system as the AC input voltage varies. Since the boost converter topology in the ML4826 PFC is of the current-averaging type, no slope compensation is required. 7 ML4826 FUNCTIONAL DESCRIPTION (Continued) 3) The output of the voltage error amplifier, VEAO. The gain modulator responds linearly to variations in this voltage. The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual-ground (negative) input of the current error amplifier. In this way the gain modulator forms the reference for the current error loop, and ultimately controls the instantaneous current draw of the PFC from the power line. The general form for the output of the gain modulator is: IGAINMOD ≅ IAC × VEAO 2 VRMS PFC OUTPUT VEAO VFB 19 2.5V IAC 2 VRMS 4 ISENSE 3 GAIN MODULATOR + + + VREF 20 AGND 11 IEAO 1 VEA IEA × 1V More exactly, the output current of the gain modulator is given by: IGAINMOD ≅ K × VEAO – 1.5V × IAC where K is in units of V-1. Note that the output current of the gain modulator is limited to ≅ 200µA. Current Error Amplifier The current error amplifier’s output controls the PFC duty cycle to keep the current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current which results from a negative voltage being impressed upon the ISENSE pin (current into ISENSE ≅ VSENSE/3.5kΩ ). The negative voltage on ISENSE represents the sum of all currents flowing in the PFC circuit, and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. In higher power applications, two current transformers are sometimes used, one to monitor the ID of the boost MOSFET(s) and one to monitor the IF of the boost diode. As stated above, the inverting input of the current error amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from the gain modulator will cause the output stage to increase its duty cycle until the voltage on ISENSE is adequately negative to cancel this increased current. Similarly, if the gain modulator’s output decreases, the output duty cycle will decrease, to achieve a less negative voltage on the ISENSE pin. There is a modest degree of gain contouring applied to the transfer characteristic of the current error amplifier, to increase its speed of response to current-loop perturbations. However, the boost inductor will usually be ( ) (1) Figure 2. Compensation Network Connections for the Voltage and Current Error Amplifiers the dominant factor in overall current loop response. Therefore, this contouring is significantly less marked than that of the voltage error amplifier. This is illustrated in the Typical Performance Characteristics. Cycle-By-Cycle Current Limiter The ISENSE pin, as well as being a part of the current feedback loop, is a direct input to the cycle-by-cycle current limiter for the PFC section. Should the input voltage at this pin ever be more negative than -1V, the output of the PFC will be disabled until the protection flip-flop is reset by the clock pulse at the start of the next PFC power cycle. Overvoltage Protection The OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load should suddenly change. A resistor divider from the high voltage DC output of the PFC is fed to VFB. When the voltage on VFB exceeds 2.7V, the PFC output driver is shut down. The PWM section will continue to operate. The OVP comparator has 125mV of hysteresis, and the PFC will not restart until the voltage at VFB drops below 2.58V. The VFB should be set at a level where the active and passive external power components and the ML4826 are within their safe operating voltages, but not so low as to interfere with the boost voltage regulation loop. 8 ML4826 FUNCTIONAL DESCRIPTION (Continued) Error Amplifier Compensation The PWM loading of the PFC can be modeled as a negative resistor; an increase in input voltage to the PWM causes a decrease in the input current. This response dictates the proper compensation of the two transconductance error amplifiers. Figure 3 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. The current loop compensation is returned to VREF to produce a soft-start characteristic on the PFC: as the reference voltage comes up from zero volts, it creates a differentiated voltage on IEAO which prevents the PFC from immediately demanding a full duty cycle on its boost converter. There are two major concerns when compensating the voltage loop error amplifier; stability and transient response. Optimizing interaction between transient response and stability requires that the error amplifier’s open-loop crossover frequency should be 1/2 that of the line frequency, or 23Hz for a 47Hz line (lowest anticipated international power frequency). The gain vs. input voltage of the ML4826’s voltage error amplifier has a specially shaped nonlinearity such that under steady-state operating conditions the transconductance of the error amplifier is at a local minimum. Rapid perturbations in line or load conditions will cause the input to the voltage error amplifier (VFB) to deviate from its 2.5V (nominal) value. If this happens, the transconductance of the voltage error amplifier will increase significantly, as shown in the Typical Performance Characteristics. This increases the gain-bandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with a conventional linear gain characteristic. The current amplifier compensation is similar to that of the voltage error amplifier with the exception of the choice of crossover frequency. The crossover frequency of the current amplifier should be at least 10 times that of the voltage amplifier, to prevent interaction with the voltage loop. It should also be limited to less than 1/6th that of the switching frequency, e.g. 16.7kHz for a 100kHz switching frequency. For more information on compensating the current and voltage control loops, see Application Notes 33 and 34. Application Note 16 also contains valuable information for the design of this class of PFC. Main Oscillator (RTCT) The oscillator frequency is determined by the values of RT and CT, which determine the ramp and off-time of the oscillator output clock: fOSC = 1 tRAMP + tDEADTIME (2) The deadtime of the oscillator is derived from the following equation: tDEADTIME = 2.5V × CT = 490 × CT 5.1 mA at VREF = 7.5V: tRAMP = CT × R T × 0.51 The ramp of the oscillator may be determined using:  V – 1.25 tRAMP = CT × R T × In  REF   VREF – 3.75 The deadtime is so small (tRAMP >> tDEADTIME) that the operating frequency can typically be approximated by: fOSC = 1 tRAMP (5) (4) (3) For proper reset of internal circuits during dead time, values of 1000pF or greater are suggested for CT. EXAMPLE: For the application circuit shown in the data sheet, with the oscillator running at: fOSC = 200kHz = 1 tRAMP tRAMP = CT × R T × 0.51 = 1× 10−5 Solving for RT x C T yields 2 x 10-4 . Selecting standard components values, CT = 1000pF, and RT = 8.63kΩ . The deadtime of the oscillator adds to the Maximum PWM Duty Cycle (it is an input to the Duty Cycle Limiter). With zero oscillator deadtime, the Maximum PWM Duty Cycle is typically 45%. In many applications, care should be taken that CT not be made so large as to extend the Maximum Duty Cycle beyond 50%. 9 ML4826 FUNCTIONAL DESCRIPTION (Continued) PFC RAMP (RAMP1) The intersection of RAMP1 and the boost current error amplifier output controls the PFC pulse width. RAMP1 can be generated in a similar fashion to the RTCT ramp. The current error amplifier maximum output voltage has a minimum of 6V. The peak value of RAMP1 should not exceed that voltage. Assuming a maximum voltage of 5V for RAMP1, Equation 6 describes the RAMP1 time. With a 100kHz PFC frequency, the resistor tied to VREF, and a 150pF capacitor, Equation 7 solves for the RAMP1 resistor.  VREF  tRAMP1 = CRAMP1 × RRAMP1 × ln   VREF – 5V  = 1.1× RRAMP1 × CRAMP1 RRAMP1 = 10µs tRAMP1 = = 60kΩ 1.1× CRAMP1 1.1× 150pF connected to a separate RC timing network to generate a voltage ramp against which VDC will be compared. Under these conditions, the use of voltage feedforward from the PFC buss can assist in line regulation accuracy and response. As in current mode operation, the DC ILIMIT input would be used for output stage overcurrent protection. No voltage error amplifier is included in the PWM stage of the ML4826, as this function is generally performed on the output side of the PWM’s isolation boundary. To facilitate the design of optocoupler feedback circuitry, an offset has been built into the PWM’s RAMP2 input which allows VDC to command a zero percent duty cycle for input voltages below 1.5V. PWM Current Limit The DC ILIMIT pin is a direct input to the cycle-by-cycle current limiter for the PWM section. Should the input voltage at this pin ever exceed 1V, the output of the PWM will be disabled until the output flip-flop is reset by the clock pulse at the start of the next PWM power cycle. VIN OK Comparator The VIN OK comparator monitors the DC output of the PFC and inhibits the PWM if this voltage on VFB is less than its nominal 2.5V. Once this voltage reaches 2.5V, which corresponds to the PFC output capacitor being charged to its rated boost voltage, the soft-start commences. RAMP2 The RAMP2 input is compared to the feedback voltage (VDC) to set the PWM pulse width. In voltage mode it can be generated using the same method used for the RTCT input. In current mode the primary current sense and slope compensation are fed into the RAMP2 input. Peak current mode control with duty cycles greater than 50% requires slope compensation for stability. Figure 4 displays the method used for the required slope compensation. The example shown adds the slope compensation signal to the current sense signal. Alternatively, the slope compensation signal can also be subtracted form the feedback signal (VDC). In setting up the slope compensation first determine the down slope in the output inductor current. To determine the actual signal required at the RAMP2 input, reflect 1/2 of the inductor downslope through the main transformer, current sense transformer to the ramp input. Internal to the IC is a 1.5V offset in series with the RAMP2 input. In the example show the positive input to the PWM comparator is developed from VREF (7.5V), this limits the RAMP2 input (current sense and slope compensation) to 6 (6) (7) VREF 60kΩ ML4826 RAMP1 150pF Figure 3. PMW SECTION Pulse Width Modulator The PWM section of the ML4826 is straightforward, but there are several points which should be noted. Foremost among these is its inherent synchronization to the PFC section of the device, from which it also derives its basic timing (at the PFC frequency in the ML4826-1, and at twice the PFC frequency in the ML4826-2). The PWM is capable of current-mode or voltage mode operation. In current-mode applications, the PWM ramp (RAMP2) is usually derived directly from a current sensing resistor or current transformer in the primary of the output stage, and is thereby representative of the current flowing in the converter’s output stage. DC ILIMIT, which provides cycleby-cycle current limiting, is typically connected to RAMP 2 in such applications. For voltage-mode operation or certain specialized applications, RAMP2 can be 10 ML4826 FUNCTIONAL DESCRIPTION (Continued) Volts peak. The composite waveform feeding the RAMP2 pin for the PWM consists of the reflected output current signal along with the transformer magnetizing current and the slope compensation signal. Equation 8 describes the composite signal feeding RAMP2, consisting of the primary current of the main transformer and the slope compensation. Equation 9 solves for the required slope compensation peak voltage.   V N VRAMP2 = IPRI + 1 × OUT × S × TS  × 1 ≤ VFB – 1.5V 2 L NP   nCT  R V N VSC =  1 × OUT × S × TS  × SENSE = 1 × 48V × 14 × 5µ sec 471Ω = 2.2V L NP nCT 2 20µH 90 200 2  It is important that the time constant of the PWM soft-start allow the PFC time to generate sufficient output power for the PWM section. The PWM start-up delay should be at least 5ms. Solving for the minimum value of CSS: CSS = 5ms × VCC The ML4826 is a current-fed part. It has an internal shunt voltage regulator, which is designed to regulate the voltage internal to the part at 13.5V. This allows a low power dissipation while at the same time delivering 10V of gate drive at the PWM OUT and PFC OUT outputs. It is important to limit the current through the part to avoid overheating or destroying the part. There are a number of different ways to supply VCC to the ML2826. The method suggested in Figure 5, is one which keeps the ML4826 ICC current to a minimum, and allows for a loosely regulated bootstrap winding. By feeding external gate drive components from the base of Q1, the constant current source does not have to account for variations in the gate drive current. This helps to keep the maximum ICC of the ML4826 to a minimum. Also, the current available to charge the bootstrap capacitor from the bootstrap winding is not limited by the constant 50µA = 167nF 1.5V (11) (8) (9) Soft Start Start-up of the PWM is controlled by the selection of the external capacitor at SS. A current source of 50µA supplies the charging current for the capacitor, and start-up of the PWM begins at 1.5V. Start-up delay can be programmed by the following equation: CSS = tDELAY × 50µA 1.5V (10) where CSS is the required soft start capacitance, and tDELAY is the desired start-up delay. 17 VCC Q14 2N2222 4 x IN4148 ISENSE x Former T3 200:1 C11 1000pF R40 47.0kΩ D1 R21 8.63kΩ 18 VREF 7 RTCT 9 RAMP2 1.5V PWM CMP – + C26 220pF R16 471Ω 11 AGND 1V DC ILIMIT DC ILIMIT – R13 2.2kΩ U2 R38 10.0kΩ 10 + 6 VDC Figure 4. Slope Compensation and Current Sense 11 ML4826 FUNCTIONAL DESCRIPTION (Continued) current source. The circuit guarantees that the maximum operating current is available at all times and minimizes the worst case power dissipation in the IC. Other methods such as a simple series resistor are possible, but can very easily lead to excessive ICC current in the ML4826. Figures 6 and 7 show other possible methods for feeding VCC. trailing edge modulation is determined during the ON time of the switch. Figure 4 shows a typical trailing edge control scheme. In the case of leading edge modulation, the switch is turned OFF right at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned ON. The effective duty-cycle of the leading edge modulation is determined during the OFF time of the switch. Figure 5 shows a leading edge control scheme. One of the advantages of this control technique is that it requires only one system clock. Switch 1 (SW1) turns off and switch 2 (SW2) turns on at the same instant to minimize the momentary “no-load” period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is reduced. Calculation and evaluation have shown that the 120Hz component of the PFC’s output ripple voltage can be reduced by as much as 30% using this method. LEADING/TRAILING MODULATION Conventional Pulse Width Modulation (PWM) techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the system clock. The error amplifier output voltage is then compared with the modulating ramp. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned OFF. When the switch is ON, the inductor current will ramp up. The effective duty cycle of the VBIAS 20V 22kΩ T1 Q2 MJE200 RECTIFIED VAC VCC ML4826 39kΩ RTN 1µF Q1 2N2222 18Ω 1500µF VCC GATE DRIVE Figure 6. VBIAS ML4826 RTN 1µF VCC Figure 5. V CC Bias Circuitry ML4826 RTN Figure 7. 12 ML4826 L1 + I1 VIN SW2 I2 I3 I4 DC SW1 C1 RL RAMP VEAO REF U3 + –EA DFF RAMP OSC U4 CLK + – U1 R Q D U2 Q CLK VSW1 TIME TIME Figure 8. Typical Trailing Edge Control Scheme. L1 + I1 VIN SW2 I2 I3 I4 DC SW1 C1 RL RAMP VEAO U3 + –EA REF VEAO + – CMP U1 DFF R Q D U2 Q CLK VSW1 TIME RAMP OSC U4 CLK TIME Figure 8. Typical Leading Edge Control Scheme. 13 14 F1 8A L1 420µH D5 HFA08TB60 Q8 CR4 IRF840 1N4747 R12 381kΩ D19 1N5819 R41 10Ω Q1 IRF840 Q2 IRF840 T2 R110 2.37kΩ C109 1nF R44 200Ω C21 47nF Y T3 D16 1N5818 R38 10kΩ D25 BYM26C C1 330µF D20 1N5818 D24 BYM26C D22 1N5818 R42 10Ω D23A 1N4747 R43 10kΩ Q10 D23B 2N2907 1N4747 T1 D18 1N5819 T2 R10 10kΩ D17A Q11 1N4747 2N2907 D17B 1N4747 Q7 IRF840 D1 1N4747 R1 10kΩ R37 200Ω R15 100mΩ 5W R6 10Ω D9 1N5818 FERRITE BEAD AC INPUT 85 TO 265VAC ML4826 C2 470nF X R2 R7 470kΩ 470kΩ BR1 6A, 600V FERRITE BEAD NC OUT A IN A VS RTN IN B R46 200Ω R14B 39kΩ 2W Q9 2N2907 D10 1N4747 R14A 39kΩ 2W R29 10Ω D12 1N5819 Q8 IRF840 NC D15 BYM26C D27 1N5818 Q7 IRF840 R30 10Ω D11 1N5819 R103 100Ω R8 10Ω D8 1N5818 VS OUT B R26 10kΩ D25 BYM26C R33 10kΩ Q6 D14 2N2907 1N4747 C103 2.2nF C3 1µF R11 10Ω C107 66nF R105 10kΩ C106 3.3nF C105 100pF R23 2.2kΩ C108 680nF R106 225kΩ Q1 MJE200 R3 18Ω C4 3300µF TC4427 R24 200Ω D21A ΩMBR20100CT-ND D26 1N5818 T1 C5 100µF T1 T1 C17 470pF L3 100nH C13 820µF L2 20µH R40 220Ω C18 470pF R39 220Ω Q12 2N2222 R104 2.2kΩ C14 820µF R36 10Ω D21B D13 20V R25 10Ω C15 4.7µF R28 330Ω C10 10nF R35 43.2kΩ C11 1µF R45 20kΩ 2W C12 1µF 48VDC R18 453kΩ R16 500kΩ R17 500kΩ IEAO IAC ISENSE C116 R101 470nF 10.2kΩ VEAO VFB VREF VCC VCC2 PFC OUT PWM 1 PWM 2 P GND C110 1µF C111 1µF R20 200Ω R19 453kΩ RTN C20 C19 100nF 100nF C102 100nF R102 100kΩ C101 470nF VRMS SS VDC RTCT RAMP 1 RAMP 2 Figure 10. 48V 300W Power Factor Corrected Power Supply Q2 2N2222 D104 1N5818 R34 10Ω Q4 2N2907 Q3 2N2222 R21 200Ω D105 1N5818 C9 C16 1µF 1µF C8 1nF R31 150Ω T2 C104 1nF C114 220pF R113 47kΩ R116 10kΩ Q104 2N2222 R115 R114 8.63kΩ 52.3kΩ C113 C112 150pF 1nF R27 1kΩ C7 1nF C6 R22 3.3kΩ 100nF R32 2.37kΩ TL431 Q5 2N2907 1N4148 BR2 4x1N4148 R112 471Ω DC ILIMIT A GND T3 200:1 ML4826 PHYSICAL DIMENSIONS inches (millimeters) Package: P20 20-Pin PDIP 1.010 - 1.035 (25.65 - 26.29) 20 PIN 1 ID 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26) 0.060 MIN (1.52 MIN) (4 PLACES) 1 0.055 - 0.065 (1.40 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) 0.016 - 0.022 (0.40 - 0.56) SEATING PLANE 0º - 15º 0.008 - 0.012 (0.20 - 0.31) Package: S20 20-Pin SOIC 0.498 - 0.512 (12.65 - 13.00) 20 0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID 1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0º - 8º 0.090 - 0.094 (2.28 - 2.39) 0.012 - 0.020 (0.30 - 0.51) SEATING PLANE 0.005 - 0.013 (0.13 - 0.33) 0.022 - 0.042 (0.56 - 1.07) 0.007 - 0.015 (0.18 - 0.38) 15 ML4826 ORDERING INFORMATION PART NUMBER ML4826CP-1 ML4826CP-2 ML4826CS-1 ML4826CS-2 ML4826IP-1 ML4826IP-2 ML4826IS-1 ML4826IS-2 PWM FREQUENCY 1 x PFC 2 x PFC 1 x PFC 2 x PFC 1 x PFC 2 x PFC 1 x PFC 2 x PFC TEMPERATURE RANGE 0°C to 70° C 0°C to 70° C 0°C to 70° C 0°C to 70° C –40°C to 85°C –40°C to 85°C –40°C to 85°C –40°C to 85°C PACKAGE 20-Pin PDIP (P20) (Obsolete) 20-Pin PDIP (P20) (EOL) 20-Pin SOIC (S20) (Obsolete) 20-Pin SOIC (S20) (EOL) 20-Pin PDIP (P20)(Obsolete) 20-Pin PDIP (P20) (Obsolete) 20-Pin SOIC (S20) (Obsolete) 20-Pin SOIC (S20) (Obsolete) © Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 DS4826-01 16