TC7129

TC7129 4-1/2 Digit Analog-to-Digital Converters with On-Chip LCD Drivers Features: • • • • • • • • • Count Resolution: ±19,999 Resolution on 200 mV Scale: 10 μV True Differential Input and Reference Low Power Consumption: 500 μA at 9V Direct LCD Driver for 4-1/2 Digits, Decimal Points, Low Battery Indicator, and Continuity Indicator Overrange and Underrange Outputs Range Select Input: 10:1 High Common Mode Rejection Ratio: 110 dB External Phase Compensation Not Required General Description: The TC7129 is a 4-1/2 digit Analog-to-Digital Converter (ADC) that directly drives a multiplexed Liquid Crystal Display (LCD). Fabricated in high-performance, lowpower CMOS, the TC7129 ADC is designed specifically for high-resolution, battery-powered digital multimeter applications. The traditional dual-slope method of A/D conversion has been enhanced with a successive integration technique to produce readings accurate to better than 0.005% of full-scale and resolution down to 10 μV per count. The TC7129 includes features important to multimeter applications. It detects and indicates low battery condition. A continuity output drives an annunciator on the display and can be used with an external driver to sound an audible alarm. Overrange and underrange outputs, along with a range-change input, provide the ability to create auto-ranging instruments. For snapshot readings, the TC7129 includes a latch-and-hold input to freeze the present reading. This combination of features makes the TC7129 the ideal choice for full-featured multimeter and digital measurement applications. Applications: • Full-Featured Multimeters • Digital Measurement Devices Device Selection Table Package Code TC7129CPL TC7129CKW TC7129CLW Pin Layout Normal Formed – Package 40-Pin PDIP 44-Pin PQFP 44-Pin PLCC Temperature Range 0°C to +70°C 0°C to +70°C 0°C to +70°C Typical Application Low Battery Continuity V+ 5 pF 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TC7129 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 120 kHz 330 kΩ * 0.1 µF 1 µF 150 kΩ + + 0.1 µF 10 pF 20 kΩ 0.1 µF V+ 10 kΩ 9V – 100 kΩ + VIN *Note: RC network between pins 26 and 28 is not required. © 2006 Microchip Technology Inc. DS21459D-page 1 TC7129 Package Types 40-Pin PDIP OSC1 OSC3 ANNUNICATOR B1, C1, CONT A1, G1, D1 F1, E1, DP1 B2, C2, LO BATT A2, G2, D2 F2, E2, DP2 1 2 3 4 5 6 7 8 9 40 OSC2 39 DP1 38 DP2 37 RANGE 36 DGND 35 REF LO 34 REF HI 33 IN HI 32 IN LO BUFF B3, C3, MINUS 10 Display Output Lines A3, G3, D3 11 F3, E3, DP3 B4, C4, BC5 A4, G4, D4 F4, E4, DP4 BP3 BP2 BP1 VDISP DP4/OR 12 13 14 15 16 17 18 19 20 TC7129CPL 31 30 CREF29 CREF+ 28 COMMON 27 CONTINUITY 26 INT OUT 25 INT IN 24 V+ 23 V22 LATCH/HOLD 21 DP3/UR ANNUNCIATOR B1, C1, CONT A1, G1, D1 B1, C1, CONT 44-Pin QFP A1, G1, D1 RANGE DGND ANNUNCIATOR 44-Pin PLCC RANGE DGND 39 REF LO 38 REF HI 37 IN HI 36 IN LO 35 BUFF 34 NC 33 CREF32 CREF+ 31 COMMON 30 CONTINUITY 29 INT OUT INT IN OSC3 OSC1 OSC2 OSC3 OSC1 OSC2 DP1 DP1 DP2 NC 44 43 42 41 40 39 38 37 36 35 34 F1, E1, DP1 1 B2, C2, BATT 2 A2, G2, D2 3 F2, E2, DP2 4 B3, C3, MINUS 5 NC 6 A3, G3, D3 7 F3, E3, DP3 8 B4, C4, BC5 9 A4, G4, D4 10 F4, E4, DP4 11 12 13 14 15 16 17 18 19 20 21 22 DP4/OR DP3/UR LATCH/HOLD VDISP INT IN NC BP3 BP2 BP1 V+ V33 REF LO 32 REF HI 31 IN HI 30 IN LO 29 BUFF F1, E1, DP1 7 B2, C2, BATT A2, G2, D2 8 9 6 5 4 3 2 1 44 43 42 41 40 F2, E2, DP2 10 B3, C3, MINUS 11 NC 12 A3, G3, D3 13 F3, E3, DP3 14 B4, C4, BC5 15 A4, G4, D4 16 F4, E4, DP4 17 18 19 20 21 22 23 24 25 26 27 28 DP4/OR NC DP3/UR BP1 BP3 BP2 VDISP LATCH/HOLD V+ V- TC7129CKW 28 NC 27 CREF26 CREF+ 25 COMMON 24 CONTINUITY 23 INT OUT TC7129CLW DS21459D-page 2 © 2006 Microchip Technology Inc. DP2 NC TC7129 1.0 ELECTRICAL CHARACTERISTICS *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings* Supply Voltage (V+ to V-)....................................... 15V Reference Voltage (REF HI or REF LO) ........ V+ to V– Input Voltage (IN HI or IN LO) (Note 1).......... V+ to V– VDISP .......................................... V+ to (DGND – 0.3V) Digital Input (Pins 1, 2, 19, 20, 21, 22, 27, 37, 39, 40) .......................... DGND to V+ Analog Input (Pins 25, 29, 30) ....................... V+ to V– Package Power Dissipation (TA ≤ 70°C) Plastic DIP ..................................................... 1.23W PLCC ............................................................. 1.23W Plastic QFP .................................................... 1.00W Operating Temperature Range ............... 0°C to +70°C Storage Temperature Range.............. -65°C to +150°C TC7129 ELECTRICAL SPECIFICATIONS Electrical Characteristics: V+ to V– = 9V, VREF = 1V, TA = +25°C, fCLK = 120 kHz, unless otherwise indicated. Pin numbers refer to 40-pin DIP. Symbol Input Zero Input Reading Zero Reading Drift Ratiometric Reading Range Change Accuracy RE NL CMRR CMVR Rollover Error Linearity Error Common Mode Rejection Ratio Common Mode Voltage Range –0000 — 9996 0.9999 — — — — — eN IIN Noise (Peak-to-Peak Value not Exceeded 95% of Time) Input Leakage Current Scale Factor Temperature Coefficient Note 1: — — — 0000 ±0.5 — 1.0000 1 1 110 (V-) + 1.5 (V+) – 1 14 1 2 +0000 — 10000 1.0001 2 — — — — — 10 7 Counts VIN = 0V, 200 mV scale μV/°C VIN = 0V, 0°C < TA < +70°C Counts VIN = VREF = 1000 mV, Range = 2V Ratio VIN = 1V on High Range, VIN = 0.1V on Low Range Parameter Min Typ Max Unit Test Conditions Counts VIN– = VIN+ = 199 mV Counts 200mV Scale dB V V μVP-P pA VCM = 1V, VIN = 0V, 200 mV scale VIN = 0V 200 mV scale VIN = 0V 200 mV scale VIN = 0V, pins 32, 33 ppm/°C VIN = 199 mV, 0°C < TA < +70°C External VREF = 0 ppm/°C Input voltages may exceed supply voltages, provided input current is limited to ±400 μA. Currents above this value may result in invalid display readings, but will not destroy the device if limited to ±1 mA. Dissipation ratings assume device is mounted with all leads soldered to printed circuit board. © 2006 Microchip Technology Inc. DS21459D-page 3 TC7129 TC7129 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: V+ to V– = 9V, VREF = 1V, TA = +25°C, fCLK = 120 kHz, unless otherwise indicated. Pin numbers refer to 40-pin DIP. Symbol Power VCOM Common Voltage Common Sink Current Common Source Current DGND Digital Ground Voltage Sink Current Supply Voltage Range IS fCLK Supply Current Excluding Common Current Clock Frequency VDISP Resistance Low Battery Flag Activation Voltage Digital Continuity Comparator Threshold Voltages Pull-down Current “Weak Output” Current Sink/Source Pin 22 Source Current Pin 22 Sink Current Note 1: 100 — — — — — — 200 200 2 3/3 3/9 40 3 — 400 10 — — — — mV mV μA μA μA μA μA VOUT pin 27 = High VOUT pin 27 = Low Pins 37, 38, 39 Pins 20, 21 sink/source Pin 27 sink/source 2.8 — — 4.5 — 6 — — — 6.3 3.2 0.6 10 5.3 1.2 9 0.8 120 50 7.2 3.5 — — 5.8 — 12 1.3 360 — 7.7 V mA μA V mA V mA kHz kΩ V VDISP to V+ V+ to V– V+ to pin 28 ΔCommon = +0.1V ΔCommon = -0.1V V+ to pin 36, V+ to V– = 9V ΔDGND = +0.5V V+ to V– V+ to V– = 9V Parameter Min Typ Max Unit Test Conditions Input voltages may exceed supply voltages, provided input current is limited to ±400 μA. Currents above this value may result in invalid display readings, but will not destroy the device if limited to ±1 mA. Dissipation ratings assume device is mounted with all leads soldered to printed circuit board. DS21459D-page 4 © 2006 Microchip Technology Inc. TC7129 2.0 PIN DESCRIPTIONS PIN FUNCTION TABLE Symbol OSC1 OSC3 ANNUNCIATOR B1, C1, CONT A1, G1, D1 F1, E1, DP1 B2, C2, LO BATT A2, G2, D2 F2, E2, DP2 B3, C3, MINUS A3, G3, D3 F3, E3, DP3 B4, C4, BC5 A4, D4, G4 F4, E4, DP4 BP3 BP2 BP1 VDISP DP4/OR DP3/UR LATCH/HOLD Input to first clock inverter. Output of second clock inverter. Backplane square wave output for driving annunciators. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Backplane #3 output to display. Backplane #2 output to display. Backplane #1 output to display. Negative rail for display drivers. Input: When high, turns on most significant decimal point. Output: Pulled high when result count exceeds ±19,999. Input: Second-most significant decimal point on when high. Output: Pulled high when result count is less than ±1000. Input: When floating, ADC operates in Free Run mode. When pulled high, the last displayed reading is held. When pulled low, the result counter contents are shown incrementing during the de-integrate phase of cycle. Output: Negative going edge occurs when the data latches are updated. Can be used for converter status signal. Negative power supply terminal. Positive power supply terminal and positive rail for display drivers. Input to integrator amplifier. Output of integrator amplifier. Input: When low, continuity flag on the display is off. When high, continuity flag is on. Output: High when voltage between inputs is less than +200 mV. Low when voltage between inputs is more than +200 mV. Sets common mode voltage of 3.2V below V+ for DE, 10X, etc. Can be used as pre-regulator for external reference. Positive side of external reference capacitor. Negative side of external reference capacitor. Output of buffer amplifier. Negative input voltage terminal. Positive input voltage terminal. Positive reference voltage. Negative reference voltage Function Descriptions of the pins are listed in Table 2-1. TABLE 2-1: Pin No. Pin No. Pin No. 40-Pin PDIP 44-Pin PQFP 44-Pin PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 40 41 42 43 44 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 18 19 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 24 25 23 24 25 26 27 20 21 22 23 24 26 27 28 29 30 V– V+ INT IN INT OUT CONTINUITY 28 29 30 31 32 33 34 35 25 26 27 29 30 31 32 33 31 32 33 35 36 37 38 39 COMMON CREF+ CREF– BUFFER IN LO IN HI REF HI REF LO © 2006 Microchip Technology Inc. DS21459D-page 5 TC7129 TABLE 2-1: PIN FUNCTION TABLE (CONTINUED) Symbol DGND RANGE DP2 DP1 OSC2 NC Function Internal ground reference for digital section. See Section 4.2.1 “±5V Power Supply”. 3 μA pull-down for 200 mV scale. Pulled high externally for 2V scale. Internal 3 μA pull-down. When high, decimal point 2 will be on. Internal 3 μA pull-down. When high, decimal point 1 will be on. Output of first clock inverter. Input of second clock inverter. No connection. Pin No. Pin No. Pin No. 40-Pin PDIP 44-Pin PQFP 44-Pin PLCC 36 37 38 39 40 — 34 35 36 37 38 6,17, 28, 39 40 41 42 43 44 12, 23, 34, 1 DS21459D-page 6 © 2006 Microchip Technology Inc. TC7129 3.0 DETAILED DESCRIPTION (All pin designations refer to 40-pin PDIP.) The TC7129 is designed to be the heart of a highresolution analog measurement instrument. The only additional components required are a few passive elements: a voltage reference, a LCD and a power source. Most component values are not critical; substitutes can be chosen based on the information given below. The basic circuit for a digital multimeter application is shown in Figure 3-1. See Section 4.0 “Typical Applications”, for variations. Typical values for each component are shown. The sections below give component selection criteria. The resistor and capacitor values are not critical; those shown work for most applications. In some situations, the capacitor values may have to be adjusted to compensate for parasitic capacitance in the circuit. The capacitors can be low-cost ceramic devices. Some applications can use a simple RC network instead of a crystal oscillator. The RC oscillator has more potential for jitter, especially in the least significant digit. See Section 4.5 “RC Oscillator”. 3.2 Integrating Resistor (RINT) 3.1 Oscillator (XOSC, CO1, CO2, RO) The integrating resistor sets the charging current for the integrating capacitor. Choose a value that provides a current between 5 μA and 20 μA at 2V, the maximum full-scale input. The typical value chosen gives a charging current of 13.3 μA: The primary criterion for selecting the crystal oscillator is to choose a frequency that achieves maximum rejection of line frequency noise. To do this, the integration phase should last an integral number of line cycles. The integration phase of the TC7129 is 10,000 clock cycles on the 200 mV range and 1000 clock cycles on the 2V range. One clock cycle is equal to two oscillator cycles. For 60 Hz rejection, the oscillator frequency should be chosen so that the period of one line cycle equals the integration time for the 2V range. EQUATION 3-1: ICHARGE = 2V 13.3 µA 150 kΩ Too high a value for RINT increases the sensitivity to noise pickup and increases errors due to leakage current. Too low a value degrades the linearity of the integration, leading to inaccurate readings. EQUATION 3-1: 1/60 second = 16.7 msec = 1000 clock cycles *2 OSC cycles/clock cycle OSC Frequency This equation gives an oscillator frequency of 120 kHz. A similar calculation gives an optimum frequency of 100 kHz for 50 Hz rejection. © 2006 Microchip Technology Inc. DS21459D-page 7 TC7129 Low Battery Continuity V+ 5 pF CO1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 DP4 /OR 21 VDISP CONTINUITY INT OUT INT IN V+ 22 23 24 25 26 27 ANNUNC OSC3 OSC1 Display Drive Outputs TC7129 COMMON REF LO RANGE REF HI CREF+ DGND CREF– BUFF IN LO IN HI 120 kHz OSC2 DP1 Crystal V– LATCH/ HOLD DP3 /UR DP2 28 29 30 31 32 33 34 35 36 37 38 39 40 330 kΩ CINT 0.1 µF CREF+ 1 µF 150 kΩ RINT + 9V RO 10 pF 0.1 µF CIF RREF 20 kΩ DREF CRF 0.1 µF CO2 V+ 10 kΩ RBIAS – VIN RIF 100 kΩ + Figure 3-1: Standard Circuit. The capacitor should have low dielectric absorption to ensure good integration linearity. Polypropylene and Teflon® capacitors are usually suitable. A good measurement of the dielectric absorption is to connect the reference capacitor across the inputs by connecting: Pin-to-Pin: 20 → 33 (CREF+ to IN HI) 30 → 32 (CREF– to IN LO) A reading between 10,000 and 9998 is acceptable; anything lower indicates unacceptably high dielectric absorption. 3.3 Integrating Capacitor (CINT) The charge stored in the integrating capacitor during the integrate phase is directly proportional to the input voltage. The primary selection criterion for CINT is to choose a value that gives the highest voltage swing while remaining within the high-linearity portion of the integrator output range. An integrator swing of 2V is the recommended value. The capacitor value can be calculated using the following equation: EQUATION 3-1: xI t CINT = INT INT VSWING Where tINT is the integration time. Using the values derived above (assuming 60 Hz operation), the equation becomes: 3.4 Reference Capacitor (CREF) EQUATION 3-2: CINT = 16.7 msec x 13.3 μA = 0.1 μA 2V The reference capacitor stores the reference voltage during several phases of the measurement cycle. Low leakage is the primary selection criterion for this component. The value must be high enough to offset the effect of stray capacitance at the capacitor terminals. A value of at least 1 μF is recommended. DS21459D-page 8 © 2006 Microchip Technology Inc. TC7129 3.5 Voltage Reference (DREF, RREF, RBIAS, CRF) +5V The reference potentiometer (RREF) provides an adjustment for adjusting the reference voltage; any value above 20 kΩ is adequate. The bias resistor (RBIAS) limits the current through DREF to less than 150 μA. The reference filter capacitor (CRF) forms an RC filter with RBIAS to help eliminate noise. TC7129 24 V+ 0.1 µF REF HI 34 3.6 Input Filter (RIF, CIF) For added stability, an RC input noise filter is usually included in the circuit. The input filter resistor value should not exceed 100 kΩ. A typical RC time constant value is 16.7 msec to help reject line frequency noise. The input filter capacitor should have low leakage for a high-impedance input. 35 REF LO 36 DGND 28 COMMON 0.1 µF 33 IN HI 0.1 µF IN LO V– 23 32 VIN + – 3.7 Battery -5V The typical circuit uses a 9V battery as a power source. However, any value between 6V and 12V can be used. For operation from batteries with voltages lower than 6V and for operation from power supplies, see Section 4.2 “Powering the TC7129”. Figure 4-1: Powering the TC7129 From a ±5V Power Supply. 4.2.2 Low Voltage Battery Source 4.0 4.1 TYPICAL APPLICATIONS TC7129 as a Replacement Part A battery with voltage between 3.8V and 6V can be used to power the TC7129 when used with a voltage doubler circuit, as shown in Figure 4-2. The voltage doubler uses the TC7660 DC-to-DC voltage converter and two external capacitors. The TC7129 is a direct pin-for-pin replacement part for the ICL7129. Note, however, that the ICL7129 requires a capacitor and resistor between pins 26 and 28 for phase compensation. Since the TC7129 uses internal phase compensation, these parts are not required and, in fact, must be removed from the circuit for stable operation. 24 V+ REF HI 36 34 + 3.8V to 6V DGND REF LO COMMON 35 28 33 32 4.2 Powering the TC7129 8 2 TC7129 IN HI IN LO V– + VIN While the most common power source for the TC7129 is a 9V battery, there are other possibilities. Some of the more common ones are explained below. – 4.2.1 ±5V Power Supply + TC7660 10 µF 4 5 23 Measurements are made with respect to power supply ground. DGND (pin 36) is set internally to about 5V less than V+ (pin 24); it is not intended to be a power supply input and must not be tied directly to power supply ground. It can be used as a reference for external logic, as explained in Section 4.3 “Connecting to External Logic”, (see Figure 4-1). 3 10 µF + Figure 4-2: Powering the TC7129 From a Low-Voltage Battery. © 2006 Microchip Technology Inc. DS21459D-page 9 TC7129 4.2.3 +5V Power Supply V + Measurements are made with respect to power supply ground. COMMON (pin 28) is connected to REF LO (pin 35). A voltage doubler is needed, since the supply voltage is less than the 6V minimum needed by the TC7129. DGND (pin 36) must be isolated from power supply ground (see Figure 4-3). +5V 24 External Logic 36 ILOGIC TC7129 DGND 24 V+ 0.1 µF 34 23 V- TC7129 35 36 0.1 µF 33 8 V+ 32 2 V– DGND 28 Figure 4-4: Directly to DGND. + VIN External Logic Referenced V+ – + 23 10 µF TC7660 GND 3 4 5 10 µF 24 External Logic + TC7129 – Figure 4-3: Powering the TC7129 From a +5V Power Supply. ILOGIC + 36 DGND 23 4.3 Connecting to External Logic External logic can be directly referenced to DGND (pin 36), provided that the supply current of the external logic does not exceed the sink current of DGND (Figure 4-4). A safe value for DGND sink current is 1.2 mA. If the sink current is expected to exceed this value, a buffer is recommended (see Figure 4-5). V– Figure 4-5: External Logic Referenced to DGND with Buffer. 4.4 Temperature Compensation For most applications, VDISP (pin 19) can be connected directly to DGND (pin 36). For applications with a wide temperature range, some LCDs require that the drive levels vary with temperature to maintain good viewing angle and display contrast. Figure 4-6 shows two circuits that can be adjusted to give temperature compensation of about 10 mV/°C between V+ (pin 24) and VDISP. The diode between DGND and VDISP should have a low turn-on voltage because VDISP cannot exceed 0.3V below DGND. DS21459D-page 10 © 2006 Microchip Technology Inc. TC7129 V+ V+ 1N4148 39 kΩ 200 kΩ 24 39 kΩ 24 2N2222 19 36 TC7129 + 5 kΩ – 75 kΩ 19 36 VDISP DGND 23 20 kΩ TC7129 VDISP DGND 23 18 kΩ V– V– Figure 4-6: Temperature Compensating Circuits. 4.5 RC Oscillator 4.6 Measuring Techniques For applications in which 3-1/2 digit (100 μV) resolution is sufficient, an RC oscillator is adequate. A recommended value for the capacitor is 51 pF. Other values can be used as long as they are sufficiently larger than the circuit parasitic capacitance. The resistor value is calculated as: Two important techniques are used in the TC7129: successive integration and digital auto-zeroing. Successive integration is a refinement to the traditional dual-slope conversion technique. 4.7 Dual-Slope Conversion EQUATION 4-1: R= 0.45 Freq * C For 120 kHz frequency and C = 51 pF, the calculated value of R is 75 kΩ. The RC oscillator and the crystal oscillator circuits are shown in Figure 4-7. TC7129 1 5 pF V+ 40 270 kΩ 10 pF V+ 2 A dual-slope conversion has two basic phases: integrate and de-integrate. During the integrate phase, the input signal is integrated for a fixed period of time; the integrated voltage level is thus proportional to the input voltage. During the de-integrate phase, the integrated voltage is ramped down at a fixed slope, and a counter counts the clock cycles until the integrator voltage crosses zero. The count is a measurement of the time to ramp the integrated voltage to zero and is, therefore, proportional to the input voltage being measured. This count can then be scaled and displayed as a measurement of the input voltage. Figure 4-8 shows the phases of the dual-slope conversion. Integrate De-integrate 120 kHz Zero Crossing TC7129 Time 1 40 75 kΩ 51 pF 2 Figure 4-8: Dual-Slope Conversion. Figure 4-7: Oscillator Circuits. The dual-slope method has a fundamental limitation. The count can only stop on a clock cycle, so that measurement accuracy is limited to the clock frequency. In addition, a delay in the zero-crossing comparator can add to the inaccuracy. Figure 4-9 shows these errors in an actual measurement. © 2006 Microchip Technology Inc. DS21459D-page 11 TC7129 Integrate De-integrate Overshoot due to zero-crossing between clock pulses Time Integrator Residue Voltage Overshoot caused by comparator delay of 1 clock pulse Clock Pulses Figure 4-9: Zero Integrate and Latch Accuracy Errors in Dual-Slope Conversion. INT1 Integrate DE1 De-integrate REST X10 DE2 REST X10 DE3 Zero Integrate TC7129 Integrator Note: Shaded area greatly expanded in time and amplitude. Residual Voltage Figure 4-10: Integration Waveform. DS21459D-page 12 © 2006 Microchip Technology Inc. TC7129 4.8 Successive Integration 4.9 Digital Auto-Zeroing The successive integration technique picks up where dual-slope conversion ends. The overshoot voltage shown in Figure 4-9 (called the “integrator residue voltage”) is measured to obtain a correction to the initial count. Figure 4-10 shows the cycles in a successive integration measurement. The waveform shown is for a negative input signal. The sequence of events during the measurement cycle is shown in Table 4-1. To eliminate the effect of amplifier offset errors, the TC7129 uses a digital auto-zeroing technique. After the input voltage is measured as described above, the measurement is repeated with the inputs shorted internally. The reading with inputs shorted is a measurement of the internal errors and is subtracted from the previous reading to obtain a corrected measurement. Digital auto-zeroing eliminates the need for an external auto-zeroing capacitor used in other ADCs. TABLE 4-1: Phase INT1 DE1 MEASUREMENT CYCLE SEQUENCE Description 4.10 Inside the TC7129 Input signal is integrated for fixed time (1000 clock cycles on 2V scale, 10,000 on 200 mV). Integrator voltage is ramped to zero. Counter counts up until zero-crossing to produce reading accurate to 3-1/2 digits. Residue represents an overshoot of the actual input voltage. Residue voltage is amplified 10 times and inverted. Integrator voltage is ramped to zero. Counter counts down until zero-crossing to correct reading to 4-1/2 digits. Residue represents an undershoot of the actual input voltage. Residue voltage is amplified 10 times and inverted. Integrator voltage is ramped to zero. Counter counts up until zero-crossing to correct reading to 5-1/2 digits. Residue is discarded. Figure 4-11 shows a simplified block diagram of the TC7129. REST Rest; circuit settles. X10 DE2 REST Rest; circuit settles. X10 DE3 © 2006 Microchip Technology Inc. DS21459D-page 13 TC7129 Low Battery Continuity Segment Drives Backplane Drives Annunciator Drive TC7129 OSC1 Latch, Decode Display Multiplexer OSC2 VDISP Up/Down Results Counter OSC3 Sequence Counter/Decoder Control Logic RANGE L/H CONT V+ V– DGND DP1 DP2 UR/DP3 OR/DP4 Analog Section REF HI REF LO INT OUT INT IN COMMON IN IN HI LO BUFF Figure 4-11: TC7129 Functional Block Diagram. CREF REF HI REF LO RINT CINT DE INT1 IN HI DE- DE – + DE+ Buffer Integrator – + 100 pF – Comparator 2 10 pF X10 Comparator 1 + To Digital Section Common INT1, INT2 IN LO DE+ DE– INT REST ZI, X10 – – Continuity V + + 500 kΩ Continuity Comparator TC7129 To Display Driver 200 mV Figure 4-12: DS21459D-page 14 Integrator Block Diagram. © 2006 Microchip Technology Inc. TC7129 4.11 Integrator Section The integrator section includes the integrator, comparator, input buffer amplifier and analog switches (see Table 4-2) used to change the circuit configuration during the separate measurement phases described earlier. (See Figure 4-12). – IN HI + Buffer TABLE 4-2: Label Label DE DE– DE+ INT1 INT2 INT REST ZI X10 X10 SWITCH LEGENDS Description COM Meaning. Open during all de-integrate phases. Closed during all de-integrate phases when input voltage is negative. Closed during all de-integrate phases when input voltage is positive. Closed during the first integrate phase (measurement of the input voltage). Closed during the second integrate phase (measurement of the amplifier offset). Open during both integrate phases. Closed during the rest phase. Closed during the zero integrate phase. Closed during the X10 phase. Open during the X10 phase. CONT IN LO – 200 mV V + 500 kΩ TC7129 To Display Driver (Not Latched) Figure 4-13: Continuity Indicator Circuit. TC7129 The buffer amplifier has a common mode input voltage range from 1.5V above V– to 1V below V+. The integrator amplifier can swing to within 0.3V of the rails. However, for best linearity, the swing is usually limited to within 1V. Both amplifiers can supply up to 80 μA of output current, but should be limited to 20 μA for good linearity. DP4/OR, Pin 20 DP3/UR, Pin 21 LATCH/HOLD Pin 22 CONTINUITY, Pin 27 500 kΩ Figure 4-14: Input/Output Pin Schematic. 4.12 Continuity Indicator 4.13 Common and Digital Ground A comparator with a 200 mV threshold is connected between IN HI (pin 33) and IN LO (pin 32). Whenever the voltage between inputs is less than 200 mV, the CONTINUITY output (pin 27) will be pulled high, activating the continuity annunciator on the display. The continuity pin can also be used as an input to drive the continuity annunciator directly from an external source (see Figure 4-13). A schematic of the input/output nature of this pin is also shown in Figure 4-14. The common and digital ground (DGND) outputs are generated from internal Zener diodes. The voltage between V+ and DGND is the internal supply voltage for the digital section of the TC7129. Common can source approximately 12 μA; DGND has essentially no source capability (see Figure 4-15). © 2006 Microchip Technology Inc. DS21459D-page 15 TC7129 4.17 24 12 µA 3.2V 28 – N + Logic Section 36 5V COM V+ LATCH/Hold TC7129 N P DGND The L/H output goes low during the last 100 cycles of each conversion. This pulse latches the conversion data into the display driver section of the TC7129. This pin can also be used as an input. When driven high, the display will not be updated; the previous reading is displayed. When driven low, the display reading is not latched; the sequence counter reading will be displayed. Since the counter is counting much faster than the backplanes are being updated, the reading shown in this mode is somewhat erratic. 4.18 23 V– Display Driver Figure 4-15: Digital Ground (DGND) and Common Outputs. 4.14 Low Battery The low battery annunciator turns on when supply voltage between V– and V+ drops below 6.8V. The internal zener diode has a threshold of 6.3V. When the supply voltage drops below 6.8V, the transistor tied to V– turns off pulling the “Low Battery” point high. The TC7129 drives a triplexed LCD with three backplanes. The LCD can include decimal points, polarity sign and annunciators for continuity and low battery. Figure 4-16 shows the assignment of the display segments to the backplanes and segment drive lines. The backplane drive frequency is obtained by dividing the oscillator frequency by 1200. This results in a backplane drive frequency of 100 Hz for 60 Hz operation (120 kHz crystal) and 83.3 Hz for 50 Hz operation (100 kHz crystal). Backplane waveforms are shown in Figure 4-17. These appear on outputs BP1, BP2, BP3 (pins 16, 17 and 18). They remain the same, regardless of the segments being driven. Other display output lines (pins 4 through 15) have waveforms that vary depending on the displayed values. Figure 4-18 shows a set of waveforms for the A, G, D outputs (pins 5, 8, 11 and 14) for several combinations of “ON” segments. The ANNUNCIATOR DRIVE output (pin 3) is a square wave, running at the backplane frequency (100 Hz or 83.3 Hz) with a peak-to-peak voltage equal to DGND voltage. Connecting an annunciator to pin 3 turns it on; connecting it to its backplane turns it off. 4.15 Sequence and Results Counter A sequence counter and associated control logic provide signals that operate the analog switches in the integrator section. The comparator output from the integrator gates the results counter. The results counter is a six-section up/down decade counter that holds the intermediate results from each successive integration. 4.16 Overrange and Underrange Outputs When the results counter holds a value greater than ±19,999, the DP4/OR output (Pin 20) is driven high. When the results counter value is less than ±1000, the DP3/UR output (Pin 21) is driven high. Both signals are valid on the falling edge of LATCH/HOLD (L/H) and do not change until the end of the next conversion cycle. The signals are updated at the end of each conversion, unless the L/H input (Pin 22) is held high. Pins 20 and 21 can also be used as inputs for external control of decimal points 3 and 4. Figure 4-14 shows a schematic of the input/output nature of these pins. DS21459D-page 16 © 2006 Microchip Technology Inc. TC7129 Low Battery Continuity BP1 BP2 Backplane Connections BP3 Low Battery Continuity F4, E4, DP4 A4, G4, D4 B4, C4, BC4 F3, E3, DP3 A3, G3, D3 B3, C3, MINUS B1, C1, Continuity A1, G1, D1 F1, E1, DP1 B2, C2, Low Battery A2, G2, D2 F2, E2, DP2 Figure 4-16: Display Segment Assignments. VDD VH VL VDISP VDD VH VL VDISP VDD VH VL VDISP VDD VH All On VL VDISP BP1 b Segment Line All Off BP2 a Segment On d, g Off BP3 a, g On d Off Figure 4-17: Backplane Waveforms. Figure 4-18: Waveforms. Typical Display Output © 2006 Microchip Technology Inc. DS21459D-page 17 TC7129 5.0 5.1 PACKAGING INFORMATION Package Marking Information Package marking data not available a this time. 5.2 Taping Forms Us er Direction of F eed P in 1 P in 1 W, Width of C arrier T ape P , P itch S tandard R eel C omponent Orientation R evers e R eel C omponent Orientation Component Taping Orientation for 44-Pin PQFP Devices User Direction of Feed Pin 1 W P Standard Reel Component Orientation for 713 Suffix Device Carrier Tape, Number of Components Per Reel and Reel Size Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 44-Pin PQFP 24 mm 16 mm 500 13 in Note: Drawing does not represent total number of pins. DS21459D-page 18 © 2006 Microchip Technology Inc. TC7129 40-Lead Plastic Dual In-line (P) – 600 mil Body (PDIP) E1 D n E 2 1 α A c β eB Units Dimension Limits n p INCHES* NOM 40 .100 .175 .150 A1 B1 B p MILLIMETERS NOM 40 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 13.46 13.84 51.94 52.26 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.51 5 10 5 10 A2 L MAX Number of Pins Pitch Top to Seating Plane A .160 .190 4.83 Molded Package Thickness .140 .160 4.06 A2 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .595 .600 .625 15.88 Molded Package Width E1 .530 .545 .560 14.22 Overall Length D 2.045 2.058 2.065 52.45 Tip to Seating Plane L .120 .130 .135 3.43 c Lead Thickness .008 .012 .015 0.38 Upper Lead Width B1 .030 .050 .070 1.78 Lower Lead Width B .014 .018 .022 0.56 eB Overall Row Spacing § .620 .650 .680 17.27 α Mold Draft Angle Top 5 10 15 15 β Mold Draft Angle Bottom 5 10 15 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-016 MIN MAX MIN © 2006 Microchip Technology Inc. DS21459D-page 19 TC7129 44-Lead Plastic Leaded Chip Carrier (LW) – Square (PLCC) E E1 #leads=n1 D1 D n12 CH2 x 45 ° CH1 x 45 ° A3 A2 α 35° A B1 B p D2 c β E2 Units Dimension Limits n p INCHES* NOM 44 .050 11 .165 .173 .145 .153 .028 .020 .024 .029 .040 .045 .000 .005 .685 .690 .685 .690 .650 .653 .650 .653 .590 .620 .590 .620 .008 .011 .026 .029 .013 .020 0 5 0 5 A1 MAX Number of Pins Pitch Pins per Side n1 Overall Height A .180 4.57 .160 4.06 Molded Package Thickness A2 .035 0.89 Standoff § A1 A3 Side 1 Chamfer Height .034 0.86 Corner Chamfer 1 CH1 .050 1.27 .010 0.25 Corner Chamfer (others) CH2 Overall Width E .695 17.65 Overall Length D .695 17.65 Molded Package Width E1 .656 16.66 Molded Package Length D1 .656 16.66 Footprint Width E2 .630 16.00 Footprint Length .630 16.00 D2 c Lead Thickness .013 0.33 Upper Lead Width B1 .032 0.81 B .021 0.53 Lower Lead Width α Mold Draft Angle Top 10 10 β Mold Draft Angle Bottom 10 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-047 Drawing No. C04-048 MIN MAX MIN MILLIMETERS NOM 44 1.27 11 4.19 4.39 3.68 3.87 0.71 0.51 0.61 0.74 1.02 1.14 0.00 0.13 17.40 17.53 17.40 17.53 16.51 16.59 16.51 16.59 14.99 15.75 14.99 15.75 0.20 0.27 0.66 0.74 0.33 0.51 0 5 0 5 DS21459D-page 20 © 2006 Microchip Technology Inc. TC7129 44-Lead Plastic Quad Flatpack (KW) 10x10x2.0 mm Body, 1.95/0.25 mm Lead Form (PQFP) E E1 p D1 D 2 1 B n CHAMFER VARIES α c φ A2 A β L Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Foot Length Footprint Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom § n p A A2 A1 L F φ E D E1 D1 c B α β .004 .012 5° 5° .077 .010 .029 0° MIN A1 INCHES NOM 44 F MILLIMETERS* MAX MIN NOM 44 0.80 BSC .096 .083 .041 7° 1.95 0.25 0.73 0° 1.95 REF. 3.5° 7° 13.90 BSC 13.90 BSC 10.00 BSC 10.00 BSC .009 .018 16° 16° 0.11 0.30 5° 5° 0.23 0.45 16° 16° 2.00 0.88 2.45 2.10 1.03 MAX .031 BSC .079 .035 .077 REF. 3.5° .547 BSC .547 BSC .394 BSC .394 BSC * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M REF: Reference Dimension, usually without tolerance, for information purposes only. See ASME Y14.5M JEDEC Equivalent: MO-112 AA-1 Revised 07-21-05 Drawing No. C04-119 © 2006 Microchip Technology Inc. DS21459D-page 21 TC7129 NOTES: DS21459D-page 22 © 2006 Microchip Technology Inc. TC7129 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temp. XX Pkg XX Taping Direction Examples: a) b) c) Device: TC7129: 4-1/2 Digit Analog-to-Digital Converter TC7129CPL: TC7129CKW713: TC7129CLW: 40-Pin PDIP 44-Pin PQFP Tape and Reel 44-Pin PLCC Temperature: C I = 0°C to +70°C = -25°C to +85°C Package: PL KW LW JL = = = = 40-Pin PDIP 40-Pin PQFP 44-Pin PLCC 40-Pin CDIP Taping Direction: 713 = Standard Taping © 2006 Microchip Technology Inc. DS21459D-page 23 TC7129 NOTES: DS21459D-page 24 © 2006 Microchip Technology Inc. TC7129 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2006 Microchip Technology Inc. DS21459D-page 25 TC7129 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: TC7129 Questions: 1. What are the best features of this document? Y N Literature Number: DS21459D FAX: (______) _________ - _________ 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21459D-page 26 © 2006 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2006 Microchip Technology Inc. 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