TC7135CKW

TC7135 4-1/2 Digit A/D Converter Features • • • • • • • • • • • • • Low Rollover Error: ±1 Count Max Nonlinearity Error: ±1 Count Max Reading for 0V Input True Polarity Indication at Zero for Null Detection Multiplexed BCD Data Output TTL-Compatible Outputs Differential Input Control Signals Permit Interface to UARTs and Microprocessors Blinking Display Visually Indicates Overrange Condition Low Input Current: 1 pA Low Zero Reading Drift: 2 µV/°C Auto-Ranging Supported with Overrange and Underrange Signals Available in PDIP and Surface-Mount Packages General Description The TC7135 4-1/2 digit A/D Converter (ADC) offers 50 ppm (1 part in 20,000) resolution with a maximum nonlinearity error of 1 count. An auto-zero cycle reduces zero error to below 10 µV and zero drift to 0.5 µV/°C. Source impedance errors are minimized by a 10 pA maximum input current. Rollover error is limited to ±1 count. Microprocessor-based measurement systems are supported by the BUSY, STROBE and RUN/HOLD control signals. Remote data acquisition systems with data transfer via UARTs are also possible. The additional control pins and multiplexed BCD outputs make the TC7135 the ideal converter for display or microprocessor-based measurement systems. Applications • Precision Analog Signal Processor • Precision Sensor Interface • High Accuracy DC Measurements Functional Block Diagram Set VREF = 1V VREF IN 100 kΩ 5V 1 2 V– TC7135 UNDERRANGE 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Clock Input 120 kHz REF IN OVERRANGE 3 ANALOG STROBE COMMON Analog GND 4 RUN/HOLD INT OUT 1 µF 0.47 µF 5 DIGTAL GND AZ IN 6 BUFF OUT POLARITY 100 kΩ 7 CLOCK IN C – Signal 1 µF 8 REF 100 kΩ BUSY Input CREF+ 9 (LSD) D1 –INPUT 0.1 µF 10 D2 +INPUT 11 D3 +5V V+ 12 D4 D5 (MSD) 13 (MSB) B8 B1 (LSB) 14 B4 B2  2004 Microchip Technology Inc. DS21460C-page 1 TC7135 Package Types 28-Pin PLCC INT OUT ANALOG COM REF IN STROBE 44-Pin MQFP DIGITAL GND RUN/HOLD POLARITY CLOCK IN V– OR UR NC NC NC AZ IN 5 BUFF OUT 6 REF CAP– 7 REF CAP+ 8 –INPUT 9 +INPUT 10 V+ 11 12 13 14 15 16 17 18 D4 (MSD) D5 (MSB) B8 (LSB) B1 D3 B2 B4 25 RUN/HOLD 24 DIGTAL GND 23 POLARITY NC 34 NC 35 STROBE 36 OVERRANGE 37 UNDERRANGE 38 V– 39 REF IN 40 COMMON ANALOG 41 NC 42 NC 43 NC 44 33 32 31 30 29 28 27 26 25 24 23 22 NC 21 NC 20 D3 19 D4 18 B8 TC7135 22 CLOCK IN 21 BUSY 20 D1 (LSD) 19 D2 TC7135 NC 17 B4 16 B2 15 B1 14 D5 13 NC 12 NC NC NC NC NC NC 48 NC 47 NC 46 NC 45 D3 44 D4 43 B8 42 B4 41 B2 40 NC 39 B1 38 D5 37 NC 36 NC 35 NC 34 NC 33 NC V+ D1 1 NC 2 INT OUT 3 4 BUFF OUT D2 8 4 3 2 1 28 27 26 BUSY 5 CREF– 6 CREF+ 7 –INPUT 9 10 11 V+ NC D2 28-Pin PDIP RUN/HOLD STROBE V– REF IN ANALOG COM INT OUT AZ IN BUFF OUT CREF– CREF+ –INPUT 1 2 3 4 5 6 7 8 9 28 UNDERRANGE 27 OVERRANGE NC NC NC NC 26 STROBE 25 RUN/HOLD 24 DIGiTAL GND 23 POLARITY NC 1 NC 2 NC 3 NC 4 NC 5 NC 6 OVERRANGE 7 UNDERRANGE 8 NC 9 V– 10 REF IN 11 ANALOG COM 12 NC 13 NC 14 NC 15 NC 16 64-Pin MQFP CLOCK IN DGND POL BUSY +INPUT –INPUT D1 AZ IN 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 l TC7135 22 CLOCK IN 21 BUSY 20 D1 (LSD) 19 D2 18 D3 17 D4 16 B8 (MSB) 15 B4 +INPUT 10 V+ 11 (MSD) D5 12 (LSB) B1 13 B2 14 TC7135 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CREF– NC NC NC NC AZ IN NC CREF+ NC INT OUT BUFF OUT +INPUT NOTE: NC = No internal connection. DS21460C-page 2 NC  2004 Microchip Technology Inc. NC TC7135 1.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings† Positive Supply Voltage.....................................................+6V Negative Supply Voltage ...................................................- 9V Analog Input Voltage (Pin 9 or 10) ...............V+ to V- (Note 2) Reference Input Voltage (Pin 2) ................................. V+ to VClock Input Voltage ................................................... 0V to V+ Operating Temperature Range .......................... 0°C to +70°C Storage Temperature Range ........................ –65°C to +150°C Package Power Dissipation; (TA ≤ 70°C) 28-Pin PDIP .......................................................... 1.14Ω 28-Pin PLCC ......................................................... 1.00Ω 44-Pin MQFP .......................................................................... 64-Pin MQFP ........................................................ 1.14Ω † Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, TA = +25°C, FCLOCK = 120 kHz, V+ = +5V, V- = -5V. (see Functional Block Diagram). Parameters Analog Display Reading with Zero Volt Input Zero Reading Temperature Coefficient Full Scale Temperature Coefficient Nonlinearity Error Differential Linearity Error Display Reading in Ratiometric Operation ± Full Scale Symmetry Error (Rollover Error) Input Leakage Current Noise Digital Input Low Current Input High Current Output Low Voltage Output High Voltage; B1, B2, B4, B8, D1 –D5 Busy, Polarity, Overrange, Underrange, Strobe Clock Frequency Note 1: 2: 3: 4: 5: 6: 7: 8: FCLK IIL IIH VOL VOH — — — 2.4 4.9 10 0.08 0.2 4.4 4.99 100 10 0.4 5 5 µA µA V V V VIN = 0V VIN = +5V IOL = 1.6 mA IOH = 1 mA IOH = 10 µA ±FSE IIN eN TCZ TCFS NL DNL -0.0000 — — — — +0.9996 — — — ±0.0000 0.5 — 0.5 0.01 +0.0000 2 5 1 — Display Reading µV/°C ppm/°C Count LSB Display Reading Count pA µVP-P Note 2, Note 3 VIN = 0V, (Note 4) VIN = 2V, (Note 4, Note 5) Note 6 Note 6 VIN = VREF, (Note 2) -VIN = +VIN, (Note 7) Note 3 Peak-to-Peak Value not Exceeded 95% of Time Sym Min. Typ. Max. Units Conditions +0.9999 +1.0000 0.5 1 15 1 10 — 0 200 1200 kHz Note 8 Limit input current to under 100 µA if input voltages exceed supply voltage. Full-scale voltage = 2V VIN = 0V 30°C ≤ TA ≤ +70°C External reference temperature coefficient less than 0.01 ppm/°C. -2V ≤ VIN ≤ +2V. Error of reading from best fit straight line. IVIN| = 1.9959 Specification related to clock frequency range over which the TC7135 correctly performs its various functions. Increased errors result at higher operating frequencies.  2004 Microchip Technology Inc. DS21460C-page 3 TC7135 DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, TA = +25°C, FCLOCK = 120 kHz, V+ = +5V, V- = -5V. (see Functional Block Diagram). Parameters Power Supply Positive Supply Voltage Negative Supply Voltage Positive Supply Current Negative Supply Current Power Dissipation Note 1: 2: 3: 4: 5: 6: 7: 8: V+ VI+ IPD 4 -3 — — — 5 -5 1 0.7 8.5 6 -8 3 3 30 V V mA mA mW FCLK = 0 Hz FCLK = 0 Hz FCLK = 0 Hz Sym Min. Typ. Max. Units Conditions Limit input current to under 100 µA if input voltages exceed supply voltage. Full-scale voltage = 2V VIN = 0V 30°C ≤ TA ≤ +70°C External reference temperature coefficient less than 0.01 ppm/°C. -2V ≤ VIN ≤ +2V. Error of reading from best fit straight line. IVIN| = 1.9959 Specification related to clock frequency range over which the TC7135 correctly performs its various functions. Increased errors result at higher operating frequencies. DS21460C-page 4  2004 Microchip Technology Inc. TC7135 2.0 PIN DESCRIPTIONS The description of the pins are listed in Table 2-1. TABLE 2-1: Pin Number 28-Pin PDIP, 28-Pin PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 PIN FUNCTION TABLE Pin Number 44-Pin MQFP* 39 40 41 2 3 4 5 6 7 8 9 14 15 16 17 18 19 20 25 26 27 Pin Number 64-Pin MQFP* 10 11 12 18 20 22 23 26 28 30 32 38 39 41 42 43 44 45 52 53 54 Symbol V– REF IN ANALOG COMMON INT OUT AZ IN BUFF OUT CREF– CREF+ –INPUT +INPUT V+ D5 B1 B2 B4 B8 D4 D3 D2 D1 BUSY Description Negative power supply input. External reference input. Reference point for REF IN. Integrator output. Integrator capacitor connection. Auto-zero inpt. Auto-zero capacitor connection. Analog input buffer output. Integrator resistor connection. Reference capacitor input. Reference capacitor negative connection. Reference capacitor input. Reference capacitor positive connection. Analog input. Analog input negative connection. Analog input. Analog input positive connection. Positive power supply input. Digit drive output. Most Significant Digit (MSD) Binary Coded Decimal (BCD) output. Least Significant bit (LSb). BCD output. BCD output. BCD output. Most Significant bit (MSb). Digit drive output. Digit drive output. Digit drive output. Digit drive output. Least Significant Digit (LSD). Busy output. At the beginning of the signal-integration phase, BUSY goes high and remains high until the first clock pulse after the integrator zero crossing. Clock input. Conversion clock connection. Polarity output. A positive input is indicated by a logic high output. The polarity output is valid at the beginning of the reference integrate phase and remains valid until determined during the next conversion. Digital logic reference input. Run/Hold input. When at a logic high, conversions are performed continuously. A logic low holds the current data as long as the low condition exists. Strobe output. The STROBE output pulses low in the center of the digit drive outputs. Overrange output. A logic high indicates that the analog input exceeds the full-scale input range. Underrange output. A logic high indicates that the analog input is less than 9% of the full-scale input range. 22 23 28 29 55 57 CLOCK IN POLARITY 24 25 30 31 58 59 DGND RUN/HOLD 26 27 28 36 37 38 60 7 8 STROBE OVERRANGE UNDERRANGE * Pins not identified or documented are NC (no connects).  2004 Microchip Technology Inc. DS21460C-page 5 TC7135 3.0 DETAILED DESCRIPTION All pin designations refer to the 28-pin PDIP package. The dual-slope converter accuracy is unrelated to the integrating resistor and capacitor values, as long as they are stable during a measurement cycle. An inherent benefit is noise immunity. Noise spikes are integrated, or averaged, to zero during the integration periods. Integrated ADCs are immune to the large conversion errors that plague successive approximation converters in high-noise environments (see Figure 3-1). Analog Input Signal 3.1 Dual-Slope Conversion Principles The TC7135 is a dual-slope, integrating A/D converter. An understanding of the dual-slope conversion technique will aid in following the detailed TC7135 operational theory. The conventional dual-slope converter measurement cycle has two distinct phases: 1. 2. Input signal integration. Reference voltage integration (de-integration). Integrator + Switch Drive Comparator + The input signal being converted is integrated for a fixed time period. Time is measured by counting clock pulses. An opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The reference integration time is directly proportional to the input signal. In a simple dual-slope converter, a complete conversion requires the integrator output to “ramp-up” and “ramp-down”. A simple mathematical equation relates the input signal, reference voltage and integration time: REF Voltage Phase Control Polarity Control Clock Control Logic Display Integrator Output VIN VIN Variable Reference Integrate Time Counter ≈ VREF ≈ 1/2 VREF EQUATION 3-1: VREF T DEINT 1 -T ----------------------- ∫ INT V IN ( T ) DT = ------------------------------RINT C INT 0 RINT C INT Where: VREF TINT TDEINT = = = Reference voltage Signal integration time (fixed) Reference voltage integration time (variable) Fixed Signal Integrate Time FIGURE 3-1: Basic Dual-Slope Converter. 3.2 TC7135 Operational Theory The TC7135 incorporates a system zero phase and integrator output voltage zero phase to the normal twophase dual-slope measurement cycle. Reduced system errors, fewer calibration steps and a shorter overrange recovery time result. The TC7135 measurement cycle contains four phases: 1. 2. 3. 4. System zero. Analog input signal integration. Reference voltage integration. Integrator output zero. For a constant VIN: EQUATION 3-2: V REF T DEINT V IN = ------------------------------T INT Internal analog gate status for each phase is shown in Figure 3-1. TABLE 3-1: System Zero INTERNAL ANALOG GATE STATUS SWI — Closed — — SWRI+ — — Closed* — SWRI— — — — SWZ Closed — — — SWR Closed — — — SW1 Closed — Closed Closed SWIZ — — — Closed Reference Figures Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Conversion Cycle Phase Input Signal Integration Reference Voltage Integration Integrator Output Zero * Assumes a positive polarity input signal. SWRI would be closed for a negative input signal. DS21460C-page 6  2004 Microchip Technology Inc. TC7135 3.2.1 SYSTEM ZERO 3.2.3 During this phase, errors due to buffer, integrator and comparator offset voltages are compensated for by charging CAZ (auto-zero capacitor) with a compensating error voltage. With a zero input voltage, the integrator output will remain at zero. The external input signal is disconnected from the internal circuitry by opening the two SWI switches. The internal input points connect to the ANALOG COMMON pin. The reference capacitor charges to the reference voltage potential through SWR. A feedback loop, closed around the integrator and comparator, charges the CAZ capacitor with a voltage to compensate for buffer amplifier, integrator and comparator offset voltages (see Figure 3-2). SWI +IN SWRISWRI+ Analog Input Buffer RINT + – SWIZ SWZ – + SWZ Integrator REFERENCE VOLTAGE INTEGRATION The previously charged reference capacitor is connected with the proper polarity to ramp the integrator output back to zero (see Figure 3-4). The digital reading displayed is: EQUATION 3-3: [ Differential Input ] Reading = 10, 000 ---------------------------------------------VREF Analog Input Buffer RINT + – SWIZ SWZ SWI +IN SWRISWRI+ CINT CSZ Comparator – + + To Integrator – Digital Section CINT CSZ Comparator + – To Digital Section SWRI+ SWZ Analog Common SWI IN SWRI- REF IN SWR CREF SWZ SWRI+ SWZ Analog Common SWI IN SWRI- REF IN SWR CREF SW1 Switch Open Switch Closed SW1 Switch Open Switch Closed FIGURE 3-4: Integration Cycle. 3.2.4 Reference Voltage FIGURE 3-2: 3.2.2 System Zero Phase. INTEGRATOR OUTPUT ZERO ANALOG INPUT SIGNAL INTEGRATION The TC7135 integrates the differential voltage between the +INPUT and -INPUT pins. The differential voltage must be within the device Common mode range; -1V from either supply rail, typically. The input signal polarity is determined at the end of this phase. SWI +IN SWRI+ SWRIAnalog Input Buffer RINT + – SWIZ SWZ This phase ensures the integrator output is at 0V when the system zero phase is entered. It also ensures that the true system offset voltages are compensated for. This phase normally lasts 100 to 200 clock cycles. If an overrange condition exists, the phase is extended to 6200 clock cycles (see Figure 3-5). Analog Input Buffer RINT + – SWIZ SWZ SWI +IN SWRI+ SWRI- CINT CSZ Comparator + + – To Integrator Digital Section – CINT CSZ Comparator + + – To Integrator Digital Section – REF IN SWR CREF SWRI+ SWRI- SWRI+ SWRI- REF IN SWR CREF SWZ Analog Common SWI IN SWZ SWZ Analog Common SWI IN SWZ SW1 Switch Open Switch Closed SW1 Switch Open Switch Closed FIGURE 3-5: Phase. Integrator Output Zero FIGURE 3-3: Phase. Input Signal Integration  2004 Microchip Technology Inc. DS21460C-page 7 TC7135 4.0 4.1 ANALOG SECTION FUNCTIONAL DESCRIPTION Differential Inputs 4.3 Reference Voltage Input The reference voltage input (REF IN) must be a positive voltage with respect to ANALOG COMMON. A reference voltage circuit is shown in Figure 4-1. V+ V+ The TC7135 operates with differential voltages (+INPUT, pin 10 and -INPUT, pin 9) within the input amplifier Common mode range, which extends from 1V below the positive supply to 1V above the negative supply. Within this Common mode voltage range, an 86 dB Common mode rejection ratio is typical. The integrator output also follows the Common mode voltage and must not be allowed to saturate. A worstcase condition exists, for example, when a large positive Common mode voltage with a near full scale negative differential input voltage is applied. The negative input signal drives the integrator positive when most of its swing has been used up by the positive Common mode voltage. For these critical applications, the integrator swing can be reduced to less than the recommended 4V full scale swing, resulting in some loss of accuracy. The integrator output can swing within 0.3V of either supply without loss of linearity. TC7135 REF IN ANALOG COMMON 10 kΩ MCP1525 2.5 VREF 1 µF 10 kΩ Analog Ground FIGURE 4-1: Reference. Using An External 4.2 Analog Common Input The ANALOG COMMON pin is used as the -INPUT return during auto-zero and de-integrate. If -INPUT is different from ANALOG COMMON, a Common mode voltage exists in the system. However, this signal is rejected by the excellent CMRR of the converter. In most applications, –INPUT will be set at a fixed, known voltage (power supply common, for instance). In this application, ANALOG COMMON should be tied to the same point, thus removing the Common mode voltage from the converter. The reference voltage is referenced to ANALOG COMMON. DS21460C-page 8  2004 Microchip Technology Inc. TC7135 5.0 DIGITAL SECTION FUNCTIONAL DESCRIPTION The major digital subsystems within the TC7135 are illustrated in Figure 5-1, with timing relationships shown in Figure 5-2. The multiplexed BCD output data can be displayed on LCD or LED displays. The digital section is best described through a discussion of the control signals and data outputs. Polarity D5 MSB D4 Digit D3 Drive Multiplexer From Analog Section Polarity FF Zero Cross Detect Latch Latch Latch Latch Latch D2 Signal D1 LSB Data Output 13 B1 14 B2 15 B4 16 B8 Counters Control Logic 24 DGND 22 Clock In 25 RUN/ HOLD 27 Overrange 28 Underrange 26 STROBE 21 Busy FIGURE 5-1: Digital Section Functional Diagram.  2004 Microchip Technology Inc. DS21460C-page 9 TC7135 5.2 Integrator Output Signal System Integrate Reference Integrate Zero 10,000 20,001 10,001 Counts Counts (Fixed) Counts (Max) Full Measurement Cycle 40,002 Counts STROBE Output During the measurement cycle, the STROBE control line is pulsed low five times. The five low pulses occur in the center of the digit drive signals (D1, D2, D3, D5) (see Figure 5-3). D5 (MSD) goes high for 201 counts when the measurement cycles end. In the center of the D5 pulse, 101 clock pulses after the end of the measurement cycle, the first STROBE occurs for one half clock pulse. After the D5 digit strobe, D4 goes high for 200 clock pulses. The STROBE then goes low 100 clock pulses after D4 goes high. This continues through the D1 digit drive pulse. The digit drive signals will continue to permit display scanning. STROBE pulses are not repeated until a new measurement is completed. The digit drive signals will not continue if the previous signal resulted in an overrange condition. The active-low STROBE pulses aid BCD data transfer to UARTs, processors and external latches. For more information, please refer to Application Note 784 (DS00784). TC835 Outputs Busy * Busy Overrange when Applicable Underrange when Applicable Expanded Scale Below Digit Scan D5 D4 D3 D2 100 Counts STROBE D1 * First D5 of System Zero and Reference Integrate One Count Longer Signal Integrate * Reference Integrate Auto-Zero Digit Scan * D5 for Overrange D4 D3 D2 D1 End of Conversion D5 (MSD) Data D1 (LSD) Data B1 B8 D4 Data D3 Data D2 Data D5 Data FIGURE 5-2: Outputs. Timing Diagrams For STROBE 200 Counts D5 201 Counts 200 Counts 200 Counts 200 Counts Note Absence of STROBE 200 Counts 5.1 RUN/HOLD Input When left open, this pin assumes a logic ‘1’ level. With a RUN/HOLD = 1, the TC7135 performs conversions continuously, with a new measurement cycle beginning every 40,002 clock pulses. When RUN/HOLD changes to a logic ‘0’, the measurement cycle in progress will be completed, with the data held and displayed as long as the logic ‘0’ condition exists. A positive pulse (>300 nsec) at RUN/HOLD initiates a new measurement cycle. The measurement cycle in progress when RUN/HOLD initially assumed the logic ‘0’ state must be completed before the positive pulse can be recognized as a single conversion run command. The new measurement cycle begins with a 10,001 count auto-zero phase. At the end of this phase, the busy signal goes high. D4 D3 D2 D1 200 Counts *Delay between Busy going Low and First STROBE pulse is dependent on Analog Input. FIGURE 5-3: Strobe Signal Low Five Times Per Conversion. DS21460C-page 10  2004 Microchip Technology Inc. TC7135 5.3 BUSY Output 5.6 POLARITY Output At the beginning of the signal integration phase, BUSY goes high and remains high until the first clock pulse after the integrator zero crossing. BUSY returns to the logic ‘0’ state once the measurement cycle ends in an overrange condition. The internal display latches are loaded during the first clock pulse after BUSY and are latched at the clock pulse end. The BUSY signal does not go high at the beginning of the measurement cycle, which starts with the auto-zero cycle. A positive input is registered by a logic ‘1’ polarity signal. The polarity bit is valid at the beginning of reference integrate and remains valid until determined during the next conversion. The polarity bit is valid even for a zero reading. Signals less than the converter's LSB will have the signal polarity determined correctly. This is useful in null applications. 5.4 OVERRANGE Output 5.7 Digit Drive Outputs If the input signal causes the reference voltage integration time to exceed 20,000 clock pulses, the OVERRANGE output is set to a logic ‘1’. The OVERRANGE output register is set when BUSY goes low and is reset at the beginning of the next reference integration phase. Digit drive signals are positive-going signals. The scan sequence is D5 to D1. All positive pulses are 200 clock pulses wide, with the exception D5, which is 201 clock pulses wide. All five digits are scanned continuously, unless an overrange condition occurs. In an overrange condition, all digit drives are held low from the final STROBE pulse until the beginning of the next reference integrate phase. The scanning sequence is then repeated. This provides a blinking visual display indication. 5.5 UNDERRANGE Output If the output count is 9% of full scale or less (-1800 counts), the UNDERRANGE register bit is set at the end of BUSY. The bit is set low at the next signal integration phase. 5.8 BCD Data Outputs The binary coded decimal (BCD) bits B8, B4, B2 and B1 are positive-true logic signals. The data bits become active at the same time as the digit drive signals. In an overrange condition, all data bits are at a logic ‘0’ state.  2004 Microchip Technology Inc. DS21460C-page 11 TC7135 6.0 6.1 6.1.1 TYPICAL APPLICATIONS Component Value Selection INTEGRATING RESISTOR 6.1.3 AUTO-ZERO AND REFERENCE CAPACITORS The integrating resistor RINT is determined by the fullscale input voltage and the output current of the buffer used to charge the integrator capacitor (CINT). Both the buffer amplifier and the integrator have a class A output stage, with 100 µA of quiescent current. A 20 µA drive current gives negligible linearity errors. Values of 5 µA to 40 µA give good results. The exact value of an integrating resistor for a 20 µA current is easily calculated. The size of the auto-zero capacitor has some influence on the noise of the system, with a larger capacitor reducing the noise. The reference capacitor should be large enough such that stray capacitance to ground from its nodes is negligible. The dielectric absorption of the reference and autozero capacitors are only important at power-on or when the circuit is recovering from an overload. Smaller or cheaper capacitors can be used if accurate readings are not required for the first few seconds of recovery. 6.1.4 REFERENCE VOLTAGE EQUATION 6-1: Full Scale Voltage RINT = ------------------------------------------20 µ A The analog input required to generate a full-scale output is VIN = 2 VREF. The stability of the reference voltage is a major factor in the overall absolute accuracy of the converter. For this reason, it is recommended that a high-quality reference be used where high-accuracy absolute measurements are being made. 6.1.2 INTEGRATING CAPACITOR (CINT) The product of integrating resistor and capacitor should be selected to give the maximum voltage swing that ensures the tolerance build-up will not saturate the integrator swing (approximately 0.3V from either supply). For ±5V supplies and ANALOG COMMON tied to supply ground, a ±3.5V to ±4V full scale integrator swing is adequate. A 0.10 µF to 0.47 µF is recommended. In general, the value of CINT is given by: 6.2 6.2.1 Conversion Timing LINE FREQUENCY REJECTION A signal integration period at a multiple of the 60 Hz line frequency will maximize 60 Hz “line noise” rejection. A 100 kHz clock frequency will reject 50 Hz, 60 Hz and 400 Hz noise. This corresponds to five readings per second (see Table 6-1 and Table 6-2). EQUATION 6-2: C INT [ 10, 000 × clock period ] × I INT = --------------------------------------------------------------------------integrator output voltage swing ( 10, 000 ) ( clock period ) × 20 µ A = ----------------------------------------------------------------------------integrator output voltage swing A very important characteristic of the integrating capacitor CINT is that it has low dielectric absorption to prevent rollover or ratiometric errors. A good test for dielectric absorption is to use the capacitor with the input tied to the reference. This ratiometric condition should read half scale 0.9999, with any deviation probably due to dielectric absorption. Polypropylene capacitors give undetectable errors at reasonable cost. Polystyrene and polycarbonate capacitors may also be used in less critical applications. TABLE 6-1: CONVERSION RATE VS. CLOCK FREQUENCY Conversion Rate (Conv./Sec.) 2.5 3 5 7.5 10 20 30 Oscillator Frequency (kHz) 100 120 200 300 400 800 1200 DS21460C-page 12  2004 Microchip Technology Inc. TC7135 TABLE 6-2: LINE FREQUENCY REJECTION VS. CLOCK FREQUENCY Line Frequency Rejection (Hz) 60 the ratio between this resistor and the integrating resistor (a few tens of ohms in the recommended circuit), the comparator delay can be compensated and the maximum clock frequency extended by approximately a factor of 3. At higher frequencies, ringing and second-order breaks will cause significant nonlinearities in the first few counts of the instrument. The minimum clock frequency is established by leakage on the auto-zero and reference capacitors. With most devices, measurement cycles as long as 10 seconds give no measurable leakage error. The clock used should be free from significant phase or frequency jitter. Several suitable low-cost oscillators are shown in Section 6.0 “Typical Applications”. The multiplexed output means that if the display takes significant current from the logic supply, the clock should have good PSRR. Oscillator Frequency (kHz) 300 200 150 120 100 40 33-1/3 250 166-2/3 125 100 100 50 6.4 50, 60,400 Zero Crossing Flip Flop The conversion rate is easily calculated: EQUATION 6-3: Clock Frequency (Hz) Reading 1/sec = ---------------------------------------------------4000 6.3 High Speed Operation The maximum conversion rate of most dual-slope A/D converters is limited by the frequency response of the comparator. The comparator in this circuit follows the integrator ramp with a 3 µsec delay, at a clock frequency of 160 kHz (6 µsec period). Half of the first reference integrate clock period is lost in delay. This means that the meter reading will change from 0 to 1 with a 50 µV input, 1 to 2 with 150 µV, 2 to 3 at 250 µV, etc. This transition at midpoint is considered desirable by most users. However, if the clock frequency is increased appreciably above 200 kHz, the instrument will flash "1" on noise peaks, even when the input is shorted. For many dedicated applications where the input signal is always of one polarity, the delay of the comparator need not be a limitation. Since the nonlinearity and noise do not increase substantially with frequency, clock rates of up to ~1 MHz may be used. For a fixed clock frequency, the extra count (or counts) caused by comparator delay will be a constant and can be subtracted out digitally. The clock frequency may be extended above 160 kHz without this error, however, by using a low value resistor in series with the integrating capacitor. The effect of the resistor is to introduce a small pedestal voltage on to the integrator output at the beginning of the reference integrate phase. By careful selection of The flip flop interrogates the data once every clock pulse after the transients of the previous clock pulse and half clock pulse have died down. False zero crossings caused by clock pulses are not recognized. Of course, the flip flop delays the true zero crossing by up to one count in every instance. If a correction were not made, the display would always be one count too high. Therefore, the counter is disabled for one clock pulse at the beginning of the reference integrate (de-integrate) phase. This one-count delay compensates for the delay of the zero crossing flip flop and allows the correct number to be latched into the display. Similarly, a onecount delay at the beginning of auto-zero gives an overload display of 0000 instead of 0001. No delay occurs during signal integrate so that true ratiometric readings result. 6.5 Generating a Negative Supply A negative voltage can be generated from the positive supply by using a TC7135 (see Figure 6-1). +5V V+ 11 8 (-5V) 10 µF 24 + 4 + 10 µF 2 3 5 TC7660 TC7135 1 V– FIGURE 6-1: Generator. Negative Supply Voltage  2004 Microchip Technology Inc. DS21460C-page 13 TC7135 +5V 20 19 18 17 12 D1 D2 D3 D4 D5 4 INT OUT 0.33 µF 1 µF AZ IN 4.7 kΩ 23 POL 6 BUFF OUT CREF – 7 100 kΩ 22 F TC7135 1 µF 200 kHz IN CREF+ 8 100 kΩ 10 + +INPUT Analog 16 1 µF B8 9 Input 15 –INPUT – B4 14 B2 3 ANALOG B1 13 COMMON REF V– IN V+ 12 11 V+ 5V 100 kΩ MCP1525 1 µF 5 b c 7 7 X7 5 9 15 7 7 Blank MSD On Zero 6 D 2 C 1 B 7 A RBI DM7447A 16 +5V FIGURE 6-2: R2 4-1/2 Digit ADC With Multiplexed Common Anode Led Display. R1 C FO 16 kΩ +5V 56 kΩ 2 + 8 7 1 4 1 kΩ 1. Gates are 74C04 R 1 R2 1 F O = ------------------------------------------------- , R P = -----------------R1 + R 2 2C ( 0.41RP + 0.7R 1 ) a. If R1 = R2 = R1, F≅ 0.55/RC b. If R2 >> R1, F ≅ 0.45/R1C c. If R2