MTA18ASF1G72PDZ-2G3A2

8GB (x72, ECC, DR) 288-Pin DDR4 RDIMM Features DDR4 SDRAM RDIMM MTA18ASF1G72PDZ – 8GB Features Figure 1: 288-Pin RDIMM (MO-309, R/C-E) • DDR4 functionality and operations supported as defined in the component data sheet • 288-pin, registered dual in-line memory module (RDIMM) • Fast data transfer rates: PC4-2400 and PC4-2133 • 8GB (1 Gig x 72) • VDD = 1.20V (NOM) • VPP = 2.5V (NOM) • VDDSPD = 2.5V (NOM) • Supports ECC error detection and correction • Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals • Low-power auto self refresh (LPASR) • Data bus inversion (DBI) for data bus • On-die V REFDQ generation and calibration • Dual-rank • On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM • 16 internal banks; 4 groups of 4 banks each • Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) • Selectable BC4 or BL8 on-the-fly (OTF) • Gold edge contacts • Halogen-free • Fly-by topology • Terminated control, command, and address bus Module height: 31.25mm (1.23in) Figure 2: 288-Pin RDIMM (MO-309, R/C-E1) Module height: 31.25mm (1.23in) Options Marking • Operating temperature – Commercial (0°C ≤ T OPER ≤ 95°C) • Package – 288-pin DIMM (halogen-free) • Frequency/CAS latency – 0.83ns @ CL = 17 (DDR4-2400) – 0.93ns @ CL = 15 (DDR4-2133) None Z -2G3 -2G1 Table 1: Key Timing Parameters Data Rate (MT/s) Industry Speed NomenGrade clature CL = 20, CL = 19 CL = 18 CL = 17 CL = 16 CL = 15 CL = 14 CL = CL = 13 12 CL = 11 CL = 10 1333 tRCD tRP tRC (ns) (ns) – 14.16 14.16 46.16 CL = 9 (ns) -2G6 PC4-2666 2666 2666 2400 2133 2133 1866 1866 1600 – -2G4 PC4-2400 – 2400 2400 2400 2133 1866 1866 1600 1600 – 1333 13.32 13.32 45.32 -2G3 PC4-2400 – 2400 2400 2133 2133 1866 1866 1600 1600 1333 – 14.16 14.16 46.16 -2G1 PC4-2133 – – – 2133 2133 1866 1866 1600 1600 – 1333 13.5 46.5 PDF: 09005aef8591cad3 asf18c1gx72pdz.pdf - Rev. E 1/16 EN 1 13.5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 8GB (x72, ECC, DR) 288-Pin DDR4 RDIMM Features Table 2: Addressing Parameter 8GB Row address 32K A[14:0] Column address 1K A[9:0] Device bank group address 4 BG[1:0] Device bank address per group 4 BA[1:0] Device configuration 4Gb (512 Meg x 8), 16 banks Module rank address 2 CS_n[1:0] Table 3: Part Numbers and Timing Parameters – 8GB Modules Base device: MT40A512M,1 4Gb DDR4 SDRAM Module Part Number2 Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MTA18ASF1G72PDZ-2G3__ 8GB 1 Gig x 72 19.2 GB/s 0.83ns/2400 MT/s 17-17-17 MTA18ASF1G72PDZ-2G1__ 8GB 1 Gig x 72 17.0 GB/s 0.93ns/2133 MT/s 15-15-15 Notes: 1. The data sheet for the base device can be found on micron.com. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MTA18ASF1G72PDZ-2G3B1. PDF: 09005aef8591cad3 asf18c1gx72pdz.pdf - Rev. E 1/16 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 288-Pin DDR4 RDIMM Pin Assignments Pin Assignments The pin assignment table below is a comprehensive list of all possible pin assignments for DDR4 RDIMM modules. See the Functional Block Diagram for pins specific to this module. Table 4: Pin Assignments 288-Pin DDR4 RDIMM Front 288-Pin DDR4 RDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 NC 37 VSS 73 VDD 109 VSS 145 NC 181 DQ29 217 VDD 253 DQ41 2 VSS 38 DQ24 74 CK0_t 110 DQS14_t/ TDQS14_t 146 VREFCA 182 VSS 218 CK1_t 254 VSS 3 DQ4 39 VSS 75 CK0_c 111 DQS14_c/ TDQS14_c 147 VSS 183 DQ25 219 CK1_c 255 DQS5_c 4 VSS 40 DQS12_t/ TDQS12_t 76 VDD 112 VSS 148 DQ5 184 VSS 220 VDD 256 DQS5_t 5 DQ0 41 DQS12_c/ TDQS12_c 77 VTT 113 DQ46 149 VSS 185 DQS3_c 221 VTT 257 VSS 6 VSS 42 VSS 78 EVENT_n 114 VSS 150 DQ1 186 DQS3_t 222 PARITY 258 DQ47 7 DQS9_t/ TDQS9_t 43 DQ30 79 A0 115 DQ42 151 VSS 187 VSS 223 VDD 259 VSS 8 DQS09_c/ TDQS9_c 44 VSS 80 VDD 116 VSS 152 DQS0_c 188 DQ31 224 BA1 260 DQ43 9 VSS 45 DQ26 81 BA0 117 DQ52 153 DQS0_t 189 VSS 225 A10/ AP 261 VSS 10 DQ6 46 VSS 82 RAS_n/ A16 118 VSS 154 VSS 190 DQ27 226 VDD 262 DQ53 11 VSS 47 CB4 83 VDD 119 DQ48 155 DQ7 191 VSS 227 NC 263 VSS 12 DQ2 48 VSS 84 CS0_n 120 VSS 156 VSS 192 CB5 228 WE_n/ A14 264 DQ49 13 VSS 49 CB0 85 VDD 121 DQS15_t/ TDQS15_t 157 DQ3 193 VSS 229 VDD 265 VSS 14 DQ12 50 VSS 86 CAS_n/ A15 122 DQS15_c/ TDQS15_c 158 VSS 194 CB1 230 NC 266 DQS6_c 15 VSS 51 DQS17_t/ TDQS17_t 87 ODT0 123 VSS 159 DQ13 195 VSS 231 VDD 267 DQS6_t 16 DQ8 52 DQS17_c/ TDQS17_c 88 VDD 124 DQ54 160 VSS 196 DQS8_c 232 A13 268 VSS 17 VSS 53 VSS 89 CS1_n/ NC 125 VSS 161 DQ9 197 DQS8_t 233 VDD 269 DQ55 18 DQS10_t/ TDQS10_t 54 CB6 90 VDD 126 DQ50 162 VSS 198 VSS 234 A17 270 VSS 19 DQS10_c/ TDQS10_c 55 VSS 91 ODT1/ NC 127 VSS 163 DQS1_c 199 CB7 235 NC/ C2 271 DQ51 20 VSS 56 CB2 92 VDD 128 DQ60 164 DQS1_t 200 VSS 236 VDD 272 VSS 21 DQ14 57 VSS 93 CS2_n/ C0 129 VSS 165 VSS 201 CB3 237 CS3_n/ C1, NC 273 DQ61 22 VSS 58 RESET_n 94 VSS 130 DQ56 166 DQ15 202 VSS 238 SA2 274 VSS 23 DQ10 59 VDD 95 DQ36 131 VSS 167 VSS 203 CKE1/ NC 239 VSS 275 DQ57 24 VSS 60 CKE0 96 VSS 168 DQ11 204 VDD 240 DQ37 276 VSS PDF: 09005aef8591cad3 asf18c1gx72pdz.pdf - Rev. E 1/16 EN 132 DQS16_t/ TDQS16_t 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 288-Pin DDR4 RDIMM Pin Assignments Table 4: Pin Assignments (Continued) 288-Pin DDR4 RDIMM Front 288-Pin DDR4 RDIMM Back Pin Symbol Pin Symbol Pin Symbol 25 DQ20 61 VDD 97 DQ32 26 VSS 62 ACT_n 98 VSS 27 DQ16 63 BG0 99 28 VSS 64 VDD 100 DQS13_c/ 136 TDQS13_c 29 DQS11_t/ TDQS11_t 65 30 DQS11_c/ TDQS11_c 66 A9 31 VSS 67 VDD A12/BC_n 101 Pin Symbol Pin Symbol Pin Symbol Pin Symbol 133 DQS16_c/ TDQS16_c Pin 169 VSS 205 NC 241 VSS 277 DQS7_c 134 VSS 170 DQ21 206 VDD 242 DQ33 278 DQS7_t DQ62 171 VSS 207 BG1 243 VSS 279 VSS VSS 172 DQ17 208 ALERT_n 244 DQS4_c 280 DQ63 DQS13_t/ 135 TDQ13_t Symbol VSS 137 DQ58 173 VSS 209 VDD 245 DQS4_t 281 VSS 102 DQ38 138 VSS 174 DQS2_c 210 A11 246 VSS 282 DQ59 103 VSS 139 SA0 175 DQS2_t 211 A7 247 DQ39 283 VSS 32 DQ22 68 A8 104 DQ34 140 SA1 176 VSS 212 VDD 248 VSS 284 VDDSPD 33 VSS 69 A6 105 VSS 141 SCL 177 DQ23 213 A5 249 DQ35 285 SDA 34 DQ18 70 VDD 106 DQ44 142 VPP 178 VSS 214 A4 250 VSS 286 VPP 35 VSS 71 A3 107 VSS 143 VPP 179 DQ19 215 VDD 251 DQ45 287 VPP 36 DQ28 72 A1 108 DQ40 144 NC 180 VSS 216 A2 252 VSS 288 VPP PDF: 09005aef8591cad3 asf18c1gx72pdz.pdf - Rev. E 1/16 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 288-Pin DDR4 RDIMM DQ Map DQ Map Table 5: Component-to-Module DQ Map Component Reference Number Component DQ U2 U4 U6 U9 U11 PDF: 09005aef8591cad3 asf18c1gx72pdz.pdf - Rev. E 1/16 EN Module DQ Module Pin Number Component Reference Number Component DQ Module DQ Module Pin Number 0 3 157 U3 0 11 168 1 0 5 1 8 16 2 2 12 2 10 23 3 1 150 3 9 161 4 7 155 4 15 166 5 4 3 5 12 14 6 6 10 6 14 21 7 5 148 7 13 159 0 19 179 0 27 190 1 16 27 1 24 38 2 18 34 2 26 45 3 17 172 3 25 183 4 23 177 4 31 188 5 20 25 5 28 36 6 22 32 6 30 43 7 21 170 7 29 181 0 CB3 201 0 35 249 1 CB0 49 1 32 97 2 CB2 56 2 34 104 3 CB1 194 3 33 242 4 CB7 199 4 39 247 U5 U8 5 CB4 47 5 36 95 6 CB6 54 6 38 102 7 CB5 192 7 37 240 0 43 260 0 51 271 1 40 108 1 48 119 2 42 115 2 50 126 3 41 253 3 49 264 4 47 258 4 55 269 5 44 106 5 52 117 6 46 113 6 54 124 7 45 251 7 53 262 0 59 282 0 56 130 1 56 130 1 59 282 2 58 137 2 57 275 3 57 275 3 58 137 4 63 280 4 60 128 5 60 128 5 63 280 6 62 135 6 61 273 7 61 273 7 62 135 U10 U12 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 288-Pin DDR4 RDIMM DQ Map Table 5: Component-to-Module DQ Map (Continued) Component Reference Number Component DQ U13 U15 U17 U19 PDF: 09005aef8591cad3 asf18c1gx72pdz.pdf - Rev. E 1/16 EN Module DQ Module Pin Number Component Reference Number Component DQ Module DQ Module Pin Number 0 48 119 U14 0 40 108 1 51 271 1 43 260 2 49 264 2 41 253 3 50 126 3 42 115 4 52 117 4 44 106 5 55 269 5 47 258 6 53 262 6 45 251 7 54 124 7 46 113 0 32 97 0 CB0 49 1 35 249 1 CB3 201 2 33 242 2 CB1 194 3 34 104 3 CB2 56 4 36 95 4 CB4 47 5 39 247 5 CB7 199 6 37 240 6 CB5 192 7 38 102 7 CB6 54 0 24 38 0 16 27 1 27 190 1 19 179 2 25 183 2 17 172 3 26 45 3 18 34 4 28 36 4 20 25 5 31 188 5 23 177 6 29 181 6 21 170 7 30 43 7 22 32 0 8 16 0 0 5 1 11 168 1 3 157 2 9 161 2 1 150 3 10 23 3 2 12 4 12 14 4 4 3 5 15 166 5 7 155 6 13 159 6 5 148 7 14 21 7 6 10 U16 U18 U20 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 288-Pin DDR4 RDIMM Functional Block Diagram Functional Block Diagram Figure 3: Functional Block Diagram CS1_n CS0_n DQS4_t DQS4_c DQS0_t DQS0_c DBI4_n/DM4_n DBI0_n/DM0_n DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VSS DM_n/ CS_n DQS_t DQS_c DBI_n DQ DQ DQ DQ DQ DQ DQ DQ ZQ U2 DM_n/ CS_n DQS_t DQS_c DBI_n DQ DQ DQ DQ DQ DQ DQ DQ U20 VSS ZQ DQS1_t DQS1_c DBI1_n/DM1_n DM_n/ CS_n DQS_t DQS_c DBI_n DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ DQ DQ DQ DQ DQ DQ DQ ZQ U8 DM_n/ CS_n DQS_t DQS_c DBI_n DQ DQ DQ DQ DQ DQ DQ DQ U15 ZQ DQS5_t DQS5_c DBI5_n/DM5_n VSS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VSS DM_n/ CS_n DQS_t DQS_c DBI_n DQ DQ DQ DQ DQ DQ DQ DQ ZQ U3 DM_n/ CS_n DQS_t DQS_c DBI_n DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ ZQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U19 VSS ZQ DQS2_t DQS2_c DBI2_n/DM2_n VSS DM_n/ CS_n DQS_t DQS_c DBI_n U9 DM_n/ CS_n DQS_t DQS_c DBI_n DQ DQ DQ DQ DQ DQ DQ DQ U14 ZQ DQS6_t DQS6_c DBI6_n/DM6_n VSS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 VSS DM_n/ CS_n DQS_t DQS_c DBI_n DQ DQ DQ DQ DQ DQ DQ DQ ZQ U4 DM_n/ CS_n DQS_t DQS_c DBI_n DQ DQ DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U18 ZQ DQS7_t DQS7_c DBI7_n/DM7_n DQS3_t DQS3_c DBI3_n/DM3_n VSS DM_n/ CS_n DQS_t DQS_c DBI_n VSS DQ DQ DQ DQ DQ DQ DQ DQ ZQ U10 DM_n/ CS_n DQS_t DQS_c DBI_n DQ DQ DQ DQ DQ DQ DQ DQ U13 ZQ VSS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VSS DM_n/ CS_n DQS_t DQS_c DBI_n DQ DQ DQ DQ DQ DQ DQ DQ ZQ U5 VSS DM_n/ CS_n DQS_t DQS_c DBI_n DQ DQ DQ DQ DQ DQ DQ DQ DM_n/ CS_n DQS_t DQS_c DBI_n DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U17 VSS ZQ DQS8_t DQS8_c DBI8_n/DM8_n DQ DQ DQ DQ DQ DQ DQ DQ ZQ U11 VSS DM_n/ CS_n DQS_t DQS_c DBI_n DQ DQ DQ DQ DQ DQ DQ DQ ZQ U6 U1 U16 SCL VTT VREFCA EVENT# DDR4 SDRAM VTT DDR4 SDRAM VDD SPD EEPROM/Temp sensor, register VSS DDR4 SDRAM, register A/BCS0_n: Rank 0 A/BCS1_n: Rank 1 A/BBA[1:0]: DDR4 SDRAM A/BBG[1:0]: DDR4 SDRAM A/BACT_n: DDR4 SDRAM A/BA[17,13:0]: DDR4 SDRAM A/B-RAS_n/A16: DDR4 SDRAM A/B-CAS_n/A15: DDR4 SDRAM A/B-WE_n/A14: DDR4 SDRAM A/BCKE0: Rank 0 A/BCKE1: Rank 1 A/BODT0: Rank 0 A/BODT1: Rank 1 A/BPAR: DDR4 SDRAM ALERT_DRAM: DDR4 SDRAM R E G I S T E R & DDR4 SDRAM, register DDR4 SDRAM U7 CS0_n CS1_n BA[1:0] BG[1:0] ACT_n A[17, 13:0] RAS_n/A16 CAS_n/A15 WE_n/A14 CKE0 CKE1 ODT0 ODT1 PAR_IN ALERT_CONN SA0 SA1 SA2 SCL SDA DDR4 SDRAM, register Control, command, and address termination VPP SDA A1 A2 SA0 SA1 SA2 ZQ CK[3:0]_t CK[3:0]_c VDD SPD EEPROM/ Temperature sensor EVT A0 Command, control, address, and clock line terminations: VDDSPD VSS CKNC_t CKNC_c VSS A/B-CS_n[1:0], A/B-BA[1:0]A/B-BG[1:0], A/B-ACT_n, A/B-A[17, 13:0], A/B-RAS_n/A16, A/B-CAS_n/A15, A/B-WE_n/A14, A/B-PAR, A/B-CKE[1:0], A/B-ODT[1:0] U12 Rank 0: U2–U6, U8–U11 Rank 1: U12–U20 DM_n/ CS_n DQS_t DQS_c DBI_n DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ ZQ VSS CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM_n/ CS_n DQS_t DQS_c DBI_n P L L CK_t CK_c RESET_CONN CK[1:0]_t DDR4 SDRAM CK[1:0]_c RESET_DRAM: DDR4 SDRAM ZQ VSS Note: PDF: 09005aef8591cad3 asf18c1gx72pdz.pdf - Rev. E 1/16 EN 1. The ZQ ball on each DDR4 component is connected to an external 240Ω ±1% resistor that is tied to ground. It is used for the calibration of the component’s ODT and output driver. 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 288-Pin DDR4 RDIMM General Description General Description High-speed DDR4 SDRAM modules use DDR4 SDRAM devices with two or four internal memory bank groups. DDR4 SDRAM modules utilizing 4- and 8-bit-wide DDR4 SDRAM devices have four internal bank groups consisting of four memory banks each, providing a total of 16 banks. 16-bit-wide DDR4 SDRAM devices have two internal bank groups consisting of four memory banks each, providing a total of eight banks. DDR4 SDRAM modules benefit from DDR4 SDRAM's use of an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM effectively consists of a single 8n-bitwide, four-clock data transfer at the internal DRAM core and eight corresponding n-bitwide, one-half-clock-cycle data transfers at the I/O pins. DDR4 modules use two sets of differential signals: DQS_t and DQS_c to capture data and CK_t and CK_c to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. Fly-By Topology DDR4 modules use faster clock speeds than earlier DDR technologies, making signal quality more important than ever. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the connector). Inherent to fly-by topology, the timing skew between the clock and DQS signals can be easily accounted for by using the write-leveling feature of DDR4. Module Manufacturing Location Micron Technology manufactures modules at sites world-wide. Customers may receive modules from any of the following manufacturing locations: Table 6: DRAM Module Manufacturing Locations Manufacturing Site Location Country of Origin Specified on Label Boise, USA USA Aguadilla, Puerto Rico Puerto Rico Xian, China China Singapore Singapore PDF: 09005aef8591cad3 asf18c1gx72pdz.pdf - Rev. E 1/16 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 288-Pin DDR4 RDIMM Address Mapping to DRAM Address Mapping to DRAM Address Mirroring To achieve optimum routing of the address bus on DDR4 multi rank modules, the address bus will be wired as shown in the table below, or mirrored. For quad rank modules, ranks 1 and 3 are mirrored and ranks 0 and 2 are non-mirrored. Highlighted address pins have no secondary functions allowing for normal operation when crosswired. Data is still read from the same address it was written. However, Load Mode operations require a specific address. This requires the controller to accommodate for a rank that is "mirrored." Systems may reference DDR4 SPD to determine if the module has mirroring implemented or not. See the JEDEC DDR4 SPD specification for more details. Table 7: Address Mirroring Edge Connector Pin DRAM Pin, Non-mirrored DRAM Pin, Mirrored A0 A0 A0 A1 A1 A1 A2 A2 A2 A3 A3 A4 A4 A4 A3 A5 A5 A6 A6 A6 A5 A7 A7 A8 A8 A8 A7 A9 A9 A9 A10 A10 A10 A11 A11 A13 A13 A13 A11 A12 A12 A12 A14 A14 A14 A15 A15 A15 A16 A16 A16 A17 A17 A17 BA0 BA0 BA1 BA1 BA1 BA0 BG0 BG0 BG1 BG1 BG1 BG0 Registering Clock Driver Operation Registered DDR4 SDRAM modules use a registering clock driver device consisting of a register and a phase-lock loop (PLL). The device complies with the JEDEC DDR4 RCD01 Specification. PDF: 09005aef8591cad3 asf18c1gx72pdz.pdf - Rev. E 1/16 EN 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 288-Pin DDR4 RDIMM Registering Clock Driver Operation To reduce the electrical load on the host memory controller's command, address, and control bus, Micron's RDIMMs utilize a DDR4 registering clock driver (RCD). The RCD presents a single load to the controller while redriving signals to the DDR4 SDRAM devices, which helps enable higher densities and increase signal integrity. The RCD also provides a low-jitter, low-skew PLL that redistributes a differential clock pair to multiple differential pairs of clock outputs. Control Words The RCD device(s) used on DDR4 RDIMMs and LRDIMMs contain configuration registers known as control words, which the host uses to configure the RCD based on criteria determined by the module design. Control words can be set by the host controller through either the DRAM address and control bus or the I2C bus interface. The RCD I 2C bus interface resides on the same I2C bus interface as the module temperature sensor and EEPROM. Parity Operations The RCD includes a parity-checking function that can be enabled or disabled in control word RC0E. The RCD receives a parity bit at the DPAR input from the memory controller and compares it with the data received on the qualified command and address inputs; it indicates on its open-drain ALERT_n pin whether a parity error has occurred. If parity checking is enabled, the RCD forwards commands to the SDRAM when no parity error has occurred. If the parity error function is disabled, the RCD forwards sampled commands to the SDRAM regardless of whether a parity error has occurred. Parity is also checked during control word WRITE operations unless parity checking is disabled. Rank Addressing The chip select pins (CS_n) on Micron's modules are used to select a specific rank of DRAM. The RDIMM is capable of selecting ranks in one of three different operating modes, dependant on setting DA[1:0] bits in the DIMM configuration control word located within the RCD. Direct DualCS mode is utilized for single- or dual-rank modules. For quad-rank modules, either direct or encoded QuadCS mode is used. PDF: 09005aef8591cad3 asf18c1gx72pdz.pdf - Rev. E 1/16 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 288-Pin DDR4 RDIMM Temperature Sensor With SPD EEPROM Operation Temperature Sensor With SPD EEPROM Operation Thermal Sensor Operations The integrated thermal sensor continuously monitors the temperature of the module PCB directly below the device and updates the temperature data register. Temperature data may be read from the bus host at any time, which provides the host real-time feedback of the module's temperature. Multiple programmable and read-only temperature registers can be used to create a custom temperature-sensing solution based on system requirements and JEDEC JC-42.2. EVENT_n Pin The temperature sensor also adds the EVENT_n pin (open-drain), which requires a pullup to V DDSPD. EVENT_n is a temperature sensor output used to flag critical events that can be set up in the sensor’s configuration registers. EVENT_n is not used by the serial presence-detect (SPD) EEPROM. EVENT_n has three defined modes of operation: interrupt, comparator, and TCRIT. In interrupt mode, the EVENT_n pin remains asserted until it is released by writing a 1 to the clear event bit in the status register. In comparator mode, the EVENT_n pin clears itself when the error condition is removed. Comparator mode is always used when the temperature is compared against the TCRIT limit. In TCRIT only mode, the EVENT_n pin is only asserted if the measured temperature exceeds the TCRIT limit; it then remains asserted until the temperature drops below the TCRIT limit minus the TCRIT hysteresis. SPD EEPROM Operation DDR4 SDRAM modules incorporate SPD. The SPD data is stored in a 512-byte, JEDEC JC-42.4-compliant EEPROM that is segregated into four 128-byte, write-protectable blocks. The SPD content is aligned with these blocks as shown in the table below. Block Range Description 0 0–127 1 128–255 080h–0FFh Module parameters 2 256–319 100h–13Fh Reserved (all bytes coded as 00h) 320–383 140h–17Fh Manufacturing information 384–511 180h–1FFh End-user programmable 3 000h–07Fh Configuration and DRAM parameters The first 384 bytes are programmed by Micron to comply with JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR4 SDRAM Modules." The remaining 128 bytes of storage are available for use by the customer. The EEPROM resides on a two-wire I2C serial interface and is not integrated with the memory bus in any manner. It operates as a slave device in the I2C bus protocol, with all operations synchronized by the serial clock. Transfer rates of up to 1 MHz are achievable at 2.5V (NOM). Micron implements reversible software write protection on DDR4 SDRAM-based modules. This prevents the lower 384 bytes (bytes 0 to 383) from being inadvertently programmed or corrupted. The upper 128 bytes remain available for customer use and are unprotected. PDF: 09005aef8591cad3 asf18c1gx72pdz.pdf - Rev. E 1/16 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 288-Pin DDR4 RDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 8: Absolute Maximum Ratings Symbol Parameter Min Max Units Notes VDD VDD supply voltage relative to VSS –0.4 1.5 V 1 VDDQ VDDQ supply voltage relative to VSS –0.4 1.5 V 1 Voltage on VPP pin relative to VSS –0.4 3.0 V 2 VIN, VOUT Voltage on any pin relative to VSS –0.4 1.5 V VPP Table 9: Operating Conditions Symbol Parameter Min Nom Max Units Notes VDD VDD supply voltage 1.14 1.20 1.26 V 1 VPP DRAM activating power supply 2.375 2.5 2.75 V 2 0.49 × VDD 0.5 × VDD 0.51 × VDD V 3 –750 – 750 mA 0.49 × VDD 20mV 0.5 × VDD 0.51 × VDD + 20mV V 4 – µA 5 VREFCA(DC) Input reference voltage – command/address bus IVTT Termination reference current from VTT VTT Termination reference voltage (DC) – command/address bus II Input leakage current; any input excluding ZQ; 0V < VIN < 1.1V – – II Input leakage current; ZQ –3 – 3 µA 6, 7 DQ leakage; 0V < VIN < VDD –4 – 4 µA 7 IOZpd Output leakage current; VOUT = VDD; DQ is disabled – – 5 µA IOZpu Output leakage current; VOUT = VSS; DQ and ODT are disabled; ODT is disabled with ODT input HIGH – – 50 µA VREFCA leakage; VREFCA = VDD/2 (after DRAM is initialized) –2 – 2 µA II/O IVREFCA Notes: PDF: 09005aef8591cad3 asf18c1gx72pdz.pdf - Rev. E 1/16 EN 7 1. VDDQ balls on DRAM are tied to VDD. 2. VPP must be greater than or equal to VDD at all times. 3. VREFCA must not be greater than 0.6 × VDD. When VDD is less than 500mV, VREF may be less than or equal to 300mV. 4. VTT termination voltages in excess of specification limit adversely affect command and address signals' voltage margins and reduce timing margins. 5. Command and address inputs are terminated to VDD/2 in the registering clock driver. Input current is dependent on termination resistance set in the registering clock driver. 6. Tied to ground. Not connected to edge connector. 7. Multiply by number of DRAM die on module. 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 288-Pin DDR4 RDIMM Electrical Specifications Table 10: Thermal Characteristics Symbol Parameter/Condition Value Units Notes TC Commercial operating case temperature 0 to 85 °C 1, 2, 3 >85 to 95 °C 1, 2, 3, 4 0 to 85 °C 5, 7 TC TOPER Normal operating temperature range TOPER Extended temperature operating range (optional) >85 to 95 °C 5, 7 TSTG Non-operating storage temperature –55 to 100 °C 6 RHSTG Non-operating Storage Relative Humidity (non-condensing) 5 to 95 % NA Change Rate of Storage Temperature 20 °C/hour Notes: PDF: 09005aef8591cad3 asf18c1gx72pdz.pdf - Rev. E 1/16 EN 1. Maximum operating case temperature; TC is measured in the center of the package. 2. A thermal solution must be designed to ensure the DRAM device does not exceed the maximum TC during operation. 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation. 4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2X refresh, which is a 3.9µs interval refresh rate. 5. The refresh rate must double when 85°C < TOPER ≤ 95°C. 6. Storage temperature is defined as the temperature of the top/center of the DRAM and does not reflect the storage temperatures of shipping trays. 7. For additional information, refer to technical note TN-00-08: "Thermal Applications" available at micron.com. 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 288-Pin DDR4 RDIMM DRAM Operating Conditions DRAM Operating Conditions Recommended AC operating conditions are given in the DDR4 component data sheets. Component specifications are available at micron.com. Module speed grades correlate with component speed grades, as shown below. Table 11: Module and Component Speed Grades DDR4 components may exceed the listed module speed grades; module may not be available in all listed speed grades Module Speed Grade Component Speed Grade -2G6 -075 -2G4 -083E -2G3 -083 -2G1 -093E -1G9 -107E Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the edge connector of the module, not at the DRAM. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. PDF: 09005aef8591cad3 asf18c1gx72pdz.pdf - Rev. E 1/16 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 288-Pin DDR4 RDIMM IDD Specifications IDD Specifications Table 12: DDR4 IDD Specifications and Conditions – 8GB (Die Revision A) Values are for the MT40A512M8 DDR4 SDRAM only and are computed from values specified in the 4Gb (512 Meg x 8) component data sheet Parameter Symbol 2400 2133 Units IDD01 One bank ACTIVATE-PRECHARGE current One bank ACTIVATE-PRECHARGE, wordline boost, IPP current One bank ACTIVATE-READ-PRECHARGE current 864 810 mA 1 63 63 mA 1 IPP0 IDD1 900 855 mA Precharge standby current IDD2N 2 900 828 mA Precharge standby ODT current IDD2NT1 810 756 mA Precharge power-down current IDD2P 2 576 540 mA Precharge quite standby current IDD2Q2 738 702 mA 1206 1134 mA 54 54 mA 2 792 792 mA 1 1728 1620 mA 2 Active standby current IDD3N Active standby IPP current IPP3N2 Active power-down current IDD3P Burst read current IDD4R 1 Burst read IDDQ current IDDQ4R 648 594 mA Burst write current IDD4W1 1908 1710 mA 1 2016 1980 mA 1 225 225 mA Self refresh current: Normal temperature range (0°C to 85°C) IDD6N 2 360 360 mA Self refresh current: Extended temperature range (0°C to 95°C) IDD6E2 486 486 mA 2 180 180 mA 2 162 162 mA Auto self refresh current (45°C) IDD6A 2 180 180 mA Auto self refresh current (75°C) IDD6A2 288 288 mA 1 2178 1935 mA 1 153 135 mA 2 324 324 mA Burst refresh current (1x REF) IDD5B Burst refresh IPP current (1x REF) IPP5B Self refresh current: Reduced temperature range (0°C to 45°C) Auto self refresh current (25°C) IDD6A Bank interleave read current IDD7 Bank interleave read IPP current IPP7 Maximum power-down current Notes: PDF: 09005aef8591cad3 asf18c1gx72pdz.pdf - Rev. E 1/16 EN IDD6R IDD8 1. One module rank in the active IDD/PP, the other rank in IDD2P/PP3N. 2. All ranks in this IDD/PP condition. 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 288-Pin DDR4 RDIMM IDD Specifications Table 13: DDR4 IDD Specifications and Conditions – 8GB (Die Revision B) Values are for the MT40A512M8 DDR4 SDRAM only and are computed from values specified in the 4Gb (512 Meg x 8) component data sheet Parameter Symbol 2400 2133 Units IDD01 One bank ACTIVATE-PRECHARGE current One bank ACTIVATE-PRECHARGE, wordline boost, IPP current One bank ACTIVATE-READ-PRECHARGE current 801 738 mA 1 54 54 mA 1 IPP0 IDD1 846 783 mA Precharge standby current IDD2N 2 810 756 mA Precharge standby ODT current IDD2NT1 711 693 mA Precharge power-down current IDD2P 2 522 486 mA Precharge quite standby current IDD2Q2 666 630 mA 1080 990 mA 54 54 mA 2 720 720 mA 1 1566 1458 mA Burst write current IDD4W 1 1836 1638 mA Burst refresh current (1x REF) IDD5B1 1836 1773 mA 1 225 225 mA 2 324 324 mA Self refresh current: Extended temperature range (0°C to 95°C) IDD6E 2 432 432 mA Self refresh current: Reduced temperature range (0°C to 45°C) IDD6R2 216 216 mA 2 162 162 mA 2 216 216 mA 2 Active standby current IDD3N Active standby IPP current IPP3N2 Active power-down current IDD3P Burst read current IDD4R Burst refresh IPP current (1x REF) IPP5B Self refresh current: Normal temperature range (0°C to 85°C) Auto self refresh current (25°C) IDD6N IDD6A Auto self refresh current (45°C) IDD6A 2 Auto self refresh current (75°C) IDD6A Bank interleave read current IDD71 Bank interleave read IPP current IPP7 Maximum power-down current Notes: PDF: 09005aef8591cad3 asf18c1gx72pdz.pdf - Rev. E 1/16 EN 324 324 mA 1971 1728 mA 1 153 135 mA 2 288 288 mA IDD8 1. One module rank in the active IDD/PP, the other rank in IDD2P/PP3N. 2. All ranks in this IDD/PP condition. 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 288-Pin DDR4 RDIMM Registering Clock Driver Specifications Registering Clock Driver Specifications Table 14: Registering Clock Driver Electrical Characteristics DDR4 RCD01 devices or equivalent Parameter Symbol Pins Min Nom Max Units DC supply voltage VDD – 1.14 1.2 1.26 V DC reference voltage VREF VREFCA 0.49 × VDD 0.5 × VDD 0.51 × VDD V DC termination voltage VTT – VREF - 40mV VREF VREF + 40mV V High-level input voltage VIH. CMOS DRST_n 0.65 × VDD – VDD V Low-level input voltage VIL. CMOS 0 – 0.35 × VDD V DRST_n pulse width tINIT_Power_stable – 1.0 – – µs AC high-level output voltage VOH(AC) All outputs except ALERT_n VTT + (0.15 × VDD) – – V AC low-level output voltage VOL(AC) – – VTT + (0.15 x VDD) V AC differential output high measurement level (for output slew rate) VOHdiff(AC) – 0.3 × VDD – mV AC differential output low measurement level (for output slew rate) VOLdiff(AC) – –0.3 × VDD – mV Note: PDF: 09005aef8591cad3 asf18c1gx72pdz.pdf - Rev. E 1/16 EN Yn_t - Yn_c, BCK_t BCK_c 1. Timing and switching specifications for the register listed are critical for proper operation of DDR4 SDRAM RDIMMs. These are meant to be a subset of the parameters for the specific device used on the module. See the JEDEC RCD01 specification for complete operating electrical characteristics. Registering clock driver parametric values are specified for device default control word settings, unless otherwise stated. The RC0A control word setting does not affect parametric values. 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 288-Pin DDR4 RDIMM Temperature Sensor With SPD EEPROM Temperature Sensor With SPD EEPROM The temperature sensor continuously monitors the module's temperature and can be read back at any time over the I2C bus shared with the serial presence-detect (SPD) EEPROM. Refer to JEDEC JC-42.4 EE1004 and TSE2004 device specifications for complete details. SPD Data For the latest SPD data, refer to Micron's SPD page: micron.com/SPD. Table 15: Temperature Sensor With SPD EEPROM Operating Conditions Parameter/Condition Symbol Min Nom Max Units VDDSPD – 2.5 – V Input low voltage: logic 0; all inputs VIL –0.5 – VDDSPD × 0.3 V Input high voltage: logic 1; all inputs VIH VDDSPD × 0.7 – VDDSPD + 0.5 V Output low voltage: 3mA sink current VDDSPD > 2V Supply voltage VOL – – 0.4 V Input leakage current: (SCL, SDA) VIN = VDDSPD or VSSSPD ILI – – ±5 µA Output leakage current: VOUT = VDDSPD or VSSSPD, SDA in High-Z ILO – – ±5 µA Table 16: Temperature Sensor and EEPROM Serial Interface Timing Parameter/Condition Min Max Units fSCL 10 1000 kHz Clock pulse width HIGH time tHIGH 260 – ns Clock pulse width LOW time tLOW 500 – ns tTIMEOUT Clock frequency Detect clock LOW timeout Symbol 25 35 ms SDA rise time tR – 120 ns SDA fall time tF – 120 ns Data-in setup time tSU:DAT 50 – ns Data-in hold time tHD:DI ns 0 – Data out hold time tHD:DAT 0 350 ns Start condition setup time tSU:STA 260 – ns Start condition hold time tHD:STA 260 – ns Stop condition setup time tSU:STO 260 – ns tBUF 500 – ns Time the bus must be free before a new transition can start Write time Warm power cycle time off Time from power-on to first command PDF: 09005aef8591cad3 asf18c1gx72pdz.pdf - Rev. E 1/16 EN tW – 5 ms tPOFF 1 – ms tINIT 10 – ms 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 288-Pin DDR4 RDIMM Module Dimensions Module Dimensions Figure 4: 288-Pin DDR4 RDIMM (R/C-E) Front view 3.9 (0.153) MAX 133.48 (5.255) 133.22 (5.244) U1 U2 0.75 (0.03) R (8X) U3 U4 U5 U6 U7 U8 U9 U10 U11 2.50 (0.098) D (2X) 31.40 (1.236) 31.10 (1.224) 16.1 (0.63) 9.5 (0.374) TYP TYP 4.8 (0.189) TYP 1.5 (0.059) 1.3 (0.051) 0.75 (0.030) R Pin 1 2.20 (0.087) TYP 0.85 (0.033) TYP 3.35 (0.132) TYP (2X) 0.60 (0.0236) TYP Pin 144 72.25 (2.84) TYP 126.65 (4.99) TYP Back view U12 U13 U14 U15 U16 1.25 (0.049) x 45° (2X) U17 U18 U19 U20 3.0 (0.118) (4X) TYP 14.6 (0.57) TYP 8.0 (0.315) TYP 0.5 (0.0197) TYP 3.15 (0.124) TYP Pin 288 22.95 (0.90) TYP 10.2 (0.4) TYP 5.95 (0.234) TYP 22.95 (0.9) TYP 25.5 (1.0) TYP PDF: 09005aef8591cad3 asf18c1gx72pdz.pdf - Rev. E 1/16 EN 28.9 (1.14) TYP 64.6 (2.54) TYP 56.10 (2.21) TYP Notes: 10.2 (0.4) TYP Pin 145 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 288-Pin DDR4 RDIMM Module Dimensions Figure 5: 288-Pin DDR4 RDIMM (R/C-E1) FRONT VIEW 3.9 (0.153) MAX 133.48 (5.255) 133.22 (5.244) U1 U7 0.75 (0.03) R (8X) U2 U3 U4 U5 U8 U6 U9 U10 31.40 (1.236) 31.10 (1.224) U11 2.50 (0.098) D (2X) 16.1 (0.63) 9.5 (0.374) TYP TYP 4.8 (0.189) TYP 1.5 (0.059) 1.3 (0.051) 0.75 (0.030) R PIN 1 2.20 (0.087) TYP 0.85 (0.033) TYP 3.35 (0.132) TYP (2X) 0.60 (0.0236) TYP PIN 144 72.25 (2.84) TYP 126.65 (4.99) TYP BACK VIEW U12 U13 U14 1.25 (0.049) x 45° (2X) U16 U15 U17 U18 U19 U20 3.0 (0.118) (4X) TYP 14.6 (0.57) TYP 8.0 (0.315) TYP 0.5 (0.0197) TYP 3.15 (0.124) TYP PIN 288 22.95 (0.90) TYP 10.2 (0.4) TYP 5.95 (0.234) TYP 22.95 (0.9) TYP 25.5 (1.0) TYP 28.9 (1.14) TYP 64.6 (2.54) TYP 56.10 (2.21) TYP Notes: 10.2 (0.4) TYP PIN 145 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000 www.micron.com/products/support Sales inquiries: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef8591cad3 asf18c1gx72pdz.pdf - Rev. E 1/16 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.