MT9094APR1

ISO2-CMOS ST-BUSTM FAMILY MT9094 Digital Telephone (DPhone-II) Data Sheet Features February 2005 • Programmable µ-Law/A-Law codec and filters • Programmable CCITT (G.711)/sign-magnitude coding • Programmable transmit, receive and side-tone gains • DSP-based: Ordering Information MT9094AP MT9094APR MT9094AP1 MT9094APR1 Speakerphone switching algorithm • DTMF and single tone generator • Tone Ringer Description • Differential interface to telephony transducers • Differential audio paths • Single 5 volt power supply The MT9094 DPhone-II is a fully featured integrated digital telephone circuit. Voice band signals are converted to digital PCM and vice versa by a switched capacitor Filter/Codec. The Filter/Codec uses an ingenious differential architecture to achieve low noise operation over a wide dynamic range with a single 5 V supply. A Digital Signal Processor provides handsfree speaker-phone operation. The DSP is also used to generate tones (DTMF, Ringer and Call Progress) and control audio gains. Internal registers are accessed through a serial microport conforming to INTEL MCS51™ specifications. The device is fabricated in Zarlink's low power ISO2-CMOS technology. Applications • Fully featured digital telephone sets • Cellular phone sets • Local area communications stations Digital Signal Processor DSTi Filter/Codec Gain ENCODER 22.5/-72dB ∆1.5dB Tx & Rx DECODER MIC- 7dB MIC+ Transducer Interface -7dB M- F0i M+ C4i VSSD Tubes Tape & Reel Tubes Tape & Reel -40°C to +85°C • DSTo 44 Pin PLCC 44 Pin PLCC 44 Pin PLCC* 44 Pin PLCC* *Pb Free Matte HSPKR+ STATUS Control Registers C-Channel Registers HSPKRSPKR+ VDD SPKR- VSSA VSS SPKR New Call Tone Generator Timing Circuits VBias VRef S/P & P/S Converter LCD Driver S1 S12 BP WD PWRST Serial Port (MCS-51 Compatible) IC Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1995-2005, Zarlink Semiconductor Inc. All Rights Reserved. DATA 2 DATA 1 SCLK CS MT9094 6 5 4 3 2 1 44 43 42 41 40 PWRST IC VRef VBias NC M+ MVSSA MIC+ MICVSS SPKR Data Sheet 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 SPKR+ SPKRHSPKR+ HSPKRVDD BP S12 S11 S10 S9 S8 IC NC NC VSSD S1 S2 S3 S4 S5 S6 S7 18 19 20 21 22 23 24 25 26 27 28 DSTi DSTo C4i F0i VSSD NC SCLK DATA 2 DATA 1 CS WD 44 PIN PLCC Figure 2 - Pin Connections Pin Description Pin # Name 1 M+ Non-Inverting Microphone (Input). Non-inverting input to microphone amplifier from the handset microphone. 2 NC No Connect. No internal connection to this pin. 3 VBias Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external amplifiers. Connect 0.1 µF capacitor to VSSA. 4 VRef Reference voltage for codec (Output). Nominally [(VDD/2)-1.5] volts. Used internally. Connect 0.1 µF capacitor to VSSA. 5 IC 6 Description Internal Connection. Tie externally to VSS for normal operation. PWRST Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low). 7 DSTi ST-BUS Serial Stream (Input). 2048 kbit/s input stream composed of 32 eight bit channels; the first four of which are used by the MT9094. Input level is TTL compatible. 8 DSTo ST-BUS Serial Stream (Output). 2048 kbit/s output stream composed of 32 eight bit channels. The MT9094 sources digital signals during the appropriate channel, time coincident with the channels used for DSTi. 9 C4i 4096 kHz Clock (Input). CMOS level compatible. 10 F0i Frame Pulse (Input). CMOS level compatible. This input is the frame synchronization pulse for the 2048 kbit/s ST-BUS stream. 11 VSSD 12 NC Digital Ground. Nominally 0 volts. No Connect. No internal connection to this pin. 2 Zarlink Semiconductor Inc. MT9094 Data Sheet Pin Description (continued) Pin # Name 13 SCLK Description Serial Port Synchronous Clock (Input). Data clock for MCS-51 compatible microport. TTL level compatible. 14 DATA 2 Serial Data Transmit. In an alternate mode of operation, this pin is used for data transmit from MT9094. In the default mode, serial data transmit and receive are performed on the DATA 1 pin and DATA 2 is tristated. 15 DATA 1 Bidirectional Serial Data. Port for microprocessor serial data transfer compatible with MCS-51 standard (default mode). In an alternate mode of operation, this pin becomes the data receive pin only and data transmit is performed on the DATA 2 pin. Input level TTL compatible. 16 CS Chip Select (Input). This input signal is used to select the device for microport data transfers. Active low. (TTL level compatible.) 17 WD Watchdog (Output). Watchdog timer output. Active high. 18 IC Internal Connection. Tie externally to VSS for normal operation. 19, 20 NC No Connection. No internal connection to these pins. 21 VSSD 22-33 S1-S12 34 BP Backplane Drive (Output). A two-level output voltage for biasing an LCD backplane. 35 VDD Positive Power Supply (Input). Nominally 5 volts. Digital Ground. Nominally 0 volts. Segment Drivers (Output). 12 independently controlled, two level, LCD segment drivers. An in-phase signal, with respect to the BP pin, produces a non-energized LCD segment. An out-of-phase signal, with respect to the BP pin, energizes its respective LCD segment. 36 HSPKR- Inverting Handset Speaker (Output). Output to the handset speaker (balanced). 37 HSPKR+ Non-Inverting Handset Speaker (Output). Output to the handset speaker (balanced). 38 SPKR- Inverting Speaker (Output). Output to the speakerphone speaker (balanced). 39 SPKR+ Non-Inverting Speaker (Output). Output to the speakerphone speaker (balanced). 40 VSS SPKR Power Supply Rail for Analog Output Drivers. Nominally 0 Volts. 41 MIC- Inverting Handsfree Microphone (Input). Handsfree microphone amplifier inverting input pin. 42 MIC+ Non-inverting Handsfree Microphone (Input). Handsfree microphone amplifier non-inverting input pin. 43 VSSA Analog Ground. Nominally 0 V. 44 M- Inverting Microphone (Input). Inverting input to microphone amplifier from the handset microphone. NOTES: Intel and MCS-51 are registered trademarks of Intel Corporation, Santa Clara, CA, USA. Overview The Functional Block Diagram of Figure 1 depicts the main operations performed within the DPhone-II. Each of these functional blocks will be described in the sections to follow. This overview will describe some of the end-user features which may be implemented as a direct result of the level of integration found within the DPhone-II. 3 Zarlink Semiconductor Inc. MT9094 Data Sheet The main feature required of a digital telephone is to convert the digital Pulse Code Modulated (PCM) information, being received by the telephone set, into an analog electrical signal. This signal is then applied to an appropriate audio transducer such that the information is finally converted into intelligible acoustic energy. The same is true of the reverse direction where acoustic energy is converted first into an electrical analog and then digitized (into PCM) before being transmitted from the set. Along the way if the signals can be manipulated, either in the analog or the digital domains, other features such as gain control, signal generation and filtering may be added. More complex processing of the digital signal is also possible and is limited only be the processing power available. One example of this processing power may be the inclusion of a complex handsfree switching algorithm. Finally, most electroacoustic transducers (loudspeakers) require a large amount of power to develop an effective acoustic signal. The inclusion of audio amplifiers to provide this power is required. The DPhone-II features Digital Signal Processing (DSP) of the voice encoded PCM, complete Analog/Digital and Digital/Analog conversion of audio signals (Filter/CODEC) and an analog interface to the external world of electroacoustic devices (Transducer Interface). These three functional blocks combine to provide a standard full-duplex telephone conversation utilizing a common handset. Selecting transducers for handsfree operation, as well as allowing the DSP to perform its handsfree switching algorithm, is all that is required to convert the full-duplex handset conversation into a half-duplex speakerphone conversation. In each of these modes, full programmability of the receive path and side-tone gains is available to set comfortable listening levels for the user as well as transmit path gain control for setting nominal transmit levels into the network. The ability to generate tones locally provides the designer with a familiar method of feedback to the telephone user as they proceed to set-up, and ultimately, dismantle a telephone conversation. Also, as the network slowly evolves from the dial pulse/DTMF methods to the D-Channel protocols it is essential that the older methods be available for backward compatibility. As an example; once a call has been established, say from your office to your home, using the D-Channel signalling protocol it may be necessary to use in-band DTMF signalling to manipulate your personal answering machine in order to retrieve messages. Thus the locally generated tones must be of network quality and not just a reasonable facsimile. The DPhone-II DSP can generate the required tone pairs as well as single tones to accommodate any in-band signalling requirement. Each of the programmable parameters within the functional blocks is accessed through a serial microcontroller port compatible with Intel MCS-51 specifications. Functional Description In this section, each functional block within the DPhone-II is described along with all of the associated control/status bits. Each time a control/ status bit(s) is described it is followed by the address register where it will be found. The reader is referred to the section titled ‘Register Summary' for a complete listing of all address map registers, the control/status bits associated with each register and a definition of the function of each control/status bit. The Register Summary is useful for future reference of control/status bits without the need to locate them within the text of the functional descriptions. Filter-CODEC The Filter/CODEC block implements conversion of the analog 3.3kHz speech signals to/from the digital domain compatible with 64 kb/s PCM B-Channels. Selection of companding curves and digital code assignment are register programmable. These are CCITT G.711 A-law or µ-Law, with true-sign/ Alternate Digit Inversion or truesign/Inverted Magnitude coding, respectively. Optionally, sign- magnitude coding may also be selected for proprietary applications. The Filter/CODEC block also implements transmit and receive audio path gains in the analog domain. These gains are in addition to the digital gain pad provided in the DSP section and provide an overall path gain resolution of 0.5 dB. A programmable gain, voice side-tone path is also included to provide proportional transmit speech feedback to the handset receiver so that a dead sounding handset is not encountered. Figure 3 depicts the nominal half-channel and side-tone gains for the DPhone-II. 4 Zarlink Semiconductor Inc. MT9094 SERIAL PORT DSP GAIN* Data Sheet TRANSDUCER INTERFACE FILTER/CODEC µ-Law –6.3 dB Α-Law –3.7 dB Receiver Driver Receive PCM –72 to +22.5 dB (1.5dB steps) DTMF, Tone Ringer & Handsfree -6 dB Receive Filter Gain 0 to –7 dB (1 dB steps) Handset Receiver (150Ω) -6 dB HSPKR+ 75 HSPKR– 75 Speaker Phone Driver 0.2dB* Side-tone –9.96 to +9.96dB (3.32 dB steps) Speaker Gain 0 to –24 dB (8 dB steps) SPKR+ SPKR– Speakerphone Speaker (40Ω nominal) (32Ω min) Tone Ringer (input from DSP) Side-tone Nominal Gain µ-Law –11 dB Α-Law –18.8 dB PCM –72 to +22.5 dB (1.5dB steps) Transmit Filter Gain 0 to +7dB (1 dB steps) µ-Law 6.1dB Α-Law 15.4dB Transmit DIGITAL DOMAIN Transmit Gain M U X MIC+ Handsfree MIC– mic M+ M– Transmitter microphone ANALOG DOMAIN Internal to Device External to Device Note: *gain the same for A-Law and m−Law Figure 3 - Audio Gain Partitioning On PWRST (pin 6) the Filter/CODEC defaults such that the side-tone path, dial tone filter and 400 Hz transmit filter are off, all programmable gains are set to 0 dB and µ-Law companding is selected. Further, the Filter/CODEC is powered down due to the PuFC bit (Transducer Control Register, address 0Eh) being reset. This bit must be set high to enable the Filter/CODEC. The internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide dynamic range from a single 5 volt supply design. This fully differential architecture is continued into the Transducer Interface section to provide full chip realization of these capabilities. A reference voltage (VRef), for the conversion requirements of the CODER section, and a bias voltage (VBias), for biasing the internal analog sections, are both generated on-chip. VBias is also brought to an external pin so that it may be used for biasing any external gain plan setting amplifiers. A 0.1 µF capacitor must be connected from VBias to analog ground at all times. Likewise, although VRef may only be used internally, a 0.1 µF capacitor from the VRef 5 Zarlink Semiconductor Inc. MT9094 Data Sheet pin to ground is required at all times. It is suggested that the analog ground reference point for these two capacitors be physically the same point. To facilitate this the VRef and VBias pins are situated on adjacent pins. The transmit filter is designed to meet CCITT G.714 specifications. The nominal gain for this filter path is 0 dB (gain control = 0 dB). An anti-aliasing filter is included. This is a second order lowpass implementation with a corner frequency at 25 kHz. Attenuation is better than 32 dB at 256 kHz and less than 0.01 dB within the passband. An optional 400 Hz high-pass function may be included into the transmit path by enabling the Tfhp bit in the Transducer Control Register (address 0Eh). This option allows the reduction of transmitted background noise such as motor and fan noise. The receive filter is designed to meet CCITT G.714 specifications. The nominal gain for this filter path is 0 dB (gain control = 0 dB). Filter response is peaked to compensate for the sinx/x attenuation caused by the 8 kHz sampling rate. The Rx filter function can be altered by enabling the DIAL EN control bit in the Transducer Control Register (address 0Eh). This causes another lowpass function to be added, with a 3 dB point at 1000 Hz. This function is intended to improve the sound quality of digitally generated dial tone received as PCM. Transmit sidetone is derived from the Tx filter and is subject to the gain control of the Tx filter section. Sidetone is summed into the receive path after the Rx filter gain control section so that Rx gain adjustment will not affect sidetone levels. The side-tone path may be enabled/disabled with the SIDE EN bit located in the Transducer Control Register (address 0Eh). See also STG0-STG2 (address 0Bh). Transmit and receive filter gains are controlled by the TxFG0-TxFG2 and RxFG0-RxFG2 control bits respectively. These are located in the FCODEC Gain Control Register 1 (address 0Ah). Transmit filter gain is adjustable from 0 dB to +7 dB and receive filter gain from 0 dB to -7 dB, both in 1 dB increments. Side-tone filter gain is controlled by the STG0-STG2 control bits located in the FCODEC Gain Control Register 2 (address 0Bh). Side-tone gain is adjustable from -9.96 dB to +9.96 dB in 3.32 dB increments. Law selection for the Filter/CODEC is provided by the A/µ companding control bit while the coding scheme is controlled by the sign-mag/CCITT bit. Both of these reside in the General Control Register (address 0Fh). Digital Signal Processor The DSP block is located, functionally, between the serial ST-BUS port and the Filter/CODEC block. Its main purpose is to provide both a digital gain control and a half-duplex handsfree switching function. The DSP will also generate the digital patterns required to produce standard DTMF signalling tones as well as single tones and a tone ringer output. A programmable (ON/OFF) offset null routine may also be performed on the transmit PCM data stream. The DSP can generate a ringer tone to be applied to the speakerphone speaker during normal handset operation so that the existing call is not interrupted. The main functional control of the DSP is through two hardware registers which are accessible at any time via the microport. These are the Receive Gain Control Register at address 1Dh and the DSP Control Register at address 1Eh. In addition, other functional control is accomplished via multiple RAM-based registers which are accessible only while the DSP is held in a reset state. This is accomplished with the DRESET bit of the DSP Control Register. Ram-based registers are used to store transmit gain levels (20h for transmit PCM and 21h for transmit DTMF levels), the coefficients for tone and ringer generation (addresses 23h and 24h), and tone ringer warble rates (address 26h). All undefined addresses below 20h are reserved for the temporary storage of interim variables calculated during the execution of the DSP algorithms. These undefined addresses should not be written to via the microprocessor port. The DSP can be programmed to execute the following micro-programs which are stored in instruction ROM, (see PS0 to PS2, DSP Control Register, address 1Eh). All program execution begins at the frame pulse boundary. PS2 0 PS1 0 PS0 0 Micro-program Power up reset program 6 Zarlink Semiconductor Inc. MT9094 Data Sheet 0 0 1 Transmit and receive gain control program; with autonulling of the transmit PCM, if the AUTO bit is set (see address 1Dh) 0 1 0 DTMF generation plus transmit and receive gain control program (autonull available via the AUTO control bit) 0 1 1 Tone ringer plus transmit and receive gain control program (autonull available via the AUTO control bit) 1 0 0 handsfree switching program 1 1 1 0 1 1 1 0 1 Last three selections reserved Note: For the DSP to function it must be selected to operate, in conjunction with the Filter/Codec, in one of the B-Channels. Therefore, one of the B-Channel enable bits must be set (see Timing Control, address 15h: bits CH2EN and CH3EN). Power Up Reset Program A hardware power-up reset (pin 6, PWRST) will initialize the DSP hardware registers to the default values (all zeros) and will reset the DSP program counter. The DSP will then be disabled and the PCM streams will pass transparently through the DSP. The RAM-based registers are not reset by the PWRST pin but may be initialized to their default settings by programming the DSP to execute the power up reset program. None of the micro-programs actually require the execution of the power up reset program but it is useful for pre-setting the variables to a known condition. Note that the reset program requires one full frame (125µSec) for execution. Gain Control Program Gain control is performed on converted linear code for both the receive and the transmit PCM. Receive gain control is set via the hardware register at address 1Dh (see bits B0 - B5) and may be changed at any time. Gain in 1.5 dB increments is available within a range of +22.5 dB to -72 dB. Normal operation usually requires no more than a +20 to -20 dB range of control. However, the handsfree switching algorithm requires a large attenuation depth to maintain stability in worst case environments, hence the large (-72 dB) negative limit. Transmit gain control is divided into two RAM registers, one for setting the network level of transmit speech (address 20h) and the other for setting the transmit level of DTMF tones into the network (address 21h). Both registers provide gain control in 1.5 dB increments and are encoded in the same manner as the receive gain control register (see address 1Dh, bits B0 - B5). The power up reset program sets the default values such that the receive gain is set to -72.0 dB, the transmit audio gain is set to 0.0dB and the transmit DTMF gain is set to -3.0 dB (equivalent to a DTMF output level of -4 dBm0 into the network). Optional Offset Nulling Transmit PCM may contain residual offset in the form of a DC component. An offset of up to ±fifteen linear bits is acceptable with no degradation of the parameters defined in CCITT G.714. The DPhone-II filter/CODEC guarantees no more than ±ten linear bits of offset in the transmit PCM when the autonull routine is not enabled. By enabling autonulling (see AUTO in the Receive Gain Control Register, address 1Dh) offsets are reduced to within ±one bit of zero. Autonulling circuitry was essential in the first generations of Filter/Codecs to remove the large DC offsets found in the linear technology. Newer technology has made nulling circuitry optional as offered in the DPhone-II. 7 Zarlink Semiconductor Inc. MT9094 Data Sheet DTMF and Gain Control Program The DTMF program generates a dual cosine wave pattern which may be routed into the receive path as comfort tones or into the transmit path as network signalling. In both cases, the digitally generated signal will undergo gain adjustment as programmed into the Receive Gain Control and the Transmit DTMF Gain Control registers. The composite signal output level in both directions is -4 dBm0 when the gain controls are set to 2Eh (-3.0 dB). Adjustments to these levels may be made by altering the settings of the gain control registers. Pre-twist of 2.0 dB is incorporated into the composite signal. The frequency of the low group tone is programmed by writing an 8-bit coefficient into Tone Coefficient Register 1 (address 23h), while the high group tone frequency uses the 8-bit coefficient programmed into Tone Coefficient Register 2 (address 24h). Both coefficients are determined by the following equation: COEFF = 0.128 x Frequency (in Hz) where COEFF is a rounded off 8 bit binary integer A single frequency tone may be generated instead of a dual tone by programming the coefficient at address 23h to a value of zero. In this case the frequency of the single output tone is governed by the coefficient stored at address 24h. Frequency (Hz) COEF Actual Frequency % Deviation 697 59h 695.3 -.20% 770 63h 773.4 +.40% 852 6Dh 851.6 -.05% 941 79h 945.3 +.46% +.20% 1209 9Bh 1210.9 1336 ABh 1335.9 .00% 1477 BDh 1476.6 -.03% 1633 D1h 1632.8 -.01% Table 1 DTMF Signal to distortion: The sum of harmonic and noise power in the frequency band from 50 Hz to 3500 Hz is typically more than 30dB below the power in the tone pair. All individual harmonics are typically more than 40 dB below the level of the low group tone. Table 1 gives the standard DTMF frequencies, the coefficient required to generate the closest frequency, the actual frequency generated and the percent deviation of the generated tone from the nominal. Tone Ringer and Gain Control Program A locally generated alerting (ringing) signal is used to prompt the user when an incoming call must be answered. The DSP uses the values programmed into Tone Coefficient Registers 1 and 2 (addresses 23h and 24h) to generate two different squarewave frequencies in PCM code. The amplitude of the squarewave frequencies is set to a mid level before being sent to the receive gain control block. From there the PCM passes through the decoder and receive filter, replacing the normal receive PCM data, on its way to the loudspeaker driver. Both coefficients are determined by the following equation: COEFF = 8000/Frequency (Hz) where COEFF is a rounded off 8 bit binary integer 8 Zarlink Semiconductor Inc. MT9094 Data Sheet The ringer program switches between these two frequencies at a rate defined by the 8-bit coefficient programmed into the Tone Ringer Warble Rate Register (address 26h). The warble rate is defined by the equation: Tone duration (warble frequency in Hz) = 500/COEFF where 0 < COEFF < 256, a warble rate of 5-20 Hz is suggested. An alternate method of generating ringer tones to the speakerphone speaker is available. With this method the normal receive speech path through the decoder and receive filter is uninterrupted to the handset, allowing an existing conversation to continue. The normal DSP and Filter/CODEC receive gain control is also retained by the speech path. When the OPT bit (DSP Control Register address 1Eh) is set high the DSP will generate the new call tone according to the coefficients programmed into registers 23h, 24h and 26h as before. In this mode the DSP output is no longer a PCM code but a toggling signal which is routed directly through the New Call Tone gain control section to the loudspeaker driver. Refer to the section titled ‘New Call Tone’. Handsfree Program A half-duplex speakerphone program, fully contained on chip, provides high quality gain switching of the transmit and receive speech PCM to maintain loop stability under most network and local acoustic environments. Gain switching is performed in continuous 1.5 dB increments and operates in a complimentary fashion. That is, with the transmit path at maximum gain the receive path is fully attenuated and vice versa. This implies that there is a mid position where both transmit and receive paths are attenuated equally during transition. This is known as the idle state. Of the 64 possible attenuator states, the algorithm may rest in only one of three stable states; full receive, full transmit and idle. The maximum gain values for full transmit and full receive are programmable through the microport at addresses 20h and 1Dh respectively, as is done for normal handset operation. This allows the user to set the maximum volumes to which the algorithm will adhere. The algorithm determines which path should maintain control of the loop based upon the relative levels of the transmit and receive audio signals after the detection and removal of background noise energy. If the algorithm determines that neither the transmit or the receive path has valid speech energy then the idle state will be sought. The present state of the algorithm plus the result of the Tx vs. Rx decision will determine which transition the algorithm will take toward its next stable state. The time durations required to move from one stable state to the next are parameters defined in CCITT Recommendation P.34 and are used by default by this algorithm (i.e., build-up time, hang-over time and switching time). Quiet Code The DSP can be made to send quiet code to the decoder and receive filter path by setting the RxMUTE bit high. Likewise, the DSP will send quiet code in the transmit (DSTo) path when the TxMUTE bit is high. Both of these control bits reside in the DSP Control Register at address 1Eh. When either of these bits are low, their respective paths function normally. Transducer Interfaces Four standard telephony transducer interfaces are provided by the DPhone-II. These are: • The handset microphone inputs (transmitter), pins M+/M- and the speakerphone microphone inputs, pins MIC+/MIC-. The transmit path is muted/not-muted by the MIC EN control bit. Selection of which input pair is to be routed to the transmit filter amplifier is accomplished by the MIC/HNSTMIC control bit. Both of these reside in the Transducer Control Register (address 0Eh). The nominal transmit path gain may be adjusted to either 6.1 dB (suggested for µ-Law) or 15.4 dB (suggested for A-Law). Control of this gain is provided by the MICA/u control bit (General Control Register, address 0Fh). This gain adjustment is in addition to the programmable gain provided by the transmit filter and DSP. 9 Zarlink Semiconductor Inc. MT9094 Data Sheet • The handset speaker outputs (receiver), pins HSPKR+/HSPKR-. This internally compensated, fully differential output driver is capable of driving the load shown in Figure 4. This output is enabled/disabled by the HSSPKR EN bit residing in the Transducer Control Register (address 0Eh). The nominal handset receive path gain may be adjusted to either -12.3 dB (suggested for µ-Law) or - 9.7 dB (suggested for A-Law). Control of this gain is provided by the RxA/u control bit (General Control Register, address 0Fh). This gain adjustment is in addition to the programmable gain provided by the receive filter and DSP. • The loudspeaker outputs, pins SPKR+/SPKR-. This internally compensated, fully differential output driver is capable of directly driving 6.5vpp into a 40 ohm load. This output is enabled/disabled by the SPKR EN bit residing in the Transducer Control Register (address 0Eh). The nominal gain for this amplifier is 0.2 dB. C-Channel Access to the internal control and status registers of Zarlink basic rate, layer 1, transceivers is through the ST-BUS Control Channel (C-Channel), since direct microport access is not usually provided, except in the case of the SNIC (MT8930). The DPhone-II provides asynchronous microport access to the ST-BUS C-Channel information on both DSTo and DSTi via a double-buffered read/write register (address 14h). Data written to this address is transmitted on the C-Channel every frame when enabled by CH1EN (see ST-BUS/Timing Control). HSPKR+ 75 Ω 1000 pF 150 ohm load MT9094 (speaker) 75 Ω 1000 pF HSPKR- ground Figure 4 - Handset Speaker Driver LCD A twelve segment, non-multiplexed, LCD display controller is provided for easy implementation of various set status and call progress indicators. The twelve output pins (Sn) are used in conjunction with 12 segment control bits, located in LCD Segment Enable Registers 1&2 (addresses 12h and 13h), and the BackPlane output pin (BP) to control the on/off state of each segment individually. The BP pin drives a continuous 62.5 Hz, 50% duty cycle squarewave output signal. An individual segment is controlled via the phase relationship of its segment driver output pin with respect to the backplane, or common, driver output. Each of the twelve Segment Enable bits corresponds to a segment output pin. The waveform at each segment pin is in-phase with the BP waveform when its control bit is set to logic zero (segment off) and is out-ofphase with the BP waveform when its control bit is set to a logic high (segment on). Refer to the LCD Driver Characteristics for pin loading information. Microport A serial microport, compatible with Intel MCS-51 (mode 0) specifications, provides access to all DPhone-II internal read and write registers. This microport consists of three pins; a half-duplex transmit/receive data pin (DATA1), a chip select pin (CS) and a synchronous data clock pin (SCLK). 10 Zarlink Semiconductor Inc. MT9094 Data Sheet On power-up reset (PWRST) or with a software reset (RST), the DATA1 pin becomes a bidirectional (transmit/receive) serial port while the DATA2 pin is internally disconnected and tri-stated. All data transfers through the microport are two-byte transfers requiring the transmission of a Command/Address byte followed by the data byte written or read from the addressed register. CS must remain asserted for the duration of this two-byte transfer. As shown in Figure 5, the falling edge of CS indicates to the DPhone-II that a microport transfer is about to begin. The first 8 clock cycles of SCLK after the falling edge of CS are always used to receive the Command/Address byte from the microcontroller. The Command/Address byte contains information detailing whether the second byte transfer will be a read or a write operation and of what address. The next 8 clock cycles are used to transfer the data byte between the DPhone-II and the microcontroller. At the end of the two-byte transfer CS is brought high again to terminate the session. The rising edge of CS will tri-state the output driver of DATA1 which will remain tri-stated as long as CS is high. Receive data is sampled and transmit data is made available on DATA1 concurrent with the falling edge of SCLK. Lastly, provision is made to separate the transmit and receive data streams onto two individual pins. This control is given by the DATASEL pin in the General Control Register (address 0Fh). Setting DATASEL logic high will cause DATA1 to become the data receive pin and DATA2 to become the data transmit pin. Only the signal paths are altered by DATASEL; internal timing remains the same in both cases. Tri-stating on DATA2 follows CS as it does on DATA1 when DATASEL is logic low. Use of the DATASEL bit is intended to help in adapting Motorola (SPI) and National Semiconductor (Micro-wire) microcontrollers to the DPhone-II. Note that whereas Intel processor serial ports transmit data LSB first other processor serial ports, including Motorola, transmit data MSB first. It is the responsibility of the microcontroller to provide LSB first data to the DPhone-II. COMMAND/ADDRESS (5) DATA 1 Receive D0 D1 D2 D3 D4 D5 D6 D7 DATA 1 or DATA 2 Transmit ✈✑✉ DATA INPUT/OUTPUT ✈✑✉ ✈✔✉ COMMAND/ADDRESS D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 SCLK (2) CS ✈✔✉ ✈✓✉ ✈✓✉ ✈✑✉Delays due to MCS-51 internal timing which are transparent. ✈✒✉The DPhone-II: -latches received data on the falling edge of SCLK -outputs transmit data on the falling edge of SCLK ✈✓✉The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data followed by CS returning high. ✈✔✉A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again. D7 ✈✕✉The COMMAND/ADDRESS byte contains: 1 bit - Read/Write 0 A5 6 bits - Addressing Data 1 bit - Not used, write logic "0" D0 A4 A3 A2 A1 A0 R/W Figure 5 - Serial Port Relative Timing ST-BUS/Timing Control A serial link is required for the transport of data between the DPhone-II and the external digital transmission device. The DPhone-II utilizes the ST-BUS architecture defined by Zarlink Semiconductor. Refer to Zarlink Application Note 11 Zarlink Semiconductor Inc. MT9094 Data Sheet MSAN-126. The DPhone-II ST-BUS consists of output and input serial data streams, DSTo and DSTi respectively, a synchronous clock signal C4i, and a framing pulse F0i. The data streams operate at 2048 kb/s and are Time Division Multiplexed into 32 identical channels of 64 kb/s bandwidth. Frame Pulse (a 244 nSec low going pulse) is used to parse the continuous serial data streams into the 32 channel TDM frames. Each frame has a 125 µSecond period translating into an 8 kHz frame rate. Valid frame pulse occurs when F0i is logic low coincident with a falling edge of C4i. C4i has a frequency (4096 MHz) which is twice the data rate. This clock is used to sample the data at the _ bit-cell position on DSTi and to make data available on DSTo at the start of the bit-cell. C4i is also used to clock the DPhone-II internal functions (i.e., DSP, Filter/CODEC, HDLC) and to provide the channel timing requirements. The DPhone-II uses channels 1, 2 & 3 of the 32 channel frame. These channels are always defined, beginning with the first channel after frame pulse, as shown in Figure 6 (DSTi and DSTo channel assignments). Channels are enabled independently by the three control bits Ch1En -Ch3En residing in the Timing Control Register (address15h). Ch1EN - C-Channel Channel 1 conveys the control/status information for Zarlink’s layer 1 transceiver. The full 64 kb/s bandwidth is available and is assigned according to which transceiver is being used. Consult the data sheet for the selected transceiver for its bit definitions and order of bit transfer. When this bit is high register data is transmitted on DSTo. When low, this timeslot is tri-stated on DSTo. Receive C-Channel data (DSTi) is always routed to the register regardless of this control bit's logic state. C-channel data is transferred on the ST-BUS MSB first by the DPhone-II. Ch2EN and Ch3EN - B1-Channel and B2-Channel Channels 2 and 3 are the B1 and B2 channels, respectively. These bits (Ch2EN and Ch3EN) are used to enable the PCM channels from/to the DPhone-II as required. Transmit PCM on DSTo When high, PCM from the Filter/CODEC and DSP is transmitted on DSTo in the selected ST-BUS channel. When low, DSTo is forced to logic 0 for the corresponding timeslot. If both Ch2EN and Ch3EN are enabled, default is to channel 2. Receive PCM from DSTi When high, PCM from DSTi is routed to the DSP and Filter/CODEC in the associated channel. If both Ch2EN and Ch3EN are enabled the default is to channel 2. New Call Tone The New Call Tone Generator produces a frequency shifted square-wave used to toggle the speaker driver outputs. This is intended for use where a ringing signal is required concurrently with an already established voice conversation in the handset. Programming of the DSP for New Call generator is exactly as is done for the tone ringer micro-program except that the OPT bit (DSP Control Register, address 1Eh) is set high. In this mode the DSP does not produce a frequency shifted squarewave output to the filter CODEC section. Instead the DSP uses the contents of the tone coefficient registers, along with the tone warble rate register, to produce a gated squarewave control signal output which toggles between the programmed frequencies. This control signal is routed to the New Call Tone block when the NCT EN control bit is set (General Control Register, address 0Fh). NCT EN also enables a separate gain control block, for controlling the loudness of the generated ringing signal. With the gain control block set to 0 dB the output is at maximum or 6 volts p-p. Attenuation of the applied signal, in three steps of 8 dB, provide the four settings for New Call tone (0, -8, -16, -24 dB). The NCT gain bits (NCTG0-NCTG1) reside in the FCODEC Gain Control Register 2 (address 0Bh). 12 Zarlink Semiconductor Inc. MT9094 Data Sheet 125 µs F0i DSTi, DSTo Not Used CHANNEL 1 C-channel CHANNEL 2 B1-channel CHANNEL 3 B2-channel CHANNELS 4 - 31 Not Used MSB first for C, B1 - & B2Channels Figure 6 - ST-BUS Channel Assignment Watchdog To maintain program integrity an on-chip watchdog timer is provided for connection to the microcontroller reset pin. The watchdog output WD (pin 17) goes high while the DPhone-II is held in reset via the PWRST (pin 6). Release of PWRST will cause WD to return low immediately and will also start the watchdog timer. The watchdog timer is clocked on the falling edge of F0i and requires only this input, along with VDD, for operation. If the watchdog reset word is written to the watchdog register (address 11h) after PWRST is released, but before the timeout period (T=512mSec) expires, a reset of the timer results and WD will remain low. Thereafter, if the reset word is loaded correctly at intervals less than 'T' then WD will continue low. The first break from this routine, in which the watchdog register is not written to within the correct interval or it is written to with incorrect data, will result in a high going WD output after the current interval 'T' expires. WD will then toggle at this rate until the watchdog register is again written to correctly. 5-BIT WATCHDOG RESET WORD X X X W4 W3 W2 W1 W0 0 1 0 1 0 x=don’t care DPhone-II Register Map Address (Hex) WRITE READ 00-09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17-1C RESERVED FCODEC GAIN CONTROL REGISTER 1 FCODEC GAIN CONTROL REGISTER 2 RESERVED RESERVED TRANSDUCER CONTROL REGISTER GENERAL CONTROL REGISTER RESERVED WATCHDOG REGISTER LCD SEGMENT ENABLE REGISTER 1 LCD SEGMENT ENABLE REGISTER 2 C-CHANNEL REGISTER (to DSTo) TIMING CONTROL REGISTER LOOP-BACK REGISTER RESERVED RESERVED VERIFY VERIFY RESERVED RESERVED VERIFY VERIFY RESERVED NOT USED VERIFY VERIFY C-CHANNEL REGISTER (from DSTi) VERIFY VERIFY RESERVED 13 Zarlink Semiconductor Inc. MT9094 Data Sheet DPhone-II Register Map Address (Hex) WRITE READ 1D 1E 1F 20 21 22 23 24 25 26 27-3F RECEIVE GAIN CONTROL REGISTER DSP CONTROL REGISTER RESERVED TRANSMIT AUDIO GAIN REGISTER TRANSMIT DTMF GAIN REGISTER RESERVED TONE COEFFICIENT REGISTER 1 TONE COEFFICIENT REGISTER 2 RESERVED TONE RINGER WARBLE RATE REGISTER RESERVED VERIFY VERIFY RESERVED VERIFY VERIFY RESERVED VERIFY VERIFY RESERVED VERIFY RESERVED Test Loops Detail LBio and LBoi Loopback Register (address 16h) LBio Setting this bit causes data on DSTi to be looped back to DSTo directly at the pins. The appropriate channel enables Ch1EN -Ch3EN must also be set. LBoi Setting this bit causes data on DSTo to be looped back to DSTi directly at the pins. 14 Zarlink Semiconductor Inc. MT9094 Data Sheet Register Summary This section contains a complete listing of the DPhone-II register addresses, the control/status bit mapping associated with each register and a definition of the function of each control/status bit. The Register Summary may be used for future reference to review each of the control/status bit definitions without the need to locate them in the text of the functional block descriptions. ADDRESSES 00h and 09h are RESERVED FCODEC Gain Control Register 1 ADDRESS = 0Ah WRITE/READ VERIFY RxFG2 RxFG1 RxFG0 7 6 Receive Gain Setting (dB) 0 5 - 4 3 RxFG2 RxFG1 RxFG0 Power Reset Value X000 X000 TxFG2 TxFG1 TxFG0 2 1 0 Transmit Gain Setting (dB) TxFG2 TxFG1 TxFG0 0 0 0 (default) 0 0 0 0 -1 0 0 1 1 0 0 1 -2 0 1 0 2 0 1 0 -3 0 1 1 3 0 1 1 -4 1 0 0 4 1 0 0 -5 1 0 1 5 1 0 1 -6 1 1 0 6 1 1 0 -7 1 1 1 7 1 1 1 (default) RxFGn = Receive Filter Gain n TxFGn = Transmit Filter Gain n FCODEC Gain Control Register 2 - NCTG1 NCTG0 - 7 ADDRESS = 0Bh WRITE/READ VERIFY 6 5 4 - STG2 3 2 STG1 1 Power Reset Value 0X00 X000 STG0 0 Side-tone Gain Setting (dB) STG2 STG1 STG0 0 (default) OFF 0 0 0 1 -9.96 0 0 1 1 0 -6.64 0 1 0 1 1 -3.32 0 1 1 0 1 0 0 3.32 1 0 1 6.64 1 1 0 9.96 1 1 1 Gain (dB) NCTG1 NCTG0 0 (default) 0 -8 0 -16 -24 NCTGn = New Call Tone Gain n STGn= Side-tone Gain n 15 Zarlink Semiconductor Inc. MT9094 Data Sheet ADDRESSES 0Ch and 0Dh are RESERVED Note: Bits marked "-" are reserved bits and should be written with logic "0". Transducer Control Register PuFC Tfhp 7 6 PuFC ADDRESS = 0Eh WRITE/READ VERIFY DIAL EN 5 SIDE EN 4 MIC EN 3 MIC/ HNSTMIC 2 SPKR EN 1 DIAL EN SIDE EN MIC EN MIC/HNSTMIC SPKR EN HSSPKR EN General Control Register RST 7 DATASEL A/u Sign-mag/CCITT RxA/u MICA/u SIDEA/u NCT EN EN Power Reset Value 0000 0000 0 When high, the Filter/CODEC is powered up. When low, the Filter/CODEC is powered down. If PuFC, SPKR EN and HSSPKR EN are all low then the VRef/VBias circuit is also powered down. When high, an additional high pass function (passband beginning at 400 Hz) is inserted into the transmit path. When low, this highpass filter is disabled. When high, a first order lowpass filter is inserted into the receive path (3 dB = 1 kHz). When low, this lowpass filter is disabled. When high, the sidetone path is enabled (assuming STG2-0 are not all low). When low, the sidetone path is disabled. When high, the selected transmit microphone is enabled to the transmit filter section. When low, the microphone path is muted. When high, the handsfree microphone (pins MIC±) is muxed into the transmit path. When low, the handset microphone (pins M±) is muxed into the transmit path. Both are contingent on "MIC EN". When high, the handsfree loudspeaker driver is powered up. When low, this driver is powered down. When high, the handset speaker driver is powered up. When low, this driver is powered down. Tfhp RST HSSPKR DATA SEL 6 ADDRESS = 0Fh WRITE/READ VERIFY A/µ 5 Sign-Mag/ CCITT 4 Rx A/µ MIC A/µ 3 2 Side A/µ NCT EN 1 0 Power Reset Value 0000 0000 Active high reset. Performs the same function as PWRST but does not affect the microport or the watchdog circuits. To remove this reset a PWRST must occur or this bit must be written low. When high, the microport transmit and receive are performed on separate pins. DATA1 is receive while DATA2 is transmit. When low, the microport conforms to Intel MCS-51 mode 0 specifications; DATA1 is a bi-directional (transmit/receive) serial data pin while DATA2 is internally disconnected and tri-stated. When high, A-Law (de)coding is selected. When low, µ-Law (de)coding is selected. When high, sign-magnitude bit coding is selected, When low, true CCITT PCM coding is selected. When high, the receiver driver nominal gain is set at -9.7 dB. When low this driver nominal gain is set at -12.3 dB. When high, the transmit amplifier nominal gain is set at 15.4 dB. When low this amplifier nominal gain is set at 6.1 dB. When high, the side-tone nominal gain is set at -18.8 dB. When low this nominal gain is set at -11 dB. When high, the new call tone generator output from the DSP is selected as the source for the loudspeaker path. When low, the CODEC output is selected for the loudspeaker path. Note that SPKR EN must also be set high for new call tone to function. ADDRESS 10h is RESERVED Note: Bits marked "-" are reserved bits and should be written with logic "0". 16 Zarlink Semiconductor Inc. MT9094 Data Sheet Watchdog Register 7 ADDRESS = 11h WRITE - - 6 5 W4 W3 W2 W1 W0 4 3 2 1 0 Power Reset Value XXX0 1010 WATCHDOG RESET WORD - XXX01010 LCD Segment Enable Register 1 ADDRESS = 12h WRITE/READ VERIFY SC8 SC7 SC6 SC5 SC4 SC3 SC2 SC1 7 6 5 4 3 2 1 0 Power Reset Value 0000 0000 Twelve segment control bits used for the LCD outputs. When high the respective segment is on. When low the respective segment is off. LCD Segment Enable Register 2 ADDRESS = 13h WRITE/READ VERIFY - - - - SC12 SC11 SC10 SC9 7 6 5 4 3 2 1 0 Power Reset Value XXXX 0000 Twelve segment control bits used for the LCD outputs. When high the respective segment is on. When low the respective segment is off. C-Channel Register ADDRESS = 14h WRITE/READ D7 D6 D5 D4 D3 D2 D1 D0 7 6 5 4 3 2 1 0 Micro-port access to the ST-BUS C-Channel information. Note: Bits marked "-" are reserved bits and should be written with logic "0". 17 Zarlink Semiconductor Inc. Power Reset Value Write = 1111 1111 Read = Not Applicable MT9094 Data Sheet Timing Control Register ADDRESS = 15h WRITE/READ VERIFY - - - - 7 6 5 4 CH3EN CH2EN CH1EN 3 2 1 Power Reset Value XX0X 0000 0 All bits active high: Ch2EN and Ch3EN Channels 2 and 3 are the B1 and B2 channels, respectively. PCM associated with the DSP, Filter/CODEC and transducer audio paths is conveyed in one of these channels as selected in the timing control register. Transmit B1 and B2 data on DSTo When high PCM from the Filter/CODEC and DSP is transmitted on DSTo in the associated channel. When low DSTo is forced to logic 0 for the corresponding timeslot. If both Ch2EN and Ch3EN are enabled, data defaults to channel 2. Receive B1 and B2 data on DSTi When enabled PCM from DSTi is routed to the DSP and Filter/CODEC in the associated channel. If both Ch2EN and Ch3EN Ch1EN are enabled, data input defaults to channel 2. Channel 1 conveys the control/status information for the layer 1 transceiver. The full 64kb/s bandwidth is available and is assigned according to which transceiver is being used. Consult the data sheets for the transceiver selected. When high register data is transmitted on DSTo. When low this timeslot is tri-stated on DSTo. Receive C-Channel data (DSTi) is always routed to the register regardless of this control bit's logic state. Loop-back Register 7 ADDRESS = 16h WRITE/READ VERIFY LBio LBoi - - - - - 6 5 4 3 2 1 0 Power Reset Value X00X XXXX LBio Active high enables data from the ST-BUS input to be looped back to the ST-BUS output directly at the pins. The DSTo tri-state driver LBoi must also be enabled using one of the channel enable signals. Active high enables data from ST-BUS output to be looped back to the ST-BUS input directly at the pins. ADDRESSES 17h - 1Ch are RESERVED Note: Bits marked "-" are reserved bits and should be written with logic "0". 18 Zarlink Semiconductor Inc. MT9094 Data Sheet Receive Gain Control Register AUTO B5-B0 ADDRESS = 1Dh WRITE/READ VERIFY - AUTO B5 B4 B3 B2 B1 B0 7 6 5 4 3 2 1 0 Power Reset Value 0000 0000 When high autonulling of the transmit PCM is enabled. When low, autonulling is disabled. This bit is used in conjunction with the PS2 PS0 bits of the DSP Control Register at address 1Eh. These 6 bits (indicated below in hexadecimal) are decoded to control Rx PCM gain: B5-B0 Gain Setting (dB) B5-B0 Gain Setting (dB) 3F 3E 3D 3C 3B 3A 39 38 37 36 35 34 33 32 31 30 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 +22.5 +21.0 +19.5 +18.0 +16.5 +15.0 +13.5 +12.0 +10.5 +9.0 +7.5 +6.0 +4.5 +3.0 +1.5 +0.0 -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 -13.5 -15.0 -16.5 -18.0 -19.5 -21.0 -22.5 -24.0 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 -25.5 -27.0 -28.5 -30.0 -31.5 -33.0 -34.5 -36.0 -37.5 -39.0 -40.5 -42.0 -43.5 -45.0 -46.5 -48.0 -49.5 -51.0 -52.5 -54.0 -55.5 -57.0 -58.5 -60.0 -61.5 -63.0 -64.5 -66.0 -67.5 -69.0 -70.5 -72.0 Note: B0-B5 of addresses 20h and 21h are encoded in the same manner Note: Bits marked "-" are reserved bits and should be written with logic "0". 19 Zarlink Semiconductor Inc. MT9094 Data Sheet DSP Control Register ADDRESS = 1Eh WRITE/READ VERIFY PS2 PS1 7 6 OPT: RxMUTE: TxMUTE: DRESET: PS0 5 OPT RxMUTE TxMUTE - DRESET 4 3 2 1 0 Power Reset Value 0000 0000 When high, the tone ringer is in New Call tone mode. When low the normal tone ringer program is executed. This bit when high turns off the receive PCM channel, substituting quiet code. This bit when high turns off the transmit PCM channel, substituting quiet code. This bit (when high) enables the DSP. If low, no programs are executed, the master clock is disabled and the program counter is reset to zero. These bits are program select bits for the DSP Rom programs. PS2-PS0: PS2 PS1 PS0 MICRO-PROGRAM 0 0 0 Power up reset program 0 0 1 Gain control program 0 1 0 DTMF & Gain control program 0 1 1 Tone Ringer & Gain control program 1 0 0 Handsfree program 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved ADDRESS 1Fh is RESERVED Transmit Audio Gain Register - 7 ADDRESS = 20h WRITE/READ VERIFY B5 B4 B3 B2 B1 B0 5 4 3 2 1 0 6 Power Reset Value XX11 0000 This register controls the transmit speech path gain in 1.5dB steps as in Receive Gain Register (address 1Dh). ADDRESS = 21h WRITE/READ VERIFY Transmit DTMF Gain Register - 7 6 B5 B4 B3 B2 B1 B0 5 4 3 2 1 0 Power Reset Value XX10 1110 This register controls the transmit DTMF level in 1.5dB steps as in Receive Gain Register (address 1Dh). ADDRESS 22h is RESERVED Note: Bits marked "-" are reserved bits and should be written with logic "0". 20 Zarlink Semiconductor Inc. MT9094 Data Sheet Tone Coeff Register 1-DTMF or Tone Ringer ADDRESS = 23h WRITE/READ VERIFY B7 B6 B5 B4 B3 B2 B1 B0 7 6 5 4 3 2 1 0 Power Reset Value 0000 0000 This register is used to program the low-group frequency of the DTMF program. The tone coefficient is calculated as follows: COEF = 0.128 x Frequency where: Frequency is in Hz (note: COEF must be converted to an 8 bit binary integer) Highest frequency possible: 1992.2 Hz Lowest frequency possible: 7.8 Hz Frequency resolution: 7.8 Hz -2.1 dB ± 0.2 dB Pre-twist: This register is used to program the first frequency of the squarewave ringer program. The tone coefficient is calculated as follows: COEF = 8000 / Frequency where: Frequency is in Hz (note: COEF must be rounded off and converted to an 8 bit binary integer) Highest frequency possible: 4000 Hz Lowest frequency possible: 31.4 Hz Frequency resolution: non-linear This tone can be disabled by writing zero to this register for single tone generation. Tone Coeff Register 2-DTMF or Tone Ringer ADDRESS = 24h WRITE/READ VERIFY B7 B6 B5 B4 B3 B2 B1 B0 7 6 5 4 3 2 1 0 Power Reset Value 0000 0000 This register is used to program the high-group frequency of the DTMF program. The tone coefficient is calculated as follows: COEF = 0.128 x Frequency where: Frequency is in Hz (note: COEF must be converted to an 8 bit binary integer) Highest frequency possible: 1992.2 Hz Lowest frequency possible: 7.8 Hz Frequency resolution: 7.8 Hz Pre-twist: 0 dB This register is used to program the second frequency of the squarewave program. The tone coefficient is calculated similarly to tone coefficient register 1. ADDRESS 25h is RESERVED 21 Zarlink Semiconductor Inc. MT9094 Data Sheet Tone Ringer Warble Rate-Tone Ringer ADDRESS = 26h WRITE/READ VERIFY B7 B6 B5 B4 B3 B2 B1 B0 7 6 5 4 3 2 1 0 Power Reset Value 0000 0000 The tone ringer will switch between squarewave frequencies at a warble frequency defined by this register. The relationship between the duration period of each tone and the 8 bit warble coefficient is as follows: Tone duration (warble frequency) = 500 / COEF where: Frequency is in Hz, and 0≤COEF 4600 Hz GRR 7 Absolute Delay DAR 240 µs at frequency of min. delay 8 Group Delay relative to DAR DDR 750 380 130 750 µs µs µs µs 500-600 Hz 600-1000 Hz 1000-2600 Hz 2600 - 2800 Hz 9 Crosstalk CTRT CTTR dB dB G.714.16 All other receive filter settings (-1 to -7 dB) are in addition to 0 dB setting D/A to A/D A/D to D/A 0.2 -12.3 -9.7 -0.25 -0.90 15.5 -75 dBrnC0 dBrn0p 0.25 0.25 0.25 -12.5 -25 dB dB dB dB dB -74 -80 µ-Law A-Law † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * Note: RxA/u, refer to General Control Register, address 0Fh. AC Electrical Characteristics† for Side-tone Path Sym. Min. Typ.‡ Max. Units Absolute path gain Gain adjust = 0 dB GAS1 GAS2 -17.213.1 -16.7 -12.6 16.2 -12.1 dB dB SIDEA/u, MICA/u, RxA/u all 0 SIDEA/u, MICA/u, RxA/u all 1 M± inputs to HSPKR± outputs 1000Hz All other settings (-9.96 to +9.96 dB) GAS GAS -0.3 -0.3 +0.3 +0.3 dB dB SIDEA/u=0 SIDEA/u=1 from nominal relative measurements w.r.t. GAS1 & GAS2 Characteristics 1 Test Conditions † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. 32 Zarlink Semiconductor Inc. MT9094 Data Sheet AC Electrical Characteristics† for New Call Tone Characteristics 1 New Call Tone Output voltage (SPKR+ to SPKR-) Sym. Typ.‡ Units VNCT1 VNCT2 VNCT3 VNCT4 6.0 2.390 0.950 0.380 Vp-p Vp-p Vp-p Vp-p Test Conditions NCTG0=0, NCTG1=0 NCTG0=1, NCTG1=0 NCTG0=0, NCTG1=1 NCTG0=1, NCTG1=1 load > 34 ohms across SPKR± † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Electrical Characteristics† for Analog Outputs Characteristics Sym. Min. Typ.‡ 260 300 ohms 300 pF each pin: % 300 ohms load across HSPKR± (tol-15%),RxA/u=1, VO≤693Vrms, Rx gain=0dB 1 Earpiece load impedance EZL 2 Allowable Earpiece capacitive load ECL 3 Earpiece harmonic distortion ED 4 Speaker load impedance SZL 5 Allowable Speaker capacitive load SCL 6 Speaker harmonic distortion SD Max. 0.5 34 Units Test Conditions across HSPKR± HSPKR+ HSPKR- 40 ohms 300 pF each pin % 40 ohms load across SPKR± (tol-15%), VO≤6.2Vp-p, Rx gain=0 dB 0.5 across SPKR± SPKR+ SPKR- † Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Electrical Characteristics† for Analog Inputs Characteristics 1 Differential input voltage without overloading CODEC 2 Input impedance Sym. Min. Typ.‡ VID ZI 50 Max. Units Test Conditions 2.87 1.02 Vp-p Vp-p MICA/u=0, A/u=0 MICA/u=0, A/u=1 across MIC± or M± inputs, Tx filter gain = 0 dB setting kΩ † Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. 33 Zarlink Semiconductor Inc. MIC+, MIC-, M+ or Mto VSS. MT9094 Data Sheet AC Electrical Characteristics† - ST-BUS Timing (See Figure 11) Characteristics Sym. Min. Typ.‡ Max. Units 1 C4i Clock Period tC4P 243 244 245 ns 2 C4i Clock High Period tC4H 121 122 123 ns 3 C4i Clock Low Period tC4L 121 122 123 ns 4 C4i Clock Transition Time 20 50 ns 5 F0i Frame Pulse Setup Time tF0iS 50 ns 6 F0i Frame Pulse Hold Time tF0iH 50 ns 7 F0i Frame Pulse Width Low tF0iW 150 ns 8 DSTo Delay tDSToD 9 DSTi Setup Time tDSTiS 30 ns 10 DSTi Hold Time tDSTiH 50 ns tT 100 125 ns Test Conditions CL=50 pF † Timing is over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. tT tC4H tC4P C4i tT 1 bit cell 2.4V 0.4V tDSToD DSTo 2.4V 0.4V tDSTiS DSTi 2.4V 0.4V tT F0i tDSTiH 2.4V 0.4V tF0iH tF0iS tT tF0iW Figure 11 - ST-BUS Timing Diagram 34 Zarlink Semiconductor Inc. tC4L MT9094 Data Sheet AC Electrical Characteristics† - Microport Timing (see Figure 12) Characteristics Sym. Min. Typ.‡ Max. Units Test Conditions 1 Receive data setup A 10 ns 2 Receive data hold B 10 ns 3 Transmit data delay from clock falling edge C 80 ns 50 pF 4 High Z to valid data from SCLK falling edge D 80 ns 50 pF 5 Valid data to high Z from CS rising edge E 80 ns 50 pF 6 Current transmit data hold from clock falling edge F 0 ns 7 Chip Select to SCLK setup and hold times G 0 ns 8 SCLK clock period (3 MHz) H 333 ns † Timing is over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. DATA 1 RECEIVE 0 1 2 7 B A H SCLK G G CS D E F C DATA 1 or DATA 2 TRANSMIT 0 1 2 6 Figure 12 - Serial Microport Timing Diagram 35 Zarlink Semiconductor Inc. 7 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE