SG1526/SG2526/SG3526
REGULATING PULSE WIDTH MODULATOR
DESCRIPTION
FEATURES
The SG1526 is a high-performance monolithic pulse width
modulator circuit designed for fixed-frequency switching
regulators and other power control applications. Included
in an 18-pin dual-in-line package are a temperature
compensated voltage reference, sawtooth oscillator, error
amplifier, pulse width modulator, pulse metering and
steering logic, and two low impedance power drivers. Also
included are protective features such as soft-start and
undervoltage lockout, digital current limiting, double pulse
inhibit, a data latch for single pulse metering, adjustable
deadtime, and provision for symmetry correction inputs.
For ease of interface, all digital control ports are TTL and
B-series CMOS compatible. Active LOW logic design
allows wired-OR connections for maximum flexibility. This
versatile device can be used to implement single-ended or
push-pull switching regulators of either polarity, both
transformerless and transformer coupled. The SG1526 is
characterized for operation over the full military ambient
junction temperature range of -55°C to +150°C. The
SG2526 is characterized for operation from -25°C to
+150°C, and the SG3526 is characterized for operation
from 0°C to +125°C.
8V to 35V Operation
5V Reference Trimmed to ±1%
1Hz to 350kHz Oscillator Range
Dual 100mA Source/Sink Outputs
Digital Current Limiting
Double Pulse Suppression
Programmable Deadtime
Undervoltage Lockout
Single Pulse Metering
Programmable Soft-start
Wide Current Limit Common Mode
Range TTL/CMOS Compatible Logic
Ports Symmetry Correction Capability
Guaranteed 6 Unit Synchronization
HIGH RELIABILITY FEATURES
Available to MIL-STD-883, ¶ 1.2.1
Available to DSCC - Standard Microcircuit
Drawing (SMD)
Radiation data available
MSC-AMS level "S" processing available
BLOCK DIAGRAM
VREF
+VIN
Reference
Regulator
GROUND
To Internal
Circuitry
RD
RT
CT
RESET
CSOFTSTART
COMPENSATION
+ ERROR
+VC
Undervoltage
Lockout
SYNC
Oscillator
OUTPUT A
Soft
Start
S
R
+VIN
S
D
Amp
— ERROR
Q
T
Q
MEMORY
F/F
Q
TOGGLE
F/F
Q
METERING
F/F
+ C.S.
Q
OUTPUT B
— C.S.
SHUTDOWN
December 2014 Rev1.2
www.microsemi.com
© 2014 Microsemi Corporation
1
ABSOLUTE MAXIMUM RATINGSte 1)
Input Voltage (VIN ) ............................................................... 40V
Collector Supply Voltage (VC) ............................................. 40V
Logic Inputs ......................................................... -0.3V to 5.5V
Analog Inputs .......................................................... -0.3V to V IN
Source/Sink Load Current (each output) ....................... 200mA
Reference Load Current .................................................. 50mA
Logic Sink Current ............................................................ 15mA
Operating Junction Temperature
Hermetic (J, L Packages) ............................................ 150°C
Plastic (N, DW Packages) ........................................... 150°C
Storage Temperature Range ............................ -65°C to 150°C
Lead Temperature (Soldering, 10 Seconds) ................... 300°C
Note 1. Exceeding these ratings could cause damage to the device.
RoHS Peak Package Solder Reflow Temp. (40 sec. max. exp.)...... 260°C (+0, -5)
THERMAL DATA
J Package:
Thermal Resistance-Junction to Case, θ JC .................. 25°C/W
Thermal Resistance-Junction to Ambient, θ JA .............. 70°C/W
N Package:
Thermal Resistance-Junction to Case, θ JC .................. 30°C/W
Thermal Resistance-Junction to Ambient, θ JA ............. 60°C/W
DW Package:
Thermal Resistance-Junction to Case, θ JC .................. 35°C/W
Thermal Resistance-Junction to Ambient, θ JA ............. 90°C/W
L Package:
Thermal Resistance-Junction to Case, θ JC ................... 35°C/W
Thermal Resistance-Junction to Ambient, θ JA ........... 120°C/W
Note A. Junction Temperature Calculation: TJ = TA + (PD x θJA).
Note B. The above numbers for θ JC are maximums for the limiting
thermal resistance of the package in a standard mounting configuration. The θ JA numbers are meant to be
guidelines for the thermal performance of the device/pcboard system. All of the above assume no ambient
airflow.
RECOMMENDED OPERATING CONDITIONS (Note 2)
Input Voltage ............................................................. 8V to 35V
Collector Supply Voltage ........................................ 4.5V to 35V
Sink/Source Load Current (each output) ................ 0 to 100mA
Reference Load Current ........................................... 0 to 20mA
Oscillator Frequency Range .............................. 1Hz to 350kHz
Oscillator Timing Resistor .................................. 2kΩ to 150kΩ
Oscillator Timing Capacitor .................................... 1nF to 20µF
Available Deadtime Range at 40kHz ...................... 3% to 50%
Operating Ambient Temperature Range:
SG1526 ......................................................... -55°C to 125°C
SG2526 ........................................................... -25°C to 85°C
SG3526 ............................................................... 0°C to 70°C
Note 2. Range over which the device is functional.
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG1526 with -55°C ≤ T A ≤ 125°C, SG2526 with
-25°C ≤ TA ≤ 85°C, SG3526 with 0°C ≤ TA ≤ 70°C, and VIN = 15V. Low duty cycle pulse testing techniques are used which maintains junction and case
temperatures equal to the ambient temperature.)
Parameter
Reference Section (Note 3)
Output Voltage
Line Regulation
Load Regulation
Temperature Stability (Note 9)
Total Output Voltage Range (Note 9)
Short Circuit Current
Undervoltage Lockout Section
RESET Output Voltage
RESET Output Voltage
Test Conditions
SG1526/2526
SG3526
Units
Min. Typ. Max. Min. Typ. Max.
TJ = 25°C
VIN = 8 to 35V
IL = 0 to 20mA
Over Operating TJ
Over Recommended Operating Conditions
VREF = 0V
4.95 5.00 5.05 4.90 5.00 5.10
10
30
10
30
30
10
50
10
15
50
15
50
4.90 5.00 5.10 4.85 5.00 5.15
50 125
50 125
VREF = 3.8V
VREF = 4.8V
2.4
2
0.2
4.8
0.4
2.4
0.2
4.8
0.4
V
mV
mV
mV
V
mA
V
V
ELECTRICAL CHARACTERISTICS
(continued)
Parameter
Oscillator Section (Note 4)
Initial Accuracy
Voltage Stability
Temperature Stability (Note 9)
Minimum Frequency (Note 9)
Maximum Frequency
Sawtooth Peak Voltage
Sawtooth Valley Voltage
Error Amplifier Section (Note 5)
Input Offset Voltage
Input Bias Current
Input Offset Current
DC Open Loop Gain
High Output Voltage
Low Output Voltage
Common Mode Rejection
Supply Voltage Rejection
PWM Comparator Section (Note 4)
Minimum Duty Cycle
Maximum Duty Cycle
Test Conditions
TJ = 25°C
VIN = 8 to 35V
Over Operating TJ
RT = 150kΩ, CT = 20µF
RT = 2kΩ, CT = 1.0nF
VIN = 35V
VIN = 8V
350
0.5
RS ≤ 2kΩ
RL ≥ 10MΩ, TJ = 25°C
VPIN1 - VPIN2 ≥ 150mV, ISOURCE = 100µA
VPIN2 - VPIN1 ≥ 150mV, ISINK = 100µA
RS ≤ 2kΩ
VIN = 8V to 35V
VCOMPENSATION = 0.4V
VCOMPENSATION = 3.6V
64
3.6
70
66
45
Digital Ports (SYNC, SHUTDOWN, and RESET)
HIGH Output Voltage
ISOURCE = 40µA
LOW Output Voltage
ISINK = 3.6mA
VIH = 2.4V
HIGH Input Current
VIL = 0.4V
LOW Input Current
Current Limit Comparator Section (Note 6)
RS ≤ 50Ω, TJ = 25°C
Sense Voltage
Input Bias Current
Soft-Start Section
Error Clamp Voltage
RESET = 0.4V
CS Charging Current
RESET = 2.4V
Output Drivers (each output) (Note 7)
HIGH Output Voltage
ISOURCE = 20mA
ISOURCE = 100mA
LOW Output Voltage
ISINK = 20mA
ISINK = 100mA
Collector Leakage
VC = 40V
Rise Time
CL = 1000pF
Fall Time
CL = 1000pF
Power Consumption Section (Note 8)
Standby Current
SHUTDOWN = 0.4V
Note 3.
Note 4.
Note 5.
Note 6.
SG1526/2526
SG3526
Units
Min. Typ. Max. Min. Typ. Max.
±3
0.5
7
±8
1.0
10
1.0
3.0
1.0
3.5
0.5
2
5
-350 -1000
35 100
72
60
4.2
3.6
0.2 0.4
94
70
66
80
49
0
45
±8
1.0
10
1.0
3.0
1.0
3.5
10
2
-350 -2000
35 200
72
4.2
0.2 0.4
94
80
49
0
%
%
%
Hz
kHz
V
V
mV
nA
nA
dB
V
V
dB
dB
%
%
2.4
4
0.2 0.4
-125 -300
-225 -500
2.4
4
0.2 0.4
-125 -300
-225 -500
V
V
µA
µA
90
100
-3
110
-10
80
100
-3
120
-10
mV
µA
0.1
100
0.4
200
0.1
100
0.4
200
V
µA
12.5 13.5
12.5 13.5
12
13
12
13
0.2 0.3
0.2 0.3
2
1.2
2
1.2
50 150
50 150
0.3 0.6
0.3 0.6
0.1 0.2
0.1 0.2
V
V
V
V
µA
µs
µs
50
18
IL = 0mA
FOSC = 40kHz (RT = 4.12kΩ ±1%, CT = .01µF ±1%, RD = 0Ω)
VCM = 0 to 5.2V
VCM = 0 to 12V
350
±3
0.5
5
30
50
18
30
mA
Note 7. VC = 15V
Note 8. VIN = 35V
Note 9. These parameters, although guaranteed over the recommended operating conditions, are not tested in production.
3
CHARACTERISTIC CURVES
FIGURE 1.
REFERENCE VOLTAGE VS. SUPPLY VOLTAGE
FIGURE 2.
REFERENCE TEMPERATURE STABILITY
FIGURE 3.
REFERENCE SHORT CIRCUIT CURRENT
FOSC = 40kHz
FOSC = 40kHz
1k
10k
FIGURE 5.
OSCILLATOR FREQUENCY TEMPERATURE
STABILITY
RT - (kΩ)
FIGURE 4.
REFERENCE RIPPLE REJECTION
100k
FIGURE 7.
OSCILLATOR PERIOD VS. RT AND CT
4
FIGURE 6.
OUTPUT DRIVER DEADTIME VS. RD VALUE
CHARACTERISTIC CURVES
(continued)
10k
1k
FIGURE 9.
ERROR AMPLIFIER OPEN LOOP GAIN
VS. FREQUENCY
FIGURE 10.
SOFTSTART TIME CONSTANT VS. CS
FIGURE 11.
CURRENT LIMIT TRANSFER FUNCTION
FIGURE 12.
COMPARATOR INPUT TO DRIVER OUTPUT DELAY
FIGURE 13.
SHUTDOWN INPUT TO DRIVER OUTPUT DELAY
FIGURE 14.
OUTPUT DRIVER SATURATION VOLTAGE VS. ISINK
FIGURE 15.
OUTPUT SUPPLY SATURATION VOLTAGE VS. ISINK
FIGURE 16.
STANDBY CURRENT VS. SUPPLY VOLTAGE
SHUTDOWN - (V)
FIGURE 8.
UNDERVOLTAGE LOCKOUT CHARACTERISTIC
100k
5
APPLICATION INFORMATION
VOLTAGE REFERENCE
The reference regulator of the SG1526 is based on a temperature compensated
Zener diode. The circuitry is fully active at supply voltages above +8 volts, and
provides up to 20mA of load current to external circuitry at +5.0 volts. In systems
where additional current is required, an external PNP transistor can be used to
boost the available current. A rugged low frequency audio-type transistor should
be used, and lead lengths between the PWM and transistor should be as short as
possible to minimize the risk of oscillations. Even so, some types of transistors
may require collector-base capacitance for stability. Up to 1 amp of load current
can be obtained with excellent regulation if the device selected maintains high
current gain.
FIGURE 17.
EXTENDING REFERENCE OUTPUT CURRENT
UNDERVOLTAGE LOCKOUT
The undervoltage lockout circuit protects the SG1526 and the power devices it controls from inadequate supply voltage. If
+VIN is too low, the circuit disables the output drivers and holds the RESET pin LOW. This prevents spurious output pulses
while the control circuitry is stabilizing, and holds the soft-start timing capacitor in a discharged state.
The circuit consists of a +1.2 volt bandgap reference and comparator circuit which
is active when the reference voltage has risen to 3VBE or 1.8 volts at 25°C. When
the reference voltage rises to approximately +4.4 volts, the circuit enables the
output drivers and releases the RESET pin, allowing a normal soft-start. The
comparator has 200mV of hysteresis to minimize oscillation at the trip point. When
+VIN to the PWM is removed and the reference drops to +4.2 volts, the undervoltage circuit pulls RESET LOW again. The soft-start capacitor is immediately
discharged, and the PWM is ready for another soft-start cycle.
The SG1526 can operate from a +5 volt supply by connecting the VREF pin to the
+VIN pin and maintaining the supply between +4.8 and +5.2 volts.
FIGURE 18.
SIMPLIFIED UNDERVOLTAGE LOCKOUT
SOFT-START CIRCUIT
The soft-start circuit protects the power transistors and rectifier diodes from high
current surges during power supply turn-on. When supply voltage is first applied
to the SG1526, the undervoltage lockout circuit holds RESET LOW with Q3. Q1
is turned on, which holds the soft-start capacitor voltage at zero. The second
collector of Q1 clamps the output error amplifier to ground, guaranteeing zero duty
cycle at the driver outputs. When the supply voltage reaches normal operating
range, RESET will go HIGH. Q1 turns off, allowing the internal 100µA current
source to charge CS. Q2 clamps the error amplifier output to 1VBE above the
voltage on CS. As the soft-start voltage ramps up to +5 volts, the duty cycle of the
PWM linearly increases to whatever value the voltage regulation loop requires for
an error null. Figure 10 gives the timing relationship between CS and ramp time
to 100% duty cycle.
FIGURE 19.
SOFT-START CIRCUIT SCHEMATIC
DIGITAL CONTROL PORTS
The three digital control ports of the SG1526 are bi-directional. Each pin can drive
TTL and 5 volt CMOS logic directly, up to a fan-out of 10 low-power Schottky gates.
Each pin can also be directly driven by open-collector voltage comparators; fanin is equivalent to 1 low-power Schottky gate. Each port is normally HIGH; the pin
is pulled LOW to activate the particular function. Driving SYNC LOW initiates a
discharge cycle in the oscillator. Pulling SHUTDOWN LOW immediately inhibits
all PWM output pulses. Holding RESET LOW discharges the soft-start capacitor.
The logic threshold is +1.1 volts at 25°C. Noise immunity can be gained at the
expense of fan-out with an external 2k pullup resistor to +5 volts.
40k
20k
FIGURE 20.
DIGITAL CONTROL PORT SCHEMATIC
6
APPLICATION INFORMATION
(continued)
OSCILLATOR
FIGURE 21 - OSCILLATOR CONNECTIONS AND WAVEFORMS
The oscillator is programmed for frequency and deadtime with three components: RT, CT, and RD. Two waveforms are
generated: a sawtooth waveform at pin 10 for pulse width modulation, and a logic clock at pin 12. The following procedure
is recommended for choosing timing values:
1. With RD = 0Ω (pin 11 shorted to ground) select values for RT and CT from Figure 7 to give the desired oscillator period.
Remember that the frequency at each driver output is half the oscillator frequency, and the frequency at the +VC terminal
is the same as the oscillator frequency.
2. If more dead time is required, select a larger value of RD using Figure 6 as a guide. At 40kHz dead time increases by
400nSec/ohm.
3. Increasing the dead time will cause the oscillator frequency to decrease slightly. Go back and decrease the value of RT
slightly to bring the frequency back to the nominal design value.
The SG1526 can be synchronized to an external logic clock by programming the oscillator to free-run at a frequency 10% slower
than the sync frequency. A periodic LOW logic pulse approximately 0.5µSec wide at the SYNC pin will then lock the oscillator
to the external frequency.
Multiple devices can be synchronized together by programming one master unit for the desired frequency, and then sharing
its sawtooth and clock waveforms with the slave units. All CT terminals are connected to the CT pin of the master, and all SYNC
terminals are likewise connected to the SYNC pin of the master. Slave RT terminals should not be left open nor should they
be tied to the +5V reference; at least 50k should be connected to each pin. Slave RD terminals may be either left open or
grounded.
ERROR AMPLIFIER
FIGURE 22A
FIGURE 22B
ERROR AMPLIFIER CONNECTIONS
The error amplifier is a transconductance design, with an output impedance of 2 megohms and an effective output capacitance
of 100 pF. Since all voltage gain takes place at the output pin, the open-loop gain can be shaped with shunt reactance to ground.
For unity gain stability the amplifier requires an additional external 100 pF to ground, resulting in an open-loop pole at 400 Hz.
The input connections to the error amplifier are determined by the polarity of the switching supply output voltage. For positive
supplies, the common-mode voltage is +5.0 volts and the feedback connections in Figure 22A are used. With negative
supplies, the common-mode voltage is ground and the feedback divider is connected between the negative output and the
+5.0 volt reference voltage, as shown in Figure 22B.
7
APPLICATION INFORMATION
(continued)
OUTPUT DRIVERS
The totem-pole output drivers of the SG1526 are designed to source and sink 100mA continuously and 200mA peak. Loads
can be driven either from the output pins 13 and 16, or from the +VC pin, as required. Curves for the saturation voltage at these
outputs as a function of load current are found in Figures 14 and 15.
Since the bottom transistor of the totem-pole is allowed to saturate, there is a momentary conduction path from the +VC terminal
to ground during switching. To limit the resulting current spikes a small resistor in series with pin 14 is always recommended.
The resistor value is determined by the driver supply voltage, and should be chosen for 200mA peak currents, as shown in
Figure 25.
FIGURE 24.
SINGLE-ENDED CONFIGURATION
FIGURE 23.
PUSH-PULL CONFIGURATION
FIGURE 25.
DRIVING N-CHANNEL POWER MOSFETS
2k
33k
10k
750Ω
1k
2k
4.12k
150k
SG1526 LAB TEST FIXTURE
2k
1k
665k
1k
-IB
10k
+IB
10k
8
CONNECTION DIAGRAMS & ORDERING INFORMATION
Package
18-PIN CERAMIC DIP
J - PACKAGE
18-PIN PLASTIC DIP
N - PACKAGE
Part No.
SG1526J-883B
SG1526J
SG2526J
SG3526J
SG2526N
SG3526N
(See Notes Below)
Ambient
Temperature Range
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
0°C to 70°C
-25°C to 85°C
0°C to 70°C
N Package: RoHS Compliant / Pb-free Transition DC: 0503
18-PIN WIDE BODY
PLASTIC SOIC
DW - PACKAGE
SG2526DW
SG3526DW
-25°C to 85°C
0°C to 70°C
DW Package: RoHS Compliant / Pb-free Transition DC: 0516
20-PIN CERAMIC
LEADLESS CHIP CARRIER
L- PACKAGE
SG1526L-883B
SG1526L
-55°C to 125°C
-55°C to 125°C
Connection Diagram
+ERROR
- ERROR
COMPENSATION
1
18
2
17
3
16
CSOFTSTART
RESET
- CURRENT SENSE
+CURRENT SENSE
SHUTDOWN
RT
4
15
5
14
6
13
7
12
8
11
9
10
OUTPUT B
GROUND
VCOLLECTOR
OUTPUT A
SYNC
RDEADTIME
CT
N Package: RoHS / Pb-free 100% Matte Tin Lead Finish
+ERROR
-ERROR
COMPENSATION
1
18
2
17
3
16
CSOFTSTART
RESET
- CURRENT SENSE
+CURRENT SENSE
4
15
5
14
6
13
7
12
SHUTDOWN
8
11
RT
9
10
VREF
+VIN
OUTPUT B
GROUND
+VCOLLECTOR
OUTPUT A
SYNC
RDEADTIME
CT
DW Package: RoHS / Pb-free 100% Matte Tin Lead Finish
1. N.C.
2. +ERROR
3. -ERROR
4. COMP
5. CSOFTSTART
6. RESET
7. -C.S.
8. +C.S.
9. SHUTDOWN
10.RT
3
2
1
20 19
4
18
5
17
6
16
7
15
8
14
9
10 11 12 13
Note 1. Contact factory for JAN and DESC product availability.
Note 2. All parts are viewed from the top.
Note 3. Hermetic Packages J, L use Pb37/Sn63 hot solder lead finish, contact factory for availability of RoHS versions.
9
VREF
+VIN
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
CT
RDEADTIME
SYNC
OUTPUT A
+VCOLLECTOR
N.C.
GROUND
OUTPUT B
+VIN
VREF
PACKAGE OUTLINE DIMENSIONS
Controlling dimensions are in inches, metric equivalents are shown for general information.
MILLIMETERS
MIN
MAX
DIM
A
10
1
9
A
24.38
0.960
B
5.59
7.11
0.220
0.280
C
5.08
0.200
D
0.38
0.51
0.015
0.020
F
1.02
1.77
0.040
0.070
G
2.54 BSC
0.100 BSC
H
2.03
0.080
J
0.20
0.38
0.008
0.015
K
3.18
5.08
0.125
0.200
L
7.37
7.87
0.290
0.310
M
15°
15°
Note: Dimensions do not include protrusions; these shall
B
18
L
C
F
K
Seating Plane
H
J
M
D
G
INCHES
MIN
MAX
not exceed 0.155mm (0.006″) on any side. Lead
dimension shall not include solder coverage.
Figure 26 · J 18-Pin CERDIP Package Dimensions
E3
D
Dim
D/E
E3
E
e
B1
A
A1
L2
8.64
9.14
0.340
0.360
-
8.128
-
0.320
1.270 BSC
0.635 TYP
0.025 TYP
1.52
0.040
0.060
A
1.626
2.286
0.064
0.090
1.016 TYP
1.372
1.68
A2
-
L2
1.91
B3
0.040 TYP
0.054
0.066
1.168
-
0.046
2.41
0.075
0.95
0.203R
0.008R
Note: All exposed metalized area shall be gold plated
1
60 µ-inch minimum thickness over nickel plated
unless otherwise specified in purchase order.
13
h
A2
0.050 BSC
1.02
A1
3
INCHES
MIN
MAX
L
h
L
8
MILLIMETERS
MIN
MAX
18
B1
e
B3
Figure 27 · L 20-Pin Ceramic LCC Package Dimensions
10
PACKAGE OUTLINE DIMENSIONS (continued)
D
18
10
H
E
9
1
e
L
B
A2
A
c
S e a tin g Pla n e
DIM
MILLIMETERS
MIN
MAX
INCHES
MIN
MAX
A
A1
A2
B
c
D
E
e
H
L
θ
*LC
2.35
2.65
0.10
0.30
2.20
2.55
0.33
0.51
0.23
0.32
11.40
11.70
7.40
7.60
1.27 BSC
10.00
10.65
0.40
1.27
0°
8°
0.10
0.093
0.104
0.004
0.012
0.086
0.100
0.013
0.020
0.009
0.013
0.449
0.461
0.291
0.299
0.05 BSC
0.394
0.419
0.016
0.050
0°
8°
0.004
* Lead Coplanarity
A1
Note: Dimensions do not include mold flash or
protrusions; these shall not exceed 0.155mm (0.006″)
on any side. Lead dimension shall not include solder
coverage.
Figure 28 · DW 18-Pin Plastic Wide-body SOIC (SOWB) Package Dimensions
Dim
D
MAX
1
b1
E
A2
A
c
A1
L
SEATING PLANE
INCHES
MIN
5.33
0.38
A2
E1
b
MIN
A
A1
e
MILLIMETERS
3.30 Typ
MAX
0.210
0.015
0.130 Typ
b
0.36
0.56
0.014
0.022
b1
1.14
1.78
0.045
0.070
c
0.20
0.36
0.008
0.014
D
22.35
23.34
0.880
0.920
e
2.54 BSC
0.100 BSC
E
7.62
8.26
0.300
0.325
E1
6.10
7.11
0.240
0.280
L
2.92
3.81
0.115
0.150
M
-
15°
-
15°
M
Note: Dimensions do not include mold flash or protrusions;
these shall not exceed 0.155mm (0.006″) on any side.
Lead dimension shall not include solder coverage.
Figure 29 · N 18-Pin Plastic Dual Inline Package Dimensions
11
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and system solutions for communications, defense & security, aerospace and industrial
markets. Products include high-performance and radiation-hardened analog mixed-signal
integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and
synchronization devices and precise time solutions, setting the world’s standard for time; voice
processing devices; RF solutions; discrete components; security technologies and scalable
anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design
capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has
approximately 3,400 employees globally. Learn more at www.microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo,
CA 92656 USA
Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
E-mail: sales.support@microsemi.com
© 2014 Microsemi Corporation. All
rights reserved. Microsemi and the
Microsemi logo are trademarks of
Microsemi Corporation. All other
trademarks and service marks are the
property of their respective owners.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or
the suitability of its products and services for any particular purpose, nor does Microsemi assume any
liability whatsoever arising out of the application or use of any product or circuit. The products sold
hereunder and any other products sold by Microsemi have been subject to limited testing and should not
be used in conjunction with mission-critical equipment or applications. Any performance specifications are
believed to be reliable but are not verified, and Buyer must conduct and complete all performance and
other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely
on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's
responsibility to independently determine suitability of any products and to test and verify the same. The
information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire
risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or
implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such
information itself or anything described by such information. Information provided in this document is
proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this
document or to any products and services at any time without notice.
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