SG2526

SG1526/SG2526/SG3526 REGULATING PULSE WIDTH MODULATOR DESCRIPTION The SG1526 is a high performance monolithic pulse width modulator circuit designed for fixed-frequency switching regulators and other power control applications. Included in an 18-pin dual-in-line package are a temperature compensated voltage reference, sawtooth oscillator, error amplifier, pulse width modulator, pulse metering and steering logic, and two low impedance power drivers. Also included are protective features such as soft-start and undervoltage lockout, digital current limiting, double pulse inhibit, a data latch for single pulse metering, adjustable deadtime, and provision for symmetry correction inputs. For ease of interface, all digital control ports are TTL and B-series CMOS compatible. Active LOW logic design allows wired-OR connections for maximum flexibility. This versatile device can be used to implement single-ended or push-pull switching regulators of either polarity, both transformerless and transformer coupled. The SG1526 is characterized for operation over the full military ambient junction temperature range of -55°C to +150°C. The SG2526 is characterized for operation from -25°C to +150°C, and the SG3526 is characterized for operation from 0°C to +125°C. FEATURES • • • • • • • • • • • • • • 8 to 35 volt operation 5V reference trimmed to ±1% 1Hz to 350KHz oscillator range Dual 100mA source/sink outputs Digital current limiting Double pulse suppression Programmable deadtime Undervoltage lockout Single pulse metering Programmable soft-start Wide current limit common mode range TTL/CMOS compatible logic ports Symmetry correction capability Guaranteed 6 unit synchronization HIGH RELIABILITY FEATURES - SG1526 ♦ Available to MIL-STD-883B and DESC SMD ♦ Radiation data available ♦ LMI level "S"processing available BLOCK DIAGRAM VREF +VIN GROUND RD RT CT Reference Regulator Undervoltage Lockout SYNC +VC To Internal Circuitry Oscillator OUTPUT A RESET CSOFTSTART COMPENSATION + ERROR Soft Start +VIN S Amp D Q METERING F/F Q S T R Q Q Q TOGGLE F/F OUTPUT B MEMORY F/F — ERROR + C.S. — C.S. SHUTDOWN Rev 1.1a 3.19.2005 Copyright © 1994 1 11861 Western Avenue ∞ Garden Grove, CA 92841 (714) 898-8121 ∞ FAX: (714) 893-2570 Microsemi Inc. SG1526/SG2526/SG3526 ABSOLUTE MAXIMUM RATINGS (Note 1) Input Voltage (VIN ) ............................................................... 40V Collector Supply Voltage (VC) ............................................. 40V Logic Inputs ......................................................... -0.3V to 5.5V Analog Inputs .......................................................... -0.3V to V IN Source/Sink Load Current (each output) ....................... 200mA Reference Load Current .................................................. 50mA Note 1. Exceeding these ratings could cause damage to the device. Logic Sink Current ............................................................ 15mA Operating Junction Temperature Hermetic (J, L Packages) ............................................ 150°C Plastic (N, DW Packages) ........................................... 150°C Storage Temperature Range ............................ -65°C to 150°C Lead Temperature (Soldering, 10 Seconds) ................... 300°C RoHS Peak Package Solder Reflow Temp. (40 sec. max. exp.)...... 260°C (+0, -5) THERMAL DATA J Package: Thermal Resistance-Junction to Case, θ JC .................. 25°C/W Thermal Resistance-Junction to Ambient, θ JA .............. 70°C/W N Package: Thermal Resistance-Junction to Case, θ JC .................. 30°C/W Thermal Resistance-Junction to Ambient, θ JA ............. 60°C/W DW Package: Thermal Resistance-Junction to Case, θ JC .................. 35°C/W Thermal Resistance-Junction to Ambient, θ JA ............. 90°C/W L Package: Thermal Resistance-Junction to Case, θ JC ................... 35°C/W Thermal Resistance-Junction to Ambient, θ JA ........... 120°C/W Note A. Junction Temperature Calculation: TJ = TA + (PD x θJA). Note B. The above numbers for θ JC are maximums for the limiting thermal resistance of the package in a standard mounting configuration. The θ JA numbers are meant to be guidelines for the thermal performance of the device/pcboard system. All of the above assume no ambient airflow. RECOMMENDED OPERATING CONDITIONS (Note 2) Input Voltage ............................................................. 8V to 35V Collector Supply Voltage ........................................ 4.5V to 35V Sink/Source Load Current (each output) ................ 0 to 100mA Reference Load Current ........................................... 0 to 20mA Oscillator Frequency Range .............................. 1Hz to 350KHz Oscillator Timing Resistor .................................. 2KΩ to 150KΩ Note 2. Range over which the device is functional. Oscillator Timing Capacitor .................................... 1nF to 20 µF Available Deadtime Range at 40KHz ...................... 3% to 50% Operating Ambient Temperature Range: SG1526 ......................................................... -55°C to 125°C SG2526 ........................................................... -25°C to 85°C SG3526 ............................................................... 0°C to 70 °C ELECTRICAL CHARACTERISTICS (Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG1526 with -55° C ≤ T A ≤ 125 °C, SG2526 with -25° C ≤ TA ≤ 85°C, SG3526 with 0° C ≤ TA ≤ 70°C, and VIN = 15V. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.) Parameter Reference Section (Note 3) Output Voltage Line Regulation Load Regulation Temperature Stability (Note 9) Total Output Voltage Range (Note 9) Short Circuit Current Undervoltage Lockout Section RESET Output Voltage RESET Output Voltage Test Conditions TJ = 25°C VIN = 8 to 35V IL = 0 to 20mA Over Operating TJ Over Recommended Operating Conditions VREF = 0V VREF = 3.8V VREF = 4.8V SG1526/2526 SG3526 Units Min. Typ. Max. Min. Typ. Max. 4.95 5.00 5.05 4.90 5.00 5.10 10 30 10 30 30 10 50 10 15 50 15 50 4.90 5.00 5.10 4.85 5.00 5.15 50 125 50 125 0.2 4.8 0.4 2.4 0.2 4.8 0.4 V mV mV mV V mA V V 2.4 Rev 1.1a Copyright © 1994 2 11861 Western Avenue ∞ Garden Grove, CA 92841 (714) 898-8121 ∞ FAX: (714) 893-2570 SG1526/SG2526/SG3526 ELECTRICAL CHARACTERISTICS Parameter Oscillator Section (Note 4) Initial Accuracy Voltage Stability Temperature Stability (Note 9) Minimum Frequency (Note 9) Maximum Frequency Sawtooth Peak Voltage Sawtooth Valley Voltage Error Amplifier Section (Note 5) Input Offset Voltage Input Bias Current Input Offset Current DC Open Loop Gain High Output Voltage Low Output Voltage Common Mode Rejection Supply Voltage Rejection PWM Comparator Section (Note 4) Minimum Duty Cycle Maximum Duty Cycle (continued) Test Conditions TJ = 25°C VIN = 8 to 35V Over Operating TJ RT = 150KΩ, CT = 20µF RT = 2KΩ, CT = 1.0nF VIN = 35V VIN = 8V RS ≤ 2KΩ RL ≥ 10MΩ, TJ = 25°C VPIN1 - VPIN2 ≥ 150mV, ISOURCE = 100µ A VPIN2 - VPIN1 ≥ 150mV, ISINK = 100µ A RS ≤ 2KΩ VIN = 8V to 35V VCOMPENSATION = 0.4V VCOMPENSATION = 3.6V SG1526/2526 SG3526 Units Min. Typ. Max. Min. Typ. Max. ±3 0.5 7 350 0.5 3.0 1.0 3.5 0.5 ±8 1.0 10 1.0 350 3.0 1.0 3.5 ±3 0.5 5 ±8 1.0 10 1.0 % % % Hz KHz V V mV nA nA dB V V dB dB % % V V µA µA mV µA V µA V V V V µA µs µs mA 64 3.6 70 66 2 5 -350 -1000 35 100 72 60 4.2 3.6 0.2 0.4 94 70 80 66 0 10 2 -350 -2000 35 200 72 4.2 0.2 0.4 94 80 0 45 2.4 49 4 0.2 0.4 -125 -300 -225 -500 100 -3 0.1 100 110 -10 0.4 200 45 2.4 49 4 0.2 0.4 -125 -300 -225 -500 100 -3 0.1 100 120 -10 0.4 200 Digital Ports (SYNC, SHUTDOWN, and RESET) HIGH Output Voltage ISOURCE = 40 µA LOW Output Voltage ISINK = 3.6mA VIH = 2.4V HIGH Input Current VIL = 0.4V LOW Input Current Current Limit Comparator Section (Note 6) RS ≤ 50Ω, TJ = 25°C Sense Voltage Input Bias Current Soft-Start Section Error Clamp Voltage RESET = 0.4V CS Charging Current RESET = 2.4V Output Drivers (each output) (Note 7) HIGH Output Voltage ISOURCE = 20mA ISOURCE = 100mA LOW Output Voltage ISINK = 20mA ISINK = 100mA Collector Leakage VC = 40V Rise Time CL = 1000pF CL = 1000pF Fall Time Power Consumption Section (Note 8) Standby Current SHUTDOWN = 0.4V Note 3. Note 4. Note 5. Note 6. IL = 0mA FOSC = 40KHz (RT = 4.12KΩ ±1%, CT = .01µ F ±1%, RD = 0Ω) VCM = 0 to 5.2V VCM = 0 to 12V 90 80 50 50 12.5 13.5 12.5 13.5 12 13 12 13 0.2 0.3 0.2 0.3 2 1.2 2 1.2 50 150 50 150 0.3 0.6 0.3 0.6 0.1 0.2 0.1 0.2 18 30 18 30 Note 7. VC = 15V Note 8. VIN = 35V Note 9. These parameters, although guaranteed over the recommended operating conditions, are not tested in production. Rev 1.1a Copyright © 1994 3 11861 Western Avenue ∞ Garden Grove, CA 92841 (714) 898-8121 ∞ FAX: (714) 893-2570 SG1526/SG2526/SG3526 CHARACTERISTIC CURVES FIGURE 1. REFERENCE VOLTAGE VS. SUPPLY VOLTAGE FIGURE 2. REFERENCE TEMPERATURE STABILITY FIGURE 3. REFERENCE SHORT CIRCUIT CURRENT FIGURE 4. REFERENCE RIPPLE REJECTION FIGURE 5. OSCILLATOR FREQUENCY TEMPERATURE STABILITY FIGURE 6. OUTPUT DRIVER DEADTIME VS. RD VALUE FIGURE 7. OSCILLATOR PERIOD VS. RT AND CT Rev 1.1a Copyright © 1994 4 11861 Western Avenue ∞ Garden Grove, CA 92841 (714) 898-8121 ∞ FAX: (714) 893-2570 SG1526/SG2526/SG3526 CHARACTERISTIC CURVES (continued) FIGURE 8. UNDERVOLTAGE LOCKOUT CHARACTERISTIC FIGURE 9. ERROR AMPLIFIER OPEN LOOP GAIN VS. FREQUENCY FIGURE 10. SOFTSTART TIME CONSTANT VS. CS FIGURE 11. CURRENT LIMIT TRANSFER FUNCTION FIGURE 12. COMPARATOR INPUT TO DRIVER OUTPUT DELAY FIGURE 13. SHUTDOWN INPUT TO DRIVER OUTPUT DELAY FIGURE 14. OUTPUT DRIVER SATURATION VOLTAGE VS. ISINK FIGURE 15. OUTPUT SUPPLY SATURATION VOLTAGE VS. ISINK FIGURE 16. STANDBY CURRENT VS. SUPPLY VOLTAGE Rev 1.1a Copyright © 1994 5 11861 Western Avenue ∞ Garden Grove, CA 92841 (714) 898-8121 ∞ FAX: (714) 893-2570 SG1526/SG2526/SG3526 APPLICATION INFORMATION VOLTAGE REFERENCE The reference regulator of the SG1526 is based on a temperature compensated zener diode. The circuitry is fully active at supply voltages above +8 volts., and provides up to 20mA of load current to external circuitry at +5.0 volts. In systems where additional current is required, an external PNP transistor can be used to boost the available current. A rugged low frequency audio-type transistor should be used, and lead lengths between the PWM and transistor should be as short as possible to minimize the risk of oscillations. Even so, some types of transistors may require collector-base capacitance for stability. Up to 1amp of load current can be obtained with excellent regulation if the device selected maintains high current gain. UNDERVOLTAGE LOCKOUT The undervoltage lockout circuit protects the SG1526 and the power devices it controls from inadequate supply voltage. If +VIN is too low, the circuit disables the output drivers and holds the RESET pin LOW. This prevents spurious output pulses while the control circuitry is stabilizing, and holds the soft-start timing capacitor in a discharged state. The circuit consists of a +1.2 volt bandgap reference and comparator circuit which is active when the reference voltage has risen to 3VBE’or 1.8 volts at 25°C. When the reference voltage rises to approximately +4.4 volts, the circuit enables the output drivers and releases the RESET pin, allowing a normal soft-start. The comparator has 200mV of hysteresis to minimize oscillation at the trip point. When +VIN to the PWM is removed and the reference drops to +4.2 volts, the undervoltage circuit pulls RESET LOW again. The soft-start capacitor is immediately discharged, and the PWM is ready for another soft-start cycle. The SG1526 can operate from a +5 volt supply by connecting the VREF pin to the +VIN pin and maintaining the supply between +4.8 and +5.2 volts. SOFT-START CIRCUIT The soft-start circuit protects the power transistors and rectifier diodes from high current surges during power supply turn-on. When supply voltage is first applied to the SG1526, the undervoltage lockout circuit holds RESET LOW with Q3. Q1 is turned on, which holds the soft-start capacitor voltage at zero. The second collector of Q1 clamps the output error amplifier to ground, guaranteeing zero duty cycle at the driver outputs. When the supply voltage reaches normal operating range, RESET will go HIGH. Q1 turns off, allowing the internal 100µA current source to charge CS. Q2 clamps the error amplifier output to 1VBE above the voltage on CS. As the soft-start voltage ramps up to +5 volts, the duty cycle of the PWM linearly increases to whatever value the voltage regulation loop requires for an error null. Figure 10 gives the timing relationship between CS and ramp time to 100% duty cycle. DIGITAL CONTROL PORTS The three digital control ports of the SG1526 are bi-directional. Each pin can drive TTL and 5 volt CMOS logic directly, up to a fan-out of 10 low-power Schottky gates. Each pin can also be directly driven by open-collector voltage comparators; fanin is equivalent to 1 low-power Schottky gate. Each port is normally HIGH; the pin is pulled LOW to activate the particular function. Driving SYNC LOW initiates a discharge cycle in the oscillator. Pulling SHUTDOWN LOW immediately inhibits all PWM output pulses. Holding RESET LOW discharges the soft-start capacitor. The logic threshold is +1.1 volts at 25°C. Noise immunity can be gained at the expense of fan-out with an external 2K pullup resistor to +5 volts. FIGURE 20. DIGITAL CONTROL PORT SCHEMATIC FIGURE 18. SIMPLIFIED UNDERVOLTAGE LOCKOUT FIGURE 17. EXTENDING REFERENCE OUTPUT CURRENT FIGURE 19. SOFT-START CIRCUIT SCHEMATIC Rev 1.1a Copyright © 1994 6 11861 Western Avenue ∞ Garden Grove, CA 92841 (714) 898-8121 ∞ FAX: (714) 893-2570 SG1526/SG2526/SG3526 APPLICATION INFORMATION OSCILLATOR (continued) FIGURE 21 - OSCILLATOR CONNECTIONS AND WAVEFORMS The oscillator is programmed for frequency and deadtime with three components: RT, CT, and RD. Two waveforms are generated: a sawtooth waveform at pin 10 for pulse width modulation, and a logic clock at pin 12. The following procedure is recommended for choosing timing values: 1. With RD = 0Ω (pin 11 shorted to ground) select values for RT and CT from Figure 7 to give the desired oscillator period. Remember that the frequency at each driver output is half the oscillator frequency, and the frequency at the +VC terminal is the same as the oscillator frequency. 2. If more dead time is required, select a larger value of RD using Figure 6 as a guide. At 40kHz dead time increases by 400nSec/ohm. 3. Increasing the dead time will cause the oscillator frequency to decrease slightly. Go back and decrease the value of RT slightly to bring the frequency back to the nominal design value. The SG1526 can be synchronized to an external logic clock by programming the oscillator to free-run at a frequency 10% slower than the sync frequency. A periodic LOW logic pulse approximately 0.5µSec wide at the SYNC pin will then lock the oscillator to the external frequency. Multiple devices can be synchronized together by programming one master unit for the desired frequency, and then sharing its sawtooth and clock waveforms with the slave units. All CT terminals are connected to the CT pin of the master, and all SYNC terminals are likewise connected to the SYNC pin of the master. Slave RT terminals should not be left open nor should they be tied to the +5V reference; at least 50K should be connected to each pin. Slave RD terminals may be either left open or grounded. ERROR AMPLIFIER FIGURE 22A ERROR AMPLIFIER CONNECTIONS FIGURE 22B The error amplifier is a transconductance design, with an output impedance of 2 megohms and an effective output capacitance of 100 pF. Since all voltage gain takes place at the output pin, the open-loop gain can be shaped with shunt reactance to ground. For unity gain stability the amplifier requires an additional external 100 pF to ground, resulting in an open-loop pole at 400 Hz. The input connections to the error amplifier are determined by the polarity of the switching supply output voltage. For positive supplies, the common-mode voltage is +5.0 volts and the feedback connections in Figure 22A are used. With negative supplies, the common-mode voltage is ground and the feedback divider is connected between the negative output and the +5.0 volt reference voltage, as shown in Figure 22B. Rev 1.1a Copyright © 1994 7 11861 Western Avenue ∞ Garden Grove, CA 92841 (714) 898-8121 ∞ FAX: (714) 893-2570 SG1526/SG2526/SG3526 APPLICATION INFORMATION OUTPUT DRIVERS The totem-pole output drivers of the SG1526 are designed to source and sink 100mA continuously and 200mA peak. Loads can be driven either from the output pins 13 and 16, or from the +VC pin, as required. Curves for the saturation voltage at these outputs as a function of load current are found in Figures 14 and 15. Since the bottom transistor of the totem-pole is allowed to saturate, there is a momentary conduction path from the +VC terminal to ground during switching. To limit the resulting current spikes a small resistor in series with pin 14 is always recommended. The resistor value is determined by the driver supply voltage, and should be chosen for 200mA peak currents, as shown in Figure 25. (continued) FIGURE 23. PUSH-PULL CONFIGURATION FIGURE 24. SINGLE-ENDED CONFIGURATION FIGURE 25. DRIVING N-CHANNEL POWER MOSFETS SG1526 LAB TEST FIXTURE Rev 1.1a Copyright © 1994 8 11861 Western Avenue ∞ Garden Grove, CA 92841 (714) 898-8121 ∞ FAX: (714) 893-2570 SG1526/SG2526/SG3526 CONNECTION DIAGRAMS & ORDERING INFORMATION Package 18-PIN CERAMIC DIP J - PACKAGE (See Notes Below) Part No. SG1526J/883B SG1526J SG2526J SG3526J SG2526N SG3526N Ambient Temperature Range -55°C to 125 °C -55°C to 125 °C -25°C to 85 °C 0°C to 70° C -25°C to 85 °C 0°C to 70° C -25°C to 85 °C 0°C to 70° C Connection Diagram +ERROR - ERROR COMPENSATION CSOFTSTART RESET - CURRENT SENSE +CURRENT SENSE SHUTDOWN RT 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VREF +VIN OUTPUT B GROUND VCOLLECTOR OUTPUT A SYNC RDEADTIME CT 18-PIN PLASTIC DIP N - PACKAGE N Package: RoHS Compliant / Pb-free Transition DC: 0503 N Package: RoHS / Pb-free 100% Matte Tin Lead Finish 18-PIN WIDE BODY PLASTIC S.O.I.C. DW - PACKAGE SG2526DW SG3526DW +ERROR -ERROR COMPENSATION CSOFTSTART RESET - CURRENT SENSE +CURRENT SENSE SHUTDOWN RT 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VREF +VIN OUTPUT B GROUND +VCOLLECTOR OUTPUT A SYNC RDEADTIME CT DW Package: RoHS Compliant / Pb-free Transition DC: 0516 DW Package: RoHS / Pb-free 100% Matte Tin Lead Finish 20-PIN CERAMIC LEADLESS CHIP CARRIER L- PACKAGE SG1526L/883B SG1526L -55°C to 125° C -55°C to 125° C 1. N.C. 2. +ERROR 3. -ERROR 4. COMP 5. CSOFTSTART 6. RESET 7. -C.S. 8. +C.S. 9. SHUTDOWN 10.RT 3 2 1 20 19 4 5 6 7 8 18 17 16 15 14 9 10 11 12 13 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. CT RDEADTIME SYNC OUTPUT A +VCOLLECTOR N.C. GROUND OUTPUT B +VIN VREF Note 1. Contact factory for JAN and DESC product availability. 2. All parts are viewed from the top. Rev 1.1a Copyright © 1994 9 11861 Western Avenue ∞ Garden Grove, CA 92841 (714) 898-8121 ∞ FAX: (714) 893-2570