MT9085

® CMOS MT9085 PAC - Parallel Access Circuit Features • Configurable for parallel-to-serial or serial-to-parallel conversion of 1024 channels Interfaces to Mitel’s MT9080 Switch Matrix Module (SMX). Generates all framing signals required in 1K or 2K switching applications Serial data rates of 2.048 Mbit/s or 4.096 Mbit/s Mitel ST-BUS ™ c ompatible serial inputs/outputs ISSUE 3 January 1993 Ordering Information MT9085AP 68 Pin PLCC • -40°C to 70°C • • Description The MT9085 Parallel Access Circuit (PAC) provides an interface between an 8 bit, parallel time division multiplexed bus and a serial time division multiplexed bus. A single PAC device will accept data clocked out on the parallel bus of the Mitel MT9080 (SMX) and output it on 32/16 time division multiplexed serial bus streams. A second device can be configured to perform the conversion from the serial format into an SMX compatible parallel format. The time division, serial multiplexed streams may operate at 2.048 Mbit/s or at 4.096 Mbit/s. The PAC generates all framing signals required by the SMX for 1024 and 2048 channel configurations. Applications • Interfacing the MT9080 Switch Matrix Module to an ST-BUS system Rate conversion between 4 Mbit/s and 2 Mbit/s serial streams Interfacing a parallel system bus to devices utilizing serial I/O • • S0 S1 • • • • • • • • • • • • • • S30 S31 • • Shift Registers Address Decoder C16 C4 LOAD C16 C4 Parallel/Serial P0 P7 C4i F0i C16i Timing Generation C2o C4o F0o DFPo DFPo CFPo OE MCA MCB CKD 2/4S Mode Control VSS VDD Figure 1 - Functional Block Diagram 2-125 MT9085 CMOS 68 67 66 65 64 63 62 VSS S8 S9 S10 S11 S12 S13 VDD VSS S14 S15 S16 S17 S18 S19 S20 S21 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 8 7 6 5 4 3 2 1 S7 S6 S5 S4 S3 S2 S1 S0 VSS VDD P7 P6 P5 P4 P3 P2 P1 P0 MCB VSS NC C2o C4o DFPo VDD VSS C16i F0i F0o DFPo CFPo IC IC MCA 2-126 VSS S22 S23 S24 S25 S26 S27 VSS VDD S28 S29 S30 S31 CKD C4i OE 2/4S Figure 2 - Pin Connections CMOS Pin Description Pin # 1 2-9 Name VSS S0-S7 Ground. Description MT9085 Serial Input/Outputs (TTL compatible with internal pullups). Time division, multiplexed serial bus streams; inputs in serial to parallel mode (MCA=0), and outputs in parallel to serial mode (MCA=1). Data rate on the serial streams can be selected to be 2.048 Mbit/s (2/4S=0) or 4.096 Mbit/s (2/4S=1). Refer to Figures 3, 4 and 5 for functional timing information. Ground. 10 11-16 17 18 VSS VDD VSS S8-S13 Serial Input/Outputs. See description for pins 2 - 9 above. Supply Input. +5V. Ground. 19-20 S14-S15 Serial Input/Outputs. See description for pins 2 - 9 above. 21-26 S16-S21 Serial Input/Outputs (TTL compatible with internal pullups). Time division, multiplexed serial bus streams which are configured as inputs in serial to parallel mode (MCA =0), and outputs in parallel to serial mode (MCA=1). Data is clocked at 2.048 Mbit/s (2/4S = 0). These input/ outputs are inactive when the device is configured for 4.096 Mbit/s operation (2/4S=1). 27 VSS VSS VDD CKD Ground. 28-33 S22-S27 Serial Input/Outputs. See description for pins 21-26 above. 34 35 Ground. Supply Input +5V. 36-39 S28-S31 Serial Input/Outputs. See description for pins 21-26 above. 40 Clock Delay (Input). Control input which configures internal device timing. CKD=0 Internal master counter is reset at the system frame boundary established by the frame pulse (F0i). CKD=1 Internal master counter is reset one C16 clock period after system frame boundary. All data input/output will be delayed by one C16 clock period. Timing for data input/output and for OE is affected by the level asserted on CKD. The relative phase between the frame boundary established by F0i and output signals F0o, C2o, C4o, DFPo, DFPo and CFPo is also affected by the state of the CKD input. See descriptions pertaining to each specific pin for more information. 4.096MHz Clock Input. The 4.096 MHz clock signal must be phase locked to the 16.384 MHz. clock. The falling edge of C4i is used to clock in the frame pulse (F0i). Output Enable (Input). When low, output data bus (serial or parallel) is actively driven. When set high, the output bus drivers are disabled. In serial to parallel mode, the outputs are disabled immediately after OE is taken High. See Figures 6 and 21 for timing information pertaining to parallel to serial mode. 2.048/4.096 Mbit/s Select (Input). Selects the data rate for the time division, multiplexed serial streams. When tied low, the data rate is 2.048 Mbit/s. When tied high, the data rate is 4.096 Mbit/s. Mode Control-A (Input). The device will perform a serial to parallel conversion when this input is tied low. When the input is tied high, the device operates in the parallel to serial mode. Internal Connection. Must be tied to VSS for normal device operation. Internal Connection. Should be left unconnected. Connect Memory Frame Pulse (Output). Framing signal with a nominal 8 kHz frequency; goes low 71 (CKD=0) or 68 (CKD=1) C16 clock cycles before the frame boundary established by F0i. The signal is used by the connection memory in a typical 1k or 2k switch configuration. See Figure 15 for timing information. 2-127 41 42 C4i OE 43 2/4S 44 45 46 47 MCA IC IC CFPo MT9085 CMOS Pin Description (continued) Pin # 48 Name DFPo Description Data Memory Frame Pulse (Output). Framing signal with nominal 4 kHz frequency; changes state 64 (CKD=0) or 65 (CKD=1) C16 clock cycles after the frame boundary established by F0i. This signal is a complement of DFPo. See Figure 15 for timing information. The signal is used by SMXs (MT9080s) making up the Data Memory in a typical 1k or 2k switch configuration. Framing Type 0 Signal (Output). 8 kHz framing signal output by the PAC to indicate the frame boundary synchronized to C16. This framing signal is aligned with C4o and is output by the PAC for use by other devices in a typical switch configuration. Refer to Figures 4 and 5 for functional timing information. Framing Type 0 Signal (TTL compatible input). This input signal establishes the frame boundary for the serial input/output streams. The first falling edge of C4i following the falling edge of F0i establishes the frame boundaries. Refer to Figure 13 for timing information. 16 MHz Clock Input. The 16.384 MHz clock signal input at this pin must be phase-locked to the 4.096 MHz clock input at C4i. See Figure 13 for timing information. Ground. Supply Input. +5V. Data Memory Frame Pulse (Output). 4 kHz framing signal; changes state 64 (CKD=0) or 65 (CKD=1) C16 clock cycles after the frame boundary established by F0i. This signal is a complement of DFPo. See Figure 15. The signal is used by SMXs (MT9080s) making up the Data Memory in a typical 2k switch configuration. 4.096 MHz Clock Output. This is a 4.096 MHz clock signal derived from the 16 MHz master clock input at C16. The falling edge of C4o occurs in the middle of the regenerated frame pulse output at F0o. Refer to Figures 4 and 5 for functional timing information. 2.048 MHz Clock Output. This is a 2.048 MHz clock signal derived from the 16 MHz master clock input. The rising edge of this clock signal occurs in the middle of the regenerated frame pulse output at F0o. Refer to Figures 4 and 5 for functional timing information. No Connection. Ground. Mode Control-B (Input). This control input performs two different functions, depending on the state of MCA pin. In parallel to serial mode (MCA=1), MCB defines which clock edge latches in the data. MCB=0 Data on the parallel bus is latched into the device with the every second falling edge of C16. See Figure 6. MCB=1 Data on the parallel bus is latched into the device with every alternate positive clock edge. In serial to parallel mode (MCA=0), the MCB pin controls the state of the parallel bus driver as follows: MCB=0 The output drivers are enabled for only half the timeslot. The data is clocked out on the first falling edge within the timeslot and disabled on the next falling edge. See Figure 7. MCB=1 The parallel data bus output drivers are enabled for the duration of the channel timeslot (two C16 Clock Periods). The data is clocked out on the first positive edge within a timeslot and disabled on the last edge. Parallel Input/Output Data Bus. This 8 bit data bus is an output in serial to parallel mode (MCA=0), and an input in parallel to serial mode (MCA=1). Data is clocked in and out of the port by the C16 clock. The state of the CKD pin determines the relative phase of the critical clock edges with respect to the frame pulse. All inputs/outputs have internal pullups. Refer to Figures 6 and 7 for functional timing information. Supply. +5V. 49 F0o 50 F0i 51 52 53 54 C16i VSS VDD DFPo 55 C4o 56 C2o 57 58 59 NC VSS MCB 60-67 P0-P7 68 VDD 2-128 CMOS MT9085 512 C4 Cycles C4 F0 S0-S31 2/4S = 0 S0-S15 2/4S = 1 0 0 1 31 0 1 2 3 63 0 Figure 3 - Serial Input/Output Functional Timing Frame Boundary Established by F0i C16i C4o C2o F0o Serial I/O 2 Mbit/s Serial I/O 4 Mbit/S Ch. 31 Bit 1 Ch. 31 Bit 0 Ch. 0 Bit 7 Ch. 0 Bit 6 Ch. 63 Bit 2 Ch. 63 Bit 1 Ch. 63 Bit 0 Ch. 0 Bit 7 Ch. 0 Bit 6 Ch. 0 Bit 5 Figure 4 - Channel and Frame Alignment (CKD = 0) Frame Boundary Established by F0i C16i C4o C2o F0o Serial I/O 2 Mbit/s Serial I/O 4 Mbit/S Ch. 31 Bit 1 Ch. 31 Bit 0 Ch. 0 Bit 7 Ch. 0 Bit 6 Ch. 63 Bit 2 Ch. 63 Bit 1 Ch. 63 Bit 0 Ch. 0 Bit 7 Ch. 0 Bit 6 Ch. 0 Bit 5 Figure 5 - Channel and Frame Alignment (CKD = 1) 2-129 MT9085 CMOS Frame Boundary established by F0i 64 Cycles C16i CKD=0 Serial Output S0-S31 Ch. 31, Bit 0 Ch. 0, Bit 7 Ch. 1, Bit 7 AAAAAAAAAAA AAAAAAAAAAA A AAAAAAA C2S0 AAAAAAAAAAA C2S1 AAAAAAAAAAA AAA AAAAAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA Parallel AAA AAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA Input AAAC0S31AAAAAAAAAAA C1S0 AAAAAAAAAAA C1S1 AAAAAAAAAAA C1S2 AAAAAAAAAAA C1S3 AAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA MCB=0 AAA OE Parallel Input MCB=1 OE C1S1 C1S2 C1S3 C1S4 C2S1 AAAAAAAAAAA AAAAAAAAAAA C2S0 AAAAAAAAAAA C 2 AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAA AAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAA AAAAAA AAAAAAC S AAAAAAAAAAAA C S AAAAAAAAAAA C S AAAAAAAAAAA C S AAAAAAAAAAAAC S AAAA AAAA AAAA AAA AAAA AAA AAAA AAAA AAAAAA 0 31 AAAAAAAAAAA 1 0 AAAAAAAAAAA 1 1 AAAAAAAAAAA 1 2AAAAAAAAAAAA 1 3 A AAAA AAAA AAAA AAAAAA AAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAA AAAAAA AAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAA AAAA C1S1 C1S2 C1S3 C1S4 C 2S1 CKD=1 Serial Output S0-S31 Parallel Input MCB=0 Ch. 31, Bit 0 Ch. 0, Bit 7 AAAAAAAAAAA AAAAAAA AAAAAAAAAAA AAAAAAAAAAAC1S3 AAAAAAA AAAAAAA AAAAAAAAAAA AAAAAAA AAAAAAAAAAA AAAAAAA Ch. 1, Bit 7 AAAAAAAA AAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAA AAAAAAAA C2S 0AAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAC0S31 AAAAAAAAAAA C1S0AAAAAAAAAAA C1S1 AAAAAAAAAAA C1S2 AAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA OE Parallel Input MCB=1 C1S1 C1S2 C1S3 C1S4 AAAAAAAAAAA AAAAAAA AAAAAAAAAAA AAAAAAAAAAA C S AAAAAAA AAAAAAA AAAAAAAAAAA AAAAAAA AAAAAAAAAAA 1 3 AAAAAAA AAAAAAAAAAA AAAAAAA C2S1 AAAA AAAAAAAA AAAA AAAA C S AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA 2 0 AAAAAAAA AAAA AAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAAAA C S AAAAAAAAAAA C S AAAAAAAAAAAA C S AAAAAAAAAAA C S AAAAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAA AAA AAAAAAAAAAAAAA 0 31 AAAAAAAAAAA 1 0AAAAAAAAAAAA 1 1 AAAAAAAAAAA 1 2 AAAAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAA AAAAAAAA C1S1 OE C1 S 2 C1S3 C1S4 C2S1 Notes: C XSY - on the parallel inputs indicates data closed in with the edge shown will be clocked out on Serial Stream Y, Channel X. Arrows in the row marked OE indicate the clock edge which latches in the state of the OE pin. CXSY written below the arrow indicates the serial output channel affected by the OE signal. For example, the level on OE clocked in with edge marked C1S1 will enable or disable the serial output drivers for stream 1 during channel 1. Figure 6 - Functional Data I/O Timing in Parallel to Serial Mode (MCA = 1) 2-130 CMOS MT9085 Frame Boundary established by F0i C16 Serial Input S0-S31 Parallel Output MCB=0 CKD=0 Ch.31 Bit 0 AAAA AAA AAA AAAA AAAA AAA AAAAAA AAA AAAA AAAA AAA A AAA AAAAAA AAAA A AAA AAAAAA AAAA A AAAA A AAA AAAAAA AAA AAAAAA AAAA A AAA AAA AAAA A AAA AAAAAAA AAAA A AAA AAAAAAA A AAA AAAAAAA AAAA A AAA AAAAAAA AAAA AAA AAAAAAA AAAAAAAAA AAAA A AAA AAAAAAA A AAA AAAA AAA AAA AAA Ch. 0, Bit 7 Ch.0 Bit 6 AAA AAAAAAAAAAA A AAAAAAAAAAA A AAA AAA AAAAAAAAAAA A AAA AAAAAAAAAAA A AAA AAAAAAAAAAA A AAAAAAAAAAA A AAA AAA AAAAAAAAAAA A AAA AAA AAAA A AAA AAAAAAA AAAA AAA AAAAA A AAA AAAAAAA AAAA AAA AAA AAAAA AAAA AAA AAA AAAAA AAAA AAA AAAA AAA AAAAA A AAA AAAAAAA AAAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA C31S0 C31S1 AAAAAAAAAAA A AAA AAAAAAAAAAA A AAA A AAA AAAAAAAAAAA A AAA AAAAAAAAAAA A AAA AAAAAAAAAAA AAAAAAAAAAA A AAA A AAA AAAAAAAAAAA AAA AAA C31S2 C31S3 Parallel AAAA AAAA AAAA Output AAAA AAAA AAAA AAAA AAAA AAAA AAAA MCB=0 AAAA AAAA AAAA CKD=1 AAAA AAAAAAAAAAAAAA AAAAAAAAAA A AA AAA AAAA A AA C30S31 AAAAAAAAAAAAAA A AA AAAAAAAAAAAAAA A AA AAAAAAAAAAAAAA AA AAAAAAAAAAAAAA A AAA AAAAAAAAAAAA AA C31S0 AAAAAAAAAAAAAA AAAA AA A AA AAAAAAAAAAAAAA A AA AAAAAAAAAAAAAA A AA AAA A AAAAAAAA AA AAAAAAAAAAAAAA AA AAAAAAAAAAAA A AAA AAAAAAAAAAAA AAAA C31S1 AAAAAAAAAAAAAA AAAA AA A AA AAAAAAAAAAAAAA A AA AAAAAAAAAAAAAA A AA AAA A AAAAAAAA AA AAAAAAAAAAAAAA AA AAAAAAAAAAAA A AAA AAAAAAAAAAAA AAAA C31S2 AAAAAAAAAAAA AAAA AAAA A AAAAAAAAAAAA A AA AAAAAAAAAAAAAA AAAA A AA AAA AAAA A AAAAAA AAAAAAAAAAAAAA AA AAAAAAAAAAAA A AAA AAAAAAAAAAAA AAAA C31S3 Parallel Output MCB=1 CKD=0 C30S31 C 31S0 C31S1 C31S2 C31S3 Parallel Output MCB=1 CKD=1 C30S31 C31S0 C31S1 C31S2 C31S3 Note: CxSY - indicates data being output is sourced from Serial Stream Y, Channel X Figure 7 - Functional Data I/O Timing in Serial to Parallel Mode (MCA = 0) 2-131 MT9085 CMOS Contiguous channels clocked into the device are output on the serial streams in an interleaved manner on each of the serial outputs. For example when the device is configured for 2.048 Mbit/s data rate, the first 32 parallel channels clocked into the device will be clocked out during channel 0 on serial streams 0 to 31. Channel 1 on serial streams 0 to 31 will contain data from the next 32 timeslots. On any single serial stream, consecutive output channels are sourced from every 32nd parallel input channel (see Figures 6 and 8). When the device is configured for 4.096 Mbit/s serial output operation, contiguous channels on the serial streams are sourced from every 16th parallel input channel. Data on the eight bit parallel bus is clocked into the device with the C16 clock. The level asserted on the MCB input specifies whether the data is clocked into the device on the falling edge or the rising edge of C16. The relative phase of the critical edge with respect to the system frame boundary is defined by the level asserted on the CKD pin as illustrated in Figure 16. The flexibility in input timing permits the PAC to be easily interfaced to the SMX in 1024 and 2048 switching applications. Refer to the applications section of this data sheet for more details. The delay through the PAC is approximately one ST-BUS channel time when the device is operated in 2.048 Mbit/s mode, i.e., any specific channel clocked into the device will be clocked out one ST-BUS channel later. In the 4.096 Mbit/s mode, the delay is equal to eight C4 clock cycles. Serial output channel timeslots can be tri-stated by setting OE high during a specific parallel channel timeslot. The timing for OE is described in Figures 6 and 21. Note that the level asserted on MCB affects the operation of OE. Functional Description The MT9085 Parallel Access Circuit (PAC) is a 68 pin monolithic device. It interfaces a parallel 8 bit, time division, multiplexed bus to 32 or 16 time division multiplexed serial streams. The device can be configured to perform either parallel to serial conversion or serial to parallel conversion. A single PAC device can handle 1024 channels. The data on the parallel bus is in a format suitable for interfacing with the Mitel MT9080 Switch Matrix Module (SMX). The data rate on the serial streams can be selected to be 2.048 or 4.096 Mbit/s. The serial input/output format conforms to the ST-BUS requirements when the data rate is 2.048 Mbit/s (see Figure 3). The ST-BUS is a time-division, multiplexed serial bus with 32, eight bit channels per frame. Frame boundaries are delinated by the frame pulse. Data on the serial streams is clocked in and out with the C16i clock. When the device is configured for 4.096 Mbit/s data rate operation, the first 16 (S0-S15) of the 32 serial streams are used. Each of the 16 time-division multiplexed serial streams is made up of 64 channels. Data is clocked in or out with the C16i clock. P arallel To Serial Conversion The MT9085 can be configured to perform parallel to serial conversion by tying the MCA input high. Data on the eight bit parallel bus (P0-P7) is clocked into the device with the C16i clock. It is clocked out on the serial streams at either 2.048 Mbit/s (2/4S =0) or at 4.096 Mbit/s (2/4S=1). See Figures 16, 17 and 19 for timing information. Parallel to Serial Conversion CH. 2 CH. 1 CH. 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Bit # PAC TS64 TS65 TS32 TS33 TS0 TS1 S0 S1 P0 P1 P2 P3 P4 P5 P6 P7 TS TS 0 1 00 1 2 3 4 5 6 7 1 2 3 4 5 6 7 TS TS TS 31 32 33 000 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 TS TS 63 64 00 1 2 3 4 5 6 7 1 2 4 5 6 7 3 • • • • TS95 • • • • TS63 • • • • TS31 • • • • S31 • • • • • • • • Serial to Parallel Conversion F igure 8 - PAC Operation at 2.048 Mbit/s 2-132 • • • • CMOS Serial to Parallel Conversion The MT9085 can be configured to perform serial to parallel conversion by tying the MCA pin low. A single PAC will accept 1024 channels on the 32 or 16 serial streams and output the data onto the parallel bus as illustrated in Figure 8. The data on the serial input streams can be clocked in at 2.048 Mbit/s or at 4.096 Mbit/s by setting the appropriate level on the 2 /4S pin. See Figures 16 and 17 for timing details. Data is clocked out on the parallel bus with the C16 clock (see Figure 18 for timing details). The parallel output bus will be actively driven for two C16 clock periods when MCB is tied high. Data is output with every second rising clock edge. Setting MCB low will enable the output drivers for only one C16 clock period in any specific parallel channel timeslot. The actual phase relationship between the system frame boundary and the parallel output timeslots is affected by the level asserted on the CKD input (see Figure 7). The flexibility in output timing permits the PAC to be easily interfaced to the SMX in 1024 and 2048 channel configurations. Refer to the applications section of this data sheet for more information. The delay through the PAC is approximately one ST-BUS channel when the device is configured for 2.048 Mbit/s serial rate. In the 4.096 Mbit/s mode, the delay is equal to approximately eight C4 clock cycles. Timing and Framing Signals The PAC requires two clock signals. A 16.384 MHz master clock (C16) is used to clock data in and out of the device on the parallel bus. A 4.096 MHz clock (C4i), phase locked to C16i, clocks in the frame pulse. The positive C16i edge immediately after the C4i falling edge which clocks in F0i defines the internal frame boundary. The two separate clock inputs permit synchronization of the MT9085 to system timing in which the frame pulse is derived from a 4.096 MHz clock. The PAC generates all framing signals necessary to construct a 1024 channel or a 2048 channel switch matrix using the SMX. The DFPo signal is used as a framing signal for the SMXs operated as the Data Memory. The CFPo is used to synchronize Connect Memory timing in a typical 1K or 2K switch application (refer to the application section in this data sheet for more information). The timing of both DFPo and CFPo signals is affected by the level asserted on the CKD input as shown in Figure 15. MT9085 The PAC outputs ST-BUS timing signals, F0o, C2o and C4o derived from C16i. The phase relationship between the frame boundary established by F0i and F0o is illustrated in Figures 4 and 5. Applications 1024 Channel Digital Time-Space Switch A 1024 channel serial time-space digital switch design is illustrated in Figure 9. The main switching function is accomplished using two MT9080s (SMXs). One SMX is operated in the Data Memory mode and the second serves as the Connection Memory. Refer to the SMX data sheet for more information on this configuration. The serial to parallel conversion function is provided by a PAC configured for 2.048 Mbit/s operation (2/4S = 0). The MCB input in this PAC is tied high to ensure data output by the PAC meets SMX input setup and hold requirement. PAC #2 performs the parallel to serial function; MCA is set high. The MCB input in this device is set low to allow data to be clocked in with the falling edge of C16. The main timing source generates a 16.384MHz clock phase locked to a 4.096MHz clock. The framing signal input to PAC#1 at F0i should meet the requirements specified in Figure 13 of this data sheet. In some applications where a master 16.384 MHz oscillator is used for system timing, the C4i and F0i c locks could be derived directly from it. In applications where a 4.096 MHz clock signal is available, the 16.384 MHz clock can be generated using a phase-lock loop. Framing signals for both the SMXs are generated by PAC #1. DFPo is connected to FP input of the Data Memory. CFPo is connected to the FP input of the Connection Memory. PAC #2 is configured to perform parallel to serial conversion. The DFPo and CFPo signals ensure that all timing requirements necessary to interface the SMXs with the PACs are met while input and output serial frames are aligned. The maximum delay through the switch is approximately one frame plus two serial channels when SMX#1 is operated in Data Memory Mode-1. When the SMX is operated in Data Memory Mode-2, the maximum delay is two frames. In this case, the channels are double buffered; frame integrity is maintained for all switching configurations. 2-133 MT9085 CMOS number Hex 0082. In order to program the matrix for switching, the input channel address is written to the Connection Memory address corresonding to the serial output channel. The bits controlling features such as OE, ME, and Mz should be set or reset accordingly at the same time. For example. if channel 4 on stream 2 is to be switched to channel 10 on stream 1, the following binary word is written to Connection Memory address corresponding to the output channel (Hex 0141): In the example configuration shown in Figure 9 the OE pin of PAC #2 is connected to D10 on the Connection Memory. Setting bit 10 high in the Connection Memory location corresponding to a serial channel timeslot will result in the output driver for the specific stream being disabled during that serial channel timeslot. D11 is connected to the ME input of SMX1 and D12 is connected to a mode select pin (Mz). Consequently, the levels on these outputs can be set high or low by writing to the appropriate memory location corresponding to the selected output channel. The mapping of the control functions on to Connection Memory data bits is illustrated in Figure 10. The data on the PAC serial streams is byte interleaved as described in the Functional Description section in this data sheet. The SMX channel number corresponding to the channel on the serial streams can be determined directly by specifying the serial channel and stream number in binary as shown in Figure 11. For example, serial channel 4, stream 2 corresponds to SMX channel Timing Source XXX0 0000 1000 0010 Stream Address Channel Address Output Enable Message Enable DM-1/DM-2 Unused From Timing Source C16 C4 F0 F0i C4i C16i PAC#1 S/P S0 S31 • • • • S0 • • • • S31 2/4S OE CKD MCA MCB ODE +5 10 P0-P7 DFPo CFPo +5 SMX #1 DM - 1/2 8 C16 D0-D7i CK FP Mz R/W D0-D7o Mx My CS DS A0-A9 ME +5 OE CKD MCA MCB 8 F0i C4i C16i PAC#2 P/S P0-P7 S0 • • • • S31 2/4S • • • • S0 S31 F0 C4 C16 DATA MEMORY D12 D0-D9 D11 SMX #2 CM - 1 D10 ODE Mx My Mz +5 +5 FP CONNECTION MEMORY CD D0-D15 A0-A15 C16 CK DTA R/W CS DS NOTE: MPU Interface Connect all inputs not shown to VSS Figure 9 - 1024 Channel Switch Matrix Using the PAC and SMX 2-134 CMOS MT9085 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Not Used Serial Channel Number Stream Address OE - Output Enable ME - Message Enable Mode Control - DM-1 or DM-2 Figure 10 - Mapping of Data Memory and PAC Control Functions on Connection Memory Data Bits 4 3 2 1 0 4 3 2 1 0 Unused Channel Address Stream Address Ex. Serial Stream 4, Channel 3 Corresponds to SMX Channel Number 100 (Hex 0064) Figure 11 - Decoding SMX Channel Number from Serial Stream & Channel Address 1024 Switch Configuration 2048 Channel Digital Space-Time Switch Application A 2048 channel serial time-space digital switch design is illustrated in Figure 12. The main switching function is accomplished using three MT9080s (SMXs). Two SMXs function as the data memory, while the third is operated in Connect Memory mode. Refer to the SMX data sheet for more information on this configuration. The Serial to parallel conversion for 2048 channels is handled by two PACs. PAC #1a and PAC #1b. Both are configured for 2.048 Mbit/s operation (2/4S=0). The MCB input is tied low in both devices. The parallel data bus on each of the devices will be actively driven for one C16 clock period. The CKD input is set low in one of the devices and set high in the other. This will cause the output timing of the two PACs to be off set by one C16 clock period. Consequently, the parallel output of one device will be disabled while the other is active. The parallel to serial conversion is also accomplished with two PACs. Data from the common SMX parallel bus is clocked into each PAC in alternate clock periods. The timing source generates a 16.384 MHz clock phase locked to a 4.096 MHz clock. The framing signal input to PAC #1a at F0i s hould meet the requirements specified in this data sheet. In some applications where a master 16.384 MHz oscillator is used for system timing, the C4i and F0i clocks could be derived directly from it. The DFPo and DFPo generated by PAC #1a are used to switch the mode of operation of the Data Memory SMXs between Counter and External modes and also serve as the frame pulse for the two SMXs. Because DFPo and DFPo are complementary signals, one of the two SMXs is operated in the Counter mode while the second one is operated in the External mode. The states of the other control inputs, R/W and ODE, are changed accordingly. The SMX configured as the Connection Memory, is fed a frame pulse from PAC #1b. The phase alignment of CFPo with respect to DFPo ensures that timing requirements for proper operation of the SMXs are met. Refer to the SMX data sheet for more information on the timing requirements. The maximum delay through the switch is two frames. Channels are double buffered and frame integrity is maintained for all switching configurations. For more information, see Mitel’s Application Note MSAN-135, “ Design of Large Digital Switching Matrices using the SMX/PAC“ (in this data book) and Application Sheet MSAS-62 “16.384 MHz Clock Generation for SMX/PAC“ (available from Mitel). 2-135 MT9085 CMOS Timing Source M4 MF F0i C4i C16i PAC#1a S/P S0 • • • S31 • S0 • • • • S31 2/4S OE CKD MCA MCB P0-P7 C16 DFPo DFPo C16 C4 F0 SMX #1 CNT/EXT 8 D0-D7i CK FP Mz R/W Mx My CS D0-D7o C16 +5 SMX #2 CNT/EXT D0-D7i CK FP Mz R/W Mx My D0-D7o 8 +5 F0i C4i C16i PAC#2a P/S P0-P7 S0 • • • • S31 2/4S • • • • S0 S31 From Timing Source F0 C4 C16 DS A0ODE A10 ME CS DS A0ODE A10 ME OE CKD MCA MCB +5 F0 C4 C16 F0 C4 C16 8 F0i C4i C16i PAC#2b P/S P0-P7 S0 • • • • S31 2/4S • • • • S0 S31 F0i C4i C16i PAC#1b S/P S0 • • S31 • • S0 • • • • S31 2/4S OE CKD MCA MCB +5 P0-P7 CFPo C16 FP CK DTA 8 D12 D0-D10 D11 SMX #3 CM - 2 ODE Mx CONNECTION MEMORY +5 My Mz +5 OE CKD MCA MCB CD D0-D15 A0-A15 MPU Interface NOTE: Connect all inputs not shown to VSS Figure 12 - 2048 Channel Switch Matrix Using the PAC and SMX 2-136 R/W CS +5 DS CMOS Absolute Maximum Ratings* - Voltages are with respect to Ground (VSS) unless otherwise stated. Parameter 1 2 3 4 5 VDD-VSS Voltage on Digital Inputs Voltage on Digital Outputs Current at Digital Outputs Storage Temperature VI VO IO TS -40 Symbol Min -0.3 VSS-0.3 VSS-0.3 MT9085 Max 7 VDD+0.3 VDD+0.3 40 125 2 Units V V V mA °C W 6 Package Power Dissipation PD * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to Ground (VSS) unless otherwise stated. Characteristics 1 2 3 Operating Temperature Positive Supply Input Voltage Sym TOP VDD VI Min -40 4.5 0 Typ‡ Max 70 5.5 VDD Units °C V V Test Conditions ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. DC Electrical Characteristics - Voltages are with respect to Ground (VSS) unless otherwise stated. Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 O U T P U T S I N P U T S Supply Current Input High Voltage - all pins except C4i, F0i, S0-S31 Input Low Voltage - all pins except C4i, F0i, S0-S31 Input High Voltage - C4i, F0i, S0-S31 Input Low Voltage - C4i, F0i, S0-S31 Input Leakage Current Output Low Current S0-S31 Output Low Current all outputs except S0-S31 Output High Current S0-S31 Output High Current all outputs except S0-S3 High Impedance Leakage Input Pin Capacitance Sym IDD VIH VIL VIH VIL IIL IOL IOL IOH IOH IOZ Ci 8 8 8 8 10 10 0.7VDD 0 2.0 0.8 ±10 0.3VDD Min Typ‡ Max 50 Units mA V V V V µA mA mA mA mA µA pF VDD=5.0V ±10 % VOL=0.4V VOL=0.3VDD VOH=2.4V VOH=0.7VDD Test Conditions Outputs unloaded 13 Output Pin Capacitance Co 10 pF ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. 2-137 MT9085 CMOS AC Electrical Characteristics†- Input Frame Pulse and Clock Timing (See Figure 13) Voltages are with respect to Ground (VSS) unless otherwise stated. Characteristics 1 2 3 4 5 6 7 C16 Clock Period C4 Clock Period C16 Pulse Width Low C16 Pulse Width High C4 Setup Time Frame Pulse Setup Time Frame Pulse Hold Time Sym tC16P tC4P tC16L tC16H tC4S tFPS tFPH Min 60 219 25 25 -10 5 5 Typ‡ 61 244 Max 62 269 Units ns ns ns ns Test Conditions 25 200 ns ns ns † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ST-BUS Frame Boundary tC16P C16i tC4S C4i tC4P F0i tC16H tC16L tFPS tFPH Figure 13 - ST-BUS Frame Pulse and Clock Timing AC Electrical Characteristics† - Output Clocks and Frame Pulse Timing (See Figure 14) Voltages are with respect to Ground (VSS) unless otherwise stated. Characteristics 1 2 3 Frame Pulse Delay C4 Clock Delay C2 Clock Delay Sym tFPD tC4D tC2D Min 0 0 0 Typ‡ Max 31 28 Units ns ns ns Test Conditions CL=85pF CL=85pF CL=85pF † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. C16i tFPD F0o tC4D C4o tC2D C2o tC4D tC4D tFPD Figure 14 - F0o, C4o and C2o Output Clock Timing 2-138 CMOS MT9085 AC Electrical Characteristics† - Data Memory and Connect Memory Frame Pulse (See Figure 15) - Voltages are with respect to Ground (VSS) unless otherwise stated. Characteristics 1 2 Data - Memory Frame Pulse Delay Connection - Memory Frame Pulse Delay Sym tDFPo tCFPo Min 0 0 Typ‡ Max 37 30 Units ns ns Test Conditions CL=85 pF CL=85 pF † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ST-BUS Frame Boundary Established by F0i ST-BUS Frame Boundary Established by F0i 64 C16 Cycles 71 C16 Cycles 64 C16 Cycles C16i CKD=0 DFPo tDFPo tDFPo tDFPo tDFPo tCFPD DFPo tCFPD CFPo 68 C16 Cycles CKD=1 DFPo tDFPo tDFPo tDFPo tDFPo DFPo tCFPo tCFPo CFPo Figure 15 - DFPo and CFPo Output Timing 2-139 MT9085 CMOS AC Electrical Characteristics† - Serial Input and Output Timing in 2 MHz Mode (2/4S=0) (See Figure 16) - Voltages are with respect to Ground (VSS) unless otherwise stated. Characteristics 1 2 3 Serial Input Setup Time Serial Input Hold Time Serial Output Delay Active to Active High Impedance to Active Active to High Impedance Sym tSS tSH tSD 47 47 44 ns ns ns CL=150pF CL=150pF CL=150pF Min 0 24 Typ‡ Max Units ns ns Test Conditions † Timing is over recommended temperature & power supply voltages ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Serial Bit Cell C4i C16i tSS S0i-S7i (CKD=0) tSH S0i-S7i (CKD=1) tSS tSH S0o-S7o (CKD=0) tSD S0o-S7o (CKD=1) tSD tSD Note: 1) The phase relationship of C4i a nd C16i depends on the user’s timing source (see Fig. 13 for device related contstraints). 2) Timing measurements for inputs are referenced to/from a low voltage of 0.8V and a high voltage of 2.0V. Measurements for outputs are referenced to/from a low voltage of 0.4V to a high voltage of 2.4V Figure 16 - Serial Input and Output Timing in 2 Mbit/s Mode (2/4S=0) 2-140 CMOS MT9085 AC Electrical Characteristics† - Serial Input and Output Timing in 4 MHz Mode (2/4S=1) (See Figure 17) - Voltages are with respect to Ground (VSS) unless otherwise stated. Characteristics 1 2 3 Serial Input Setup Time Serial Input Hold Time Serial Output Delay Active to Active High Impedance to Active Active to High Impedance Sym tSS tSH tSD 47 47 44 ns ns ns CL=150pF CL=150pF CL=150pF Min 0 24 Typ‡ Max Units ns ns Test Conditions † Timing is over recommended temperature & power supply voltages ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Serial Bit Cell C4i C16i tSS S0i-S7i (CKD=0) tSS S0i-S7i (CKD=1) tSD S0o-S7o (CKD=0) tSD S0o-S7o (CKD=1) tSD tSD tSH tSS tSH tSH tSH tSS Note: 1) 2) The phase relationship of C4i a nd C16i depends on the user’s timing source (see Fig. 13 for device related contstraints). Timing measurements for inputs are referenced to/from a low voltage of 0.8V and a high voltage of 2.0V. Measurements for outputs are referenced to/from a low voltage of 0.4V to a high voltage of 2.4V Figure 17 - Serial Input and Output Timing in 4 Mbit/s Mode (2/4S=1) 2-141 MT9085 CMOS AC Electrical Characteristics† - Parallel Output Timing (See Figure 18) - Voltages are with respect to Ground (VSS) unless otherwise stated. Characteristics 1 2 3 Parallel Output Delay Parallel Output Delay High Impedance to Active Parallel Output Delay Active to High Impedance Sym tPD tPZA tPAZ Min Typ‡ Max 28 28 28 Units ns ns ns Test Conditions C L=85pF C L=85pF C L=85pF † Timing is over recommended temperature & power supply voltages ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. C16i P0 to P7 MCB=1 tPD P0 to P7 MCB=0 tPZA NOTE: tPAZ 10% 90% tPD tPZA See Figure 7 for functional timing information Figure 18 - Parallel Output Timing AC Electrical Characteristics† - Parallel Input Timing (See Figure 19) - Voltages are with respect to Ground (VSS) unless otherwise stated. Characteristics 1 2 Parallel Input Setup Time Parallel Input Hold Time Sym tPS tPH Min 0 5 Typ‡ Max Units ns ns Test Conditions † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. C16i tPH tPS P0 to P7 MCB=1 tPH tPS P0 to P7 MCB=0 tPS tPH tPS tPH NOTE: See Figure 6 for functional timing information Figure 19 - Parallel Input Timing 2-142 CMOS MT9085 AC Electrical Characteristics† - Output Enable Timing, Serial to Parallel Mode (See Figure 20) - Voltages are with respect to Ground (VSS) unless otherwise stated. Characteristics 1 2 Parallel Output Delay Active to High Impedance Parallel Output Delay High Impedance to Active Sym tPAZ tPZA Min Typ‡ Max 23 25 Units ns ns Test Conditions CL=85pF CL=85pF † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. OE 90% P0 to P8 Output 10% tPAZ tPZA Figure 20 - OE Timing in Serial to Parallel Mode AC Electrical Characteristics† - Output Enable (OE) Timing, in Parallel to Serial Mode (See Figure 21) - Voltages are with respect to Ground (VSS ) unless otherwise stated. Characteristics 1 2 OE Setup Time OE Hold Time Sym tOES tOEH Min 2 10 Typ‡ Max Units ns ns Test Conditions † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Frame Boundary Established by F0i C16i tOES OE CKD=0 tOEH tOES OE CKD=1 tOEH tOEH tOES tOEH tOES Figure 21 - OE Timing in Parallel to Serial Mode 2-143 MT9085 NOTES: CMOS 2-144