SP5668

SP5668 2.7GHz 3-Wire Bus Controlled Synthesiser Preliminary Information DS4538 - 1.6 January 1997 . The SP5668 is a single chip frequency synthesiser designed for tuning systems up to 2.7GHz. The RF preamplifer contains a divide by two prescaler which can be disabled for applications up to 2GHz so enabling a step size equal to the comparison frequency up to 2GHz and twice the comparison frequency up to 2.7GHz. Comparison frequencies are obtained either from a crystal controlled on–chip oscillator or from an external source. The device contains three switching ports, P0 – P2, together with an ’in–lock’ flag output. Various test modes including varactor disable and charge pump disable are also included. CHARGE PUMP CAP Q1 CRYSTAL Q2 ENABLE DATA CLOCK PORT P2 PORT P1/OC DRIVE VEE RF INPUT RF INPUT VCC LOCK REF PORT P0/OC FEATURES s Complete 2.7GHz single chip system s Optimised for low phase noise s Selectable divide by two prescaler s Selectable reference division ratio s Charge pump disable s Varactor line disable s ‘In–lock’ flag s Two selectable charge pump currents s Three switching ports s Reference frequency output s ESD protection (Normal ESD handling procedures should be observed) MP16 Fig. 1 Pin connections - top view APPLICATIONS s SAT, TV, VCR and Cable tuning systems s Communications systems ORDERING INFORMATION SP5668/KG/MP1S (Tubes,) SP5668/KG/MP1T Tape and Reel) SP5668 Fref PROGRAMMABLE DIVIDER 13 INPUTS 14 RF ÷ 2/1 ÷ 16/17 13 BIT COUNT Fpd PHASE COMP Fcomp REFERENCE DIVIDER See Table 1 OSC REF CRYSTAL Q1 CRYSTAL Q2 1 CHARGE PUMP DRIVE DE 4 BIT COUNT CHARGE PUMP OS CO 1 BIT LATCH 3 BIT LATCH (R0,R1,R2) 1 BIT LATCH 16 18 BIT LATCH DISABLE ENABLE 4 CLOCK 5 DATA 6 DATA INTERFACE 3 BIT LATCH AND PORT INTERFACE 1 BIT LATCH FLOCK P2 P1 P0 LOCK Fig. 2 SP5668 block diagram TAMB = 120°C to +80°C, VCC = +4.5 to +5.5V. Reference frequency = 4MHz. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Characteristic Pin Min Supply current, Icc RF input voltage 13, 14 13,14 RF input impedance Data, Clock, Enable Input high voltage Input low voltage Input high current Input low current Hysteresis Clock Rate 400 6 500 12 13, 14 40 40 13, 14 4,5,6 3 0 VCC 0.7 10 -10 V V µA µA mV kHz Input voltage = VCC Input voltage = VEE 100 Value Typ 65 58 Max 81 72 300 300 300 mA mA mVrms mVrms mVrms Vcc = 5V Prescaler enabled, PE = 1 Vcc = 5V Prescaler disabled, PE = 0 100MHz Prescaler enabled, PE = 1 See Fig. 5b. 300MHz - 2.7GHz Prescaler enabled, PE = 1, See Fig. 5b. 100MHz to 2.0GHz Prescaler disabled, PE = 0, See Fig. 5a See Fig. 4. Units Conditions ELECTRICAL CHARACTERISTICS 2 SP5668 TAMB = 120°C to +80°C, VCC = +4.5 to +5.5V. Reference frequency = 4MHz. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Characteristic Pin Min Bus timing Data set up , tSU Data hold, tHD Enable set up, tES Enable hold , tEH Clock to enable, tCE Charge pump output Current Charge pump output leakage Drive output current Drive output saturation Voltage when disabled External reference input frequency External reference input amplitude Crystal frequency Recommended crystal Series resistance 1 1 16 16 3 3 3 2 200 4 10 1 350 20 500 12 200 ±10 nA mA mV MHz mVp-p MHz Ω 4, 5, 6 300 600 300 600 300 ns ns ns ns ns See Fig. 3 See Fig. 3 See Fig. 3 See Fig. 3 See Fig. 3 See Table 3, Vpin1 =2V Vpin1 = 2V VPIN16 = 0.7V OS = 1 AC coupled sinewave AC coupled sinewave Value Typ Max Units Conditions ELECTRICAL CHARACTERISTICS (continued) Applies to 4MHz crystal only. "Parallel resonant" crystal. Figure quoted is under all conditions Reference oscillator bias current REF output voltage* Phase detector comparison frequency Equivalent phase noise at phase detector RF division ratio Reference division ratio Output ports P0-P2 Sink current Leakage current Lock output Sink current Leakage current 3 10 200 350 4 µA mVp-p MHz dBc/Hz including start up. See Fig. 11 AC coupled, 4MHz reference frequency, See Fig. See **Note PE = 0, Prescaler disabled PE = 1, Prescaler enabled See Table 1 240 480 7-9 10 131071 262142 mA 10 µA mA µA VPORT = 0.7V VPORT = 13.2V VPIN10 = 0.7V, 'out of lock' 'in lock' 1 10 * REF output should be connected to VCC if unused ** Note: 1. -148dB @ 1KHz offset with 1MHz comparison frequency measured at the phase comparator. 2. When external reference is used, a high signal level is required for low phase noise. 3 SP5668 ABSOLUTE MAXIMUM RATINGS All voltages are referred to VEE at 0V Charateristics Supply voltage, VCC RF input voltage RF input offset Port output voltage Total port current REFoutput DC offset Lock output DC offset Lock output current Charge pump DC offset Drive DC offset Crystal oscillator DC offset Data, Clock & inputs Storage temperature Junction temperature MP16 Thermal resistance Chip to ambient Chip to case Power consumption at VCC = 5.5V ESD protection ALL 2 Pin 12 13, 14 13, 14 7-9 7-9 7-9 10 11 11 1 16 2, 3 4,5,6 Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55 Max 7 2.5 VCC+0.3 14 6 50 VCC+0.3 VCC+0.3 10 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 +150 +150 111 41 407 Units V Vp-p V V V mA V V mA V V V V °C °C °C/W °C/W mV kV All ports off, prescaler enabled MIL-STD 883 TM3015 Port in off state Port in on state Conditions FUNCTIONAL DESCRIPTION The SP5668 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varicap tuned local oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. The RF preamplifier contains a selectable divide by two for operation above 2.0GHz. Up to 2GHz the RF input interfaces directly with the programmable divider, so eliminating degradation in phase noise due to the prescaler action. The block diagram is shown in Fig.2. The SP5668 is controlled by a standard 3–wire bus comprising data, clock and enable inputs. The programming word contains 27 bits. P0 - P2 are used for port selection, 217 - 20 set the programmable divider ratio R2 - R0 select the reference division ratio (Table1). C0 sets the charge pump current (Table 3) and the remaining two bits T0, OS access test modes and disable the varactor drive (Table 2).The programming format is shown in Fig. 3. The clock input is disabled by an enable low signal, data is therefore only clocked into the internal shift registers during an enable high and is loaded into the controlling buffers by an enable high to low transition. This load is also synchronised with the programmable divider so giving smooth fine tuning. The RF signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier is fed to the ÷ 2/1 selectable prescaler and then to the 17 bit fully programmable divider, which is of MN+A architecture. The M counter is 13 bit and the A counter 4. If bit PE is set to a 0 the prescaler is disabled; the control function PE cannot be used dynamically. The output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on board crystal controlled oscillator or from an external source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 8 ratios as described in Table 1. The output of the phase comparator feeds the charge pump and loop amplifier section, which when used with an external high voltage transistor and loop filter integrates the current pulses into the varactor line voltage. The charge pump current is selected by bit C0 as described in Table 3. The phase comparator also drives the lock detect circuit which generates a lock flag. 'In-lock' is indicated by a high impedance state on the lock output. The crystal frequency Fref is available at the REF output. This may be used as the reference for a second synthesiser as shown in Fig. 6. The REF output is disabled by connecting the output, pin 3, to VCC. 4 SP5668 PHASE NOISE The SP5668 has been designed to offer good phase noise performance even when operated with a standard low profile 4MHz crystal and a high comparison frequency, e.g. 2MHz. The typical phase noise performance measured in the standard application is contained in Table 4. It has been demonstrated that even higher levels of performance will be achieved in a tuner application. TEST MODES The programmable divider output divided by two Fpd/2 and the comparison frequency Fcomp, can be switched to ports P0 and P1 respectively. The charge pump can be forced to either source or sink current, and may be disabled to high impedance state. The varactor DRIVE output can be disabled by the OS bit within the data word, so switching the external transistor 'OFF' and allowing an external voltage to be written to the varactor line for tuner alignment purposes. The test modes are described in Table 2. CLOCK ENABLE DATA MSB 2 26 2 25 2 24 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 P2 P1 P0 TO OS CO R2 R1 R0 PE FREQUENCY DATA 216 to 20 PE R2 , R1 , R0 P2, P1, P0 CO OS T0 t : Programmable divider ratio control bits : ÷2 Prescaler (Enable = 1, Disable = 0) t : Reference divider ratio control bits (see Table 1) t : Port control bits t : Charge Pump current select (see Table 3) t : Drive output disable switch t : Test mode enable (see Table 2) 2 0 LSB Fig. 3 Data format and timing R2 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 RATIO 2 4 8 16 32 64 128 256 Comparison Frequency with a 4MHz external reference 2MHz 1MHz 500kHz 250kHz 125kHz 62.5kHz 31.25kHz 15.625kHz Table 1 Reference division ratio P1 X 0 0 1 1 X = Don't care P0 X 0 1 0 1 T0 0 1 1 1 1 FUNCTIONAL DESCRIPTION Normal operation Charge pump sink. LOCK output = Lo Z Charge pump source. LOCK output = Hi Z Charge pump disable. LOCK output = Lo Z Port P1 = Fcomp: Port 0 = Fpd/2 Table 2 Test modes 5 SP5668 C0 0 1 MIN 0.23 0.68 CURRENT IN mA TYP 0.30 0.90 MAX 0.37 1.12 Table 3 Charge pump FLO Fcomp (4MHz XTAL) RF Division RATIO VCO PHASE NOISE @1kHZ OFFSET (dBc/Hz) -84 -80 EQUIVALENT PHASE NOISE PHASE DETECTOR (dBc/Hz) -146 -144 2GHz 2GHz 1MHz 2MHz 2000 1000 Table 4 Typical phase noise +j1 +j0.5 +j2 +j0.2 +j5 0 0.2 0.5 1 2 5 X –j0.2 X X –j5 S11:Z 0 = 50 NORMALISED TO 50Ω –j0.5 –j1 X –j2 FREQUENCY MARKERS AT 100MHz, 500MHz, 1GHz AND 2.7GHz Fig. 4. Typical input impedance 6 SP5668 300 VIN (mV RMS INTO 50Ω) 100 50 40 10 300 VIN (mV RMS INTO 50Ω) OPERATING WINDOW 100 40 10 OPERATING WINDOW 80 100 1000 2000 3000 3500 80 300 1000 2000 3000 3500 2700 FREQUENCY (MHz) FREQUENCY (MHz) Fig. 5a Typical input sensitivity (Prescaler disabled, PE=0) Fig. 5b Typical input sensitivity (Prescaler enabled, PE=1) 1.6GHZ 50 - 900MHz 38.9MHz 1650-2700MHz 2 3 SP5668 VCO 3 10 10nF Fig. 6. Example of double conversion from VHF/UHF frequencies to TV IF SP5668 VCO 18pF 2 39pF 3 4MHz +30V 68pF 15nF 13k3 BCW31 22k +5V +12V 16k 47k 2n2 Optional application utilising on–board crystal controlled oscillator 1 2 16 15 REFERENCE CONTROL MICRO ENABLE DATA CLOCK LOCK P2 P1 1n 1n OSCILLATOR OUTPUT 10n P0 TUNER 4 5 6 7 8 SP5668 3 14 13 12 11 10 9 Fig. 7. typical application, SP5668 7 SP5668 APPLICATION NOTES A generic set of application notes AN168 for designing with synthesisers such as the SP5668 has been written. This covers aspects such as loop filter design and decoupling. This application note is also featured in the Media IC Handbook. A generic test/demo board has been produced which can be used for the SP5668. A circuit diagram is shown in Fig. 8. The board can be used for the following purposes: (A) Measuring RF sensitivity performance. (B) Indicating port function (C) Synthesising a voltage controlled oscillator (D) Testing of external reference sources P2 +5V C10 100nF C3 68pF 47µF +30V +12V C9 100nF R2 22K R9 C11 100nF R10 47K C14 2n2F RF INPUT C3 1nF SKT1 VAR GND 47µF EXTERNAL REFERENCE SKT2 C7 10nF *(NOT FITTED) C2 15nF R6 13K3 1 2 3 4 5 6 16 15 14 16K T1 BCW31 C5 C6 18pF C8 39pF P1 ENABLE DATA / SDA CLOCK / SCL C12 100pF C13 100pF X1 4MHz 13 12 11 10 9 1nF SW2 C4 10nF 7 8 REFERENCE OUTPUT SKT LOCK P0 P1 P2 SW1 R6 4K7 R7 4K7 R4 4K7 D1 D2 PIN NO : 7 D4 D5 8 LOCK Fig. 8 Evaluation board 8 R5 4K7 SP5668 LOOP BANDWIDTH The majority of applications for which the SP5668 is intended require a loop filter bandwidth of between 2kHz and 10kHz. Typically the VCO phase noise will be specified at both 1kHz and10kHz offset. It is common practice to arrange the loop filter bandwidth such that the 1kHz figure lies within the loop bandwidth. Thus the phase noise depends on the synthesiser comparator noise floor, rather than the VCO. The 10kHz offset figure should depend on the VCO providing the loop is designed correctly, and is not underdamped. REFERENCE SOURCE The SP5668 offers optimal LO phase noise performance when operated with a large step size. This is due to the fact that the LO phase noise within the loop bandwidth is: phase comparator noise floor + 20 log ( LO frequency phase comparator frequency ) Assuming the phase comparator noise floor is flat irrespective of sampling frequency, this means that the best performance will be achieved when the overall LO to phase comparator division ratio is a minimum. There are two ways of achieving a higher phase comparator sampling frequency:– A) reduce the division ratio between the reference source and the phase comparator B) use a higher reference source frequency. Approach B) may be preferred for best performance since it is possible that the noise floor of the reference oscillator may degrade the phase comparator performance if the reference division ratio is very small. 9 SP5668 VREF VCC 500 500 CHARGE PUMP RF INPUTS 200 OS (Output disable) DRIVE OUTPUT RF inputs Loop amplifier VCC PORT/LOCK 25K BIAS Disable, Enable, Data and Clock inputs Output Ports and Lock Output VCC VCC XTAL CAP REF 1.2mA Reference oscillator Reference output Fig.9 Input/Output interface circuits 10 http://www.mitelsemi.com World Headquarters - Canada Tel: +1 (613) 592 2122 Fax: +1 (613) 592 6909 North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Asia/Pacific Tel: +65 333 6193 Fax: +65 333 6192 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. However, Mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Mitel or licensed from third parties by Mitel, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Mitel, or non-Mitel furnished goods or services may infringe patents or other intellectual property rights owned by Mitel. This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Mitel’s conditions of sale which are available on request. M Mitel (design) and ST-BUS are registered trademarks of MITEL Corporation Mitel Semiconductor is an ISO 9001 Registered Company Copyright 1999 MITEL Corporation All Rights Reserved Printed in CANADA TECHNICAL DOCUMENTATION - NOT FOR RESALE