74LS12

SN54/74LS122 SN54/74LS123 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS These dc triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance values. The LS122 has an internal timing resistor that allows the circuits to be used with only an external capacitor. Once triggered, the basic pulse width may be extended by retriggering the gated low-level-active (A) or high-level-active (B) inputs, or be reduced by use of the overriding clear. RETRIGGERABLE MONOSTABLE MULTIVIBRATORS LOW POWER SCHOTTKY • • • • • Overriding Clear Terminates Output Pulse Compensated for VCC and Temperature Variations DC Triggered from Active-High or Active-Low Gated Logic Inputs Retriggerable for Very Long Output Pulses, up to 100% Duty Cycle Internal Timing Resistors on LS122 16 1 J SUFFIX CERAMIC CASE 620-09 SN54 / 74LS123 (TOP VIEW) (SEE NOTES 1 THRU 4) 1R ext/ V CC 16 C ext 15 1 C ext 14 1Q 13 2Q 12 2 CLR 2B 10 2A 9 16 1 N SUFFIX PLASTIC CASE 648-08 11 Q CLR Q CLR Q Q 16 1 6 2 7 2 R ext/ C ext 8 GND D SUFFIX SOIC CASE 751B-03 1 1A 2 1B 3 1 CLR 4 1Q 5 2Q C ext J SUFFIX CERAMIC CASE 632-08 14 1 SN54 / 74LS122 (TOP VIEW) (SEE NOTES 1 THRU 4) R ext/ V CC 14 C ext 13 NC 12 C ext 11 NC 10 R int 9 Q 8 R int Q 14 1 N SUFFIX PLASTIC CASE 646-06 CLR Q 1 A1 2 A2 3 B1 4 B2 5 CLR 6 Q 7 GND 14 1 D SUFFIX SOIC CASE 751A-02 NC NO INTERNAL CONNECTION. NOTES: 1. An external timing capacitor may be connected between Cext and Rext/Cext (positive). 2. To use the internal timing resistor of the LS122, connect Rint to VCC. 3. For improved pulse width accuracy connect an external resistor between Rext/Cext and VCC with Rint open-circuited. 4. To obtain variable pulse widths, connect an external variable resistance between Rint/Cext and VCC. ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC FAST AND LS TTL DATA 5-197 SN54/74LS122 • SN54/74LS123 LS122 FUNCTIONAL TABLE INPUTS CLEAR L X X X H H H H H H H ↑ ↑ A1 X H X X L L X X H ↓ ↓ L X A2 X H X X X X L L ↓ ↓ H X L B1 X X L X ↑ H ↑ H H H H H H B2 X X X L H ↑ H ↑ H H H H H OUTPUTS Q L L L L Q H H H H CLEAR L X X H H ↑ LS123 FUNCTIONAL TABLE INPUTS A X H X L ↓ L B X X L ↑ H H OUTPUTS Q L L L Q H H H TYPICAL APPLICATION DATA The output pulse tW is a function of the external components, Cext and Rext or Cext and Rint on the LS122. For values of Cext ≥ 1000 pF, the output pulse at VCC = 5.0 V and VRC = 5.0 V (see Figures 1, 2, and 3) is given by tW = K Rext Cext where K is nominally 0.45 If Cext is on pF and Rext is in kΩ then tW is in nanoseconds. The Cext terminal of the LS122 and LS123 is an internal connection to ground, however for the best system performance Cext should be hard-wired to ground. Care should be taken to keep Rext and Cext as close to the monostable as possible with a minimum amount of inductance between the Rext/Cext junction and the Rext/Cext pin. Good groundplane and adequate bypassing should be designed into the system for optimum performance to insure that no false triggering occurs. It should be noted that the Cext pin is internally connected to ground on the LS122 and LS123, but not on the LS221. Therefore, if Cext is hard-wired externally to ground, substitution of a LS221 onto a LS123 socket will cause the LS221 to become non-functional. The switching diode is not needed for electrolytic capacitance application and should not be used on the LS122 and LS123. To find the value of K for Cext ≥ 1000 pF, refer to Figure 4. Variations on VCC or VRC can cause the value of K to change, as can the temperature of the LS123, LS122. Figures 5 and 6 show the behavior of the circuit shown in Figures 1 and 2 if separate power supplies are used for VCC and VRC. If VCC is tied to VRC, Figure 7 shows how K will vary with VCC and temperature. Remember, the changes in Rext and Cext with temperature are not calculated and included in the graph. As long as Cext ≥ 1000 pF and 5K ≤ Rext ≤ 260K (SN74LS122 / 123) or 5K ≤ Rext ≤ 160 K (SN54LS122 / 123), the change in K with respect to Rext is negligible. If Cext ≤ 1000 pF the graph shown on Figure 8 can be used to determine the output pulse width. Figure 9 shows how K will change for Cext ≤ 1000 pF if VCC and VRC are connected to the same power supply. The pulse width tW in nanoseconds is approximated by tW = 6 + 0.05 Cext (pF) + 0.45 Rext (kΩ) Cext + 11.6 Rext In order to trim the output pulse width, it is necessary to include a variable resistor between VCC and the Rext/Cext pin or between VCC and the Rext pin of the LS122. Figure 10, 11, and 12 show how this can be done. Rext remote should be kept as close to the monostable as possible. Retriggering of the part, as shown in Figure 3, must not occur before Cext is discharged or the retrigger pulse will not have any effect. The discharge time of Cext in nanoseconds is guaranteed to be less than 0.22 Cext (pF) and is typically 0.05 Cext (pF). For the smallest possible deviation in output pulse widths from various devices, it is suggested that Cext be kept ≥ 1000 pF. FAST AND LS TTL DATA 5-198 SN54/74LS122 • SN54/74LS123 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Rext Cext Rext / Cext Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low External Timing Resistance External Capacitance Wiring Capacitance at Rext / Cext Terminal Parameter 54 74 54 74 54, 74 54 74 54 74 54, 74 54, 74 5.0 5.0 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 0.4 4.0 8.0 180 260 No Restriction 50 pF Unit V °C mA mA kΩ WAVEFORMS RETRIGGER PULSE (See Application Data) B INPUT Q OUTPUT tW OUTPUT WITHOUT RETRIGGER EXTENDING PULSE WIDTH B INPUT CLEAR INPUT CLEAR PULSE OUTPUT WITHOUT CLEAR PULSE Q OUTPUT OVERRIDING THE OUTPUT PULSE FAST AND LS TTL DATA 5-199 SN54/74LS122 • SN54/74LS123 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) LS122 ICC Power Supply Current LS123 20 – 20 – 0.4 –100 11 mA VCC = MAX 0.35 0.5 20 IIH IIL IOS V µA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 – 0.65 3.5 0.8 – 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tW min tWQ Parameter Propagation Delay, A to Q Propagation Delay, A to Q Propagation Delay, B to Q Propagation Delay, B to Q Propagation Delay, Clear to Q Propagation Delay, Clear to Q A or B to Q A to B to Q 4.0 Min Typ 23 32 23 34 28 20 116 4.5 Max 33 ns 45 44 ns 56 45 ns 27 200 5.0 ns µs Cext = 1000 pF, Rext = 10 kΩ, CL = 15 pF, RL = 2.0 kΩ Cext = 0 CL = 15 pF Rext = 5.0 kΩ RL = 2.0 kΩ Unit Test Conditions AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits Symbol tW Pulse Width Parameter Min 40 Typ Max Unit ns Test Conditions FAST AND LS TTL DATA 5-200 SN54/74LS122 • SN54/74LS123 V CC V CC V RC R ext V CC V CC V RC R ext C ext C ext R / ext C ext CLR B V CC Q 0.1 µF C ext CLR C ext R / ext C ext Q V CC 0.1 µF P out B2 B1 A2 P out 1/2 LS123 Q P in 51 LS122 Q P in 51 A A1 Ω GND GND Ω Figure 1 Figure 2 P in P out t W RETRIGGER Figure 3 10 5K ≤ Rext ≤ 260K µF) EXTERNAL CAPACITANCE, C ext ( 1 0.1 0.01 0.001 0.3 0.35 0.4 K 0.45 0.5 0.55 Figure 4 FAST AND LS TTL DATA 5-201 SN54/74LS122 • SN54/74LS123 0.55 V =5V RC C = 1000 pF ext 0.55 V =5V CC C = 1000 pF ext 0.55 C = 1000 pF ext 0.5 0.5 K 0.45 - 55 C ° 0C ° - 55 C ° 0.5 - 55 C ° K 0.45 70 C 0C ° 25 C ° K 0.45 0C ° 25 C ° ° ° 25 C ° 70 C 125 C 0.4 0.4 ° 70 C 0.4 ° 125 C ° 125 C ° 0.35 4.5 5 5.5 0.35 4.5 5 5.5 0.35 4.5 5 5.5 VCC Figure 5. K versus VCC VRC Figure 6. K versus VRC VCC = VRC Figure 7. K versus VCC and VRC 100000 R = 260 k ext 10000 R = 160 k ext Ω Ω , OUTPUT PULSE WIDTH (ns) 1000 t W 100 Ω Ω R = 20 kΩ ext R = 10 kΩ ext R = 5 kΩ ext R = 80 k ext R = 40 k ext 10 1 10 100 1000 C , EXTERNAL TIMING CAPACITANCE (pF) ext Figure 8 FAST AND LS TTL DATA 5-202 SN54/74LS122 • SN54/74LS123 0.65 Cext = 200 pF - 55°C 0.6 0°C 25°C 70°C K 0.55 125°C 0.5 4.5 4.75 5 VCC VOLTS 5.25 5.5 Figure 9 VCC Rext REMOTE PIN 7 OR 15 Cext PIN 6 OR 14 Rext Figure 10. LS123 Remote Trimming Circuit FAST AND LS TTL DATA 5-203 SN54/74LS122 • SN54/74LS123 VCC PIN 9 OPEN Rext Rext REMOTE PIN 13 Cext PIN 11 Figure 11. LS122 Remote Trimming Circuit Without Rext VCC Rext REMOTE PIN 9 PIN 13 PIN 11 Figure 12. LS122 Remote Trimming Circuit with Rint FAST AND LS TTL DATA 5-204 -A- Case 751B-03 D Suffix 16-Pin Plastic SO-16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: MILLIMETER. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. 751B 01 IS OBSOLETE, NEW STANDARD 751B 03. 16 9 -B1 8 P 8 PL 0.25 (0.010) M B M R X 45° G -TD 16 PL 0.25 (0.010) M C SEATING PLANE K T B S M F J A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 3.80 1.35 0.35 0.40 10.00 4.00 1.75 0.49 1.25 INCHES MIN MAX 0.386 0.150 0.054 0.014 0.016 0.393 0.157 0.068 0.019 0.049 1.27 BSC 0.19 0.10 0 0.25 0.25 7 0.050 BSC 0.008 0.004 0 0.009 0.009 7 ° ° ° ° 5.80 0.25 6.20 0.50 0.229 0.010 0.244 0.019 Case 648-08 N Suffix 16-Pin Plastic -A16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: INCH. DIMENSION L" TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B" DOES NOT INCLUDE MOLD FLASH. 5. 6. ROUNDED CORNERS OPTIONAL. 648 01 THRU 07 OBSOLETE, NEW STANDARD 648 08. B 1 8 F S C -TK SEATING PLANE L H G D 16 PL 0.25 (0.010) M J M T A M DIM A B C D F G H J K L M S MILLIMETERS MIN MAX 18.80 6.35 3.69 0.39 1.02 19.55 6.85 4.44 0.53 1.77 INCHES MIN MAX 0.740 0.250 0.145 0.015 0.040 0.770 0.270 0.175 0.021 0.070 2.54 BSC 1.27 BSC 0.21 2.80 7.50 0 0.38 3.30 7.74 10 0.100 BSC 0.050 BSC 0.008 0.110 0.295 0 0.015 0.130 0.305 10 ° ° ° ° 0.51 1.01 0.020 0.040 -A16 9 Case 620-09 J Suffix 16-Pin Ceramic Dual In-Line NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. -B1 8 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. C L 5. 620 01 THRU 08 OBSOLETE, NEW STANDARD 620 09. -TSEATING PLANE K E F D 16 PL 0.25 (0.010) M N G T A S M J 16 PL 0.25 (0.010) M T B S DIM A B C D E F G J K L M N MILLIMETERS MIN MAX 19.05 6.10 19.55 7.36 4.19 0.39 0.53 INCHES MIN MAX 0.750 0.240 0.770 0.290 0.165 0.015 0.021 1.27 BSC 1.40 1.77 0.050 BSC 0.055 0.070 2.54 BSC 0.23 0.27 5.08 7.62 BSC 0 0.100 BSC 0.009 0.011 0.200 0.300 BSC 0 ° 15 ° ° 15 ° 0.39 0.88 0.015 0.035 FAST AND LS TTL DATA 5-205 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. 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ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. ◊ FAST AND LS TTL DATA 5-206