74LS569A

SN54/74LS569A FOUR-BIT UP/DOWN COUNTER WITH THREE-STATE OUTPUTS The SN54 / 74LS569A is designed as programmable up/down BCD and Binary counters respectively. These devices have 3-state outputs for use in bus organized systems. With the exception of output enable (OE) and asynchronous clear (ACLR), all functions occur on the positive edge of the clock pulse (CP). When the LOAD input is LOW, the outputs will be programmed by the parallel data inputs (A, B, C, D) on the next clock edge. Enabling of the counters occurs only when CEP and CET are LOW and LOAD is HIGH. Direction of the count is controlled by the up-down input (U/D), HIGH counts up and LOW counts down. High-speed counting and cascading is implemented by internal look-ahead carry logic and an active LOW ripple carry output (RCO). On the LS569A, the RCO is LOW at binary 15 during up-count and during down-count it is also LOW at binary 0. During normal cascading operation RCO connected to the succeeding block at CET is the only requisite. When counting and when RCO is LOW, the clocked carry output (CCO) provides a HIGH-LOW-HIGH pulse for a duration equal to the LOW time of the clock pulse. Two active LOW reset lines are provided, a master reset asynchronous clear (ACLR) and a synchronous clear (SCLR). When in a HIGH state, the output control (OE) input forces the counter output into a HIGH impedance state and when LOW, the counter outputs are enabled. FOUR-BIT UP/ DOWN COUNTER WITH THREE-STATE OUTPUTS LOW POWER SCHOTTKY 20 1 J SUFFIX CERAMIC CASE 732-03 20 1 N SUFFIX PLASTIC CASE 738-03 • ESD > 3500 Volts CONNECTION DIAGRAM (TOP VIEW) 20 V CC 20 RCO 19 CCO 18 OE 17 Y A 16 Y B 15 Y C 14 Y D 13 CET 12 LOAD 11 V = PIN 20 CC GND = PIN 10 DW SUFFIX SOIC CASE 751D-03 1 ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC Note: Pin 1 is marked for orientation. 1 U/D 2 CP 3 A 4 B 5 C 6 D 7 8 9 10 GND CEP ACLR SCLR GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOH IOL IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Except RCO, CCO Output Current — High RCO, CCO Output Current — Low Except RCO, CCO Output Current — Low, RCO, CCO Parameter 54 74 54 74 54 74 54, 74 54 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 1.0 – 2.6 – 0.44 12 24 4.0 8.0 Unit V °C mA mA mA mA FAST AND LS TTL DATA 5-573 SN54/74LS569A FUNCTION TABLE INPUTS CP ↑ ↑ ↑ ↑ Ω ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ X X X X DCBA X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X LOAD H H H H X X X X X X L X X X X X X X X X CET L L H L L L H L L H X H L L H X L L H X CEP L L X H L H X L H X X X L H X X L H X X U/D H L X X H H H L L L X H L L L H L L L X ACLR H H H H H H H H H H H H H H H L L L L X SCLR H H H H H H H H H H H L L L L X X X X X OE L L L L L L L L L L L L L L L L L L L H RCO A/R A/R H A/R L L H L L H H H L L H H L L H X CCO A/R A/R H H H H H H H H H H H H H X OUTPUTS YD YC YB YA Count Up Count Down Count Inhibit Count Inhibit Overflow Overflow Overflow Inhibit Underflow Underflow Underflow Inhibit Load Example Clear (Synchronous) Clear (Synchronous) Clear (Synchronous) Clear (Synchronous) Asynchronous Clear Asynchronous Clear Asynchronous Clear Asynchronous Clear Output Disabled (QT – CP) + 1 (QT – CP) – 1 NC NC NC NC NC NC NC NC H H H L L L L L L L L L L L L H H H L L L H L L L L L L L L Hi-Z H H H L L L L L L L L L L L L H H H L L L H L L L L L L L L LHLH XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX (QT — CP) = Output state prior to clock edge NC = No change A/R = Assumes required output state; High except during Overflow and Underflow X = Don’t care LOGIC DIAGRAM OE * D Q ACLR R CP Q A * Y A B * Y B C * Y C D SCLR LOAD * Y D CEP CET CP U/D RCO CCO FAST AND LS TTL DATA 5-574 SN54/74LS569A DEFINITION OF FUNCTIONAL TERMS A, B, C, D CEP The four programmable data inputs. Count Enable Parallel. Can be used to enable and inhibit counting in high speed cascaded operation. CEP must be LOW to count. Count Enable Trickle. Enables the ripple carry output for cascaded operation. Must be LOW to count. Clock Pulse. All synchronous functions occur on the LOW-to-HIGH transition of the clock. Enables parallel load of counter outputs from data inputs on the next clock edge. Must be HIGH to count. Up/Down Count Control. HIGH counts up and LOW counts down. ACLR Asynchronous Clear. Master reset of counters to zero when ACLR is LOW, independent of the clock. Synchronous clear of counters to zero on the next clock edge when SCLR is LOW. A HIGH on the output control sets the four counter outputs in the high impedance, and a LOW, enables the output. SCLR OE CET CP YA, YB, YC, YD The four counter outputs. RCO Ripple Carry Output. Output will be LOW on the maximum count on up-count. Upon down-count, RCO is LOW at 0000. Clock Carry Output. While counting and RCO is LOW, CCO will follow the clock HIGH-LOW-HIGH transition. LOAD CCO U/D LOW-POWER SCHOTTKY INPUT/OUTPUT CURRENT INTERFACE CONDITIONS VCC DRIVING OUTPUT IOH DRIVING OUTPUT IOH IIL DRIVEN INPUT IOL IOL IIH Note: Actual current flow direction shown FAST AND LS TTL DATA 5-575 SN54/74LS569A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Voltage VOH RCO, CCO YA– YD 54 74 54 74 54, 74 VOL IOZH IOZL IIH Output LOW Voltage 74 Output Off Current HIGH Output Off Current LOW Input HIGH Current 0.1 Others IIL Input LOW Current CET Short Circuit Current (Note 1) RCO, CCO Others – 20 – 30 – 0.8 –100 – 130 43 mA mA mA mA VCC = MAX VCC = MAX – 0.4 0.35 0.5 20 – 20 20 V µA µA µA mA mA VCC = MAX, VIN = 0.4 V 2.4 2.4 2.5 2.7 – 0.65 3.4 3.1 3.5 3.5 0.25 0.4 0.8 – 1.5 V V V V V V IOL = IOL MAX VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = – 18 mA VCC = MAX, VO = 2.7 V VCC = MAX, VO = 0.4 V VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V IOS ICC Power Supply Current, 3-State Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Typ Max Unit Test Conditions FAST AND LS TTL DATA 5-576 fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Toggle Frequency Propagation Delay Clock to Q Propagation Delay CET to RCO Propagation Delay U/D to RCO Propagation Delay Clock to RCO Propagation Delay CET to CCO Propagation Delay CEP to CCO Propagation Delay Clock to CCO Propagation Delay ACLR to Q Output Enable Time Output Disable Time 35 15 20 14 15 20 24 20 25 16 28 16 26 15 17 22 32 15 20 20 27 MHz ns ns ns ns ns ns ns ns ns ns CL = 5.0 pF VCC = 5.0 V CL = 45 pF RL = 667 Ω FAST AND LS TTL DATA 5-577 SN54/74LS569A AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits Symbol tW ts ts ts ts ts th trec Parameter Clock Pulse Width (Low) Setup Time, A, B, C, D Setup Time, SCLR Setup Time, LOAD Setup Time, U/D Setup Time, CET, CEP Hold Time, Any Inputs ACLR Min 20 20 20 25 30 20 0 15 Typ Max Unit ns ns ns ns ns ns ns ns VCC = 5.0 V Test Conditions MICROPROGRAMMABLE DUAL-EVENT 8-BIT COUNTERS LOAD1 U/D1 COUNT1 ACLR1 OE1 LOAD2 U/D2 COUNT2 ACLR2 OE2 4 4 4 4 CP A-D ACLR OE U/D LOAD CET CEP YA-D RCO CP A-D ACLR OE U/D LOAD CET CEP YA-D CP A-D ACLR U/D OE LOAD CET CEP YA-D RCO CP A-D ACLR OE U/D LOAD CET CEP YA-D LS569A LS569A 4 8 4 8-BIT BUS LS569A 4 8 4 FAST AND LS TTL DATA 5-578 LS569A Case 751D-03 DW Suffix 20-Pin Plastic SO-20 (WIDE) -A20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: MILLIMETER. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. -B1 10 P 0.25 (0.010) M B M 5. 751D 01, AND 02 OBSOLETE, NEW STANDARD 751D 03. 10 PL G R X 45° C K M -T- SEATING PLANE M D 20 PL 0.25 (0.010) T B S F J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 7.40 2.35 0.35 0.50 12.95 7.60 2.65 0.49 0.90 INCHES MIN MAX 0.499 0.292 0.093 0.014 0.020 0.510 0.299 0.104 0.019 0.035 1.27 BSC 0.25 0.10 0 0.32 0.25 7 0.050 BSC 0.010 0.004 0 0.012 0.009 7 ° ° ° ° 10.05 0.25 10.55 0.75 0.395 0.010 0.415 0.029 A S Case 732-03 J Suffix 20-Pin Ceramic Dual In-Line NOTES: 1. LEADS WITHIN 0.25 mm (0.010) DIA., TRUE POSITION AT SEATING PLANE, AT MAXIMUM 20 1 11 2. MATERIAL CONDITION. DIM L TO CENTER OF LEADS WHEN FORMED PARALLEL. 10 3. DIM A AND B INCLUDES MENISCUS. B A F C L N H D SEATING PLANE J M G K DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 23.88 6.60 3.81 0.38 1.40 25.15 7.49 5.08 0.56 1.65 INCHES MIN MAX 0.940 0.260 0.150 0.015 0.055 0.990 0.295 0.200 0.022 0.065 2.54 BSC 0.51 0.20 3.18 1.27 0.30 4.06 0.100 BSC 0.020 0.008 0.125 0.050 0.012 0.160 7.62 BSC 0 ° 15 ° 0.300 BSC 0 ° 15 ° 0.25 1.02 0.010 0.040 Case 738-03 N Suffix 20-Pin Plastic -A20 1 11 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: INCH. DIMENSION L" TO CENTER OF LEAD WHEN FORMED PARALLEL. B C L 4. DIMENSION B" DOES NOT INCLUDE MOLD FLASH. 5. 738 02 OBSOLETE, NEW STANDARD 738 03. -TSEATING PLANE K E G F D 20 PL 0.25 (0.010) M N M J 20 PL 0.25 (0.010) T A M M T B M DIM A B C D E F G J K L M N MILLIMETERS MIN MAX 25.66 6.10 3.81 0.39 27.17 6.60 4.57 0.55 INCHES MIN MAX 1.010 0.240 0.150 0.015 1.070 0.260 0.180 0.022 1.27 BSC 1.27 1.77 0.050 BSC 0.050 0.070 2.54 BSC 0.21 2.80 0.38 3.55 0.100 BSC 0.008 0.110 0.015 0.140 7.62 BSC 0 ° 15 ° 0.300 BSC 0 ° 15 ° 0.51 1.01 0.020 0.040 FAST AND LS TTL DATA 5-579 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. tPZH Open Closed EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. tPZL Closed Open ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. SYMBOL SW1 SW2 tPLZ Closed Closed Closed Closed tPHZ ◊ FAST AND LS TTL DATA 5-580