AN1687

MOTOROLA ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005 SEMICONDUCTOR APPLICATION NOTE Order this document by AN1687/D AN1687 A FULL-FEATURED WIRELESS INTERFACE FOR RS-232 COMMUNICATIONS Prepared by; Paul Sofianos Motorola, Inc., WSSG RF/IF Applications Engineering INTRODUCTION This application note describes a full–duplex, wireless data communication link targeted for RS–232 applications. An encoding technique has been designed which addresses many of the problems incurred when attempting to implement the RS–232 (EIA–232) standard, including but not limited to: hardware flow control, the DC component of the transmitted signal, automatic synchronization from host to slave and error detection. The design emulates a RS–232 null modem cable for computer–to–computer communications. The actual design was realized with standard SSI logic from the high speed CMOS family (MC74HCxxx), an HC05 based MCU, and Motorola’s ISM Band RF chipset. The targeted data rate was 57,600 Baud, although both higher and lower data rates are easily attainable. It is expected that most applications would embed the logic functions (and possibly the MCU functions) into a FPGA, CPLD, ASIC, or other LSI logic building block. Throughout this application note, it is assumed the user is familiar with standard TTL–compatible CMOS devices and the ISM Band RF chipset. Please refer to DL110/D and DL129/D for additional details on individual device specifications. ARCHIVE INFORMATION 1. The DC component should be as close to zero as possible. This maintains the best noise immunity at the receiver. 2. A minimum frequency component must be maintained at all times. If this condition is not met, the transmitter’s PLL and receiver’s coilless demodulator will tend to “track–out” the modulating signal. 3. The maximum frequency component should be known. This will help define the modulation index and total bandwidth required for the transceiver. 4. The system should be able to tolerate reasonable bit–errors. THE WIRELESS LINK The actual implementation of the wireless link transceiver was accomplished with the Motorola’s ISM Band RF chipset. This consists of a MC13145 RF Receiver, MC13146 RF Antenna The MC33411 baseband controls all of the synthesizer functions via a MCU SPI compatible interface. None of the audio processing capabilities of the device are used. Table 1 lists various MC33411 register values for both baseset and handset for the 5 channels used for the prototype. Figure 1. RF Transceiver Block Diagram Receiver RF In DETO LO2 FRX RXMC RXPD RSSI Transmitter RF Out FTX TXD TXMC TXPD DETI LO2 FRX RXMC RXPD RSSI FTX TXMC TXPD ENB DATA DCK RCD Baseband TXD ENB DATA DCK RCD REV 1 MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION  Motorola, Inc. 1999 1 ARCHIVE INFORMATION Transmitter and MC33411 Baseband. Figure 1 depicts the block diagram of the RF transceiver. Figures 2, 3, and 4 are the actual schematics for the Receiver, Transmitter, and Baseband, respectively. The transceiver was designed to operate in the unlicensed (i.e. FCC Part 15) 902–928 MHz Industrial, Scientific and Medical (ISM) band with low–power transmission. Since direct–conversion FSK modulation is used in conjunction with a PLL synthesized carrier, the digital modulation source must meet certain requirements: AN1687 ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005 Figure 2. RF Receiver C7 100 p R2 300 C8 1.0 n VCC U1 RF In CF4 C6 100 p L5 6.8 n C10 100 p CF3 C35 1.0 n VCC 22 C11 C37 100 p R9 33 k D1 C12 RXPD L6 2.2 n C36 100 p 4.7 p 24 30 33 oscB Mix2 In LO2 IF2+ 35 C34 100 p 4.7 p 23 oscE C45 + 1.0 oscC IF128 19 27 14 LNA In LNA Out 17 C9 100 p C26 0.01 C39 100 p T1 C13 16 p C40 12 p C14 10 p R10 10 VCC Mix1 In IF1+ ARCHIVE INFORMATION VCC C46 1.0 n C47 1.0 n C50 100 p C51 100 p L7 L8 C16 39 p 2.7 2.7 C48 1.0 n C49 1.0 n C52 100 p C53 100 p LO2 C41 0.01 C15 36 p IF2IF Dec1 36 39 C42 100 p C27 0.01 VCC C30 1.0 n 20 Lin Adj1 C18 1.0 n CF1 C17 1.0 n C29 0.1 VCC C31 1.0 n 29 C28 0.1 Lin Adj2 IF Dec2 40 C19 1.0 n 38 IF In 41 IF Out 45 Lim Dec1 R4 R5 R6 100 k 2.85 k 120 k 47 2 BWadj Fadj C20 1.0 n CF2 C23 1.0 n C24 0.1 VCC 3 C32 1.0 4 C22 0.1 AFT Out AFT In Lim Dec2 Lim In Det G 46 44 5 R3 27 k C21 1.0 n VCC 21 EN Det Out RSSI 6 7 9 C25 47 p DETO R11 33 k RSSI RXMC 10 MC MC13145 PRES Out C43 22 n C44 0.01 FRX Default Units: Ohms, Microfarads and Microhenries CF1,CF2 Toko Type CFSK Series SK107MX–AE–XXX, 330 kHz BW CF3,CF4 Handset: TDK CF6118702 Baseset: TDK CF6118902 D1 MMBV809LT1 T1 Toko A638AN–A099YWN 2 MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION ARCHIVE INFORMATION ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005 TXPD TXD Appx. 1.5 VPP C75 0.5 p R20 10 k C77 47 p D3 R19 10 k C78 C74 47 p 15 p D2 C65 47 p L10 1.8 n C66 9 C63 2.7 p 11 C64 2.7 p 12 VCC R13 5 MIX/BUF_IN C71 100 p LINADJ R14 200 PA_OUT 19 C72 100 p 14 C70 0.01 CF5 AN1687 Figure 3. RF Transmitter VCC R22 51 MC13146 OSCB U2 RF- 1 VCC 3 C56 1.0 OSCE RF+ + 100 p C67 1.0 n C57 1.0 n C58 1.0 n C61 100 p C59 1.0 n C62 100 p OSCC VCC C60 100 p ARCHIVE INFORMATION C54 1.0 n C68 100 p TXMC VCC Default Units: Ohms, Microfarads and Microhenries CF5 Handset: TDK CF 6118902 Baseset: TDK CF 6118702 D2,D3 MMBV809LT1 L9 10 n 4 C55 1.0 n 22 PA_IN RF Out 16 17 MC EN PRSCOUT FTX MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION 3 ARCHIVE INFORMATION 150 AN1687 ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005 Figure 4. Baseband C94 V CCA C114 100 p C95 4.7 0.1 V CC R31 10 C97 1.0 V CC R30 51 R35 18 k C93 100 p C107 1.0 37 RSSI In 38 Rx Audio In 39 DS In 40 Gnd Audio 41 LO2 Out 42 LO2 V CC 43 LO2+ 44 LO2 Ctl 45 46 47 48 LO2LO2 Gnd LO2 PD LO2 Gnd R x O u t 3 6 333 333222 22 543 210987 65 EEEPGPPVVVM AnAACBAC I cOI dOOC GI nau pt S-+S A A R32 10 C111 1.0 24 23 22 21 20 19 18 17 C83 Y1 11.2 M C84 20 p V CCA C96 1.0 n RSSI DETI V CCR C98 1.0 n MCO VCC Audio C In C cap V CCA C113 100 p C112 1.0 C99 1.0 n LO2 V CC C92 27 p U3 MC33411 ARCHIVE INFORMATION L12 150 n 5-40 p C104 82 p R29 C105 270 k 3.9 n V CCR P F L R LR xFVx MRCP CxCD 1 234 P L L G n d T x P D P L F L T D VFx Ca CTMEL t CxCNKa 11 01 56789 1 2 DATA DCK ENB TXMC FTX R28 68 k C91 470 p RXMC FRX C89 C88 C90 0.01 2.7 n R27 180 k 51 k R24 R25 C85 20 k 2.0 k 0.33 C86 1.0 C87 0.1 200 p R26 RXPD TXPD Default Units: Ohms, Microfarads and Microhenries 4 MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION ARCHIVE INFORMATION C Out Lim In Tx Out DS Out Fref Out 16 Fref In 15 Gnd Digital 14 MCU Clk Out 13 RCD ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005 DIGITAL ENCODING DESCRIPTION As mentioned above, it is necessary to encode the raw RS–232 data prior to RF transmission since the incoming data stream can, and usually will, contain a DC component AN1687 and has no pre–defined minimum frequency component. Figure 5 is a block diagram of the digital encoder/decoder section, and Figure 6 shows a possible implementation of the encoder. Figure 5. Encoder/Decoder Block Diagram (Baseset Shown) 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 Translator ETXD ERXD ERTS ECTS TXD RXD RTS CTS TXD RXD RTS CTS MCU D(0-7) I D/C NTXA TXR CK DCK ENB DATA Parallel-Serial/ Encoder D(0-7) I D/C NTXA TXR CK Serial-Parallel/ Decoder DETI I NRXA RXR FE 16XCK D/C NRXA RXR FE CK DIN RCD DOUT TXD ARCHIVE INFORMATION To RF Transceiver Baseband DB25 P2 MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION 5 ARCHIVE INFORMATION AN1687 ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005 Figure 6. Encoder U1 VCC U5D 14 15 1 2 3 SER A B C D 9 8 74HC04A D/C D7 D6 CK CK 4 E 5 F 6 G 7 H 11 SRCLK 13 SRLOAD 10 SRCLR 12 RCLK 74HC597A QH 9 CK NTXA ARCHIVE INFORMATION D(0-7) U2 D5 D4 D3 D2 D1 D0 I 11 U5E 10 74HC04A 14 SER 15 A 1 B 2 C 3 D 4 E 5 F 6 G 7 H 11 SRCLK 13 SRLOAD 10 SRCLR 12 RCLK U15D U24C 8 74HC32A VCC QA QB QC QD RCO 14 13 12 11 15 13 74HC04A U5F 12 74HC109 CK PR 14 J 12 CLK 13 K CL 10 9 74HC597A 11 74HC86A 13 12 11 74HC32A 5k R13 QH 9 C17 2200 p DOUT C23 U24D 4700 p 13 12 U3 3 4 5 6 7 10 2 9 1 A B C D ENP ENT CLK LOAD CLR 74HC163A U4B 11 Q Q 15 10 9 TXR VCC VCC CK Figure 7 illustrates the encoding scheme which was developed for this purpose. Four additional bits surround a data byte: the I bit, I bit, D/C bit and D/C bit. The function of these bits are: I (Invert) Bit: A logic low on this bit indicates that the data byte and D/C bit are in true form. A logic high on this bit indicates that the data byte and D/C bit are complemented from their original form. I (Invert Bar) Bit: Just the complement of the I bit. D/C (Data/Control) Bit: A logic low on this bit indicates that the data byte should be interpreted as a control word. A logic high on this bit indicates that the data byte contains real data. D/C (Data/Control): Just the complement of the D/C bit. Figure 7. D/C I I D0 D1 D2 D3 D4 D5 D6 D7 D/C D/C I 6 MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION ARCHIVE INFORMATION ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005 This encoding scheme allows for the representation of 256 unique data words and 256 unique control words. The control byte $h00 is reserved and referred to as the idle byte. When the Parallel–Input/Serial–Output (PISO) register is ready to transmit a data byte (TXR asserted), a check is made to see if real data has been transferred into the Serial Communications Interface (SCI) data register of the MCU. If data has been received, the data byte will be read, and the initial state of D/C will be set to 1. If data has not been received, the data byte will be set to $h00 (the idle byte) and the initial state of D/C will be set to 0. Next, the data byte is examined for a DC component. Each 0 bit of the data byte represents –1 and each 1 bit of the data byte represents +1. All of these values are summed together: a negative result indicates a low DC component, zero indicates no DC component, and a positive (non–zero) result indicates a high DC component. This component is compared to a cumulative sum (which may be negative, zero, or positive) and the following actions are taken: If the current DC component sum is negative, and the cumulative sum is positive or zero OR if the current DC component sum is positive or zero and the cumulative sum is negative THEN clear the I bit (I=0). The new cumulative sum is equal to the old cumulative sum plus the current sum. OTHERWISE set the I bit (I=1). The new cumulative sum is equal to the old cumulative sum minus the current sum. If the I bit is set, the contents of the data byte and D/C bit are complemented. The updated value of the I bit, data byte, and D/C bit are placed on the PISO, and a transmission acknowledge signal (NTXA) is asserted. Please note, the net effect of the DC component contributed by the I and I bits and D/C and D/C bits will always equal zero. An analysis of this encoding scheme brings to light a few interesting observations: 1. The average DC component over time will approach zero. 2. The minimum frequency component which will be observed in the data stream will equal 1/(2 x transmitted bit period x 10). AN1687 3. The maximum (fundamental) frequency component which will be observed in the data stream will equal 1/(2 x transmitted bit period). 4. A sequence of ten consecutive zeros or ones indicates the presence of an idle byte. Item 4 is perhaps the most interesting observation, since it will allow the receiver to synchronize the incoming data and align the serial stream on a byte–wide basis. TRANSMITTING FREQUENCY for ENCODED DATA For RS–232 communications which take the form of one start bit, eight data bits, no parity, and one stop bit, the SCI will receive 10 bits of data to represent one actual data byte. For our encoding scheme, 12 bits must be transmitted for each data or control byte received. If the transmit pipeline is set to a frequency of at least 1.2 times the SCI receive pipeline, the receive bandwidth will not have to be reduced (i.e. no stop or hold conditions would be required). In actual practice, the transmit pipeline was set to a frequency 25% greater than the receive pipeline. As a result, at a minimum, there will be at least one idle byte transmitted for every 24 real data bytes. This useful feature allows the receiver to re–synchronize from time to time. ARCHIVE INFORMATION ADDITIONAL FEATURES As mentioned above, the opportunity presents itself to transmit a control word (the idle byte just being a special case of a control word) from time to time. With 255 control words remaining, various special features can be built into the link, all transparent to the actual RS–232 data communications. One of the more obvious features which can be implemented is hardware (RTS/CTS) flow control. The RTS signal (for the baseset) and CTS signal (for the handset) can be monitored and transmitted/received and interpreted by the link. The latency will mostly be a function of the overhead bandwidth. Other features which can be implemented include, but are not limited to: Remote channel changing Adaptive channel selection Acknowledgments DCD/DSR, etc. commands CRC or other error checking Half duplex handshaking Power conservation modes MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION 7 ARCHIVE INFORMATION AN1687 ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005 Figure 8. Decoder VCC VCC 3 A 4 B 5 C 6 D 74HC109 6 16XCK 7 PR 14 J 12 CLK 13 K CL 15 VCC U16 14 QA 13 QB 12 QC 11 QD 15 RCO RCLK (Recovered CK) 74HC109 DIN 16XCK 16XCK 3 PR 2 J 4 CLK K CL U14A 5 Q Q 1 U14B 11 Q Q 10 9 1 U15A 2 74HC86A 16XCK 3 VCC 7 ENP 10 ENT 2 CLK 9 LOAD 1 CLR 74HC163A VCC 3 A 4 B 5 C 6 D 10 9 4 5 74HC86A VCC U15B 6 VCC RCLK 7 ENP 10 ENT 2 CLK 9 LOAD 1 CLR 1 RDAT (Recovered Data) U18 14 QA 13 QB 12 QC 11 QD 15 RCO VCC ARCHIVE INFORMATION 74HC109 RCLK 3 PR 2 J 4 CLK K CL U17A 5 Q Q 1 6 16XCK 7 74HC109 PR 14 J 12 CLK 13 K CL U17B 11 Q Q 15 PR 14 J 12 CLK 13 K CL 15 Q Q 10 9 RXR D/C 74HC163A D(0-7) D(0-7) VCC 3 A 4 B 5 C 6 D U21 14 QA 13 QB 12 QC 11 QD 15 RCO VCC 1 2 74HC32A U24A 3 3 74HC109 PR 2 J 4 CLK K CL 1 8 74HC86A 14 5 SER U20 U19A Q Q 6 7 VCC 15 QA 1 QB 2 QC 3 QD 4 QE 5 QF 6 QG 7 QH QH ′ 74HC595A 9 14 D7 D6 D5 D4 D3 D2 SER U22 QA QB QC QD QE QF QG QH QH ′ 74HC595A NRXA 15 1 2 3 4 5 6 7 9 D1 D0 I RCLK 11 10 12 13 SRCLK SRCLR RCLK G RCLK 11 SRCLK 10 SRCLR VCC 12 13 RCLK G RCLK VCC 7 ENP 10 ENT 2 CLK 9 LOAD 1 CLR VCC RCLK 9 10 U15C 74HC163A 1 2 U23A 3 74HC86A VCC 9 10 U23C 8 74HC86A 4 5 11 74HC86A 74HC32A U24B 6 FE 4 5 U23B 6 74HC86A 12 13 U23D 8 MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION ARCHIVE INFORMATION VCC 74HC109 U19B 11 ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005 Figure 8 illustrates a possible implementation of the digital decoder section of the design. Received data is “squared up” by the data slicer of the MC33411 baseband IC. The transmitted data is generally frequency limited in order to preserve bandwidth (i.e. low–pass filtered). Because of this limiting, as well as noise components and hysteresis in the data slicer, the duty cycle of the received data stream can vary substantially from that of the transmitted data. For this reason, a data and clock recovery block is utilized which oversamples the incoming data (digital noise filtering) and captures the embedded clock. Once the clock and data have been recovered, they are presented to the Serial–Input/Parallel–Output (SIPO) register. Data is transferred into the register every 12 bits, this representing the I, I, data byte, D/C and D/C bits. Another circuit analyzes the serial data stream looking for ten consecutive bits without a transition. If this condition is observed, it indicates an idle byte has been received, and the SIPO register clock can be synchronized. When the SIPO register indicates that a byte has been received (RXR asserted), the MCU asserts an acknowledgement (NRXA), loads the data byte, the I bit and D/C bit from the bus. At this time, a comparison is made which verifies that the I bit is the complement of the I bit and the D/C bit is the complement of the D/C bit. If either of these conditions is not met, a framing error has occurred and the received data is simply ignored. If a valid byte has been received, the MCU checks the status of the I bit. If the I bit is set, the byte, as well as the D/C AN1687 bit, is complemented. Next, the MCU checks the value of the updated D/C bit; a logic zero indicates a control word, and the MCU can take appropriate action. If the D/C bit indicates real data has been received, the data is placed on an internal First–In/First–Out (FIFO) memory stack. The SCI transmitter is checked: if empty, the next data byte is placed into the SCI transmitter and if full, the data will be transferred at a later time. As can be seen, the decoding of the data is a relatively simple task. If desired, the MCU can consider the lack of an idle byte, within a given period of time or reception of some number of bytes, an indication that the RF link has failed. Again, this condition can be used to re–initialize the RF link, or other courses of action can be taken. SUMMARY ARCHIVE INFORMATION MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION 9 ARCHIVE INFORMATION This application note has described a robust, full featured RS–232 wireless interface which can be implemented with an inexpensive MCU. For slower data rates, it is possible to eliminate all of the external “glue logic” shown in this note. A plethora of additional features can be added by the use of embedded control words which are transparent to the actual data transceiver. Motorola’s inexpensive and easy to use ISM Band RF chipset is easily capable of accomplishing the wireless portion of the task as long as the digital information presented to the transmitter and receiver have been properly preconditioned prior to modulation and demodulation. AN1687 Baseband Register Address $h01 $h02 $h01 $h02 $h01 $h02 $h01 $h02 ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005 Table 1. Handset Value $h004822 $h004C27 $h004827 $h004C2C $h00482C $h004C31 $h004831 $h004C36 $h004836 $h004C3B $h0E0276 $h160070 $h000010 $h0000FF $h01C000 Transmit Frequency (MHz) 925.0 – 925.5 – 926.0 – 926.5 – 927.0 – – – – – – Receive Frequency (MHz) – 903.0 – 903.5 – 904.0 – 904.5 – 905.0 – – – – – Baseset Value $h004686 $h004E03 $h00468B $h004E08 $h004690 $h004E0D $h004695 $h004E12 $h00469A $h004E17 $h0E0276 $h160070 $h000010 $h0000FF $h01C000 Transmit Frequency (MHz) 903.0 – 903.5 – 904.0 – 904.5 – 905.0 – – – – – – Receive Frequency (MHz) – 925.0 – 925.5 – 926.0 – 926.5 – 927.0 – – – – – Channel Number 0 0 1 1 2 2 3 3 ARCHIVE INFORMATION $h02 $h03 $h04 $h05 $h06 $h07 4 X X X X X 10 MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION ARCHIVE INFORMATION $h01 4 ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005 NOTES AN1687 ARCHIVE INFORMATION MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION 11 ARCHIVE INFORMATION AN1687 ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005 ARCHIVE INFORMATION Motorola reserves the right to make changes without further notice to any products herein. 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